Insul ati on Resi stance (IR) i s a measure of the

i nsul ati ng property of di el ectri c materi al s and

i s t y p i cal l y ex p r essed i n meg - oh ms. Th e
i nsul ati on resi stance i ncl udes both vol ume and
surface resi stance and can be expressed as the
paral l el combi nati on of the two.
In su latio n R esistan ce = R
V
x R
S
/ R
V
+R
S
)
Volume resistivity: R
v
(ohms cm) al so cal l ed
bul k r esi stance r epr esents the r esi stance per
u n i t v o l u m e asso ci at ed w i t h a d i el ect r i c
materi al .
Surface resistance: R
s
(ohms/ sq.) al so cal l ed sheet
r esi stance r epr esents r esi st -
an ce p er u n i t ar ea and
accounts for the leakage path
on the outside surfaces of the
capaci tor . Thi s i s a mater i al
pr oper t y; how ever , sur f ace
cont ami nat i on and por osi t y
also influence this parameter.
I R M e a su re m e n ts:
An I R m et er i s set u p t o
measu r e i n su l at i on r esi st -
ance by appl yi ng a vol tage,
t y p i cal l y eq u al t o t h e
capaci tor s rated worki ng vol tage (WVDC), for
about one mi nute. After the capaci tor has been
charged, the l eakage current i s then measured.
The IR val ue i s determi ned by taki ng the rati o
of the appl i ed dc vol tage across the capaci tor
and t he r esul t ant l eak age cur r ent af t er t he
i ni ti al chargi ng peri od. Thi s val ue i s expressed
as l eakage or insulation resistance. A typi cal IR
for an ATC por cel ai n chi p capaci tor i s i n the
order of 10
12
ohms at 25C.
The fi gure represents a si mpl i fi ed ci rcui t of an
IR meter w i th a capaci tor IR model depi cted
bet w een t he dot t ed l i nes. R
L1
i s pl aced i n
seri es wi th the dc source i n order to l i mi t the
chargi ng current to 50ma. In addi ti on R
L1
wi l l
l i mi t the current i n i nstances w here the IR i s
very l ow or the test sampl e i s shorted. R
L2
i s
pl aced i n ser i es w i t h t he mi cr oammet er i n
order to cal i brate the l eakage current i nto the
appr opr i ate i nsul ati on r esi stance val ue. The
bl eed er r esi st or (R
B
) i s p l aced acr oss t h e
capaci tor i n order to di scharge the test sampl e
after the measurement has been performed.
Fa cto rs A ffe ctin g I R :
Di el ectr i c mater i al pr oper ti es and pr ocessi ng
p l ay a m aj o r r o l e i n d et er m i n i n g t h e I R
ch ar act er i st i cs of cer ami c ch i p cap aci t or s.
Speci fi c formul ati ons as wel l as cerami c fi ri ng
pr ofi l es ar e maj or factor s that deter mi ne the
i nsul ati on r esi stance. Mi cr ostr uctur al defects
such as v oi ds, cr ack s, del ami nat i ons, and
f or ei gn mat er i al s ar e al so associ at ed w i t h
vari ati ons of i nsul ati on resi stance. These defects
ar e undesi r abl e and r equi r e t i ght cont r ol of
man u f act u r i n g p r ocesses t o p r ev en t t h ei r
occurrence.
Insul ati on resi stance i s pri mari l y i nfl uenced by
i o n i c i m b al an ces i n t h e cer am i c cr y st al
structure creati ng charge carri ers that become
mobi l e i n t he pr esence of an el ect r i c f i el d.
Incr eased number s of mobi l e char ge car r i er s
resul t i n l eakage current paths that degrade the
IR. Charge carri er mobi l i ty al so i ncreases wi th
temperature, hence l eadi ng to l ower i nsul ati on
resistance at elevated temperatures. At 125C the
IR w i l l degr ade appr oxi mat el y one or der of
mag n i t u d e. Cap aci t or s f r om v ar i ou s
manufacturi ng l ots are frequentl y tested at the
highest rated operating temperature to make it
easier to uncover defects in the dielectric. Other
factors that effect IR are listed below.
Additives: Chemi cal addi t i ves used i n t he
dielectric formulation may exhibit a valence that will
influence the IR of the dielectric. Care in selecting
chemical additives such as various oxides must be
exercised in order to optimize the IR.
Particle Size & Grain Boundaries: Smal l
cerami c parti cl e si zes wi l l provi de a fi ne grai n
structure in the ceramic. This is desirable because
smal l grai n si zes yi el d the greatest number of
grain boundaries and will therefore act as a barrier
to leakage current, thereby enhancing the IR.
Binder Systems: Used i n the preparati on of
cer am i c sl u r r y an d el ect r o d e p ast e an d
subsequentl y r emoved. Thi s i s accompl i shed
duri ng a sl ow heati ng cycl e i n whi ch organi c
compounds are decomposed and el i mi nated. If
the bi nders are not properl y removed they may
l eave traces of carbon and other i mpuri ti es i n
the cerami c. These resi dual el ements, reacti ng
wi th the di el ectri c duri ng si nteri ng, may al ter
the di stri buti on of mobi l e charge carri ers and
create conducti ve paths, thereby degradi ng the
i nsul ati on resi stance.
Impurities: Care must be taken throughout the
m an u f act u r i n g p r o cess t o av o i d p r o cess
contami nati on. Thi s condi ti on can degrade the
di el ectri c s IR property and therefore must be
ti ghtl y control l ed.
Surface Contamination: So l d er f l u x ,
m o i st u r e, sal t s an d an y n u m b er o f
en v i r o n m en t al co n t am i n an t s can easi l y
degr ade the capaci tor s i nsul ati on r esi stance.
Care must be taken to cl ean the surface free of
forei gn materi al s.
Density/Porosity: Ceramic dielectrics must be
manufactured as close to the theoretical density
of the dielectric material as possible to minimize
pores in the ceramic. Large pores in the ceramic
mi cr ost r u ct u r e can absor b en v i r on men t al
contami nants as w el l as moi stur e l eadi ng to
degraded IR. Thi s effect i s most evi dent under
high operating humidity and can be temporarily
r ev er sed by heat i ng t he capaci t or , t her eby
baking out the moisture.
A p p lica tio n C o n sid e ra tio n s:
Low IR can al ter the bi as condi ti on of an FET
am p l i f i er b y o f f er i n g ad d i t i o n al sh u n t
resi stance i n the bi as network.
Capaci tors used i n dc bl ocki ng and coupl i ng
ap p l i cat i on s n eed t o ex h i bi t h i g h I R t o
prevent dc l eakage current from fl owi ng.
Fi l ter and matchi ng appl i cati ons requi re hi gh
I R so t h at t h e ov er al l ci r cu i t Q r emai n s
unaffected.
The capaci t or s l ow f r equency di ssi pat i on
factor (DF) can be affected by l ow IR. Thi s wi l l
make IR appear as a si gni fi cant part of the
di el ectri c l oss, thereby degradi ng the DF. Thi s
degradati on occurs because IR appears as a
shunt resi stance i n paral l el wi th the capaci tor.
Low IR i n a hi gh pow er bypass appl i cati on
may resul t i n excessi ve heat di ssi pati on and
degraded ci rcui t performance.
Over al l ci r cui t per f or mance and r el i abi l i t y
m ay b e af f ect ed o v er t i m e b y v o l t ag e
st r esses and el evat ed oper at i ng t emper a-
tures i f th e IR i s i ni ti al l y degraded.
Richard Fiore
Director, RF Applications Engineering
American Technical Ceramics Corp.
R
v
- Dielectricvolume resistance. R
s
- Dielectricsurface resistance.
R
L1
- Source current limit resistor. R
L2
- Capacitor calibration resistor.
R
B
- Bleeder resistor. DUT - Device under test.
Schematic of IR meter with capacitor IR Model.
CIRCUIT DESIGNERS NOTEBOOK
Understanding Insulation Resistance
A me r i c a n T e c h n i c a l C e r a mi c s

w w w . a t c e r a mi c s . c o m
Excerpt from complete Circuit Designers Notebook, Document #001-927, Rev. E, 1/05