2011

Cadence Tutorial [Analog Design Flow]

Narashimaraja. P Asst. Prof., E&C Dept., RVCE, Bangalore 10/18/2011

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Table of Contents
Introduction: ............................................................................................................................... 1 Design Specifications: ........................................................................................................... 3 Schematic Capture: ................................................................................................................ 3 Symbol Creation: ................................................................................................................... 4 Simulation: ............................................................................................................................. 5 Mask Layout: ......................................................................................................................... 6 Design Rule Check (DRC)..................................................................................................... 7 Circuit Extraction ................................................................................................................... 8 Layout versus Schematic Check ............................................................................................ 9 Post-layout Simulation ........................................................................................................... 9 Manual Layout Example .......................................................................................................... 11 Example: CMOS Inverter Layout ........................................................................................ 11 Steps of Layout Design .................................................................................................... 11 Automatic Layout Generation Tools ....................................................................................... 42 Example: Automatic Layout Generation Tools (Device Level Placer) ............................... 42 Steps of Automatic Layout Generation............................................................................ 42

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Cadence Tutorial [Analog Design flow]

Introduction:
This tutorial is for a typical bottom-up design flow using CADENCE Custom IC Design Tools (version 97A). The examples were generated using the HP 0.6 um CMOS14TB process technology files, prepared at North Carolina State University (NCSU) and made available through MOSIS.

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Cadence Tutorial [Analog Design flow] The above flow chart is discussed in detail. (Click on the following topics to navigate to the discussion area). [Design Specifications:] [Schematic Capture:] [Symbol Creation:] [Simulation:] [Mask Layout:] [Design Rule Check (DRC)] [Circuit Extraction] [Layout versus Schematic Check] [Post-layout Simulation]

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Cadence Tutorial [Analog Design flow]

Design Specifications:
The bottom-up design flow for a transistor-level circuit layout always starts with a set of design specifications. The "specs" typically describe the expected functionality (Boolean operations) of the designed block, as well as the maximum allowable delay times, the silicon area and other properties such as power dissipation. Usually, the design specifications allow considerable freedom to the circuit designer on issues concerning the choice of a specific circuit topology, individual placement of the devices, the locations of input and output pins, and the overall aspect ratio (width-to-height ratio) of the final design. Note that the limitations spelled out in the initial design specs typically require certain design trade-offs, such as increasing the dimensions of the transistors in order to reduce the delay times. In a large-scale design, the initial design specifications may also evolve during the design process to accommodate other specs or limitations. This implies that the designer(s) of individual blocks or modules must communicate clearly and frequently about the spec updates, in order to avoid later inconsistencies. As an example, the initial design specs of a one-bit binary full adder circuit are listed below: Technology: 0.8 um twin-well CMOS Propagation delay of "sum" and "carry_out" signals < 1.2 ns (worst case) Transition times of "sum" and "carry_out" signals <1.2 ns (worst case) Circuit area < 1500 um^2 Dynamic power dissipation (at VDD=5 V and fmax=20 MHz) < 1 mW It can be seen that one can design a number of different adders (with different topologies, different maximum delays, different total silicon areas, etc.), all of which essentially conform to the specs listed above. This indicates that the starting point of a typical bottom-up design process usually leaves the designer a considerable amount of design freedom.

Schematic Capture:
The traditional method for capturing (i.e. describing) your transistor-level or gate-level design is via the schematic editor. Schematic editors provide simple, intuitive means to draw, to place and to connect individual components that make up your design. The resulting schematic drawing must accurately describe the main electrical properties of all components and their interconnections. Also included in the schematic are the power supply and ground connections, as well as all "pins" for the input and output signals of your circuit. This information is crucial for generating the corresponding netlist, which is used in later stages of the design. The generation of a complete circuit schematic is therefore the first important step of the transistor-level design flow. Usually, some properties of the components (e.g. transistor dimensions) and/or the interconnections between the devices are subsequently modified as a result of iterative optimization steps. 3|Page

Cadence Tutorial [Analog Design flow] These later modifications and improvements on the circuit structure must also be accurately reflected in the most current version of the corresponding schematic.

Symbol Creation:
If a certain circuit design consists of smaller hierarchical components (or modules), it is usually very beneficial to identify such modules early in the design process and to assign each such module a corresponding symbol (or icon) to represent that circuit module. This step largely simplifies the schematic representation of the overall system. The "symbol" view of a circuit module is an icon that stands for the collection of all components within the module. A symbol view of the circuit is also required for some of the subsequent simulation steps, thus, the schematic capture of the circuit topology is usually followed by the creation of a symbol to represent the entire circuit. The shape of the icon to be used for the symbol may suggest the function of the module (e.g. logic gates - AND, OR, NAND, NOR), but the default symbol icon is a simple rectangular box with input and output pins. Note that this icon can now be used as the building block of another module, and so on, allowing the circuit designer to create a system-level design consisting of multiple hierarchy levels.

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Simulation:
After the transistor-level description of a circuit is completed using the Schematic Editor, the electrical performance and the functionality of the circuit must be verified using a Simulation tool. The detailed transistor-level simulation of your design will be the first indepth validation of its operation, hence, it is extremely important to complete this step before proceeding with the subsequent design optimization steps. Based on simulation results, the designer usually modifies some of the device properties (such as transistor width-to-length ratio) in order to optimize the performance. The initial simulation phase also serves to detect some of the design errors that may have been created during the schematic entry step. It is quite common to discover errors such as a missing connection or an unintended crossing of two signals in the schematic. The second simulation phase follows the "extraction" of a mask layout (post-layout simulation), to accurately assess the electrical performance of the completed design.

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Mask Layout:
Manual Layout Example Automatic Layout Generation Tools The creation of the mask layout is one of the most important steps in the full-custom (bottom-up) design flow, where the designer describes the detailed geometries and the relative positioning of each mask layer to be used in actual fabrication, using a Layout Editor. Physical layout design is very tightly linked to overall circuit performance (area, speed and power dissipation) since the physical structure determines the transconductances of the transistors, the parasitic capacitances and resistances, and obviously, the silicon area which is used to realize a certain function. On the other hand, the detailed mask layout of logic gates requires a very intensive and time-consuming design effort. The physical (mask layout) design of CMOS logic gates is an iterative process which starts with the circuit topology and the initial sizing of the transistors. It is extremely important that the layout design must not violate any of the Layout Design Rules, in order to ensure a high probability of defect-free fabrication of all features described in the mask layout.

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Please follow this example link for a detailed description of the main procedures in "Mask Layout Design". Another alternative of generating the mask layout is to make use of automated tools. Please follow this example link for a detailed description of generating a layout from a schematic using the device level placer.

Design Rule Check (DRC)

The created mask layout must conform to a complex set of design rules, in order to ensure a lower probability of fabrication defects. A tool built into the Layout Editor, called Design Rule Checker, is used to detect any design rule violations during and after the mask layout design. The detected errors are displayed on the layout editor window as error markers, and the corresponding rule is also displayed in a separate window. The designer must perform DRC (in a large design, DRC is usually performed frequently before the entire design is completed), and make sure that all layout errors are eventually removed from the mask layout, before the final design is saved.

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Circuit Extraction
Circuit extraction is performed after the mask layout design is completed, in order to create a detailed net-list (or circuit description) for the simulation tool. The circuit extractor is capable of identifying the individual transistors and their interconnections (on various layers), as well as the parasitic resistances and capacitances that are inevitably present between these layers. Thus, the "extracted net-list" can provide a very accurate estimation of the actual device dimensions and device parasitics that ultimately determine the circuit performance. The extracted net-list file and parameters are subsequently used in Layout-versus-Schematic comparison and in detailed transistor-level simulations (postlayout simulation).

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Layout versus Schematic Check

After the mask layout design of the circuit is completed, the design should be checked against the schematic circuit description created earlier. The design called "Layoutversus-Schematic (LVS) Check" will compare the original network with the one extracted from the mask layout, and prove that the two networks are indeed equivalent. The LVS step provides an additional level of confidence for the integrity of the design, and ensures that the mask layout is a correct realization of the intended circuit topology. Note that the LVS check only guarantees topological match: A successful LVS will not guarantee that the extracted circuit will actually satisfy the performance requirements. Any errors that may show up during LVS (such as unintended connections between transistors, or missing connections/devices, etc.) should be corrected in the mask layout - before proceeding to post-layout simulation. Also note that the extraction step must be repeated every time you modify the mask layout.

Post-layout Simulation
The electrical performance of a full-custom design can be best analyzed by performing a post-layout simulation on the extracted circuit net-list. At this point, the designer should have a complete mask layout of the intended circuit/system, and should have passed the DRC and LVS steps with no violations. The detailed (transistor-level) simulation 9|Page

Cadence Tutorial [Analog Design flow] performed using the extracted net-list will provide a clear assessment of the circuit speed, the influence of circuit parasitics (such as parasitic capacitances and resistances), and any glitches that may occur due to signal delay mismatches. If the results of post-layout simulation are not satisfactory, the designer should modify some of the transistor dimensions and/or the circuit topology, in order to achieve the desired circuit performance under "realistic" conditions, i.e., taking into account all of the circuit parasitics. This may require multiple iterations on the design, until the post-layout simulation results satisfy the original design requirements. Finally, note that a satisfactory result in post-layout simulation is still no guarantee for a completely successful product; the actual performance of the chip can only be verified by testing the fabricated prototype. Even though the parasitic extraction step is used to identify the realistic circuit conditions to a large degree from the actual mask layout, most of the extraction routines and the simulation models used in modern design tools have inevitable numerical limitations. This should always be one of the main design considerations, from the very beginning. After all, there is no substitute for the "real silicon" !

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Manual Layout Example

Example: CMOS Inverter Layout
In this tutorial, a simple CMOS inverter layout will be drawn step by step. We will start with a simple design idea and will complete the mask layout using different techniques.

Steps of Layout Design Starting up: Design Idea: Create Layout Cellview Virtuoso and LSW NMOS: Drawing the N-Diffusion (Active) The Gate Poly Making Active Contacts Covering Contacts with Metal-1 The N-Select Layer PMOS Drawing the P-Diffusion (Active) Transistor Features The P-Select Layer Drawing the N-Well Connecting both transistors Placing the PMOS and NMOS transistors Connecting the Output Connecting the Input Making a Metal-1 connection for the Input Power Rails 11 | P a g e

Cadence Tutorial [Analog Design flow] P-Substrate Contact N-Substrate Contact Enclosing the substrate contact DRC and Finalizing Design Rule Checking Final Layout Starting up: Design Idea: To draw the mask layout of a circuit, two main items are necessary at the beginning: 1. 2. A circuit schematic A signal flow diagram

1. Circuit schematic Any physical layout will actually correspond to a circuit schematic. It is important that the schematic of a functionally correct circuit is present and the layout is drawn according to the schematic (and not the other way around). The schematic will the contain exact connection diagram and individual device properties. Two example inverter schematics can be seen below. While both schematics are identical, the one on the right is drawn in a way to resemble the final layout.

In this example the NMOS transistor and the PMOS transistor have identical dimensions W=1.2u and L=0.6u 2. Signal flow diagram

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Cadence Tutorial [Analog Design flow] A layout can be drawn in a number of different ways. The most important factor determining the actual layout is the signal flow. The layout will almost in all cases be a part of a larger structure or the basic building element of an array of identical blocks. In modern fabrication technologies, more than one physical layer can be used to transfer signals. For example with the fabrication technology used throughout this manual, a total of 4 layers (poly, Metal-1, Metal-2, Metal-3) can be used. The general flow of the signal connections as well as their layers need to be pre-determined. The following is an sample flow diagram used for the example layout:

In this flow diagram, it has been decided that all signals are on the same layer (blue, Metal-1) and that all signals will travel horizontally. Note that the signal flow diagram is just a concept that you can visualize for a particular circuit, or a simple sketch that you can scribble on the back of an envelope. The actual mask layout will roughly follow this concept. Create Layout Cellview We will assume, that you have logged on and started Cadence Design Tools, and that you already have created a design library for yourself. Please refer to Starting Cadence Section if you have not done so. 1. From the Library Manager, choose File then New and then Cellview ( File --> New --> Cellview )

2. Enter cellname and choose layout cellview A dialog box will appear prompting you for the design library, cellname and cellview. Make sure that the library name corresponds to your design library, choose a name for your cell and choose Virtuoso as the design tool. The cellview will be selected as layout.

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Virtuoso and LSW Two design windows will pop-up after you have entered the design name.

LSW The Layer Selection Window (LSW), lets the user select different layers of the mask layout. Virtuoso will always use the layer selected in the LSW for editing. The LSW can also be used to determine which layers will be visible and which layers will be selectable. To select a layer, simply click on the desired layer within the LSW. Virtuoso Virtuoso is the main layout editor of Cadence design tools. There is a small button bar on the left side of the editor. Commonly used functions can be accessed by pressing these buttons. There is an information line at the top of the window. This information line, (from left to right) contains the X and Y coordinates of the cursor, number of selected objects, the travelled distance in X and Y, the total distance and the command currently in use. This information can be very handy while editing. At the bottom of the window, another line shows what function the mouse buttons have at any given moment. Note that these functions will change according tto the command you are currently executing. 14 | P a g e

Cadence Tutorial [Analog Design flow] Most of the commands in Virtuoso will start a mode, the default mode is selection, as long as you do not choose a new mode you will remain in that mode. To quit from any mode and return to the default selection mode, the "ESC" key can be used. NMOS: Drawing the N-Diffusion (Active) Now we will start drawing our first transistor. which will be the NMOS transistor of the CMOS inverter. From the schematic, we know that this transistor has a channel width of 1.2u. The width of the transistor will correspond to the width of the active area. We will select the n-diffusion layer and draw a rectangular active area to define the transistor. 1. Select nactive layer from the LSW

2. From the Create menu in Virtuoso select Rectangle ( Create --> Rectangle )

3. Draw the box You are now in rectangle mode. Select the first corner of rectangle in the layout window (you may select any point within the window but try to select a point close to the origin), click once, and then move the mouse cursor to the opposite corner. Using the information bar, draw a box that is 3.6u horizontal and 1.2u vertical. All units are in micrometers by default. To simplify the drawing, a grid of half a lambda is used, that is the cursor moves in 0.15u increments only.

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The Gate Poly The second step is to draw the gate. We will use a vertical polysilicon rectangle to create the channel. Note that the length of the transistor channel will be determined by the width of this poly rectangle. 1. Select poly layer from the LSW

2. From the menu Misc choose Ruler ( Misc --> Ruler )

The ruler is a very handy function. In our case we need to draw the poly rectangle in the middle of the diffusion region. Furthermore, design rules tell us that poly must extend at least by 0.6u (2 Lambda) from edge of the diffusion . To pinpoint the location of the poly gate we can use two rulers. One ruler will be used to determine the horizontal distance of the poly gate from the diffusion edge, while a second ruler will show the minimum amount of poly extension outside the diffusion according to the design rules 3. Draw poly rectangle

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The starting point is pinpointed by two rulers. The rectangle function is used to draw a poly rectangle that is 0.6u horizontal and 2.4u vertical. Making Active Contacts The next step is to make the active contacts. These contacts will provide access to the drain and source regions of the NMOS transistor. 1. Select the ca (Active Contact) layer from the LSW.

2. Use the ruler to pinpoint a location 0.30u from the edges of diffusion. 3. Create a square with a width and height of 0.6u within the active area.

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Cadence Tutorial [Analog Design flow] 4. From the Edit menu choose Copy ( Edit --> Copy )

You could choose to draw the second contact the same way as you have drawn the first one. However, copying existing features is also a viable alternative. The copy dialog box will pop-up as soon as you select the copying mode. For this operation the default values are appropriate. The Snap Mode is an interesting option. When this is in orthogonal setting the copied objects will move only along one axis. This is a good feature to help you avoid alignment problems.

5. Copy the contact After you enter the copy mode, an object must be selected. Click in the contact, you'll notice that the outline of contact will attach to your cursor. Now move the object, and click when you are satisfied with the location.

Design rules state that the minimum contact to poly spacing must be 0.6u (2 lambda). You can use a ruler to pinpoint the location. Please note that you can interrupt any mode for

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Cadence Tutorial [Analog Design flow] placing a ruler (and zooming in and out). After you are finished (by hitting "ESC" key) you'll return to the mode you were in.

Now you have placed an active contact each into the source and drain diffusion regions of the transistor. Covering Contacts with Metal-1 Active contacts in fact only define holes in the oxide (connection terminals). The actual connection to the corresponding diffusion region is made by the Metal layer. 1. Select layer Metal-1 from the LSW

2. Draw two rectangles 1.2u wide to cover the contacts

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Cadence Tutorial [Analog Design flow] Note that Metal-1 has to extend over the contact in all directions by at least 0.3u (1 lambda). The N-Select Layer Each diffusion area of each transistor must be selected as being of n-type or p-type. This is accomplished by a defining the "window: of n-type (or p-type) doping (implantation), through a special mask layer called n-select (p-select). 1. Select nselect layer from the LSW.

2. Draw a rectangle extending over the active area by 0.6u (2 lambda) in all directions.

This is it ! Our first transistor is finished, now let us make a few million more of the same :-) PMOS Drawing the P-Diffusion (Active) Now that we have drawn the NMOS transistor, the next step is to draw the PMOS transistor. The basic steps involved in drawing the PMOS are the same. 1. Select pactive layer from the LSW

2. Draw a rectangle 3.6u by 1.2u You can use the cursor keys and the zoom function to find yourself a place to build the transistor. Make sure you leave enough separation between the NMOS and the PMOS. Note that the PMOS transistor will also be surrounded by the N-well region.

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Transistor Features These three steps are identical to the ones done for the NMOS. 1. Draw the gate poly

2. Place the contacts

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3. Cover contacts with Metal-1

The P-Select Layer As with the NMOS transistor, the p-type doping (implantation) window over the active area must be defined using the n-pelect layer. 1. Select pselect layer from the LSW

2. Draw a rectangle that extends over the active area by 0.6u (2 lambda) in all directions.

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Drawing the N-Well In this process, the silicon substrate is originally doped with p-type impurities. NMOS transistors can be realized on this p-type substrate simply by creating n-type diffusion areas. For the PMOS transistors however a different approach must be taken: A larger n-type region (n-well) must be created, which acts like a substrate for the PMOS transistors. From the process point of view, the n-well is one of the first structures to be formed on the surface during fabrication. Here we chose to draw the n-well after almost everything else is finished. Note that the drawing sequence of different layers in a mask layout is completely arbitrary, it does not have to follow the actual fabrication sequence. 1. Select the nwell layer from the LSW

2. Draw a large n-well rectangle extending over the P-Diffusion

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The n-well must extend over the PMOS active area by a large margin, at least 1.8u (6 lambda) Connecting both transistors Placing the PMOS and NMOS transistors In this example, we did not pay much attention to the location of the transistors while building them. As long as the design rules are not violated, the transistors can be placed in any arbitrary arrangement. Yet based on our original signal flow diagram, it is more desirable to place the PMOS transistor directly on top of the NMOS transitor- for a more compact layout. 1. Select the PMOS transistor First make sure that you are in selection mode. If you are in any other mode (like rectangle drawing mode) exit the mode by pressing "ESC". Now using the mouse, click and drag a box that covers your PMOS. If you were successful, all the objects within the PMOS would be highlighted as in the figure below:

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2. From the menu Edit select the option Move ( Edit --> Move )

A window will pop-up similar to the copy window. This time we will have to change the Snap Mode option to Anyangle so that we can move the transistor freely.

3. Pick the reference point We will be asked to find a reference point for the object to be moved. The cursor will practically grab the object from that reference point. Since we want an accurate placement, it is advisable to select a point for which alignment is simpler. The corner between the diffusion and the poly is a good place to grab the PMOS. After we have picked the reference point, the outline of the shape will appear attached to the cursor and we will be able to move the shape around. Since the minimum distance from diffusion to the n-well edge is 1.8u, the PMOS and NMOS have to be at least 3.6u apart. We can place a ruler to help us aligning the two shapes and to measure the distance.

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4. Place the transistor You can drop the selected object (in this case consisting of the n-well, the p-active, poly and contacts) into its final location by clicking once on the left mouse button.

Connecting the Output 1. Draw a Metal-1 rectangle between NMOS and PMOS drain region contacts Note that the minimum Metal-1 width is 0.9u (3 lambda), thus narrower than the Metal-1 covering the contacts. Also note that the transistors are completely symmetric, the source and drain regions are interchangeable.

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Connecting the Input The next step will be to connect the gates of both transistors, which will form the input. To do this, we could use the rectangle command again, but this time we will use a different command, the path command. Throughout this tutorial, you will see that you typically have multiple options, commands or procedures available to create the same features in the layout. Please become familiar with as many of such options as possible. 1. Select poly layer from the LSW

2. From the Create menu select Path ( Create --> Path )

The path options box will pop up:

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Cadence Tutorial [Analog Design flow] In the path mode you can draw lines (or paths) with the selected layer. The width of the drawn line can be adjusted, the default is the minimum width of the selected layer. 3. Start path To start the path, click on the middle of the PMOS poly extension. You'll see a ghost line appear. Move this ghost line to the NMOS poly extension.

4. Double click to finish path A single click will finish a line segment and let you continue drawing, a double click will finish the path.

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Cadence Tutorial [Analog Design flow] Making a Metal-1 connection for the Input We have already decided in our signal flow graph that we want the input in Metal-1. Therefore we have to make a connection from the poly layer to the Metal-1 layer. This connection can be done manually by drawing a poly contact layer between Metal-1 and poly, but we will use the path command to automatically add the contacts. 1. Starting from the poly line connecting the gates, start drawing a horizontal poly path 2. On the Path Options dialog box, click on Change To Layer and switch to Metal1

This will automatically add a contact to the end of the current path, note that this will still be a ghost line. You can place the contact at a certain location by clicking once, thereafter the path will continue using the new layer.

3. Finish the path You can finish the path by double clicking. Note that you will not be able to see the contact between the metal and poly layers, there will be a red square instead. This is called an instance. An instance is practically a finished layout that is included completely in your circuit. Since it is a complete layout, it is not possible to edit that layout from within your cell, it is said to be on a lower level of hierarchy.

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By default, only the current layer of hierarchy is visible. Objects that you include as instances will be shown as boxes corresponding to their size. You can press SHIFT-F to see all levels of hierarchy. CTRL-F will return you to viewing only a single layer of hierarchy. Power Rails Now that our transistors are placed and connected, we will have to add Power and Ground rails. Usually a layout consists of a large number of cells, all of which need power and ground connections. Therefore it is common to design cells such that they will have one continuous, wide power and ground connection when placed side by side. Our Signal Flow Graph suggests horizontal power and ground lines in Metal-1. 1. Draw the Power Rail in Metal-1 above the PMOS

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Make sure to connect the Power Rail and the Ground rail to the source contact of the PMOS and to that of NMOS, respectively. P-Substrate Contact The substrate on which the transistors are built must be properly biased. The way to do this is to add substrate contacts. The NMOS transistors are build on a p-type substrate, we will have to create a p-type substrate contact. 1. Draw a P-select square next to the NMOS transistor. Since the contact will be made to p-substrate, the contact area will have to be p-type.

2. Draw a P-active square inside the P-select area.

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Cadence Tutorial [Analog Design flow] This will define the active area of the substrate contact. Make sure that you are not violating any design rules associated with active area spacing.

3. Draw the active contact square inside the p-type active area.

4. Make a metal connection to ground, covering the entire substrate contact.

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Note that the susbtrate contact can also be created and placed as an instance, instead of drawing every item seperately. this alternative approach will be demonstrated in the next step, for the n-well contact. N-Substrate Contact The PMOS transistor was placed within the n-well, this well also has to be biased with the VDD potential. This will be done with an n-type substrate contact. We can follow the same steps that we did for the p substrate contact, but we will try to introduce another method. Almost all of the interlayer connections are already available as instances in your design library. We used the metal-poly contact instance while connecting the input. Similar instances also exist for the substrate connections. 1. From the menu Create select option Instance ( Create --> Instance )

This will pop-up the instance options menu.

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You'll have to provide a cell name and library here. It may be the case that you already know the cell name and cell view, but in this case it is better to Browse in your library to find the appropriate cell. This is essentially the same library browser that you access when you start Cadence Design Tools. It lets you choose the library, cell and cell view, your selection will be transferred to the Instance options menu.

The N-substrate contact is named NTAP, and only has a symbolic view. 2. Move the instance to the desired location. Once you have selected the instance, the cursor will show a ghost image representing the instance, and you'll be able to move the instance to the desired location:

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3. Place the instance. Once satisfied, you can click to place the instance. You'll remain in the instance mode after you have placed the instance, press "ESC" to go back to selection mode again. Note that in this example, the n-well contact has been placed right on top of the n-well boundary, which will obviously generate a rule violation. The n-well is simply not wide enough to accommodate both the PMOS transistor and the contact. This will have to be dealt with in the next step.

4. Make the power connection. The instance will not automatically connect itself to the power supply rail. This connection has to be made by either a Metal-1 rectangle or path.

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Enclosing the substrate contact In the previous step we tried to place the n-type substrate contact in the n-well. Since we had drawn the n-well to cover the P-diffusion at minimum length, the well is not wide enough to accommodate the additional contact. We must enlarge the n-well, so that it also covers the substrate contact. One way to do this would be to simply draw an adjoining rectangle using the n-well layer. Instead, we will try to modify the existing rectangle, so that it covers the contact. 1. Press F4 on the keyboard to toggle selection mode. By default, the selection mode will only select whole objects. Pressing "F4" will change this default to partial selection. The information bar will start displaying "(P) Select" (P for partial) instead of "(F) Select" (F for Full). 2. Move cursor over the left edge of the n-well. You'll notice that as soon as the cursor is close to the edge, only the edge line will be highlighted as a pale dashed line.

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3. Click once to select the edge. 4. Move mouse over the selected edge (without pressing any mouse buttons). You'll notice that the cursor changes shape when you are close to the edge. 5. Press and hold left mouse button when cursor changes above the selected edge. You have grabbed the edge, and as long as you do not release the mouse button you can "stretch" the edge. Move the edge of the n-well so that all the of the substrate contact is covered by n-well.

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Cadence Tutorial [Analog Design flow] DRC and Finalizing Design Rule Checking The layout must be drawn according to strict design rules. After you have finished your design, an automatic program will check each and every feature in your design against these design rules and report violations. This process is called Design Rule Checking. Our design is finished; we must now perform a Design rule Check to see if we have any errors. 1. From the menu Verify select option DRC ( Check --> DRC )

This will pop-up the DRC options dialog box.

2. Start DRC The default options for the DRC are adequate for most situations. DRC results and progress will be displayed in the CIW.

You'll have to check the results from the CIW. In this example we have two poly-to-poly contact spacing errors. You can also see that the rule number for this is 5.5, and the spacing is supposed to be at least 1.5um 38 | P a g e

Cadence Tutorial [Analog Design flow] The errors are also highlighted on the layout.

As it is mostly the case, one misplacement will cause multiple DRC errors. The error can be corrected by moving the contact further to the left.

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After moving the contact to the left, we will have to perform another DRC.

This is a successful DRC. Final Layout This is the completed layout of the CMOS inverter. Congratulations.

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Automatic Layout Generation Tools

Example: Automatic Layout Generation Tools (Device Level Placer)
In this tutorial an alternative way of drawing layouts will be introduced. This tutorial assumes that the reader is familiar with the Virtuoso layout tool and has followed the layout manual.

Since the manual creation of the physical layout is labour intensive, significant amount of work has been put into the automation of the physical layout design process. The device level placer is one of the lower-level answers. The device level placer, will read in a schematic and place all the transistors and I/O pins in the layout window. This tool will use parametric instances that will generate appropriately sized transistors. Although the device level placer and similar contemporary tools provide some nice features, the quality of the layouts they produce are still far from hand optimized layouts. Steps of Automatic Layout Generation Step 1 : Starting the Automatic Layout Tool Step 2 : Placing the Components Step 3 : Making Connections Step 4 : Finishing Touches Step 1 : Starting the Automatic Layout Tool To start the automatic layout generation, you must have finished your circuit schematic first. Please follow the Schematic Tutorial Example first if you have not done so. 1. Open the schematic view of your design.

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In this example, the PMOS transistor has a channel width of W=4.5u and a channel length of L=0.6u, while the NMOS transistor has a channel width of W=3u and a channel length of L=0.6u. 2. From the menu select Tools --> Design Synthesis --> Device-Level Editor.

Selecting this option will first open up a small dialog box that will let the user select the cell name for the layout. It is a good idea to use the same cell name and specify layout as the cell view name.

Upon the selection of the view name, the user will be prompted another small dialog box. This box will ask for a pin layer, pins in the layout will be placed as connections in the given layer. Choose Metal-1 as the I/O Pin Layer, and all of the pins that you have specified in your schematic will be placed as connections in Metal-1.

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Cadence Tutorial [Analog Design flow] In addition to the already open schematic window, a new layout window and the layer selection window will pop up. These three windows define the working environment for the automatic layout generation flow.

After the I/O pin layer is selected, two rectangles representing the transistors (the nmos and the pmos) and two Metal-1 squares will show up in the bottom half of the layout window. Notice the cyan colored square on the upper half of the layout window: This is the estimated size of the layout, this size is not mandatory, it is calculated roughly from the sizes of the active elements. With the next step, you'll start forming the layout within the box above. Step 2 : Placing the Components The default behavior of the layout editor is to show only the current hierarchy. You can press shift-f to display all the hierarchy levels, this way you'll be able to see actual transistors instead of the red instance rectangles. The first step is to place all the components within the design area. 1. Select the PMOS transistor by clicking once.

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2. Move the selected transistor by dragging it with the mouse.

Note that in addition to the ghost image of the selected object, lines to other objects will show up. These lines represent the connections of the selected (and dragged) object to other objects of the design. In this example the poly of the PMOS transistor will be shown connected to the poly of the NMOS transistor and the input, and the drain region of the transistor will be shown connected to the output and the drain region of the NMOS. 3. Release the mouse button to place the selected transistor.

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4. Move the remaining objects the same way

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Note that the automatic layout tool looks almost identical to the Virtuoso layout editor. All of the commands that were available in the manual layout tool are available in this tool too. You can use rulers to pinpoint the exact location of the devices.

The I/O pins correspond to the pins drawn in the schematic. Although they just look like an ordinary Metal-1 patch they contain information about the name, type and direction of the connection.

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As the last step, move and place the output pin too. 5. Final placement

Your final working environment should look more or less like this. Note that this placement is not obligatory, you can choose to place the transistors and the I/O pins any way you desire. Step 3 : Making Connections In the previous step we have placed the components, the next step is to make the connections between individual objects. We will be using the same methods that we used during manually drawing a layout here. The automatic layout tool has an additional menu which provides some useful options to faciliate signal connections. 1. From the menu DLE select option Probe.

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Cadence Tutorial [Analog Design flow] The probe option will display a small dialog box:

Now you can go and select connections (nets) devices, and terminals in either layout or the schematic window and the corresponding object will be highlighted in the other window. This is called cross-probing.

As an example try clicking and selecting the wire connecting the drains of both transistors to the output pin, notice that two drain regions as well as the output I/O pin in the layout window will be highlighted. 2. Connect the drain regions with Metal-1 using the path command.

Notice that the new connection will also be highlighted as it is drawn.

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Connect the gates of both transistors using a poly path and connect this path to the input. Step 4 : Finishing Touches At this point the design is almost finished. Unfortunately the automatic design creation process for this fabrication technology is unable to add substrate connections. So these will have to be added by the user. 1. Using the Create --> Instance command select a PTAP substrate contact.

Place the instance close to the bottom of the NMOS transistor, close to the source region (which has not been connected to a ground rail yet).

2. Using the Create --> Instance command select a NTAP substrate contact.

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Cadence Tutorial [Analog Design flow] This contact will be used as the n-well contact.

As in the previous manual layout example, the N-Substrate contact will not fit in a n-well that is drawn according to the minimum distance rules from the transistor. Since the transistor is an instance, it is not possible to stretch the n-well edge as it has been done in the layout example.

To address this problem, we can easily draw an extension to the already existing n-well using the rectangle command. The next step is to draw the ground rail and the power rail. 3. Using the Rectangle command draw the ground rail with Metal-1.

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Make sure to connect the NMOS source and the substrate contact to the ground rail you have just drawn. 4. Draw the power rail with Metal-1. Notice that the power rail and the ground rail are symmetric. So instead of redrawing the power rail you can copy the ground rail.

To select multiple objects press "SHIFT" key while selecting objects. When you are done, use Edit --> Copy command to copy the selected image. You can flip the selected image upsidedown by clicking the "upsidedown" button on the copy dialog box.

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5. Place the pins. The next step is to give connection information to the power rails and ground rails. To do this, first select the Metal-1 layer from the layer selection window and then use the Create --> Pin command.

This will pop-up a dialog box to allow you enter various parameters of the pin.

For the power rail enter the name: "vdd!" (without quotes, watch case and the exclamation mark). The exclamation mark is important, it defines a global signal, that is a signal name that is unique across your entire design.

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Define a rectangle with the Metal-1 layer on the power rail, as the pin location. The location of the pin and the size are not relevant (at least not in this context), as a good practice try to make it a minimum sized box (0.9u x 0.9u) and make sure it is on the power rail. Place a pin on the ground rail in a similar way. Use the name "gnd!" (without the quotes, watch for the case and exclamation mark) for the pin name.

Place the pin:

This is the final layout, created by the automatic device level editor.

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