IEEE 2008 Custom Intergrated Circuits Conference (CICC)

Voltage References for Ultra-Low Supply Voltages

P. Kinget, C. Vezyrtzis, E. Chiang, B. Hung* and T.L. Li*
Dept. of Electrical Engineering Columbia University New York, NY 10027, USA * United Microelectronics, Taiwan, R.O.C.
AbstractThe majority of integrated voltage references have, so far, been limited to a minimum supply voltage above 0.7-V often due to the voltage headroom required for the forward-biased operation of a PN-junction. This paper reviews design techniques for low voltage reference design and explores the feasibility of designing a voltage reference with a supply voltage below 0.7-V in a standard CMOS process. Two ultra-low-voltage solutions are explored in detail, a reference circuit based on CMOS compatible Schottky diodes and a MOS-only reference circuit.

I. INTRODUCTION Voltage references are indispensible building blocks of many analog and mixed-signal system-on-a-chip integrated circuits. They provide references for on-chip power management blocks, for signal conditioning and signal measurement, or for building blocks such as ADCs and DACs and further make possible the appropriate biasing of analog circuits so that they become much less unaffected by process, temperature and voltage (PVT) variations. Parts of reference circuits can further often be configured to serve as on-chip die temperature monitors, e.g. on large digital microprocessors. The continued scaling of transistor dimensions in CMOS technologies in combination with the need to reduce power density in large digital ICs is driving down the supply voltage for nanoscale CMOS technologies. Supply voltages well below 1V and even down to 0.5V for low power applications are projected in the ITRS roadmap [1]. The most energy efficient operation of digital circuits and systems occurs in the supply voltage range of 0.3V to 0.5V in deeply scaled technologies [2][3]. Other applications such as self-powered sensor nodes to enable ambient intelligence also require ultralow voltage mixed-signal ICs [4]. Recent research has demonstrated the feasibility of designing analog and RF circuits that can operate with ultra-low supply voltages down to 0.5V; this includes basic building blocks, analog filters, analogto-digital converters, and even fully integrated RF receivers (see [5] and its references). In this paper, the realization of voltage references operating down to 0.5V is investigated. The widely used bandgap voltage reference [6] configurations with PN diodes cannot be operated with such low supply voltages [7]. We explore several alternatives that are available in any standard CMOS technology for the design of a voltage reference. They resemble the technique used in standard bandgap designs to create a temperature independent quantity, namely the addition of two quantities, one of which experiences a positive temperature dependence and the other a negative, which results in a temperature independent reference.

II. SUPPLY VOLTAGE REQUIREMENTS FOR CMOS VOLTAGE REFERENCE S The bandgap voltage reference [6] has been the most established on-chip voltage reference circuit for many years. It uses the complementary-to-absolute-temperature (CTAT) characteristic of the forward voltage drop across a PN junction and linearly combines it with the proportional-to-absolutetemperature (PTAT) characteristic of the voltage difference between two PN junctions with equal currents, but different current densities, to obtain a temperature independent output voltage. When these voltages are combined for a zero temperature coefficient, the resulting output reference voltage is around 1.205V, which is the bandgap voltage for Silicon. In bipolar ICs the PN junctions are typically formed using bipolar transistors. In CMOS processes, parasitic vertical bipolar PNP devices are generally used. These reference circuits typically require a supply voltage larger that 1.4V to properly function (see e.g., [7]). Instead of linearly summing voltage drops, a CTAT current, derived using a forward-biased PN junction, and a PTAT current can be linearly combined, and converted back into a temperature-independent output voltage with arbitrary value using the circuit topology presented in [8]. This topology has a minimum supply voltage equal to the PN-diode turn on voltage (about 0.7V) plus a saturation voltage across a current source (about 0.2V) and can thus be operated below 1V, down to about 0.85V or 0.9V [9][10][11]. CMOS-only voltage references can operate with lower supply voltages and are not bound by the limitations due to the PN diode turn on voltage. Most designs exploit the negative temperature dependence of the threshold voltage of MOS devices (see e.g. [12]) and combine it with a PTAT characteristic which can be obtained with MOS devices in weak inversion; high performance references operating down to 0.85V VDD have been demonstrated [13]. Using enhancement and depletion mode devices in a fully depleted MOS/SIMOX process, a reference operating from a supply down to 0.6V was demonstrated in [14]. However, such design is not compatible with standard digital CMOS technologies. Specialized techniques for the realization of high precision reference voltages include floating-gate designs [15]; they require special devices and each reference needs to be programmed after fabrication. Additionally, increasing gate leakage effects make such structures less compatible with deeply-scaled CMOS processes.

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In this paper we first explore the replacement of the PN diode in a low voltage bandgap structure with a standardCMOS-compatible Schottky diode in Section III. We then investigate in Section IV the use of the CTAT characteristic of the forward drop across a diode-connected nMOS device with its body shorted to its gate, and thus with a forward-biased body-source junction and reduced threshold voltage VT. For both designs a proof-of-principle IC prototype is presented with experimental data. Section V compares the results of various low voltage approaches.

diode I-V relationship or the IC-VBE dependence for a bipolar transistor. The difference of the forward voltage of two Schottky diodes operated with identical currents but different current densities can be used to generate a PTAT voltage. The dependence of the forward voltage drop to temperature for a fixed or temperature dependent current, is also very similar to the results obtained for a PN diode. (Note that the R* term is only very weakly temperature dependent.) For the Schottky diode, the extrapolated forward voltage at zero Kelvin is equal to the Schottky barrier !B. It depends on the work function of the metal and semiconductor used and is typically in the order of 0.2 to 0.6V. These properties make the Schottky diode an excellent replacement for the traditional PN-junction diode for voltage references operating with ultra-low supply voltages. Although Schottky diodes can be readily designed in standard CMOS processes, they are typically not included in the standard designkit or simulation models. For the purpose of demonstrating an ultra-low VDD reference, we characterized a number of diode test structures provided by the foundry. We further built a custom verilog-A based model to incorporate the diodes in the circuit design flow. I-V characteristics were measured over temperature to extract the temperature coefficient.

(a)

(b)
Figure 1 Layout (a) of 4 Schottky diode unit cells; (b) cross-section of a Schottky diode-unit in a standard CMOS process

III. SCHOTTKY DIODES AND THEIR USE IN A VOLTAGE REFERENCE A. CMOS-Compatible Schottky Diodes Schottky diodes can be realized in a standard CMOS process, by directly contacting an N-WELL region without an N+ implant. Figure 1 shows the layout and a cross section of the Schottky diodes laid out in a standard 90nm CMOS technology from UMC. In modern CMOS processes silicides are used at the Silicon-Metal interface and the Schottky barrier diode is formed where the silicide contacting the metal is in contact with the N-WELL; the N-WELL is then contacted with an ohmic contact. The metal is the diode anode and the well is the cathode. The current through the diode, ID, is determined by thermionic emission across the barrier:

Figure 2

Measured I-V characteristics for various temperatures of a 32 unit Schottky diode with the layout of Fig. 1.

* $ "# B '- * $ VD ' I D = , AR *T 2 exp& )/ 0, exp& ) " 1/ % nkT / q (. + % nkT / q ( . +

(1)

where VD is the voltage across the diode, kT/q is the thermal voltage, n is the diode ideality factor and is close to 1; !B is the Schottky barrier height, A is the area of the diode, T is the absolute temperature and R* is the effective Richardson constant [16]. This I-V dependence is very similar to the PN-

Figure 2 shows the measured I-V characteristics for various temperatures for a 32-unit diode test structure. The turn-on voltage of the Schottky diode is between 0.2 and 0.3V, which is significantly lower that the 0.6 to 0.7V typically needed to turn on a PN junction diode. The forward voltage across the Schottky diode had a measured temperature coefficient of -0.4mV/oC (from 10 to 100oC). The I-V characteristics also show a parasitic resistance in series with the diode, which is caused by the series resistance due to the NWELL used to contact the structure. A parasitic resistance of approximately 100 Ohms/unit-diode was extracted from the I-V characteristics.

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Figure 3

Schematic of the Schottky-diode-based reference.

B. Voltage Reference Using Schottky Diodes Schottky diodes have been used in the design of voltage reference operating from a 2.5-V supply voltage in [17]. Here, we demonstrate that they enable the realization of ultra-low VDD references when used in the current-summing based bandgap topology from [8]. The schematic of the designed reference is shown in Figure 3. The reference circuit consists of two almost identical branches; one branch contains a single Schottky diode unit and the other branch has N diode units in parallel (N=6 in this design). An operational transconductance amplifier (OTA) is used to force the voltages across resistors R2a and R2b to be equal, with a nominal value of 250mV, which drops with a rate of 0.4mV/oC for increasing temperature. The difference of the forward-bias voltage of the diodes is dropped across resistor R1, creating the PTAT current, while the current through R2a and R2b is a CTAT current. The nominal value of the voltage across the resistor R1 increases with a rate of 0.22mV/oC. Resistors R1 and R2a (which is equal to R2b) are sized as 1k! and 2.13k! respectively, in order to obtain a zero temperature dependence. The sum of the PTAT and CTAT current is mirrored into resistor R3 to create the reference voltage. Devices Ms1-Ms2 and Ps1 form a startup circuit, which ensures that the circuit can not stay in the zero-current state. An ultra-low voltage OTA is required in this circuit and was designed as a two stage Miller compensated amplifier. Its schematic is included in Figure 3. It employs a differential input pair, consisting of transistors M1 and M2, operating in weak inversion so that sufficient headroom remains available for the current source M4 while the input common mode level is about 250mV. The amplifier is self-biased from the supply (using the resistor Rb and transistor M3) and consumes 100uA of current, providing a DC gain of 40dB.

Figure 4

Die Microphotograph (right) and corresponding layouts (left) of the Schottky and MOS-only reference circuits.

C. Experimental Results The layout and die photograph of the experimental prototype in a standard 90nm CMOS technology is shown in Figure 4. The circuit is very compact and occupies only 0.019um2. The circuit samples were measured using wafer probing. Figure 5 shows the measured reference output voltage w.r.t. the supply voltage VDD; the reference is functional with supply voltages down to 0.5V. For the nominal VDD of 0.6V the supply sensitivity is 3mV/100mV.

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Figure 7

Schematic of the MOS-only reference .

Measurements over temperature, plotted in Figure 6, show that the output voltage reference ranges from 250mV to 256mV when measured from 10 to 100oC with a supply voltage VDD of 0.6V, which results in an effective temperature coefficient of 0.07mV/oC or 263ppm/oC. At the same VDD, the reference voltage range was 251 4mV for 18 samples. No trimming was performed for any of the measurements. The performance of the reference circuit for supply voltages of 0.55V, 0.6V and 0.65V is summarized in Table 1. This proofof-principle circuit consumes 375uW at room temperature. For this design, limited diode data and models were available restricting the choice of bias points. As more characterization data and better device models become available to the designers, significant power savings can be expected. Also the power consumption of the OTA can be significantly reduced.
Figure 5 Measured Schottky reference supply voltage dependence

IV. VOLTAGE REFERENCE UTILIZING ONLY MOS DEVICES Several MOS-only references have been demonstrated operating below 1V down to 0.85V [12][13]. They typically rely on the negative temperature coefficient of the threshold voltage to obtain a CTAT characteristic and use the gate-source voltage difference of weakly inverted MOS devices with different current densities for the PTAT characteristic [18]. To obtain low voltage operation, threshold reduction techniques such as forward body biasing is often applied. E.g. in [13] the body of a weakly inverted PMOS transistor is connected to the gate and used as the basis for a high precision, 0.85-V VDD reference. Next we explore an ultra-low voltage, MOS-only design with an NMOS device with a forward-biased bodysource connection using the commonly available deep n-well implants used in standard CMOS technologies.. Note that ultra-low supply voltages (<0.7V), the risk of latchup due to forward biasing is generally not present. A. CMOS PTAT The replacement of the PTAT cell in the voltage reference can be achieved by replacing the PN diodes with MOS devices operating in the weak inversion region, exploring the I-VGS

Figure 6

Measured Schottky reference temperature dependence between 10 and 100oC while operating from different supply voltages.

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characteristic behavior of weak inversion operation. In this design we used the topology shown in Figure 8 (b) [19] which greatly reduces the effect of OTA offset voltages compared to the conventional topology (Figure 8 (b)). The PTAT voltage is created as the difference between the VGS voltages of transistors M1 and M2, creating a PTAT current of nominal value 150uA in this design. M1 and M2 are deep-n-well devices with source and body shorted. This circuit is incorporated in the MOS-only reference shown in Figure 7.

Figure 9

Measured reference voltage VREF w.r.t. supply voltage VDD

Figure 8 The conventional circuit (a) to create a PTAT voltage across resistor R with weakly inverted MOS devices is more sensitive than the circuit in (b) .

B. CMOS Ultra-Low Voltage CTAT The CTAT part of the reference in Figure 7 is created as the drain-to-source voltage of an NMOS device, M7, operating in the weak inversion region, whose gate and body are tied to the drain. The body-source junction is forward biased effectively lowering the threshold voltage of the device. This configuration is called a dynamic-threshold MOS in [13]. Due to the CTAT dependence of the threshold voltage, the VGS has a CTAT characteristic when the device is biased in weak inversion with a PTAT current. The temperature coefficient of this CTAT voltage will increase with increasing current through the device, as well as with an increased body effect coefficient and transistor W/L ratio. C. CMOS-only Ultra-Low VDD Reference The complete schematic of the designed voltage reference is presented in Figure 7. The PTAT current, generated by devices M1 and M2 and resistors R1 and R2, is mirrored to resistor R5 and transistor M7, which create the PTAT and CTAT parts of the voltage reference respectively. Transistors M3-M6, along with M8-M10 and P1-P2, form a low-voltage cascade current mirror, to accurately copy the PTAT current. Transistors M11-M12 form the startup circuit of the reference, ensuring that the transistors M1 and M2 do not operate in zerocurrent state. Capacitor CC is used for compensation. In this proof-of-principle design, the same OTAs as for the Schottky reference (Figure 3) have been reused. D. Experimental Results A circuit prototype was realized in a standard 90nm CMOS technology. The layout and die photo are shown in Figure 4; the circuit occupies only 0.07um2.

Measurements of the MOS-only reference circuit showed its functionality for supply voltages as low as 0.5V. The reference voltage supply dependence is shown in Figure 9. The reference voltages temperature dependence, shown in Figure 10, is from 241.5 to 245mV when measured from 5 to 100oC, which corresponds toan effective temperature coefficient of 0.04mV/oC or 160ppm/oC, at a VDD of 0.6-V. The nominal output voltage is 256 4mV for 16 measured samples. No trimming was performed on any of the circuits. The total consumed power of this proof-of-principle prototype was 547uW at room temperature.

Figure 10 MOS-only reference temperature dependence

V. DISCUSSION AND CONCLUSIONS Table 1 reviews the different performance characteristics of sub-1V reference circuits, both bandgap based as well as MOS-only based designs. As outlined in the paper several design techniques exist to design references that can operate with a supply voltage significantly below the Si bandgap voltage. In this paper we presented two solutions to further reduce the supply voltage for reference circuits to well below 0.7V and demonstrate functionality down to 0.5V. Lower reference voltage designs intrinsically have a poorer relative temperature dependence performance (in ppm/oC) than higher reference voltage designs. Still, at this point the performance of the (untrimmed) ultra-low voltage designs cannot match the performance of designs based on more

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established design techniques and well characterized and modeled components. Schottky diodes offer a promising alternative to design ultra-low voltage references. An attractive feature of a Schottky based reference is that the reference voltage can be traced back to a physical parameters, the Schottky barrier, which is primarily dependent on material properties. MOS-only reference designs also offer interesting opportunities, in particular in combination with forward body biasing. Although MOS based designs are often more prone to process variations, experimental data in [13] suggests a better matching behavior for such MOS configuration which can be safely used in an ultra-low voltage context. The performance of ultra-low voltage references can be expected to significantly improve as more reliable circuit models and device characterization data becomes available to the designer, and as design techniques are further developed and mature driven by the growing need for ultra-low voltage system-on-a-chip ICs. VI. ACKNOWLEDGMENTS The authors thank United Microelectronic Corp. (UMC) for chip fabrication and Y. Baeyens and Y.K. Chen of Bell Laboratories for temperature-sweep measurement support. VII. REFERENCES
[1] [2] [3] [4] The International Technology Roadmap for Semiconductors (2006 edition), ITRS, 2006, (Online), http://public.itrs.net. B. Calhoun, A. Wang, and A. Chandrakasan, Modeling and sizing for minimum energy operation in subthreshold circuits, IEEE J. of SolidState Circuits, Vol. 40, no. 9, pp. 1778 1786, Sept. 2005. S. Hanson et al., Ultralow-voltage minimum-energy CMOS, IBM Journal of Research and Development, vol. 50, no. 4/5, pp. 469-489, July/Sept. 2006. J. Rabaey et al., "Ultra-low-power design, the roadmap to disappearing electronics and ambient intelligence," IEEE Circuits and Devices Magazine, vol.22, no.4, pp. 23-29, July-Aug. 2006

[5] [6] [7]

[8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]

P. Kinget, "Designing analog and RF circuits for ultra-low supply voltages," Proceedings of the 33rd European Solid State Circuits Conference (ESSCIRC), pp.58-67, Sept. 2007. R.J. Widlar, New Developments in IC Voltage Regulators, IEEE J. of Solid-State Circuits, vol. SC-16, pp. 2-7, Feb. 1971. P. K. T. Mok and K. N. Leung, Design considerations of recent advanced low-voltage low-temperature-coefcient CMOS bandgap voltage reference, in Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 635-642, 3-6 Oct. 2004. H. Banba et al. A CMOS Bandgap Reference Circuit with Sub-1V Operation, IEEE J. Solid-State Circuits, vol. 34, pp. 670-674, May 1999. K.N. Leung et al., A Sub-1-V 15-ppm/oC Bandgap Voltage Reference Without Requiring Low Threshold Voltage Device, IEEE J. Solid-State Circuits, vol. 37, pp. 526-530, April 2002. A. Boni, Op-Amps and Startup Circuits for CMOS Bandgap Referecnces With Near 1-V Supply, IEEE J. Solid-State Circuits, vol. 37, pp. 1339-1342, October 2002. J. Doyle et al., A CMOS Subbandgap Reference Circuit with 1-V Power Supply Voltage, IEEE J. of Solid-State Circuits, vol. 39, no. 1, pp. 252-255, Jan. 2004 G. Giustolisi et. al., A Low-Voltage Low-Power Voltage Reference Based on Subthreshold MOSFETs, IEEE J. Solid-State Circuits, vol. 38, pp. 151-154, Jan. 2003. A. Annema, "Low-power bandgap references featuring DTMOSTs," IEEE J. of Solid-State Circuits, vol. 34, no. 7, pp. 949-955, Jul 1999. M. Ugajin et. al., A 0.6-V voltage reference circuit based on "-VTH architecture in CMOS/SIMOX, Symp. VLSI Circuits Dig., pp. 141 142, June 2001. B. K. Ahuja et al., A 0.5uA Precision CMOS Floating-Gate Analog Reference, IEEE International Solid State Circuits Conference, 2005, pp. 286-288. K. N. Ng, Complete Guide to Semiconductor Devices, McGraw Hill, Inc. 1995. D. Butler et. Al., Low-Voltage Bandgap Reference Utilizing Schottky Diodes, Midwest Symposium on Circuits and Systems, vol. 2, pp. 17941797, Aug. 2005. Y. Tsividis, R. Ulmer, A CMOS voltage reference," IEEE J. of SolidState Circuits, vol.13, no.6, pp. 774-778, Dec 1978. F. Serra-Graels, J. L. Huertas, Sub-1V CMOS Proportional-to-Absolute Temperature References, IEEE J. of Solid-State Circuits, vol. 38, no. 1, Jan. 2003

TABLE I.

PERFORMANCE COMPARISON FOR SUB-1V VDD VOLTAGE REFERENCES

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