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pll.m in PLL.rar
Several phase-locked loop simulation program- communication technologies- do not...Original Link
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function pll % STUDYING THE PHASE LOCKED LOOP (PLL) CHARACHTERISTICS % Step response of 1st order closed loop transmittance of pll kv = 1; kd = 1; dt = .01; t = 0 : dt : 2; step = ones(1,length(t)); clt_1 = tf([2*pi*kv*kd],[1 2*pi*kv*kd]); [out_1 t] = lsim(clt_1,step,t); figure subplot(3,1,1) plot(out_1); xlabel('Time in seconds') ylabel('Amplitude') TITLE ('Step Response of 1st Order Transmittance of PLL') grid on; % Step response of 1st order closed loop error transmittance of pll clt_e1 = tf([1 0],[1 2*pi*kv*kd]); [out_e1 t] = lsim(clt_e1,step,t); subplot(3,1,2) plot(out_e1) xlabel('Time in seconds') ylabel('Amplitude') TITLE ('Step Response of 1st Order Error Transmittance of PLL') grid on; % Step response of 1st order transmittance between VCO & Input clt1 = tf([kd 0],[1 2*pi*kv*kd]); [out1 t] = lsim(clt1,step,t); subplot(3,1,3) plot(out1) xlabel('Time in seconds') ylabel('Amplitude') TITLE ('Step Response of 1st Order Transmittance between VCO & Input')

grid on; % Step resonse of 2nd order closed loop transmittance of pll a = 3.15; zeta = sqrt((pi*kv*kd)/(2*a)); wn = sqrt(2*pi*kv*kd*a); clt_2 = tf([2*zeta*wn wn^2],[1 2*zeta*wn wn^2]); [out_2 t] = lsim(clt_2,step,t); figure subplot(3,1,1) plot(out_2) xlabel('Time in seconds') ylabel('Amplitude') TITLE ('Step Response of 2nd Order transmittance of PLL') grid on; % Step response of 2nd order closed loop error transmittance of pll clt_e2 = tf([1 0 0],[1 2*zeta*wn wn^2]); [out_e2 t] = lsim(clt_e2,step,t); subplot(3,1,2) plot(out_e2) xlabel('Time in seconds') ylabel('Amplitude') TITLE ('Step Response of 2nd Order Error Transmittance of PLL') grid on; % Step response of 2nd order transmittance between VCO & Input clt2 = tf([kd kd*a 0],[1 2*pi*kv*kd 2 ... ... ... to be continued. This is a preview. To get the complete source file, please click here to download the whole source code package.

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Name Phasell.m pll.m Experiment2_0.m Experiment2_0.rar Experiment2_1.m Experiment2_2.m lin.m c6_PLLpost.m c6_PLLpre.m c6_PLLsim.m <Phase> <PLL> <pll_simulation> ...

Size 3.24 kB 4.04 kB 530.00 B 440.00 B 2.04 kB 956.00 B 307.00 B 1.46 kB 1.11 kB 1.14 kB 0.00 B 0.00 B 0.00 B

Date 14-06-06 16:24 14-06-06 16:21 10-05-00 18:59 05-07-05 17:49 10-05-00 18:59 10-05-00 19:01 10-05-00 19:01 07-06-06 09:25 07-06-06 09:13 07-06-06 09:03 0 0% 17-11-04 12:16 29-08-01 01:21

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Phasell.m in PLL.rar
Several phase-locked loop simulation program- communication technologies- do not...Original Link
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%The phase locked loop(PLL),adjusts the phase of a local oscillator %w.r.t the incoming modulated signal.In this way,the phase of the %incoming signal is locked and the signal is demodulated.This scheme %is used in PM and FM as well. %We will implement it by using a closed loop system.Control systems %techniques are applied here. %**************************************************************

%STEP RESPONSE OF THE FIRST ORDER CLOSED LOOP TRANSMITTANCE OF PLL %H(S) = 1; %SYSTEM TYPE NUMBER = 1; %THETAo/THETAi (output phase/input phase)

close all kv = 1;

kd = 1; dt = 0.01 t = 0:dt:2 u = ones(1,length(t)) g11 = [tf([2*pi*kv*kd],[1 2*pi*kv*kd])] given in the handout [y11 t] = lsim(g11,u,t) figure plot(t,y11) xlabel('TIME IN SECONDS') ylabel('AMPLITUDE') title('STEP RESPONSE OF 1st ORDER CLOSED LOOP TRANSMITTANCE') %*************************************************************** %its the transfer function

%STEP RESPONSE OF THE FIRST ORDER CLOSED LOOP ERROR TRANSMITTANCE OF PLL %ALL THE OTHER FACTORS H(S) etc ARE SAME HERE %THETAe/THETAi (same interp. as above) g12 = [tf([1 0],[1 2*pi*kv*kd])] handout [y12 t] = lsim(g12,u,t) figure plot(t,y12) xlabel('TIME IN SECONDS') ylabel('AMPLITUDE') title('STEP RESPONSE OF 1st ORDER CLOSED LOOP ERROR TRANSMITTANCE') %**************************************************************** %STEP RESPONSE OF THE FIRST ORDER CLOSED LOOP TRANSMITTANCE OF PLL %BETWEEN VCO AND INPUT SIGNAL PHASE %H(S) = 1; %SYSTEM TYPE NUMBER = 1; %V2/THETAi Kd =1; g13 = [tf([Kd 0],[1 2*pi*kv*kd])] transm ... ... %vco voltage and input signal %error transmittance given in the

... to be continued. This is a preview. To get the complete source file, please click here to download the whole source code package.

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Name Phasell.m pll.m Experiment2_0.m Experiment2_0.rar Experiment2_1.m Experiment2_2.m lin.m c6_PLLpost.m c6_PLLpre.m c6_PLLsim.m

Size 3.24 kB 4.04 kB 530.00 B 440.00 B 2.04 kB 956.00 B 307.00 B 1.46 kB 1.11 kB 1.14 kB

Date 14-06-06 16:24 14-06-06 16:21 10-05-00 18:59 05-07-05 17:49 10-05-00 18:59 10-05-00 19:01 10-05-00 19:01 07-06-06 09:25 07-06-06 09:13 07-06-06 09:03

<Phase> <PLL> <pll_simulation> ...

0.00 B 0.00 B 0.00 B

0 0% 17-11-04 12:16 29-08-01 01:21

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Phasell.m in PLL.rar
Several phase-locked loop simulation program- communication technologies- do not...Original Link
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%The phase locked loop(PLL),adjusts the phase of a local oscillator %w.r.t the incoming modulated signal.In this way,the phase of the %incoming signal is locked and the signal is demodulated.This scheme %is used in PM and FM as well. %We will implement it by using a closed loop system.Control systems %techniques are applied here.

%**************************************************************

%STEP RESPONSE OF THE FIRST ORDER CLOSED LOOP TRANSMITTANCE OF PLL %H(S) = 1; %SYSTEM TYPE NUMBER = 1; %THETAo/THETAi (output phase/input phase)

close all kv = 1; kd = 1; dt = 0.01 t = 0:dt:2 u = ones(1,length(t)) g11 = [tf([2*pi*kv*kd],[1 2*pi*kv*kd])] given in the handout [y11 t] = lsim(g11,u,t) figure plot(t,y11) xlabel('TIME IN SECONDS') ylabel('AMPLITUDE') title('STEP RESPONSE OF 1st ORDER CLOSED LOOP TRANSMITTANCE') %*************************************************************** %its the transfer function

%STEP RESPONSE OF THE FIRST ORDER CLOSED LOOP ERROR TRANSMITTANCE OF PLL %ALL THE OTHER FACTORS H(S) etc ARE SAME HERE %THETAe/THETAi (same interp. as above) g12 = [tf([1 0],[1 2*pi*kv*kd])] handout [y12 t] = lsim(g12,u,t) figure plot(t,y12) xlabel('TIME IN SECONDS') ylabel('AMPLITUDE') title('STEP RESPONSE OF 1st ORDER CLOSED LOOP ERROR TRANSMITTANCE') %**************************************************************** %error transmittance given in the

%STEP RESPONSE OF THE FIRST ORDER CLOSED LOOP TRANSMITTANCE OF PLL %BETWEEN VCO AND INPUT SIGNAL PHASE %H(S) = 1; %SYSTEM TYPE NUMBER = 1; %V2/THETAi Kd =1; g13 = [tf([Kd 0],[1 2*pi*kv*kd])] transm ... ... ... to be continued. This is a preview. To get the complete source file, please click here to download the whole source code package. %vco voltage and input signal

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Size 3.24 kB

Date 14-06-06 16:24

pll.m Experiment2_0.m Experiment2_0.rar Experiment2_1.m Experiment2_2.m lin.m c6_PLLpost.m c6_PLLpre.m c6_PLLsim.m <Phase> <PLL> <pll_simulation> ...

4.04 kB 530.00 B 440.00 B 2.04 kB 956.00 B 307.00 B 1.46 kB 1.11 kB 1.14 kB 0.00 B 0.00 B 0.00 B

14-06-06 16:21 10-05-00 18:59 05-07-05 17:49 10-05-00 18:59 10-05-00 19:01 10-05-00 19:01 07-06-06 09:25 07-06-06 09:13 07-06-06 09:03 0 0% 17-11-04 12:16 29-08-01 01:21

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SimPowerSystems Provide feedback about this page

Static Synchronous Compensator (Phasor Type)

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Implement phasor model of three-phase static synchronous compensator

Library
Flexible AC Transmission Systems (FACTS)/Power-Electronics Based FACTS

Description

The Static Synchronous Compensator (STATCOM) is a shunt device of the Flexible AC Transmission Systems (FACTS) family using power electronics to control power flow and improve transient stability on power grids [1]. The STATCOM regulates voltage at its terminal by controlling the amount of reactive power injected into or absorbed from the power system. When system voltage is low, the STATCOM generates reactive power (STATCOM capacitive). When system voltage is high, it absorbs reactive power (STATCOM inductive).

The variation of reactive power is performed by means of a Voltage-Sourced Converter (VSC) connected on the secondary side of a coupling transformer. The VSC uses forcedcommutated power electronic devices (GTOs, IGBTs or IGCTs) to synthesize a voltage V2 from a DC voltage source. The principle of operation of the STATCOM is explained on the figure below showing the active and reactive power transfer between a source V1 and a source V2. In this figure, V1 represents the system voltage to be controlled and V2 is the voltage generated by the VSC. Operating Principle of the STATCOM

In steady state operation, the voltage V2 generated by the VSC is in phase with V1 (=0), so that only reactive power is flowing (P=0). If V2 is lower than V1, Q is flowing from V1 to V2 (STATCOM is absorbing reactive power). On the reverse, if V2 is higher than V1, Q is flowing from V2 to V1 (STATCOM is generating reactive power). The amount of reactive power is given by

A capacitor connected on the DC side of the VSC acts as a DC voltage source. In steady state the voltage V2 has to be phase shifted slightly behind V1 in order to compensate for transformer and VSC losses and to keep the capacitor charged. Two VSC technologies can be used for the VSC:

VSC using GTO-based square-wave inverters and special interconnection transformers. Typically four three-level inverters are used to build a 48-step voltage waveform. Special interconnection transformers are used to neutralize harmonics contained in the square waves generated by individual inverters. In this type of VSC, the fundamental component of voltage V2 is proportional to the voltage Vdc. Therefore Vdc has to be varied for controlling the reactive power. VSC using IGBT-based PWM inverters. This type of inverter uses Pulse-Width Modulation (PWM) technique to synthesize a sinusoidal waveform from a DC voltage source with a typical chopping frequency of a few kilohertz. Harmonic voltages are cancelled by connecting filters at the AC side of the VSC. This type

of VSC uses a fixed DC voltage Vdc. Voltage V2 is varied by changing the modulation index of the PWM modulator. The STATCOM (Phasor Type) block models an IGBT-based STATCOM (fixed DC voltage). However, as details of the inverter and harmonics are not represented, it can be also used to model a GTO-based STATCOM in transient stability studies. A detailed model of a GTO-based STATCOM is provided in the FACTS demo library (power_statcom_gto48p demo). The figure below shows a single-line diagram of the STATCOM and a simplified block diagram of its control system. Single-line Diagram of a STATCOM and Its Control System Block Diagram

The control system consists of:

A phase-locked loop (PLL) which synchronizes on the positive-sequence component of the three-phase primary voltage V1. The output of the PLL (angle =t) is used to compute the direct-axis and quadrature-axis components of the AC three-phase voltage and currents (labeled as Vd, Vq or Id, Iq on the diagram). Measurement systems measuring the d and q components of AC positivesequence voltage and currents to be controlled as well as the DC voltage Vdc. An outer regulation loop consisting of an AC voltage regulator and a DC voltage regulator. The output of the AC voltage regulator is the reference current Iqref for the current regulator (Iq = current in quadrature with voltage which controls reactive power flow). The output of the DC voltage regulator is the reference current Idref for the current regulator (Id = current in phase with voltage which controls active power flow).

An inner current regulation loop consisting of a current regulator. The current regulator controls the magnitude and phase of the voltage generated by the PWM converter (V2d V2q) from the Idref and Iqref reference currents produced respectively by the DC voltage regulator and the AC voltage regulator (in voltage control mode). The current regulator is assisted by a feed forward type regulator which predicts the V2 voltage output (V2d V2q) from the V1 measurement (V1d V1q) and the transformer leakage reactance.

The STACOM block is a phasor model which does not include detailed representations of the power electronics. You must use it with the phasor simulation method, activated with the Powergui block. It can be used in three-phase power systems together with synchronous generators, motors, dynamic loads and other FACTS and DR systems to perform transient stability studies and observe impact of the STATCOM on electromechanical oscillations and transmission capacity at fundamental frequency.
STATCOM V-I Characteristic

The STATCOM can be operated in two different modes:

In voltage regulation mode (the voltage is regulated within limits as explained below) In var control mode (the STATCOM reactive power output is kept constant)

When the STATCOM is operated in voltage regulation mode, it implements the following V-I characteristic. STATCOM V-I characteristic

As long as the reactive current stays within the minimum and minimum current values (Imax, Imax) imposed by the converter rating, the voltage is regulated at the reference voltage Vref. However, a voltage droop is normally used (usually between 1% and 4% at maximum reactive power output), and the V-I characteristic has the slope indicated in the figure. In the voltage regulation mode, the V-I characteristic is described by the following equation:

where V I Xs Positive sequence voltage (pu) Reactive current (pu/Pnom) (I > 0 indicates an inductive current) Slope or droop reactance (pu/Pnom)

Pnom Three-phase nominal power of the converter specified in the block dialog box
STATCOM vs SVC

The STATCOM performs the same function as the SVC. However at voltages lower than the normal voltage regulation range, the STATCOM can generate more reactive power than the SVC. This is due to the fact that the maximum capacitive power generated by a SVC is proportional to the square of the system voltage (constant susceptance) while the maximum capacitive power generated by a STATCOM decreases linearly with voltage (constant current). This ability to provide more capacitive reactive power during a fault is one important advantage of the STATCOM over the SVC. In addition, the STATCOM will normally exhibits a faster response than the SVC because with the VSC, the STATCOM has no delay associated with the thyristor firing (in the order of 4 ms for a SVC).

Dialog Box and Parameters

The STATCOM parameters are grouped in two categories: Power data and Control parameters. Use the Display listbox to select which group of parameters you want to visualize.

Power Data Parameters

System nominal voltage and frequency [Vrms f]

The nominal line-to-line voltage in Vrms and the nominal system frequency in hertz.
Converter rating Snom

The nominal power of the converter in VA.

Converter impedance [R L]

The positive-sequence resistance and inductance of the converter, in pu based on the nominal power and voltage ratings. R and L represent the resistance and leakage inductance of the coupling transformer and the resistance and inductance of the series filtering inductors connected at the VSC output.
Converter initial current [Mag Phase]

The initial value of the positive-sequence current phasor (Magnitude in pu and Phase in degrees). If you know the initial value of the current corresponding to the STATCOM operating point you may specify it in order to start simulation in steady state. If you don't know this value, you can leave [0 0]. The system will reach steady-state after a short transient.
DC link nominal voltage

The nominal voltage of the DC link in volts.

DC link total equivalent capacitance

The total capacitance of the DC link in farads. This capacitance value is related to the STATCOM rating and to the DC link nominal voltage. The energy stored in the capacitance (in joules) divided by the STATCOM rating (in VA) is a time duration which is usually a fraction of a cycle at nominal frequency. For example, for the default parameters, (C=375 F, Vdc=40 000 V, Snom=100 MVA) this ratio is 3.0 ms, which represents 0.18 cycle for a 60 Hz frequency. If you change the default values of the nominal power rating and DC voltage, you should change the capacitance value accordingly.

Control Parameters

Mode of operation

Specifies the STATCOM mode of operation. Select either Voltage regulation or Var Control.
External control of reference voltage Vref

If this parameter is checked, a Simulink input named Vref appears on the block, allowing to control the reference voltage from an external signal (in pu). Otherwise a fixed reference voltage is used, as specified by the parameter below.
Reference voltage Vref

This parameter is not visible when the Mode of operation parameter is set to Var Control or when the External control of reference voltage Vref parameter is checked. Reference voltage, in pu, used by the voltage regulator.
Maximum rate of change of reference voltage Vref

This parameter is not visible when the Mode of operation parameter is set to Var Control. Maximum rate of change of the reference voltage, in pu/s, when an external reference voltage is used.
Droop (pu):

This parameter is not visible when the Mode of operation parameter is set to Var Control. Droop reactance, in pu/converter rating Snom, defining the slope of the V-I characteristic.
Vac Regulator Gains: [Kp Ki]

This parameter is not visible when the Mode of operation parameter is set to Var Control. Gains of the AC voltage PI regulator. Specify proportional gain Kp in (pu of I)/(pu of V), and integral gain Ki, in (pu of I)/(pu of V)/s, where V is the AC voltage error and I is the output of the voltage regulator.
Reactive power setpoint Qref

This parameter is not visible when the Mode of operation parameter is set to Voltage Control. Reference reactive power, in pu, when the STATCOM is in Var Control.
Maximum rate of change of reactive power setpoint Qref

This parameter is not visible when the Mode of operation parameter is set to Voltage Control. Maximum rate of change of the reference reactive power, in pu/s.

Vdc Regulator Gains: [Kp Ki]

Gains of the DC voltage PI regulator which controls the voltage across the DC bus capacitor. Specify proportional gain Kp in (pu of I)/Vdc, and integral gain Ki, in (pu of I)/Vdc/s, where Vdc is the DC voltage error and I is the output of the voltage regulator.
Current Regulators Gains: [Kp Ki Kf]

Gains of the inner current regulation loop. Specify proportional gain Kp in (pu of V)/(pu of I), integral gain Ki, in (pu of V)/(pu of I)/s, and feed forward gain Kf in (pu of V)/(pu of I), where V is the output V2d or V2q of the current regulator and I is the Id or Iq current error. For optimal performance, the feed forward gain should be set to the converter reactance (in pu) given by parameter L in the Converter impedance [R L] parameters.

Inputs and Outputs

A B C

The three terminals of the STATCOM.

Trip

Apply a simulink logical signal (0 or 1) to this input. When this input is high the STATCOM is disconnected and its control system is disabled. Use this input to implement a simplified version of the protection system.
Vref

Simulink input of the external reference voltage signal. This input is visible only the External control of reference voltage Vref parameter is checked.
m

Simulink output vector containing 16 STATCOM internal signals. These signals are either voltage and current phasors (complex signals) or control signals. They can be individually accessed by using the Bus Selector block. They are, in order:

Signal 1-3

Signal Group Power Vabc (cmplx)

Signal Names Va_prim (pu) Vb_prim (pu) Vc_prim (pu)

Definition Phasor voltages (phase to ground) Va, Vb, Vc at the STATCOM primary terminals (pu)

4-6

Power Iabc (cmplx) Power Control Control Control Control Control

Ia_prim (pu) Phasor currents Ia, Ib, Ic flowing into the Ib_prim (pu) STATCOM (pu) Ic_prim (pu) Vdc (V) Vm (pu) Vref (pu) Qm (pu) Qref (pu) Id (pu) DC voltage (V) Positive-sequence value of the measured voltage (pu) Reference voltage (pu) STATCOM reactive power. A positive value indicates inductive operation. Reference reactive power (pu) Direct-axis component of current (active current) flowing into STATCOM (pu). A positive value indicates active power flowing into STATCOM. Quadrature-axis component of current (reactive current) flowing into STATCOM (pu). A positive value indicates capacitive operation. Reference value of direct-axis component of current flowing into STATCOM (pu) Reference value of quadrature-axis component of current flowing into STATCOM (pu) The modulation index m of the PWM modulator. A positive number 0<m<1. m=1 corresponds to the maximum voltage V2 which can be generated by the VSC without overmodulation.

7 8 9 10 11 12

13

Control

Iq (pu)

14 15 16

Control Control Control

Idref (pu) Iqref (pu) modindex

Example

See the power_statcom demo which illustrates the steady-state and dynamic performance of a STATCOM regulating voltage on a 500 kV, 60 Hz, system. The demo also compares the performance of the STACOM with an SVC having the same rating.

References
[1] N. G. Hingorani, L. Gyugyi, "Understanding FACTS; Concepts and Technology of Flexible AC Transmission Systems," IEEE Press book, 2000.

See Also
Static Var Compensator (Phasor Type), Unified Power Flow Controller (Phasor Type)
Provide feedback about this page Speed Reducer Static Synchronous Series Compensator (Phasor Type)

1984-2007 The MathWorks, Inc. Terms of Use Patents Trademarks Acknowledgments

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F.A.Q. HOME Forum Faadoo Engineers Zone - For Students in Engineering Colleges Engineering Ebooks Download/ Engineering Lecture Notes Electrical Engineering Ebooks Download/ Electrical Engineering Notes A way to find Kp and Ki using Matlab for PI controller

Top of Form Bottom of Form + Reply to Thread Results 1 to 1 of 1 Thread: A way to find Kp and Ki using Matlab for PI controller Thread Tools Display 28th March 2013 02:05 PM #1 shiv_dream08

Fuchcha FaaDoO Engineer

City Jaipur Join Date Sep 2011 Gender Male Posts 1 Likes Gifted 0 Likes Received 0 Groans Gifted 0 Groans Received 0 A way to find Kp and Ki using Matlab for PI controller Analysis of Poly Phase Boost Converter Using PI Control Algorithms Shiv Shanker Sharma1, Alka Agrawal2 1M.Tech. II Year (Power System) Student Institute of Technology & Managemnet, Bhilwara, Rajasthan, India

2Asst. Professor, Department of Electrical Engineering Institute of Technology & Managemnet, Bhilwara, Rajasthan, India

Abstract This paper explains about the poly-phase boost converter and control algorithm which overcomes the problem of high ripple current in the tank capacitor. For the improvement of the functionality of the boost converter there are many methods available among which I consider PI controller in voltage mode control path. Initially I discussed the basic function of the boost converter. Then I derived the transfer function of the complete system. Then I considered model and simulate into matlab without PI controller. Finally I used PI controller in which the values of Kp and Ki has been derived using the Ziegler-nichols method and loop shaping method. Then I applied the control method on four phase boost converter. At last the output response of the both systems is compared and conclusion made upon that comparison. Keywords -transfer function of boost converter; closed loop system transfer function; ZieglarNichols methodt; Loop shaping method Parallel operation, Poly-phase converter I. INTRODUCTION In designing DC converters, parameters such as ratio of energy stored in inductor and capacitor to energy delivered to load in one period, maximum current in the switch and the value of the RMS current in the output capacitor have great importance and it is necessary to be considered. The motivation for this work is expressed through consideration of the above parameters in per unit measured for the two basic converters namely the buck and the boost converter [1]. Consider the boost converter in Fig.1 with per unit values defined as. Vdc=1, D=0.5, Ts=1, E0=1, Po=1, Io/IL=20%, Vo/Vo=1% [IMG]file:///C:\Users\John\AppData\Local\Temp\msohtmlclip1\01\clip_image002.jpg[/IMG] Fig 1 Buck & Boost Converter respectively Table I gives the reactive elements and their energy storage capacity for the basic converters. From the table it is obvious that the boost converter requires total energy storage far in excess of buck converter Table. I: Comparing Buck & Boost Converters (per unit values) L (p.u.) BOOST BUCK 2.5 1.25 C (p.u.) 12.5 10 V (p.u.) 2 0.5 (p.u.) 1.25 1.25 (p.u.) 25 1.25

One-way of reducing the storage requirement is increasing the switching frequency however this is not practicable in all instances. During the on state of the switch, the capacitor has to supply the entire load current in the boost converter; this discontinuity of current in the capacitor increases the RMS value of current and also increases the amount of capacitor which is needed to keep the ripple voltage low. The power dissipation in the ESR of the capacitor is also high. In standard designs it is not uncommon to see tank capacitors one or two orders of magnitude higher than the ideally required capacitance A way to overcome this problem is using poly-phase operation with appropriate phase shift in the control circuit of main switches [2,3]. Fig 2 shows such a polyphase boost converter (N=4). Fig. 3 shows the conduction intervals of the four switches in the converter. It is seen that at any time at least one of the converters is supplying the load in addition to the capacitor. The frequency of ripple current in the output capacitor is N times compared to the single stage and therefore the value of the capacitor required can be reduced. The same circuit topology is also applicable to UPF rectifiers [4-6] In such a scheme, the following advantages are obvious. Output capacitor is rated for lower ripple current and higher ripple frequency (nfs). Source current has higher ripple and at higher frequency (nfs). Another no obvious advantage is that the multi-phase converter may be operated with less number of stages when the load current is low. This will lead to operation under CCM at light load as well as better efficiency [IMG]file:///C:\Users\John\AppData\Local\Temp\msohtmlclip1\01\clip_image008.jpg[/IMG] Fig 2 Multi-phase boost Converter(N=4) [IMG]file:///C:\Users\John\AppData\Local\Temp\msohtmlclip1\01\clip_image010.gif[/IMG] Fig 3 The case with Dmax 1-1/4 II. MATHEMATICAL MODELING Transfer Function of Boost Converter - Basic circuit of the boost converter is shown in Figure 4

[IMG]file:///C:\Users\John\AppData\Local\Temp\msohtmlclip1\01\clip_image012.jpg[/IMG] Fig 4 Basic boost converter Here, L is the inductor, C is the output capacitor and RL is the resistor which is consider as a load. IL is the current flow through the circuit. Switch is triggered by the pulse which is generated by PWM technique. Switch remains on during Ton cycle and off during Toff cycle so triggering is depends on the duty cycle. Vdc is the D.C. input voltage supply which is taken from the bridge rectifier which converts A.C. input voltage into D.C., Vo is the output of the boost converter which is larger than the input voltage Vdc. Now to achieve proper objective of converter, it is need to measure and maintain output voltage at required voltage level. So for that purpose it is needed to use feedback loop into the system that is shown in Fig 5 By technique of averaging and linearising small signal model around a operating point the

Control-to-output, input to output voltage transfer function for open loop boost converter are obtained as: [IMG]file:///C:\Users\John\AppData\Local\Temp\msohtmlclip1\01\clip_image014.gif[/IMG](1) [IMG]file:///C:\Users\John\AppData\Local\Temp\msohtmlclip1\01\clip_image016.gif*/IMG+(2) [IMG]file:///C:\Users\John\AppData\Local\Temp\msohtmlclip1\01\clip_image018.gif[/IMG] Fig 5 Single Phase Closed Loop System of Converter Fig 5 shows the close loop control scheme of a boost converter using PI algorithm. Here Vo is compared to Vref. The error signal of the comparator is processed by PI controller and voltage control signal is sent to PWM block, which eventually produce duty ratio. Then it is added with Vin which is given to the system III. SIMULATION For the simulation purpose I considered the following model: Input Voltage (dc) :24 volt Output Voltage (dc) :48 Volt Boost Inductor (L) :100 mH Rated Power :16 W Switching Frequency :1 kHz Normally, duty cycle for boost converter is considered in between 0.5 to 1. Selection of duty cycle depends on input voltage supply and required output voltage [1]. When boost converter is used without using PI controller it gives steady state error of 25%. So I used PI controller to improve the performance of boost converter. To find out the value of Kp and Ki , I used ZieglerNichols step response method and Loop shaping method [4, 5]. Applying step function to the system and analyzing its output response, I got two parameters L = 1 and T = 0.004 Using these, the value of Kp and Ki can be found by Ziegler-Nichols method which is given below. Kp = 0.0036 and Ki= 3.33

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Now, applying these values into PI controller of the closed loop system and simulate it into the matlab I got the response as shown in fig. 6. From fig. 6 it is shown that it removes steady state error but initially it provide high oscillations. Now, using the Loop shaping method, eq. 9 and parameter of the considered model I got the following two relation [4 ,5]. 2 * =(3000 * Kp 750(3) 3000 * Ki = 2...(4) [IMG]file:///C:\Users\John\AppData\Local\Temp\msohtmlclip1\01\clip_image020.gif[/IMG] Fig. 6 Output Response of system using Ziegler-Nichols Method For PI controller, is maintained at 0.7 and parameters Kp and Ki must be a larger *6+. So, using eq.3 and eq.4 Kp = 2.68 and Ki= 13146 Now, applying these values into PI controller of the closed loop system and simulate it into the matlab I got the response as shown in fig.7. From the fig. 7 it is shown that it reduce steady state error and it doesnt produce any oscillation which was presented during the Ziegler-Nichols method. The performance of the system is improved by the PI controller using loop shaping method [IMG]file:///C:\Users\John\AppData\Local\Temp\msohtmlclip1\01\clip_image022.gif[/IMG] Fig. 7 Output voltage of close loop single phase boost converter From fig. 7 it is revealed that transient time is 4ms, steady state error is 1.04% and ripple are 5%. Now the same PI algorithm I applied to proposed four phase boost covereter. Here four PWM gate signal shifted by 90 degrees phase from each other and a single common duty ratio is imposed on the switches, I got the response as shown in fig 8 [IMG]file:///C:\Users\John\AppData\Local\Temp\msohtmlclip1\01\clip_image024.jpg[/IMG] Fig 8 Output voltage of close loop four phase boost converter Fig. 8 revealed that steady state error is juat 0.0625%., transient response time is only of 1s. No overshoot and output voltage ripple is less than 0.1% IV. COMPARISON OF SINGLE PHASE AND FOUR PHASE BOOST CONVERTERS S.No Features Single Phase Boost Conv. A single inductor of same Rating High Poly Phase Boost Conv.

Inductor size

Same inductance required divided in N parts for N phase

Storage

Reduces by factor 1/N2

requirement 3 Frequency of operation Power dissipation in ESR Efficiency Output ripple Mode of operation Steady state error Transient time Low (f) High (Nf)

High

Low

4 5 6

Low High Only DCM with low load current High Of the order of mili seconds High (up to 40%)

High Low CCM is possible even with low load current, thus less stages of operation Low Of the order of nano seconds

7 8

Overshoot

Low (maximum 0.1%)

V. CONCLUSION This paper presents analysis of the boost converter using Ziegler-Nichols method and loop shaping method. From the above result, following are the conclusion that can be drawn from this paper. Using the boost converter without PI controller, it produces steady state error of 25%. Boost converter used with PI controller applying Ziegler-Nichols method removes steady state error after 2.5 sec. But it produce high oscillation and maximum peak overshoot of 900% that shown in fig. 6. It also produced 14.5% of output ripple. So it is undesirable. Boost converter used with PI controller applying loop shaping method removes steady state error faster and also removes oscillation which is shown in fig. 7. It also produced only 0.5% output ripple which is lower than the Ziegler-Nichols method.So, from above conclusion can be made that loop shaping method gives better response than the Ziegler-Nichols method for the proposed model On comparing the performance of single phase and four phase boost converters we found that steady state as well as transient performance of multi phase converter is much superior to

single phase. Besides having same size inductor and small size storage multi phase converter can be operated with reduced input current ripple and less output voltage ripple V. FUTURE WORK A fully digitized implementation of the proposed control methods should be carried out through the development of FPGA. Further the development of application specific integrated circuit (ASIC) should be explored to provide a smaller, more reliable and cheaper controllers. Further, scope of future work is to implement the open loop and closed loop control of Multi-phase Boost Converter using the DSPTMS320LF2407 REFERENCES [1]. R. Mirzaei And V. Ramanarayanan, P Boost Converter For Automotive And Upf Applications With Digital Control, National Power Electronics Conference, Inspec Accession Number: 9026617, pp.327-332, Dec 2005 *2+. R.Redl and L.Balogh, Power-factor correction with interleaved boost converters in continuous-inductor-current mode, Eighth Annual Applied Power Electronics Conference and Exposition, pp.168174, Mar 1993. [3] Mohammed, B. M Hasaneen, and Adel A. Elbaset. "Design and Simulation of DC-DC Boost Converter," 2008. [4] Astrom,and Hagglund , PID Controllers,1988. [5] Copeland, Brain R. "The Design of PID Controllers using Ziegler Nichols Tuning," 2008. [6] D.P.Eckman, Automatic Process Control. New Delhi: Wiley Eastern,1992 [7] Chen Zhou, and M.Jovanovic, "Design Trade-offs in Continuous Current-Mode Controlled Boost Power-Factor Correction Circuit," Virginia, May 1992

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