What is a quad-core processor?

A four independent cores into a single package composed of a single IC. A dual-core processor contains two cores, and a quad-core processor contains four cores.

The quad core processors contains 731 million transistors. The die area is 263 sq mm, and the size of the physical package is 4 !42. mm

Features "uad#core processor

Benefits $ro%ides four complete e!ecution cores in a single processor. &our dedicated, physical threads help operating systems and applications deli%er additional performance.

'ntel( )ide *ynamic +!ecution 'ntel( ,mart -emory .ccess

'mpro%es e!ecution speed and efficiency, deli%ering more instructions per clock cycle. 'mpro%es system performance /y optimizing the use of the a%aila/le data /and0idth.

2ptimized for multi#core processors, pro%iding higher#performance 0ith a 'ntel( .d%anced ,mart more efficient cache su/system. .ccelerates a /road range of multimedia, encryption, scientific and financial applications /y significantly impro%ing 1ache2 performance 0hen e!ecuting 'ntel( ,treaming ,'-* 3Single Instruction stream Multiple Data stream4 +!tensions 3,,+5,,+25,,+34 instructions.

'ntel( .d%anced *igital 'ntel( 7* 6oost, implemented on 4 nm processors, offers ne0 'ntel( -edia 6oost ,treaming ,'-* +!tension 4 3'ntel ,,+44 instructions for e%en greater multimedia performance and faster high definition %ideo editing and encoding. 'ntel( 8irtualization .llo0s one hard0are platform to function as multiple 9%irtual: platforms. Technology 3'ntel( 8T43

'ntel( 644 architecture .llo0s the processor to access larger amounts of memory. +!ecute *isa/le 6it $ro%ides e!tended %irus defense 0hen deployed 0ith a supported operating system. *igital thermal sensor $ro%ides for more efficient processor and platform thermal control 3*T,4 impro%ing system acoustics.

'ntel#designed thermal 'ncludes a 4#pin connector for fan speed control to help minimize the solution for /o!ed acoustic noise le%els generated from running the fan at higher speeds for processors thermal performance.6

# of Processor Cores 4

L1 Cache

L2 Advanced Cache

Front Side Bus Frequency 1600 MHz 1333 MHz 1066 MHz

Package

32 KB instruction per core 32 KB data per core

2x6 MB shared

FC-LG !!1 Lands

The Quad Core !nte"# $eon# Processor %&'' Series has ()1 *ins or ++1 "ands

Quad-Core Intel Xeon Processor 5400 Series "he #uad-Core $nte% &eon 'rocessor (400 )eries-*ased p%at+or,s i,p%e,ent independent core -o%ta.e /0CC 1 po2er p%anes +or each processor3 F)B ter,ination -o%ta.e /0"" 1 is shared and ,ust connect to a%% F)B a.ents3 "he processor core -o%ta.e uti%izes po2er de%i-er4 .uide%ines speci+ied *4 05M67058 1130 and its associated %oad %ine /0o%ta.e 5e.u%ator Modu%e /05M1 and 7nterprise 0o%ta.e 5e.u%ator-8o2n /70581 113013 05M67058 1130 2i%% support the po2er re9uire,ents o+ a%% +re9uencies o+ the #uad-Core $nte% &eon 'rocessor (400 )eries inc%udin. F%exi*%e Mother*oard Guide%ines /FMB13

Quad-Core Intel Xeon Processor 5400 Series - Intel 64-bit microprocessor intended for dual processor servers and workstations based on Intel s 4! nanometer process, in t"e #C-$%A &&' package wit" four processor cores. 45 nanometer means transistors keep getting small and better(and Innovation is alive. )e ll keep getting to see t"e advent of smaller, cooler and faster running computers It means Intel can keep bringing better performance at relativel* t"e same or even lower prices over time, or w"at we often "ear+ e,tending t"e benefits of -oore s $aw into t"e future
./"e number of transistors and resistors on a c"ip doubles ever* '0 mont"s.. 1* Intel co-founder %ordon -oore regarding t"e pace of semiconductor tec"nolog*. 2e made t"is famous comment in '36! w"en t"ere were appro,imatel* 64 devices on a c"ip. #roving -oore5s law to be rat"er accurate, four decades later, Intel placed '.& billion transistors on its Itanium c"ip.

It means more efficiencies and new features can be s6uee7ed onto processors so t"at computer makers can focus on t"ings like e,tending batter* life of laptops, creating ever sleeker designs and building in new wireless Internet capabilities into ever* new compute device

FC- !" #Flip Chip and !rid "rra$% Pac&a'e 8 /"e 9uad-Core Intel :eon #rocessor !444 ;eries package is a $and %rid Arra*, consisting of a processor core mounted on a pinless substrate wit" &&' lands, and includes an integrated "eat spreader <I2;=. Flip chip, also known as Controlled Collapse Chip Connection is a met"od for interconnecting semiconductor devices, suc" as IC c"ips and ->-; <(icro)lectro(ec"anical S*stems=, to e,ternal circuitr* wit" solder bumps t"at "ave been deposited onto t"e c"ip pads. < and !rid "rra*= A c"ip package wit" a ver* "ig" densit* of contacts. $%As differ from traditional c"ips wit" protruding pins t"at are inserted into a socket. An $%A c"ip "as flat pads on t"e bottom of its package t"at touc" contacts on t"e mot"erboard socket.

 !"**+ soc&et 8 /"e 9uad-Core Intel :eon #rocessor !444 ;eries interfaces to t"e baseboard t"roug" t"is surface mount, &&' $and socket. S$mmetric "'ent 8 A s*mmetric agent is a processor w"ic" s"ares t"e same I?@ subs*stem and memor* arra*, and runs t"e same operating s*stem as anot"er processor in a s*stem. ;*stems using s*mmetric agents are known as ;*mmetric -ultiprocessing <;-#= s*stems. Processor core 8 #rocessor core wit" integrated $' cac"e. $A cac"e and s*stem bus interface are s"ared between t"e two cores on t"e die. All AC timing and signal integrit* specifications are at t"e pads of t"e s*stem bus interface. Front Side ,us #FS,% 8 /"e electrical interface t"at connects t"e processor to t"e c"ipset. Also referred to as t"e processor s*stem bus or t"e s*stem bus. All memor* and I?@ transactions, as well as interrupt messages, pass between t"e processor and c"ipset over t"e B;1. -ual Independent ,us #-I,% 8 Bront side bus arc"itecture wit" one processor on eac" of several processor buses, rat"er t"an a processor bus s"ared between two processor agents. /"e CI1 arc"itecture provides improved performance b* allowing increased B;1 speeds and bandwidt". Inte'rated .eat Spreader #I.S% 8 A component of t"e processor package used to en"ance t"e t"ermal performance of t"e package. Component t"ermal solutions interface wit" t"e processor at t"e I2; surface.

Intel/4 "rchitecture 8 An en"ancement to Intel5s IA-DA <Intel Arc"itecture, DA-bit= arc"itecture t"at allows t"e processor to e,ecute operating s*stems and applications written to take advantage of t"e 64-bit e,tension tec"nolog*. 01( #0olta'e 1e'ulator (odule% 8 CC-CC converter built onto a module t"at interfaces wit" a card edge socket and supplies t"e correct voltage and current to t"e processor based on t"e logic state of t"e processor EIC bits. )01- #)nterprise 0olta'e 1e'ulator -o2n% 8 CC-CC converter integrated onto t"e s*stem board t"at provides t"e correct voltage and current to t"e processor based on t"e logic state of t"e processor EIC bits. 0CC 8 /"e processor core power suppl*. 0SS 8 /"e processor ground. 033 8 B;1 termination voltage. "ssisted !unnin' 3ranscei4er o'ic #"!3 5% - /"is tec"nolog* provides improved noise margins and reduced ringing t"roug" low voltage swings and controlled edge rates. A%/$F buffers are open-drain and re6uire pull-up resistors to provide t"e "ig" logic level and termination.

(echanical Speci6ications /"e 9uad-Core Intel :eon #rocessor !444 ;eries is packaged in a Blip C"ip $and %rid Arra* <BC-$%A= package t"at interfaces to t"e baseboard via a $%A&&' socket. /"e package consists of a processor core mounted on a pinless substrate wit" &&' lands. An integrated "eat spreader <I2;= is attac"ed to t"e package substrate and core and serves as t"e interface for processor component t"ermal solutions suc" as a "eatsink. Integrated 2eat ;preader <I2;= /"ermal Interface -aterial </I-= #rocessor Core <die= #ackage ;ubstrate $andside capacitors #ackage $ands

Processor Pac&a'e "ssem7l$ S&etch

Processor (aterials /"e 9uad-Core Intel :eon #rocessor !444 ;eries is assembled from several components. /"e basic material properties are described below.
Co,*onent $nte.rated Heat )preader /$H)1 )u*strate )u*strate Lands -ateria" :ic;e% o-er copper Fi*er-rein+orced resin Go%d o-er nic;e%

#3hermal .eat Spreader%

#inte'rated .eat Spreader%

Processor and Coordinates

Quad-Core Intel Xeon Processor 5400 Series Pin "ssi'nments

Pin name

Pin No.

Signal Buffer

Direction

.*,;

*2

1ommon 'nput52u 1lk tput

Pin name

Pin No.

Signal Buffer

Direction

BPM2# or BPM[5:0]#

D2

!ommon !l"

#ut$ut

Signal Definitions

[%&:%]#

.<37=3>; 3 ((ress4 define a 23?#/yte physical memory address space. 'n su/#phase 1 of the address phase, these signals transmit the address of a transaction. 'n su/#phase 2, these signals transmit transaction type information. I'# These signals must connect the appropriate pins of all agents on the &,6. .<37=3>; are protected /y parity signals .$<1=@>;. .<37=3>; are source synchronous signals and are latched into the recei%ing /uffers /y .*,T6<1=@>;. 2n the acti%e#to#inacti%e transition of A+,+T;, the processors sample a su/set of the .<37=3>; lands to determine their po0er#on configuration. 'f .2@-; 3 ((ress)20 Mas"4 is asserted, the processor masks physical address /it 2@ 3.2@;4 /efore looking up a line in any internal cache and /efore dri%ing a read50rite transaction on the /us. .sserting .2@-; emulates the ?@?6 processorBs address 0raparound at the 1 -6 /oundary. .ssertion of .2@-; is only supported in real mode. .2@-; is an asynchronous signal. 7o0e%er, to ensure recognition of this signal follo0ing an '52 0rite instruction, it must /e %alid along 0ith the TA*C; assertion of the corresponding '52 0rite /us transaction.

20M#

DS#

I'#

.*,; 3 ((ress Data Stro*e4 is asserted to indicate the %alidity of the transaction address on the .<37=3>; lands. .ll /us agents o/ser%e the .*,; acti%ation to /egin parity checking, protocol checking, address decode, internal snoop, or deferred reply '* match operations associated 0ith the ne0 transaction. This signal must /e connected to the appropriate pins on all "uad#1ore 'ntel( Deon( $rocessor 4@@ ,eries &,6 agents. ((ress stro*es are used to latc- .<37=3>; and A+"<4=@>; on their rising and falling edge. ,tro/es are associated 0ith signals as sho0n /elo0. . +!/, an electronic circuit 0hich has t0o sta/le states and there/y can store one /it of information.
Signals stro*es A+"<4=@>;, .<16=3>;, .<37=36>; .<3 =17>; ssociate( .*,T6@;

DS+B[,:0]#

I'#

.*,T61;

P[,:0]#

I'#

.$<1=@>; 3 ((ress Parit04 are dri%en /y the request initiator along 0ith .*,;, .<37=3>;, and the transaction type on the A+"<4=@>; signals. . correct parity signal is high if an e%en num/er of co%ered signals are lo0 and lo0 if an odd num/er of co%ered signals are lo0. This allo0s parity to /e high 0hen all the co%ered signals are high. .$<1=@>; must /e connected to the appropriate pins of all "uad#1ore 'ntel( Deon( $rocessor 4@@ ,eries &,6 agents. "he di++erentia% *us c%oc; pair BCLK<1=0> /Bus C"ock1 deter,ines the F)B +re9uenc43 %% processor F)B a.ents ,ust recei-e these si.na%s to dri-e their outputs and %atch their inputs3 %% externa% ti,in. para,eters are speci+ied 2ith respect to the risin. ed.e o+ BCLK0 crossin. 0C5?)) 3 6'E'T; 3Bus Initiali2ation4 may /e o/ser%ed and dri%en /y all processor &,6 agents and if used, must connect the appropriate pins of all such agents. 'f the 6'E'T; dri%er is ena/led during po0er on configuration, 6'E'T; is asserted to signal any /us condition that pre%ents relia/le future operation. 'f 6'E'T; o/ser%ation is ena/led during po0er#on configuration and 6'E'T; is sampled asserted, s0mmetric agents reset their /us F21G; acti%ity and /us request ar/itration state machines. The /us agents do not reset their '52 "ueue 3'2"4 and transaction tracking state machines upon o/ser%ation of 6'E'T; assertion. 2nce the 6'E'T; assertion has /een o/ser%ed, the /us agents 0ill re#ar/itrate for the &,6 and attempt completion of their /us queue and '2" entries. 'f 6'E'T; o/ser%ation is disa/led during po0er#on configuration, a priority agent may handle an assertion of 6'E'T; as appropriate to the error handling architecture of the system.

B!.1[,:0]

BINI+#

BN3#

I'#

6EA; 3Bloc" Ne4t 3e5uest4 is used to assert a /us stall /y any /us agent 0ho is una/le to accept ne0 /us transactions. *uring a /us stall, the current /us o0ner cannot issue any ne0 transactions. ,ince multiple agents might need to request a /us stall at the same time, 6EA; is a 0ired#2A signal 0hich must connect the appropriate pins of all processor &,6 agents. 'n order to a%oid 0ired#2A glitches associated 0ith simultaneous edge transitions dri%en /y multiple ri%ers, 6EA; is acti%ated on specific clock edges and sampled on specific clock edges.

BPM5# BPM6#

I'# #

6$-< =@>; 3Brea"$oint Monitor4 are /reakpoint and performance monitor signals. They are outputs from the processor 0hich indicate the status of /reakpoints and programma/le counters used for monitoring processor performance. 6$-< =@>; should connect the appropriate pins of all &,6 agents. BPM6# pro%ides $A*C; 3Pro*e 3ea(04 functionality for the T.$ port. $A*C; is a processor output used /y de/ug tools to determine processor (e*ug readiness. BPM5# pro%ides $A+"; 3Pro*e 3e5uest4 functionality for the T.$ port. $A+"; is used /y de/ug tools to request de/ug operation of the processors. 6$-< =4>; must /e /ussed to all /us agents. de/ug To correct a pro/lem in hard0are or soft0are. *e/ugging soft0are means locating the errors in the source code 3the program logic4. *e/ugging hard0are means finding errors in the circuit design 3logical circuits4 or in the physical interconnections of the circuits. 6$-/<3=@>; 3Brea"$oint Monitor4 are /reakpoint and performance monitor signals. They are outputs from the processor 0hich indicate the status of /reakpoints and programma/le counters used for

BPM*%# BPM*[2:,]#

I'# #

BP.!#

B./10'1#

BS4L/20'1

6$A'; 3Bus Priorit0 3e5uest4 is used to ar/itrate for o0nership of the processor &,6. 't must connect the appropriate pins of all processor &,6 agents. 2/ser%ing 6$A'; acti%e 3as asserted /y the ! priority agent4 causes all other agents to stop issuing ne0 requests, unless such requests are part of an ongoing locked operation. The priority agent keeps 6$A'; asserted until all of its requests are completed then releases the /us /y deasserting 6$A';. "he B5<1=0>@ si.na%s are sa,p%ed on the acti-e-to-inacti-e transition !23 o+ 57)7"@3 "he si.na% 2hich the a.ent sa,p%es asserted deter,ines its a.ent $83 B50@ dri-es the B57#0@ si.na% in the s4ste, and is used *4 the processor to re9uest the *us3 "hese si.na%s do not ha-e on-die ter,ination and ,ust *e ter,inated3 "he BCLK<1=0> +re9uenc4 se%ect si.na%s B)7L<2=0> /Bus Se"ect5 are # used to se%ect the processor input c%oc; +re9uenc43 "he re9uired +re9uenc4 is deter,ined *4 the processorsA chipsetA and c%oc; s4nthesizer3 %% F)B a.ents ,ust operate at the sa,e +re9uenc43 ! C?M'<3=0> ,ust *e ter,inated to 0)) on the *ase*oard usin. precision resistors3 "hese inputs con+i.ure the G"LB dri-ers o+ the processor3

C3-P/60'1

7/860'1#

8<63=0>@ /7ata1 are the data si.na%s3 "hese si.na%s pro-ide a 64-*it !23 data path *et2een the processor F)B a.entsA and ,ust connect the appropriate pins on a%% such a.ents3 "he data dri-er asserts 858C@ to indicate a -a%id data trans+er3

7B!/60'1#

7B.#

7BS9#

74F4.#

7P/60'1#

8B$<3=0>@ /7ata Bus !nversion1 are source s4nchronous and !23 indicate the po%arit4 o+ the 8<63=0>@ si.na%s3 "he 8B$<3=0>@ si.na%s are acti-ated 2hen the data on the data *us is in-erted3 $+ ,ore than ha%+ the data *itsA 2ithinA 2ithin a 16-*it .roupA 2ou%d ha-e *een asserted e%ectronica%%4 %o2A the *us a.ent ,a4 in-ert the data *us si.na%s +or that particu%ar su*-phase +or that 16-*it .roup3 8B5@ is used on%4 in s4ste,s 2here no de*u. port connector is 3 i,p%e,ented on the s4ste, *oard3 8B5@ is used *4 a de*u. port interposer so that an in-tar.et pro*e can dri-e s4ste, reset3 $+ a de*u. port connector is i,p%e,ented in the s4ste,A 8B5@ is a no connect on the #uad-Core $nte%D &eonD 'rocessor (400 )eries pac;a.e3 8B5@ is not a processor si.na%3 8B)C@ /7ata Bus Busy1 is asserted *4 the a.ent responsi*%e +or !23 dri-in. data on the processor F)B to indicate that the data *us is in use3 "he data *us is re%eased a+ter 8B)C@ is deasserted3 87F75@ is asserted *4 an a.ent to indicate that a transaction cannot ! *e .uaranteed in-order co,p%etion3 ssertion o+ 87F75@ is nor,a%%4 the responsi*i%it4 o+ the addressed ,e,or4 or $6? a.ent3 8'<3=0>@ /7ata Parity1 pro-ide parit4 protection +or the 8<63=0>@ !23 si.na%s3 "he4 are dri-en *4 the a.ent responsi*%e +or dri-in. 8<63=0>@A and ,ust connect the appropriate pins o+ a%% processor F)B a.ents3 !23 858C@ /7ata .eady1 is asserted *4 the data dri-er on each data trans+erA indicatin. -a%id data on the data *us3 $n a ,u%ti-co,,on c%oc; data trans+erA 858C@ ,a4 *e deasserted to insert id%e c%oc;s3

7.79#

8ata stro*e used to %atch in 8<63=0>@3 7STB:/60'1# !23

Signa"s *<1 =@>;, *6'@; *<31=16>;, *6'1; *<47=32>;, *6'2; *<63=4?>;, *6'3; Associated Stro;es *,T6E@; *,T6E1; *,T6E2; *,T6E3;

F4..#2PB4#

F755@6'B7@ /f"oating *oint error2*ending ;reak event1 is a ,u%tip%exed si.na% and its ,eanin. is 9ua%i+ied *4 )"'CLK@3 Ehen )"'CLK@ is not assertedA F755@6'B7@ indicates a +%oatin.-point error and 2i%% *e asserted 2hen the processor detects an un,as;ed +%oatin.-point error3 Ehen )"'CLK@ is not assertedA F755@6'B7@ is si,i%ar to the 755?5@ si.na% on the $nte%3F! coprocessorA and is inc%uded +or co,pati*i%it4 2ith s4ste,s usin. M)-8?)G-t4pe +%oatin.point error reportin.3 Ehen )"'CLK@ is assertedA an assertion o+ F755@6'B7@ indicates that the processor has a pendin. *rea; e-ent 2aitin. +or ser-ice3 "he assertion o+ F755@6'B7@ indicates that the processor shou%d *e returned to the :or,a% state3

F3.C4P.#

=!T# =!T-#

"he F?5C7'5@ /force *o<er reduction1 input can *e used *4 the ! p%at+or, to cause the #uad-Core $nte%D &eonD 'rocessor (400 )eries to acti-ate the "her,a% Contro% Circuit /"CC13 H$"@ /Snoo* =it1 and H$"M@ /=it -odified1 con-e4 transaction !23 snoop operation resu%ts3 n4 F)B a.ent ,a4 assert *oth H$"@ and !23 H$"M@ to.ether to indicate that it re9uires a snoop sta%%A 2hich can *e continued *4 reassertin. H$"@ and H$"M@ to.ether3

!4..#

!>::4#

!:!T#

$755@ /!nterna" 4rror1 is asserted *4 a processor as the resu%t o+ an interna% error3 ssertion o+ $755@ is usua%%4 acco,panied *4 a )HH"8?E: transaction on the processor F)B3 "his transaction ,a4 optiona%%4 *e con-erted to an externa% error si.na% /e3.3A :M$1 *4 s4ste, core %o.ic3 "he processor 2i%% ;eep $755@ asserted unti% the assertion o+ 57)7"@3 "his si.na% does not ha-e on-die ter,ination3 $G::7@ /!gnore :u,eric 4rror1 is asserted to +orce the processor to i.nore a nu,eric error and continue to execute non-contro% +%oatin.-point instructions3 $+ $G::7@ is deassertedA the processor .enerates an exception on a non-contro% +%oatin.-point instruction i+ a pre-ious +%oatin.-point instruction caused an error3 $G::7@ has no e++ect 2hen the :7 *it in contro% re.ister 0 /C501 is set3 $G::7@ is an as4nchronous si.na%3 Ho2e-erA to ensure reco.nition o+ this si.na% +o%%o2in. an $6? 2rite instructionA it ,ust *e -a%id a%on. 2ith the "58C@ assertion o+ the correspondin. $6? 2rite *us transaction3 $:$"@ /!nitia"i?ation1A 2hen assertedA resets inte.er re.isters inside a%% processors 2ithout a++ectin. their interna% caches or +%oatin.-point re.isters3 7ach processor then *e.ins execution at the po2er-on 5eset -ector con+i.ured durin. po2er-on con+i.uration3 "he processor continues to hand%e snoop re9uests durin. $:$"@ assertion3 $:$"@ is an as4nchronous si.na% and ,ust connect the appropriate pins o+ a%% processor F)B a.ents3

L!:T/10'1

LL@!7/10'1

L3CA#

L$:"<1=0> /Loca" AP!C !nterru*t1 ,ust connect the appropriate pins o+ a%% F)B a.ents3 Ehen the '$C +unctiona%it4 is disa*%edA the L$:"06$:"5 si.na% *eco,es $:"5A a ,as;a*%e interrupt re9uest si.na%A and L$:"16:M$ *eco,es :M$A a non-,as;a*%e interrupt3 $:"5 and :M$ are *ac;2ard co,pati*%e 2ith the si.na%s o+ those na,es on the 'entiu,D processor3 Both si.na%s are as4nchronous3 "hese ! si.na%s ,ust *e so+t2are con+i.ured -ia B$?) pro.ra,,in. o+ the '$C re.ister space to *e used either as :M$6$:"5 or L$:"<1=0>3 Because the '$C is ena*%ed *4 de+au%t a+ter 5esetA operation o+ these pins as L$:"<1=0> is the de+au%t con+i.uration3 /Ad-anced Pro.ra,,a*%e !nterrupt Contro%%er1 circuit that hand%es the priorit4 o+ interrupts in a co,puter3 8esi.ned to support s4,,etric ,u%tiprocessin. /)M'1A the '$C hand%es ,ore interrupts and is ,ore +%exi*%e than the pro.ra,,a*%e interrupt contro%%er /'$C1A 2hich it rep%aced3 "he LLI$8<1=0> /Line List !75 si.na%s are used to se%ect the correct 3 %oad %ine s%ope +or the processor3 "hese si.na%s are not connected to the processor die3 L?CK@ indicates to the s4ste, that a transaction ,ust occur ato,ica%%43 "his si.na% ,ust connect the appropriate pins o+ a%% processor F)B a.ents3 For a %oc;ed se9uence o+ transactionsA L?CK@ is asserted +ro, the *e.innin. o+ the +irst transaction to the end o+ !23 the %ast transaction3 Ehen the priorit4 a.ent asserts B'5$@ to ar*itrate +or o2nership o+ the processor F)BA it 2i%% 2ait unti% it o*ser-es L?CK@ deasserted3 "his ena*%es s4,,etric a.ents to retain o2nership o+ the processor F)B throu.hout the *us %oc;ed operation and ensure the ato,icit4 o+ %oc;3

-C4..#

-S@!7/10'1

P.3C=3T#

MC755@ /-achine Check 4rror1 is asserted to indicate an !23 unreco-era*%e error 2ithout a *us protoco% -io%ation3 $t ,a4 *e dri-en *4 a%% processor F)B a.ents3 MC755@ assertion conditions are con+i.ura*%e at a s4ste, %e-e%3 ssertion options are de+ined *4 the +o%%o2in. options= J 7na*%ed or disa*%ed3 J ssertedA i+ con+i.uredA +or interna% errors a%on. 2ith $755@3 J ssertedA i+ con+i.uredA *4 the re9uest initiator o+ a *us transaction a+ter it o*ser-es an error3 J sserted *4 an4 *us a.ent 2hen it o*ser-es an error in a *us transaction3 "hese si.na%s are pro-ided to indicate the Mar;et )e.,ent +or the 3 processor and ,a4 *e used +or +uture processor co,pati*i%it4 or +or ;e4in.3 "hese si.na%s are not connected to the processor die3 Both the *its 0 and 1 are %o.ic 1 and are no connects on the pac;a.e3 '5?CH?"@ /Processor =ot1 2i%% .o acti-e 2hen the processorKs 3 te,perature ,onitorin. sensor detects that the processor has reached its ,axi,u, sa+e operatin. te,perature3 "his indicates that the "her,a% Contro% Circuit /"CC1 has *een acti-atedA i+ ena*%ed3 "he "CC 2i%% re,ain acti-e unti% short%4 a+ter the processor deasserts '5?CH?"@3

PB.>337

$)AH22* 3Po7er 8oo(4 is an input. The processor requires this signal to /e a clean indication that all processor clocks and po0er supplies are sta/le and 0ithin their specifications. 91lean: implies that the signal 0ill remain lo0 3capa/le of sinking leakage current4, 0ithout glitches, from the time that the po0er supplies are turned on until they come 0ithin specification. The signal must then transition monotonically to a high state. $)AH22* can /e dri%en inacti%e at any time, /ut clocks and po0er must again /e sta/le /efore a su/sequent rising edge of $)AH22*. 't must also meet the minimum pulse 0idth specification in Ta/le 2#1?, and /e follo0ed /y a 1#1@ ms A+,+T; pulse. The $)AH22* signal must /e supplied to the processorI it is used to protect internal circuits against %oltage sequencing issues. 't should /e dri%en high throughout /oundary scan operation.

.4Q/&0'1#

.4S4T#

A+"<4=@>; 33e5uest !omman(4 must connect the appropriate pins !23 of all processor &,6 agents. They are asserted /y the current /us o0ner to define the currently acti%e transaction type. These signals are source synchronous to .*,T6<1=@>;. .sserting the A+,+T; signal resets all processors to kno0n states and in%alidates their internal caches 0ithout 0riting /ack any of their ! contents. &or a po0er#on Aeset, A+,+T; must stay acti%e for at least 1 ms after 811 and 61FG ha%e reached their proper specifications. 2n o/ser%ing acti%e A+,+T;, all &,6 agents 0ill deassert their outputs 0ithin t0o clocks. A+,+T; must not /e kept asserted for more than 1@ ms 0hile $)AH22* is asserted. . num/er of /us signals are sampled at the acti%e#to#inacti%e transition of A+,+T; for po0er#on configuration. This signal does not ha%e on#die termination and must

.S/20'1#

5)<2=0>@ /.es*onse Status1 are dri-en *4 the response a.ent /the a.ent responsi*%e +or co,p%etion o+ the current transaction1A and ,ust connect the appropriate pins o+ a%% processor F)B a.ents3 5)'@ /.es*onse Parity1 is dri-en *4 the response a.ent /the a.ent responsi*%e +or co,p%etion o+ the current transaction1 durin. assertion o+ 5)<2=0>@A the si.na%s +or 2hich 5)'@ pro-ides parit4 protection3 $t ,ust connect to the appropriate pins o+ a%% processor F)B a.ents3 correct parit4 si.na% is hi.h i+ an e-en nu,*er o+ co-ered si.na%s are %o2 and %o2 i+ an odd nu,*er o+ co-ered si.na%s are %o23 Ehi%e 5)<2=0>@ L 000A 5)'@ is a%so hi.hA since this indicates it is not *ein. dri-en *4 an4 a.ent .uaranteein. correct parit43 )K"?CC@ /Socket occu*ied1 2i%% *e pu%%ed to .round *4 the processor to indicate that the processor is present3 "here is no connection to the processor si%icon +or this si.na%3 )M$@ /Syste, -anage,ent !nterru*t1 is asserted as4nchronous%4 *4 s4ste, %o.ic3 ?n acceptin. a )4ste, Mana.e,ent $nterruptA processors sa-e the current state and enter )4ste, Mana.e,ent Mode /)MM13 n )M$ c;no2%ed.e transaction is issuedA and the processor *e.ins pro.ra, execution +ro, the )MM hand%er3 $+ )M$@ is asserted durin. the deassertion o+ 57)7"@ the processor 2i%% tristate its outputs3

.SP#

SAT3CC#

S-!#

STPCLA#

TCA T7! T73

! ! 3

)"'CLK@ /Sto* C"ock1A 2hen assertedA causes processors to enter a %o2 po2er )top-Grant state3 "he processor issues a )top-Grant c;no2%ed.e transactionA and stops pro-idin. interna% c%oc; si.na%s to a%% processor core units except the F)B and '$C units3 "he processor continues to snoop *us transactions and ser-ice interrupts 2hi%e in )top-Grant state3 Ehen )"'CLK@ is deassertedA the processor restarts its interna% c%oc; to a%% units and resu,es execution3 "he assertion o+ )"'CLK@ has no e++ect on the *us c%oc;M )"'CLK@ is an as4nchronous input3 "CK /Test C"ock1 pro-ides the c%oc; input +or the processor "est Bus /a%so ;no2n as the "est ccess 'ort13 "8$ /Test 7ata !n1 trans+ers seria% test data into the processor3 "8$ pro-ides the seria% input needed +or N" G speci+ication support3 "8? /Test 7ata 3ut1 trans+ers seria% test data out o+ the processor3 "8? pro-ides the seria% output needed +or N" G speci+ication support3 "7)"H$<12=10> ,ust *e connected to a 0"" po2er source throu.h a resistor +or proper processor operation3 "7)"$:1 ,ust *e connected to a 0"" po2er source throu.h a resistor

T4ST=!/1201'1

T4ST!:1 T4ST!:2

! !

as 2e%% as to the "7)"$:2 %and o+ the sa,e soc;et +or proper processor operation3 "7)"$:2 ,ust *e connected to a 0"" po2er source throu.h a resistor as 2e%% as to the "7)"$:1 %and o+ the sa,e soc;et +or proper processor operation3

T=4.-T.!P#

.ssertion of T7+A-TA'$; 3+-ermal +ri$4 indicates the processor Junction temperature has reached a temperature /eyond 0hich permanent silicon damage may occur. -easurement of the temperature is accomplished through an internal thermal sensor. Kpon assertion of T7+A-TA'$;, the processor 0ill shut off its internal clocks 3thus halting program e!ecution4 in an attempt to reduce the processor Junction temperature. To protect the processor its core %oltage 3811 4 must /e remo%ed follo0ing the assertion of T7+A-TA'$;. 'ntel also recommends the remo%al of 8TT 0hen T7+A-TA'$; is asserted. *ri%ing of the T7+A-TA'$; signals is ena/led 0ithin 1@ Ls of the assertion of $)AH22* and is disa/led on de#assertion of $)AH22*. 2nce acti%ated, T7+A-TA'$; remains latched until $)AH22* is deasserted. )hile the de#assertion of the $)AH22* signal 0ill deassert T7+A-TA'$;, if the processorMs Junction temperature remains at or a/o%e the trip le%el, T7+A-TA'$; 0ill again /e asserted 0ithin 1@ Ls of the assertion of $)AH22*. T-, 3+est Mo(e Select4 is a NT.H specification support signal used /y de/ug tools. 39oint +est ction 8roup4 is an '+++ standard for /oundary scan technology. TA*C; 3+arget 3ea(04 is asserted /y the target to indicate that it is ready to recei%e a 0rite or implicit 0rite/ack data transfer. TA,T; 3+est 3eset4 resets the Test .ccess $ort 3T.$4 logic. TA,T; must /e dri%en lo0 during po0er on Aeset. 8'*<6=1> 3:oltage ID4 pins are used to support automatic selection of po0er supply %oltages 38114. These are 1-2, signals that are dri%en /y the processor and must /e pulled up through a resistor.

T-S

T.79# T.ST#

! !

C!7/8011