EE114 Fundamentals of Analog Integrated Circuit Design

R. Dutton, B. Murmann Stanford University Uni ersit

R. Dutton, B. Murmann

EE 114 (HO #3)

EE114 Basics (1)

Teaching assistants Mahmoud Saadat, Kamal Aggarwal Administrative support Ann Guerra, CIS 207 Lectures are televised But please come to class to keep the discussion interactive! Web page: http://ccnet.stanford.edu/ee114 Check regularly, especially bulletin board Register R i t f for online li access t to grades d and d solutions l ti
Only enrolled students can register; we manually control the access list based on Axess data Please be patient; after you have registered in Axess, it may take up to one day before you can log into Ccnet
R. Dutton, B. Murmann EE 114 (HO #3) 2

EE114 Basics (2)

No textbook required We will (try to) hand out chapters of a preliminary draft of
B. Murmann, , R. T. Howe and C. G. Sodini, , Analysis y and Design of Elementary MOS Amplifier Stages, National Technology and Science Press, to appear in 2009.

Course prerequisites EE101B or equivalent Basic device physics and models

PN junctions, MOSFETs, BJTs

Basic linear systems

Frequency response, poles, zeros

R. Dutton, B. Murmann

EE 114 (HO #3)

EE114 Basics (3)

Background and reference texts R. T. Howe and C. G. Sodini, Microelectronics: An Integrated Approach, Prentice Hall, 1996 B. Razavi, Fundamentals of Microelectronics, Wiley, 2008 R. J. Baker, CMOS Circuit Design, Layout, and Simulation, 2nd Edition, Wiley, 2007 B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2000 P. R. Gray, P. J. Hurst, S. H. Lewis, R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 4th Edition, Edition Wiley, Wiley 2001
Textbook for EE214
More difficult

R. Dutton, B. Murmann

EE 114 (HO #3)

Assignments
Homework (20%) Handed out on Fri, due following Fri in class Lowest HW score will be dropped Policy for off-campus students: Fax/email to SCPD before deadline stated on handout Midterm Exam (30%) Project (20%) Design of an amplifier using HSpice (no layout) Work in teams of two
OK to discuss with other teams teams, but no file exchange!

Final Exam (30%)

R. Dutton, B. Murmann

EE 114 (HO #3)

Honor Code
Please remember you are bound by the honor code We will trust you not to cheat We will try not to tempt you But if you are found cheating it is very serious There is a formal hearing You can be thrown out of Stanford Save yourself and me a huge hassle and be honest For more info http://www.stanford.edu/dept/vpsa/judicialaffairs/guiding/pdf/ honorcode.pdf

R. Dutton, B. Murmann

EE 114 (HO #3)

Be Reasonable When Asking TAs

The TAs will not give you "the answer times two" They Th will ill also l NOT debug d b your Spice S i deck d k Figuring out what's wrong with your circuit is an essential component of this class

R. Dutton, B. Murmann

EE 114 (HO #3)

The Big Picture

Transducer Antenna Sensor Frequency Translation, Filtering User Interface

Amplifier

ADC

DSP

EE252 EE312 ...

EE114 EE214 EE314

EE314 EE315A

EE315B

EE264 EE271 .

Most modern electronic information processing systems rely on amplification of "small" physical signals
E.g. signal from RF antenna, disk drive head, microphone,

EE114 uses amplifiers as a vehicle to teach you the basics of analog integrated circuit analysis and design
Material forms basis for other and/or more complex circuits
R. Dutton, B. Murmann EE 114 (HO #3) 8

Analog Circuit Sequence

Fundamentals for upperlevel undergraduates and entry-level graduate students Analysis and design techniques for highperformance circuits in advanced Technologies Design of application and function- specific mixed-signal/RF building blocks

EE314 RF Integrated Circuit Design EE114 Fundamentals of Analog Integrated Circuit Design EE214 Advanced Analog Integrated Circuit Design EE315A VLSI Signal Conditioning Circuits EE315B VLSI Data Conversion Circuits

RF modeling Resonant circuits Transceiver building blocks Transceiver architectures

Switched capacitor circuits Active filters Precision sensor interfaces OTA design

Biasing and small-signal analysis Elementary transistor stages Introduction to feedback Voltage and current references

Device models for advanced technology Noise and distortion analysis Feedback, root locus Wideband gain stages

ADC and DAC architectures Voltage comparators Calibration techniques

R. Dutton, B. Murmann

EE 114 (HO #3)

Learning Goals
Develop deeper understanding of MOS device behavior relevant to analog design and prepare for advanced courses on this j ( (EE214, , EE314, , EE315A,B, , , ) ) subject Develop a feel for limits and tradeoffs in analog circuits Develop a systematic design style Learn to use an advanced circuit simulator Well use HSpice in this course Solidify the above aspects in a hands-on design project Design and optimization of an amplifier circuit

R. Dutton, B. Murmann

EE 114 (HO #3)

10

Analysis versus Design

Unlike common perception, analog circuit analysis and design is not "black magic" Circuit analysis The art of decomposing a circuit into manageable pieces Based on the simple, but sufficiently accurate model
"Just-in-time" modeling; do not use a complex model unless you know why it's needed

One circuit one solution Circuit design The art of synthesizing circuits based on experience from extensive analysis One set of specifications Many solutions Design skills are best acquired through "learning by doing"
This is why we'll have a design project
R. Dutton, B. Murmann EE 114 (HO #3) 11

Outline for the Quarter (TENTATIVE)

9/22 9/24 9/26 9/29 10/1 10/3 10/6 10/8&10 10/13 10/15 10/17&20 10/22 10/24 10/27&29 10/31 11/3 11/5 11/7 11/10 11/12&14 11/17&19 11/21 11/24-28 12/1&3 12/5 12/12 Intro. + IC Technology Long Ch. MOS Model Common Source Amp.+SS model Op point Calculations, Spice Gain considerations, finite ro Intrinsic capacitance Extrinsic capacitance Miller & ZVTC Backgate effect, Common Gate Amp. Common Drain Amp. Diff. Pair Current Mirrors Bias Network Design Supply Independent Biasing Halloween (OOOH!) MIDTERM Multi-stage (morestarted 10/31) Systematic y Design g Approaches pp Process Variations, Ratiometric Design Intro. Feedback Basic OTA circuits Feedback and Port Impedances THANKSGIVING (AAAH!) Bandgap References Project Discussion; Class Summary FINAL EXAM (8:30-10AM = 90 Min.) Project(due) HW6(due);Project(out) HW5(due) HW6(out) HW4(due);HW5(out) HW3(due);HW4(out) HW2(due);HW3(out) HW1(due); HW2(out) HW1(out)

Lets get started!

Modeling (next time)

Basic Amps

More modeling, Spice

Diff. Pair

Biasing

Multi-stage

Design Approaches

Feedback

Bandgap Ref.
EE 114 (HO #3) 12

R. Dutton, B. Murmann