Power Electronics: First Course On

Copyright Ned Mohan 2007 1
Ned Mohan
Oscar A. Schott Professor of Power Electronics and Systems
Department of Electrical and Computer Engineering
University of Minnesota
Minneapolis, MN 55455
USA
First Course on
Power Electronics
Chapter 1 Power Electronics: An Enabling Technology
1-1 Introduction to Power Electronics
1-2 Applications and the Role of Power Electronics
1-3 Energy and the Environment
1-4 Need for High Efficiency and High Power Density
1-5 Structure of Power Electronics Interface
1-6 Voltage-Link Structure
1-7 Recent and Potential Advancements
References
Problems
3
Role of Power Electronics
Figure 1-1 Power electronics interface between the source and the load.
Converter
Controller
Source Load
Power Electronics
Interface
Converter
Controller
Source Load
Power Electronics
Interface
The power electronics interface facilitates the transfer of power from the source to the
load by converting voltages and currents from one form to another, in which it is possible
for the source and load to reverse roles. The controller shown in Fig. 1-1 allows
management of the power transfer process in which the conversion of voltages and
currents should be achieved with as high energy-efficiency and high power density as
possible.
Powering the Information Technology
Figure 1-2 Regulated low-voltage dc power supplies.
Power
Converter
Controller
o
V
, o ref
V
in
V
Utility
24V(dc)
5V(dc)
3.3V(dc)
0.5V(dc)
(a) (b)
Power
Converter
Controller
o
V
, o ref
V
in
V
Power
Converter
Controller
o
V
, o ref
V
in
V
Utility
24V(dc)
5V(dc)
3.3V(dc)
0.5V(dc)
Utility
24V(dc)
5V(dc)
3.3V(dc)
0.5V(dc)
(a) (b)
Boost Converter
Figure 1-3 Boost dc-dc converter needed in cell operated equipment.
Battery
Cell (1.5V)
9V(dc)
Battery
Cell (1.5V)
9V(dc)
Adjustable Speed Drives
Figure 1-4 Block diagramof adjustable speed drives.
Power
Processing
Unit (PPU)
fixed
form
measured
speed/ position
speed/
position
Motor
Electric
Drive
Load
input command
(speed/ position)
Power
Signal
adjustable
form
ElectricSource
(utility)
Sensors
Controller
Induction Heating
Figure 1-5 Power electronics interface required for induction heating.
High
Frequency
AC
Power
Electronics
Interface
Utility
High
Frequency
AC
Power
Electronics
Interface
Utility
Electric Welding
Figure 1-6 Power electronics interface required for electric welding.
DC
Power
Electronics
Interface
Utility
DC
Power
Electronics
Interface
Utility
Energy and the Environment: The Percentage
Energy Consumption
Figure 1-7 Percentage use of electricity in various sectors in the U.S.
Motors 51% HVAC16%
IT
14%
Lighting 19%
Motors 51% HVAC16%
IT
14%
Lighting 19%
Motors 51% HVAC16%
IT
14%
Lighting 19%
Figure 1-8 Role of adjustable speed drives in pump-driven systems.
Adjustable
Speed Drive
(ASD)
Inlet
Outlet
Pump
utility
Adjustable
Speed Drive
(ASD)
Inlet
Outlet
Pump
utility
Role of adjustable speed drives in
pump-driven systems
Compact Fluorescent Lamps
Figure 1-9 Power electronics interface required for CFL.
CFL
Power
Electronics
Interface
Utility
CFL
Power
Electronics
Interface
Utility
Hybrid electric vehicles with much higher gas mileage
light rail, fly-by-wire planes
all-electric ships
drive-by-wire automobiles.
Transportation
Figure 1-10 Hybrid electric vehicles with much higher gas mileage.
Renewable Energy
Photovoltaic Systems
Figure 1-11 Photovoltaic Systems.
(a)
Power
Electronics
Interface
Utility
DCInput
(b)
(a)
Power
Electronics
Interface
Utility
DCInput
(b)
Power
Electronics
Interface
Utility
DCInput Power
Electronics
Interface
Utility
DCInput
(b)
Wind-Electric Systems
Figure 1-12 Wind-electric systems.
Utility
Generator
and
Power Electronics
Utility
Generator
and
Power Electronics
Utility
Generator
and
Power Electronics
Uninterruptible Power Supplies
Figure 1-13 Uninterruptible power supply (UPS) system.
Utility
Critical
Load
Uninterruptible
Power Supply
Utility
Critical
Load
Uninterruptible
Power Supply
Strategic Space and Defense Applications
Electric Warship More Electric Aircraft
Source: James Soeder, NASA and Terry Ericsen, ONR.
NEED FOR HIGH EFFICIENCY AND
HIGH POWER DENSITY
o
o loss
P
P P
=
+ 1
o loss
P P
Figure 1-14 Power output capability as a function of efficiency.

in
P
o
P
loss
P
( ) a
Power
Electronics
Equipment
0.8 0.82 0.84 0.86 0.88 0.9 0.92 0.94 0.96
0
50
100
150
200
250
300
350
400
450
500
Efficiency
P
o
w
e
r

R
a
t
i
n
g
( ) b
o
P
20
loss
P W =
10
loss
P W =
in
P
o
P
loss
P
( ) a
Power
Electronics
Equipment
0.8 0.82 0.84 0.86 0.88 0.9 0.92 0.94 0.96
0
50
100
150
200
250
300
350
400
450
500
Efficiency
P
o
w
e
r

R
a
t
i
n
g
( ) b
o
P
20
loss
P W =
10
loss
P W =

Summarizing the Role of Power Electronics
Output to Load
- Adjustable DC
- Sinusoidal AC
- High-frequency AC
utility
Power
Electronics
Interface
Output to Load
- Adjustable DC
- Sinusoidal AC
- High-frequency AC
utility
Power
Electronics
Interface
Figure 1-15 Block diagramof power electronic interface.
Output to Load
- Adjustable DC
- Sinusoidal AC
- High-frequency AC
utility
Power
Electronics
Interface
Output to Load
- Adjustable DC
- Sinusoidal AC
- High-frequency AC
utility
Power
Electronics
Interface
Figure 1-15 Block diagramof power electronic interface.
STRUCTURE OF POWERELECTRONICS INTERFACE
Voltage-link structure of power electronics interface
Unipolar voltage handling transistors used
Decoupling of two converters
Immunity from momentary power interruptions
Figure 1-16 Voltage-link structure of power electronics interface.
conv1 conv2
controller
utility Load
conv1 conv2
controller
utility Load
Current-Link Systems
Matrix Converters
Figure 1-17 Current-link structure of power electronics interface.
AC1 AC2 AC1 AC2 AC1 AC2 AC1 AC2
Figure 1-18 Matrix converter structure of power electronics interface [13].
v
C
v
B
v
A
v
c
v
b
v
a
i
a
d
aA
d
bA
d
cA
d
aB
d
aC
d
bB
d
bC
d
cB
d
cC
v
C
v
B
v
A
v
c
v
b
v
a
i
a
d
aA
d
bA
d
cA
d
aB
d
aC
d
bB
d
bC
d
cB
d
cC
Figure 1-19 Load-side converter in a voltage-source structure.
conv1 conv2
controller
utility Load
conv1 conv2
controller
utility Load
SWITCH-MODE LOAD-SIDE CONVERTER
Group 1 Adjustable dc or a low-frequency sinusoidal ac output in
- dc and ac motor drives
- uninterruptible power supplies
- regulated dc power supplies without electrical isolation
Group 2 High-frequency ac in
- compact fluorescent lamps
- induction heating
- regulated dc power supplies where the dc output voltage needs to be
electrically isolated from the input, and the load-side converter
internally produces high-frequency ac, which is passed through a
high-frequency transformer and then rectified into dc.
Switch-Mode Conversion: Switching Power-
Pole as the Building Block
Figure 1-20 Switching power-pole as the building block in converters.
(b)
A
v
0
t
in
V
+
-
(a)
+
-
A
v
A
q
(b)
A
v
0
t
(b)
A
v
0
t
in
V
+
-
(a)
+
-
A
v
A
q
in
V
+
-
(a)
+
-
A
v
A
q
in
V
A
v
0
1
A
q =
(b)
A
v
0
t
in
V
+
-
(a)
+
-
A
v
A
q
(b)
A
v
0
t
(b)
A
v
0
t
in
V
+
-
(a)
+
-
A
v
A
q
in
V
+
-
(a)
+
-
A
v
A
q
in
V
A
v
0
(b)
A
v
0
t
in
V
+
-
(a)
+
-
A
v
A
q
(b)
A
v
0
t
(b)
A
v
0
t
in
V
+
-
(a)
+
-
A
v
A
q
in
V
+
-
(a)
+
-
A
v
A
q
in
V
A
v
0
1
A
q =
Pulse-Width Modulation (PWM) of the Switching Power-Pole
up
A in A in
s
T
v V d V
T
= = 0 1
A
d
( / )
A up s
d T T =
Figure 1-21 PWM of the switching power-pole.
(a) (b)
A
v
in
V
+
-
+
-
A
i
1or 0
A
q =
A s
d T
dA
i
up
T
s
T
A
q
A
v
0
0
t
t
1
in
V
A
v
A
v
in
V
+
-
+
-
A
i
1or 0
A
q =
A s
d T
dA
i
up
T
s
T
A
q
A
v
0
0
t
t
1
in
V
A
v
(a) (b)
A
v
in
V
+
-
+
-
A
i
1or 0
A
q =
A s
d T
dA
i
up
T
s
T
A
q
A
v
0
0
t
t
1
in
V
A
v
A
v
in
V
+
-
+
-
A
i
1or 0
A
q =
A s
d T
dA
i
up
T
s
T
A
q
A
v
0
0
t
t
1
in
V
A
v
A
d
(a) (b)
A
v
in
V
+
-
+
-
A
i
1or 0
A
q =
A s
d T
dA
i
up
T
s
T
A
q
A
v
0
0
t
t
1
in
V
A
v
A
v
in
V
+
-
+
-
A
i
1or 0
A
q =
A s
d T
dA
i
up
T
s
T
A
q
A
v
0
0
t
t
1
in
V
A
v
(a) (b)
A
v
in
V
+
-
+
-
A
i
1or 0
A
q =
A s
d T
dA
i
up
T
s
T
A
q
A
v
0
0
t
t
1
in
V
A
v
A
v
in
V
+
-
+
-
A
i
1or 0
A
q =
A s
d T
dA
i
up
T
s
T
A
q
A
v
0
0
t
t
1
in
V
A
v
A
d
Switching Power-Pole in a Buck DC-DC Converter:
An Example
o A A in
V v d V = = 0
o in
V V
Figure 1-22 Switching power-pole in a Buck converter.
in
V
+
A
q
+
A
v
+
o
V
in
i
L
i
A s
d T
s
T
A
q
A
v
L
i
in
i
0
0
0
0
t
in
V
t
t
t
1
(a)
(b)
in
V
+
A
q
+
A
v
+
o
V
in
i
L
i
in
V
+
A
q
+
A
v
+
o
V
in
i
L
i
A s
d T
s
T
A
q
A
v
L
i
in
i
0
0
0
0
t
in
V
t
t
t
1
A s
d T
s
T
A
q
A
v
L
i
in
i
0
0
0
0
t
in
V
t
t
t
1
(a)
(b)
A
v
in
V
+
A
q
+
A
v
+
o
V
in
i
L
i
A s
d T
s
T
A
q
A
v
L
i
in
i
0
0
0
0
t
in
V
t
t
t
1
(a)
(b)
in
V
+
A
q
+
A
v
+
o
V
in
i
L
i
in
V
+
A
q
+
A
v
+
o
V
in
i
L
i
A s
d T
s
T
A
q
A
v
L
i
in
i
0
0
0
0
t
in
V
t
t
t
1
A s
d T
s
T
A
q
A
v
L
i
in
i
0
0
0
0
t
in
V
t
t
t
1
(a)
(b)
A
v
Figure 1-23 Waveforms in the converter of Example 1-2.
A
q
A
v
20
in
V V =
12
o
V V =
0
1
3 s
5 s
t
t
0
A
q
A
v
20
in
V V =
12
o
V V =
0
1
3 s
5 s
t
t
A
q
A
v
20
in
V V =
12
o
V V =
0
1
3 s
5 s
t
t
0
Example 1-2 In the converter of Fig. 1-22a, the input voltage 20
in
V V = . The
output voltage 12
o
V V = . Calculate the duty-ratio
A
d and the pulse
width
up
T , if the switching frequency 200
s
f kHz = .
Solution 12
A o
v V V = = . Using Eq. 1-4,
12
0.6
20
o
A
in
V
d
V
= = = and
1
5
s
s
T s
f
= = .
Therefore, as shown in Fig. 1-23, 0.6 5 3
up A s
T d T s s = = = .
Transistor and diode forming a switching power-pole
in a Buck converter
Figure 1-24 Transistor and diode forming a switching power-pole in a Buck converter.
(b) (c)
(a)
in
V
+
L
i
L
i
L
i
1
A
q = 0
A
q =
+
o
V
+
o
V
+
o
V
in
V
+
in
V
+
(b) (c) (c)
(a)
in
V
+
L
i
L
i
L
i
1
A
q = 0
A
q =
+
o
V
+
o
V
+
o
V
in
V
+
in
V
+
RECENT AND POTENTIAL ADVANCEMENTS
Devices that can handle voltages in kVs and currents in kAs
ASICs
DSPs
Micro-controllers
FPGA
Integrated and intelligent power modules
Packaging
SiC-based solid-state devices
High energy density capacitors
CONCEPT OF PEBB
It has numerous benefits such as technology insertion and upgrade via
standard interfaces, reduced maintenance via plug and play modules,
reduced cost via increased product development efficiency, reduced time to
market, reduced commissioning cost, reduced design and development risk,
a nd i nc r e a s e d compet i t i on i n cr i t i cal t echnol ogi es [ 14] .
Power Electronics Building Block (PEBB) [15] is a broad concept that
incorporates the progressive integration of power devices, gate drives,
and other components into building blocks, with clearly defined
functionality that provides interface capabilities able to serve multiple
applications. This building block approach results in reduced cost,
losses, weight, size, and engineering effort for the application and
maintenance of power electronics systems. Based on the functional
specifications of PEBB and the performance requirements of the
intended applications, the PEBB designer addresses the details of
device stresses, stray inductances, switching speed, losses, thermal
management, protection, measurements of required variables, control
interfaces, and potential integration issues at all levels.
Chapter 2 Design of Switching Power-Pole
2-1 Power Transistors and Power Diodes
2-2 Selection of Power Transistors
2-3 Selection of Power Diodes
2-4 Switching Characteristics and Power Losses in Power-Poles
2-5 Justifying Switches and Diodes as Ideal
2-6 Design Considerations
2-7 The PWM Controller IC
References
Problems
Appendix 2A Diode Reverse-Recovery and Power Losses
POWER TRANSISTORS AND POWER DIODES
Voltage Rating
Current Rating
Switching Speeds
On-State Voltage
SELECTION OF POWER TRANSISTORS
MOSFETs
IGBTs
IGCTs
GTOs
Niche devices: BJTs, SITs, MCTs
Figure 15-1 Power semiconductor devices.
Thyristor IGBT MOSFET IGCT
(a)
10
1
10
2
10
3
10
4
10
2
10
4
10
6
10
8
T
h
y
r
i
s
t
o
r
IGBT
MOSFET
P
o
w
e
r

(
V
A
)
Switching Frequency (Hz)
IGCT
(b)
(a)
(a)
10
1
10
2
10
3
10
4
10
2
10
4
10
6
10
8
T
h
y
r
i
s
t
o
r
IGBT
MOSFET
P
o
w
e
r

(
V
A
)
IGCT
(b)
10
1
10
2
10
3
10
4
10
2
10
4
10
6
10
8
T
h
y
r
i
s
t
o
r
IGBT
MOSFET
P
o
w
e
r

(
V
A
)
IGCT
10
1
10
2
10
3
10
4
10
2
10
4
10
6
10
8
T
h
y
r
i
s
t
o
r
IGBT
MOSFET
P
o
w
e
r

(
V
A
)
IGCT
(b)
MOSFETs
2.5 2.7
( )
to
DS on DSS
R V
Figure 2-1 MOSFET: (a) symbol, (b) i-v characteristics, (c) transfer characteristic.
G
D
S
GS
V
+
DS
V
D
i
+
(a) (c) (b)

GS
V 11V =
9V
7V
5V
DS
V
D
i
0
( ) GS GS th
V V
( )
1/slope
DS on
R =
GS
V
D
i
0
o
I
( ) GS th
V
( )
o
GS I
V
IGBTs
Figure 2-2 IGBT: (a) symbol, (b) i-v characteristics.
+
C
E
G
CE
V
GE
V
+
C
i
GE
V
CE
V
C
i
(a) (b)
+
C
E
G
CE
V
GE
V
+
C
i
+
C
E
G
CE
V
GE
V
+
C
i
GE
V
CE
V
C
i
GE
V
CE
V
C
i
(a) (b)
Power Semiconductor Price Trends
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
1990 1995 2000 2005
USD/A
Pricing (USD/A) 1200 V IGBTs
SELECTION OF POWER DIODES
Line-frequency diodes
Fast-recovery diodes
Schottky diodes
SiC Schottky diodes
Figure 2-3 Diode: (a) symbol, (b) i-v characteristic.
(a) (b)
A
K
AK
i
AK
v
0
(a) (b)
A
K
AK
i
AK
v
0
SWITCHING CHARACTERISTICS AND
POWER LOSSES IN POWER-POLES
Figure 2-4 MOSFET in a switching power-pole.
(a) (b)
in
V
+
D
i
o
I
D
i
0
DS
v
off
on
o
I
GG
R
GG
V
DS
v
+
in
V
(a) (b)
in
V
+
D
i
o
I
D
i
0
DS
v
off
on
o
I
GG
R
GG
V
DS
v
+
in
V
Turn-on Characteristic
Figure 2-5 MOSFET turn-on.
(c) (b)
D
i
DS
v
o
I
on
off
A
0
0
0
GS
v
t
t
o
I
D
i
in
V DS
v
( ) d on
t
ri
t
fv
t
GG
v
(a)
o
I
in
V
+
G
S
D
D
i
0
GG
v
B
DS
v
in
V
( )
o
GS I
v
( ) GS th
v
(c) (b)
D
i
DS
v
o
I
on
off
A
0
0
0
GS
v
t
t
o
I
D
i
in
V DS
v
( ) d on
t
ri
t
fv
t
GG
v
(a)
o
I
in
V
+
G
S
D
D
i
0
GG
v
B
DS
v
in
V
( )
o
GS I
v
( ) GS th
v
Example 2-1 In the converter of Fig. 2-4a, the transistor is a MOSFET which carries
a current of 5 A when it is fully on. If the current through the
transistor is to be limited to 40 A during a malfunction in which case
the entire input voltage of 50 V appears across the transistor, what
should be the maximum on-state gate voltage that the gate-drive circuit
should provide? Assume the junction temperature
j
T of the MOSFET
to be
0
175 C .
Solution The transfer characteristic of this MOSFET is shown in Fig. 2-6. It shows that
if 7.5
GS
V V = is used, the current through the MOSFET will be limited to 40 A.
Figure 2-6 MOSFET transfer characteristic.
40 A
10 A
1A
0.1A
100 A
4.0 5.0 6.0 7.0 8.0 9.010.0
7.5V
D
I
GS
V
40 A
10 A
1A
0.1A
100 A
4.0 5.0 6.0 7.0 8.0 9.010.0
7.5V
D
I
GS
V
Turn-off Characteristic
Figure 2-7 MOSFET turn-off.
(a)
o
I
in
V
+
G
S
D
D
i
0
GG
v
(b)
D
i
DS
v
o
I
on
off
D
0
C
(c)
0
0
GS
v
t
t
o
I
D
i
in
V
DS
v
( ) d off
t
rv
t
fi
t
GG
v
( )
o
GS I
v
( ) GS th
v
DS
v
in
V
(a)
o
I
in
V
+
G
S
D
D
i
0
GG
v
(b)
D
i
DS
v
o
I
on
off
D
0
C
(c)
0
0
GS
v
t
t
o
I
D
i
in
V
DS
v
( ) d off
t
rv
t
fi
t
GG
v
( )
o
GS I
v
( ) GS th
v
DS
v
in
V
PSpice Modeling: C:\FirstCourse_PE_Book07\Power_pole_PSpice_Diode.sch
Time
0s 0.2us 0.4us 0.6us 0.8us 1.0us 1.2us 1.4us 1.6us
V(M2:d,M2:s) -I(V2)
-10
0
10
20
30
40
50
DS
v
D
i
Simulation Results: MOSFET Voltage and Current
Calculating Power Losses Within the MOSFET
(assuming an ideal diode)
Conduction Loss:
2
( ) cond DS on o
P d R I =
Switching Losses:
, ,
1
( )
2
sw in o c on c off s
P V I t t f = +
, c on ri fv
t t t = +
, c off rv fi
t t t = +
Figure 2-8 MOSFET switching losses.
0
t
o
I
DS
v
, c on
t
ri
t fv
t
0
t
D
i
in
V
, c off
t
rv
t fi
t
DS
v
in
V
D
i
, c on
t
, c off
t
sw
p
in o
V I
in o
V I
sw
p
0
t
o
I
DS
v
, c on
t
ri
t fv
t
0
t
D
i
in
V
, c off
t
rv
t fi
t
DS
v
in
V
D
i
, c on
t
, c off
t
sw
p
in o
V I
in o
V I
sw
p
Gate Driver Integrated Circuits (ICs) with Built-
in Fault Protection
Figure 2-9 Gate-driver IC functional diagram.
12
ext
V V =
CC
V
c
v
S
12
ext
V V =
CC
V
c
v
S
JUSTIFYING SWITCHES AND DIODES AS
IDEAL
Very High Converter Efficiencies
Low on-state voltage drops across devices
Low switching losses
Switching Frequency
Selection of Transistors and Diodes
Magnetic components
Capacitor Selection
DESIGN CONSIDERATIONS
max max
rms
p
w
LII
A
k J B
=
,
max max
conv y y rms
p
w s
k V I
A
k B J f
=

Figure 2-10 Capacitor ESR and ESL.
C ESL ESR C ESL ESR
PSpice Modeling: C:\FirstCourse_PE_Book07\Capacitor_Characteristics.sch
Frequency
1.0KHz 3.0KHz 10KHz 30KHz 100KHz 300KHz 1.0MHz
I(L2) I(L1) -I(V3)
0A
10A
20A
30A
40A
50A
Simulation Results: Individual and Total Admittances
Thermal Design
( )
j a jc cs sa diss
T T R R R P

= + + +
Figure 2-11 Thermal design: (a) semiconductor on a heat sink, (b) electrical analog.
jc
R
diss
P
(b)
cs
R
sa
R
a
T
a
T
s
T
c
T
j
T
(a)
chip
heat sink isolation pad
j
T
c
T
s
T
a
T
ambient
case
jc
R
diss
P
(b)
cs
R
sa
R
a
T
a
T
s
T
c
T
j
T
(a)
chip
heat sink isolation pad
j
T
c
T
s
T
a
T
ambient
case
Design Tradeoffs
Magnetics and
capacitors
size
Heatsink
S
f
Magnetics and
capacitors
size
Heatsink
S
f
Figure 2-12 Size of magnetic components and
heat sink as a function of frequency.
PWM CONTROLLER IC
( )
( )
c
r
v t
d t
V
=
Figure 2-13 PWMICwaveforms.
0
s
dT
s
T
t
r
V
( )
c
v t
t
r
v
( ) q t
0
1
0
s
dT
s
T
t
r
V
( )
c
v t
t
r
v
( ) q t
0
1
APPENDIX 2A: Diode Reverse Recovery and Power Losses
Diode Forward Loss: ,
(1 )
diode F FM o
P d V I =
Diode Reverse Recovery Characteristic:
Diode Switching Losses:
, ,
1
( )
2
diode sw RRM b d neg s
P I t V f =
Figure 2A-1 Diode reverse recovery characteristic.
0
rr
t
a
t
b
t
RRM
I
t
t
0
FM
V
, d neg
V
rr
Q
0
rr
t
a
t
b
t
RRM
I
t
t
0
FM
V
, d neg
V
rr
Q
PSpice Modeling: C:\FirstCourse_PE_Book07\ Power_pole_MUR2020.sch
Time
0s 0.2us 0.4us 0.6us 0.8us 1.0us 1.2us 1.4us 1.6us
V(M2:d,M2:s) -I(V2)
-10
0
10
20
30
40
50
Simulation Results: MOSFET Voltage and Current
Example 2A-1 In the switching power-pole of Fig. 2-4a, 40
in
V V = and the output
current is 5
o
I A = . The switching frequency 200
s
f kHz = . The MOSFET switching
times are 15 and 15
ri fv
t ns t ns = = . The diode snaps-off at reverse recovery such that
20
rr a
t t ns = = (such that 0
b
t = ) and the peak reverse-recovery current 2
RRM
I A = .
Calculate the additional power loss in the MOSFET due to the diode reverse recovery.
Figure 2A-2 Waveforms with diode reverse-recovery current.
DS
v
0
0
0 t
t
t
ri
t
in
V
fv
t
a rr
t t =
o
I
D
i
RRM
I
sw
p
fv
t
DS
v
0
0
0 t
t
t
ri
t
in
V
fv
t
a rr
t t =
o
I
D
i
RRM
I
sw
p
fv
t
Chapter 3 Switch-Mode DC-DC Converters: Switching Analysis, Topology
Selection and Design
3-1 DC-DC Converters
3-2 Switching Power-Pole in DC Steady State
3-3 Simplifying Assumptions
3-4 Common Operating Principles
3-5 Buck Converter Switching Analysis in DC Steady State
3-6 Boost Converter Switching Analysis in DC Steady State
3-7 Buck-Boost Converter Switching Analysis in DC Steady State
3-8 Topology Selection
3-9 Worst-Case Design
3-10 Synchronous-Rectified Buck Converter for Very Low Output Voltages
3-11 Interleaving of Converters
3-12 Regulation of DC-DC Converters by PWM
3-13 Dynamic Average Representation of Converters in CCM
3-14 Bi-Directional Switching Power-Pole
3-15 Discontinuous-Conduction Mode (DCM)
References
Problems
Regulated switch-mode dc power supplies
Figure 3-1 Regulated switch-mode dc power supplies.
in
V
o
V
, o ref
V
controller
dc-dc
converter
topology
,
in o
V V
,
in o
I I
(a) (b)
in
V
o
V
, o ref
V
controller
dc-dc
converter
topology
,
in o
V V
,
in o
I I
(a) (b)
Switching power-pole as the building block of dc-dc converters
( ) ( )
L L s
i t i t T =
0
area
area
1
0
s s
s
DT T
L L L
s DT
A
B
V v d v d
T

= + =

_
_
( ) ( )
C C s
v t v t T =
Figure 3-2 Switching power-pole as the building block of dc-dc converters.
in
V
L
v
L
i
q
A
L
v
L
i
t
t
B
0
0
s
DT
s
T
( ) b ( ) a
in
V
L
v
L
i
q
in
V
L
v
L
i
q
A
L
v
L
i
t
t
B
0
0
s
DT
s
T
L
v
L
i
t
t
B
0
0
s
DT
s
T
( ) b ( ) a
Example 3-1 If the current waveform in steady state in an inductor of 50 H is as
shown in Fig. 3-3a, calculate the inductor voltage waveform ( )
L
v t .
Solution During the current rise-time,
(4 3) 1
3 3
di A
dt s

= =

. Therefore,
1
50 16.67
3
L
di
v L V
dt

= = = .
During the current fall-time,
(3 4) 1
2 2
di A
dt s

= =

. Therefore,
1
50 ( ) 25
2
L
di
v L V
dt

= = = .
Therefore, the inductor voltage waveform is as shown in Fig. 3-3b.
Figure 3-3 Example 3-1.
L i
0
3A
4A
3 s
5 s
16.67V
t
L v
0
t
25V
( ) a
( ) b
L i
0
3A
4A
3 s
5 s
16.67V
t
L v
0
t
25V
( ) a
( ) b
C i
0
0.5A
0.5A
t
, C ripple v
0
t
( ) a
( ) b
3 s 2 s
2.5 s
1 t 2 t
p p V
Q
C i
0
0.5A
0.5A
t
, C ripple v
0
t
( ) a
( ) b
3 s 2 s
2.5 s
1 t 2 t
p p V
Q
Example 3-2 The capacitor current
C
i , shown in Fig. 3-4a, is flowing through a
capacitor of 100 F . Calculate the peak-peak ripple in the capacitor
voltage waveform due to this ripple current.
Solution For the given capacitor current waveform, the capacitor voltage waveform, as
shown in Fig. 3-4b, is at its minimum at time
1
t , prior to which the capacitor current has
been negative. This voltage waveform reaches its peak at time
2
t , beyond which the
current becomes negative.
The hatched area in Fig. 3-4a equals the charge Q

2
1
1
0.5 2.5 0.625
2
t
C
t
Q i dt C = = =

Using Eq. 3-6, the peak-peak ripple in the capacitor voltage is 6.25
p p
Q
V mV
C
= = .

Simplifying Assumptions
Two-Step Process
Common Operating Principles
BUCK CONVERTER SWITCHING ANALYSIS IN DC STEADY STATE
o A in
V V DV = =
(1 )
in o o
L s s
V V V
i DT D T
L L
= =
o
L o
V
I I
R
= =
,
( ) ( )
C L ripple
i t i t =
in L o
I DI DI = =
in in o o
V I V I =
Figure 3-5 Buck dc-dc converter.
in
V
L
i
A
v
L in o
v V V =
L
v
o
V
1 q =
in
V
L
i
A
v
L o
v V =
o
V
0 q =
0
A
v =
in
V
in
i
L
i
A
v
L
v
o
V
q
C
i
o
I
(a)
(b)
q
A
v
L
v
, L ripple
i
L
i
in
i
in
V
A o
V V =
( )
in o
V V
( )
o
V
L
i
L o
I I =
in
I
A
B
t
t
t
t
t
t 0
0
0
0
0
0
1
(c)
(d)
in
V
L
i
A
v
L in o
v V V =
L
v
o
V
1 q =
L
i
A
v
L in o
v V V =
L
v
o
V
1 q =
in
V
L
i
A
v
L o
v V =
o
V
0 q =
0
A
v =
in
V
L
i
A
v
L o
v V =
o
V
0 q =
0
A
v =
in
V
in
i
L
i
A
v
L
v
o
V
q
C
i
o
I
(a)
(b)
q
A
v
L
v
, L ripple
i
L
i
in
i
in
V
A o
V V =
( )
in o
V V
( )
o
V
L
i
L o
I I =
in
I
A
B
t
t
t
t
t
t 0
0
0
0
0
0
1
q
A
v
L
v
, L ripple
i
L
i
in
i
in
V
A o
V V =
( )
in o
V V
( )
o
V
L
i
L o
I I =
in
I
A
B
t
t
t
t
t
t 0
0
0
0
0
0
1
(c)
(d)
Example 3-3 In the Buck dc-dc converter of Fig. 3-5a, 24 L H = . It is operating in
dc steady state under the following conditions: 20
in
V V = , 0.6 D = , 14
o
P W = , and
200
s
f kHz = . Assuming ideal components, calculate and draw the waveforms shown
earlier in Fig. 3-5d.
Solution With 200
s
f kHz = , 5
s
T s = and 3
on s
T DT s = = . 12
o in
V DV V = = .
The inductor voltage
L
v fluctuates between ( ) 8
in o
V V V = and ( ) 12
o
V V = , as shown in
Fig. 3-6.
L
i
, L ripple
i
L
v
A
v
q
in
i
t
t
t
t
t
t
20
in
V =
12
A o
V V V = =
( ) 8
in o
V V V =
12
o
V V =
L
i
1
L o
I I A = =
0.6
in
I A =
3 s
5 s
0
1
0
0
0
0
0
1.5
1.5
0.5
0.5
0.5
0.5
L
i
, L ripple
i
L
v
A
v
q
in
i
t
t
t
t
t
t
20
in
V =
12
A o
V V V = =
( ) 8
in o
V V V =
12
o
V V =
L
i
1
L o
I I A = =
0.6
in
I A =
3 s
5 s
0
1
0
0
0
0
0
1.5
1.5
0.5
0.5
0.5
0.5
0.5 A
0.5 A
1
L
i A =
0 1.167 L I I A = = 0.667A
1.667A
1.667A
0.667A
0.7 in I A =
Fig. 3-6
PSpice Modeling: C:\FirstCourse_PE_Book07\Buckconv.sch
Simulation Results
Time
450us 455us 460us 465us 470us 475us 480us 485us 490us 495us 500us
I(C1) I(L1) V(L1:1,L1:2)
-8
-4
0
4
8
12
16
BOOST CONVERTER SWITCHING ANALYSIS IN DC STEADY STATE
Figure 3-7 Boost dc-dc converter.
o
V
in
V
q p
C
L
v
L
i
in
V
o
V
p
C
L
v
q
L
i
(a) (b)
o
V
in
V
q p
C
L
v
L
i
o
V
in
V
q p
C
L
v
L
i
in
V
o
V
p
C
L
v
q
L
i
in
V
o
V
p
C
L
v
q
L
i
(a) (b)
Boost converter: operation and waveforms
1
1
o
in
V
V D
=
( )
o in
V V >
(1 )
in o in
L s s
V V V
i DT D T
L L
= =
in in o o
V I V I =
1
1 1
o o o
L in o
in
V I V
I I I
V D D R
= = = =

,
( ) ( )
C diode ripple diode o
i t i t i I = =
Figure 3-8 Boost converter: operation and waveforms.
in
V
o
V
L in
v V =
L
i 0
A
v =
1 q =
in
V
o
V
L in o
v V V =
L
i
0 q =
A o
v V =
L
v
A
v
q
, L ripple
i
L
i
diode
i
C
i
t
t
t
t
t
t
t 0
0
0
0
0
0
0
o
V
A in
v V =
A
B
( )
o in
V V
L
i
L
I
( )
diode o
I I =
in
V
(a)
(b) (c)
0
( ) I
in
V
o
V
L in
v V =
L
i 0
A
v =
1 q =
in
V
o
V
L in
v V =
L
i 0
A
v =
1 q =
in
V
o
V
L in o
v V V =
L
i
0 q =
A o
v V =
L
v
A
v
q
, L ripple
i
L
i
diode
i
C
i
t
t
t
t
t
t
t 0
0
0
0
0
0
0
o
V
A in
v V =
A
B
( )
o in
V V
L
i
L
I
( )
diode o
I I =
in
V
(a)
(b) (c)
0
( ) I
Example 3-4 In a Boost converter of Fig. 3-8a, the inductor current has 2
L
i A = . It
is operating in dc steady state under the following conditions: 5
in
V V = , 12
o
V V = ,
11
o
P W = , and 200
s
f kHz = . (a) Assuming ideal components, calculate L and draw the
waveforms as shown in Fig. 3-8c.
Solution From Eq. 3-19, the duty-ratio 0.583 D = . With 200
s
f kHz = , 5
s
T s = and
2.917
on s
T DT s = = .
L
v fluctuates between 5
in
V V = and ( ) 7
o in
V V V = . Using the
conditions during the transistor on-time, from Eq. 3-21,
7.29
in
s
L
V
L DT H
i
= =
.
The average inductor current is ( ) / 2.2
L in in o in
I I P P V A = = = = , and
, L L L ripple
i I i = + . When
the transistor is on, the diode current is zero; otherwise
diode L
i i = . The average diode
current is equal to the average output current:
(1 ) 0.917
diode o in
I I D I A = = = .
The capacitor current is
C diode o
i i I = . When the transistor is on, the diode current is zero
and 0.917
C o
i I A = = . The capacitor current jumps to a value of 2.283 A and drops to
1 0.917 0.083 A = .
L
v
A
v
q
, L ripple
i
in
i
diode
i
C
i
t
0
0
0
0
0
0
12
o
V V = 5
A in
v V V = =
( ) 7
o in
V V V =
2
L
i A =
2.2
L
I A =
( ) 0.917
diode o
I I A = =
5
in
V V =
3 s
5 s
t
t
t
t
t
t
0
1A
1A
0.917 A
2.283A
0.283A
3.2 A
1.2 A
3.2 A
1.2 A
L
v
A
v
q
, L ripple
i
in
i
diode
i
C
i
t
0
0
0
0
0
0
12
o
V V = 5
A in
v V V = =
( ) 7
o in
V V V =
2
L
i A =
2.2
L
I A =
( ) 0.917
diode o
I I A = =
5
in
V V =
3 s
5 s
t
t
t
t
t
t
0
1A
1A
0.917 A
2.283A
0.283A
3.2 A
1.2 A
3.2 A
1.2 A
PSpice Modeling: C:\FirstCourse_PE_Book07\Boost.sch
Time
1.950ms 1.955ms 1.960ms 1.965ms 1.970ms 1.975ms 1.980ms 1.985ms 1.990ms 1.995ms 2.000ms
I(L1) V(L1:1,L1:2)
-15
-10
-5
0
5
10
15
Simulation Results
Boost converter: voltage transfer ratio
Figure 3-10 Boost converter: voltage transfer ratio.
0
1
1 D
, L crit
I
DCM CCM
L
I
o
in
V
V
1
0
1
1 D
, L crit
I
DCM CCM
L
I
o
in
V
V
1
BUCK-BOOST CONVERTER ANALYSIS IN DC
STEADY STATE
Figure 3-11 Buck-Boost dc-dc converter.
q
A
A
v
L
v
L
i
in
V
o
V
diode
i
o
I
L
v
A
v
o
V
in
V
o
I
(a) (b)
L
i
q
A
A
v
L
v
L
i
in
V
o
V
diode
i
o
I
q
A
A
v
L
v
L
i
in
V
o
V
diode
i
o
I
L
v
A
v
o
V
in
V
o
I
(a) (b)
L
i
Buck-Boost converter: operation and waveforms
1
o
in
V D
V D
=
(1 )
in o
L s s
V V
i DT D T
L L
= =
L in o
I I I = +
in in o o
V I V I =
1
o
in o o
in
V D
I I I
V D
= =
1 1
1 1
o
L in o o
V
I I I I
D D R
= + = =

,
( ) ( )
C diode ripple
i t i t =
Figure 3-12 Buck-Boost converter: operation and waveforms.
in
i
L in
v V =
A in o
v V V = +
o
V
in
V
L
i
in
V
L
i
L o
v V =
0
A
v =
o
V
(a)
(b)
L
v
A
v
q
, L ripple
i
L
i
diode
i
C
i
t
t
t
t
t
t
t 0
0
0
0
0
0
0
o
V
A
B
( )
in o
V V +
L
i
L
I
( )
diode o
I I =
in
V
(c)
in
i
o
I
o
I
s DT
s
T
A o
V V =
0
( ) I
in
i
L in
v V =
A in o
v V V = +
o
V
in
V
L
i
L in
v V =
A in o
v V V = +
o
V
in
V
L
i
in
V
L
i
L o
v V =
0
A
v =
o
V
(a)
(b)
L
v
A
v
q
, L ripple
i
L
i
diode
i
C
i
t
t
t
t
t
t
t 0
0
0
0
0
0
0
o
V
A
B
( )
in o
V V +
L
i
L
I
( )
diode o
I I =
in
V
(c)
in
i
o
I
o
I
s DT
s
T
A o
V V =
0
( ) I
Example 3-5 A Buck-Boost converter of 3-11b is operating in dc steady state under
the following conditions: 14
in
V V = , 42
o
V V = , 21
o
P W = , 1.8
L
i A = and 200
s
f kHz = .
Assuming ideal components, calculate L and draw the waveforms as shown in Fig. 3-
12c.
Solution From Eq. 3-26, 0.75 D = . 1/ 5
s s
T f s = = and 3.75
on s
T DT s = = as shown in
Fig. 3-13. The inductor voltage
L
v fluctuates between 14
in
V V = and 42
o
V V = . Using
Eq. 3-28
29.17
in
s
L
V
L DT H
i
= =
.
The average input current is ( ) / 1.5
in in o in
I P P V A = = = . / 0.5
o o o
I P V A = = . Therefore,
2
L in o
I I I A = + = . When the transistor is on, the diode current is zero; otherwise
diode L
i i = .
The average diode current is equal to the average output current: 0.5
diode o
I I A = = . The
capacitor current is
C diode o
i i I = . When the transistor is on, the diode current is zero and
0.5
C o
i I A = = . The capacitor current jumps to a value of 2.4 A and drops to
1.1 0.5 0.6A = .

L
v
A
v
q
, L ripple
i
L
i
diode
i
C
i
t
t
t
t
t
t
t
0
0
0
0
0
0
0
42
o
V V =
( ) 56
in o
V V V + =
1.8
L
i A =
2
L
I A =
( ) 0.5
diode o
I I A = =
14
in
V V =
3.75 s
5 s
42
A o
V V V = =
0.9 A
0.9 A
2.9A
1.1A
2.9A
1.1A
2.4A
0.5A
0.6A
L
v
A
v
q
, L ripple
i
L
i
diode
i
C
i
t
t
t
t
t
t
t
0
0
0
0
0
0
0
42
o
V V =
( ) 56
in o
V V V + =
1.8
L
i A =
2
L
I A =
( ) 0.5
diode o
I I A = =
14
in
V V =
3.75 s
5 s
42
A o
V V V = =
0.9 A
0.9 A
2.9A
1.1A
2.9A
1.1A
2.4A
0.5A
0.6A
PSpice Modeling: C:\FirstCourse_PE_Book07\Buck-Boost_Switching.sch
Simulation Results
Time
I(L1) V(L1:1,L1:2)
-30
-20
-10
0
10
20
Buck-Boost converter: voltage transfer ratio
Figure 3-14 Buck-Boost converter: voltage transfer ratio.
0
1
D
D
, L crit
I
DCM
CCM
L
I
o
in
V
V
0
1
D
D
, L crit
I
DCM
CCM
L
I
o
in
V
V
Other Buck-Boost Topologies
SEPIC Converters (Single-Ended Primary Inductor Converters)
Cuk Converters
SEPIC Converters (Single-Ended Primary Inductor Converters)
(1 )
in o
DV D V =
1
o
in
V D
V D
=
Figure 3-15 SEPIC converter.

in
V
2 L
i
q
C
v
o
V
L
i
diode
i
2 L
v
(a)
in
V
C
v
o
V
2 L C
v v = 1 q =
2 L
v
o
V
in
V
0 q =
C
v
2 L
v
2 L o
v V =
(b) (c)
in
V
2 L
i
q
C
v
o
V
L
i
diode
i
2 L
v
(a) in
V
2 L
i
q
C
v
o
V
L
i
diode
i
2 L
v
in
V
2 L
i
q
C
v
o
V
L
i
diode
i
2 L
v
(a)
in
V
C
v
o
V
2 L C
v v = 1 q =
2 L
v
o
V
in
V
0 q =
C
v
2 L
v
2 L o
v V =
(b) (c)
in
V
C
v
o
V
2 L C
v v = 1 q =
2 L
v
in
V
C
v
o
V
2 L C
v v = 1 q =
2 L
v
o
V
in
V
0 q =
C
v
2 L
v
2 L o
v V =
o
V
in
V
0 q =
C
v
2 L
v
2 L o
v V =
(b) (c)
Cuk Converter
(1 )
o in
DI D I =
1
in
o
I D
I D
=
1
o
in
V D
V D
=
Figure 3-16 Cuk converter.

in
V
q
C
v
o
V
L
i
o
i
o
I
C
1
L
2
L
(a)
in
V
1 q =
C
v
o
V
in
i
o
i
in
V
0 q =
C
v
o
V
in
i
o
i
(b) (c)
in
V
q
C
v
o
V
L
i
o
i
o
I
C
1
L
2
L
(a)
in
V
q
C
v
o
V
L
i
o
i
o
I
C
1
L
2
L
in
V
q
C
v
o
V
L
i
o
i
o
I
C
1
L
2
L
(a)
in
V
1 q =
C
v
o
V
in
i
o
i
in
V
0 q =
C
v
o
V
in
i
o
i
(b) (c)
TOPOLOGY SELECTION
Criterion Buck Boost Buck-Boost
Transistor
V in
V
o
V ( )
in o
V V +
Transistor
I o
I
in
I
in o
I I +
rms
I Transistor
o
DI
in
DI ( )
in o
D I I +
Transistor
o
DI
in
DI
( )
in o
D I I +
avg
I
Diode (1 )
o
D I (1 )
in
D I
( ) (1 )
in o
D I I +
L
I
o
I
in
I
in o
I I +
Effect of L onC significant little little
Pulsating Current input output both

WORST-CASE DESIGN
The worst-case design should consider the ranges in which the input voltage and the
output load vary. As mentioned earlier, often converters above a few tens of watts are
designed to operate in CCM. To ensure CCM even under very light load conditions
would require prohibitively large inductance. Hence, the inductance value chosen is
often no larger than three times the critical inductance ( ) 3
c
L L < , where, as discussed in
section 3-15, the critical inductance
c
L is the value of the inductor that will make the
converter operate at the border of CCM and DCM at full-load.
SYNCHRONOUS-RECTIFIED BUCK CONVERTER FOR
VERY LOW OUTPUT VOLTAGES
Figure 3-17 Buck converter: synchronous rectified.
in
V
o
V
A
v
T
+
T
q
+
q
L
i
( ) a
q
+
q
A
v
L
i
t
t
t
0 t =
s
DT
s
T
in
V
o
V
0
0
0
0
L
I
( ) b
in
V
o
V
A
v
T
+
T
q
+
q
L
i
( ) a
in
V
o
V
A
v
T
+
T
q
+
q
L
i
( ) a
q
+
q
A
v
L
i
t
t
t
0 t =
s
DT
s
T
in
V
o
V
0
0
0
0
L
I
( ) b
q
+
q
A
v
L
i
t
t
t
0 t =
s
DT
s
T
in
V
o
V
0
0
0
0
L
I
( ) b
INTERLEAVING OF CONVERTERS
Figure 3-18 Interleaving of converters.
1
q
2
q
1
q
2
q
0
0
t
t
(a) (b)
in
V
+
+
o
V
1 L
i
2 L
i
1
q
2
q
1
q
2
q
0
0
t
t
(a) (b)
in
V
+
+
o
V
1 L
i
2 L
i
REGULATION OF DC-DC CONVERTERS BY PWM
( )
( )
c
r
v t
d t
V
=
Figure 3-19 Regulation of output by PWM.
in
V
o
V
, o ref
V
controller
dc-dc
converter
topology
(a) (b)
0
s
d T
s
T
t
r
V
( )
c
v t
t
r
v
( ) q t
0
1
in
V
o
V
, o ref
V
controller
dc-dc
converter
topology
(a) (b)
0
s
d T
s
T
t
r
V
( )
c
v t
t
r
v
( ) q t
0
1
DYNAMIC AVERAGE REPRESENTATION OF
CONVERTERS IN CCM
( ) ( ) ( )
cp vp
v t d t v t =
( ) ( ) ( )
vp cp
i t d t i t =
cp vp
V DV =
vp o
I DI =
Figure 3-20 Average dynamic model of a switching power-pole.
( ) q t
( )
r
v t
( )
c
v t
vp
v
cp
v
cp
i
vp
i
vp
V
cp
V
cp
I
vp
I
1: D
cp
v
1: ( ) d t
( )
c
v t
^
1
r V
(c) (a) (b)
vp
i
vp
v
cp
i
( ) q t
( )
r
v t
( )
c
v t
vp
v
cp
v
cp
i
vp
i
vp
V
cp
V
cp
I
vp
I
1: D
cp
v
1: ( ) d t
( )
c
v t
^
1
r V
(c) (a) (b)
vp
i
vp
v
cp
i
Average dynamic models of three converters
Figure 3-21 Average dynamic models: Buck (left), Boost (middle) and Buck-Boost (right).
q
in
V
o
v
L
v
L
i
o
V
in
V
q
p
A
A
q
o
V
in
V
in
V
1: ( ) d t
in
V
1: (1 ( )) d t
p
1: ( ) d t
in
V
(a)
(b)
L
i
L
i
L
i
L
i
L
i
o
v o
v
o
v

q
in
V
o
v
L
v
L
i
o
V
in
V
q
p
A
A
q
o
V
in
V
in
V
1: ( ) d t
in
V
1: (1 ( )) d t
p
1: ( ) d t
in
V
(a)
(b)
L
i
L
i
L
i
L
i
L
i
o
v o
v
o
v

PSpice Modeling: C:\FirstCourse_PE_Book07\Buck-Boost_Avg_CCM.sch
PSpice Modeling: C:\FirstCourse_PE_Book07\Buck-Boost_Switching_LoadTransient.sch
Simulation Results
Time
0s 0.5ms 1.0ms 1.5ms 2.0ms 2.5ms 3.0ms 3.5ms 4.0ms 4.5ms 5.0ms
I(L1) V(L1:1,L1:2)
-40
-20
0
20
40
BI-DIRECTIONAL SWITCHING POWER-POLE
Figure 3-22 Bi-directional power flow through a switching power-pole.
q
in
V
L
i
Buck Boost
(1 ) q q
=
in
V
1 q =
0 q =
Buck
0( 1) q q
= =
1( 0) q q
= =
in
V
Boost
(a) (b) i
L
= positive (c) i
L
= negative
q q
q
q
in
V
L
i
Buck Boost
(1 ) q q
=
in
V
1 q =
0 q =
Buck
0( 1) q q
= =
1( 0) q q
= =
in
V
Boost
(a) (b) i
L
= positive (b) i
L
= positive (c) i
L
= negative (c) i
L
= negative
q q
q

Average dynamic model of the switching power-pole with
bi-directional power flow
Figure 3-23 Average dynamic model of the switching power-pole with bi-directional power
flow.
q
in
V
L
i
Buck Boost
(1 ) q q
= 1: d
L
i
in
V
(a) (c) (b)
L
i
q
1 q =
q
in
V
L
i
Buck Boost
(1 ) q q
= 1: d
L
i
in
V
(a) (c) (b)
L
i
q
1 q =
DISCONTINUOUS-CONDUCTION MODE (DCM)
Figure 3-24 Inductor current at various loads; duty-ratio is kept constant.
1 L
i
2 L
i
, L cri
i
1 L
I
2 L
I
, L crit
I
t
L
i
0
1 L
i
2 L
i
, L cri
i
1 L
I
2 L
I
, L crit
I
t
L
i
0
, , , , -
2
in
L crit Boost L crit Buck Boost
s
V
I I D
Lf
= =
, ,
(1 )
2
in
L crit Buck
s
V
I D D
Lf
=
Critical Inductor Currents
and Load Resistances
,
, 2
, 2
2
(1 )
2
(1 )
2
(1 )
s
crit Buck
s
crit Boost
s
crit Buck Boost
Lf
R
D
Lf
R
D D
Lf
R
D

Buck converter in DCM
Figure 3-25 Buck converter in DCM.
L
i
L
I s
t
T
A
v
o
V
in
V
0
0
D ,1 off
D
,2 off
D
1
o
in
V
V
, L crit
I DCM CCM
L
I
(a)
0
D
1
s
t
T
(b)
L
i
L
I s
t
T
A
v
o
V
in
V
0
0
D ,1 off
D
,2 off
D
1
o
in
V
V
, L crit
I DCM CCM
L
I
(a)
0
D
1
s
t
T
(b)
Boost Converters in DCM
Figure 3-26 Boost converter in DCM.
L
i
L
I
s
t
T
A
v
o
V
in
V
0
0
D ,1 off
D
,2 off
D
1
(a)
0
1
1 D
, L crit
I
DCM CCM
L
I
o
in
V
V
1
(b)
s
t
T
L
i
L
I
s
t
T
A
v
o
V
in
V
0
0
D ,1 off
D
,2 off
D
1
(a)
0
1
1 D
, L crit
I
DCM CCM
L
I
o
in
V
V
1
(b)
s
t
T
Buck-Boost converter in DCM
Figure 3-27 Buck-Boost converter in DCM.
L
i
L
I s
t
T
A
v
o
V
in o
V V +
0
0
D ,1 off
D
,2 off
D
1
(a)
0
1
D
D
, L crit
I
DCM CCM
L
I
o
in
V
V
(b)
s
t
T
L
i
L
I s
t
T
A
v
o
V
in o
V V +
0
0
D ,1 off
D
,2 off
D
1
(a)
0
1
D
D
, L crit
I
DCM CCM
L
I
o
in
V
V
(b)
s
t
T
Figure 3-28 Average representation of a switching power-pole valid in CCM and DCM.
(a) Buck and Buck-Boost
vp
v
cp
v
vp
i
cp
i
k
v
k
i
1: ( ) d t
(1 ) :1 d
cp
v
cp
i
k
v
k
i
vp
i
vp
v
(b) Boost (a) Buck and Buck-Boost
vp
v
cp
v
vp
i
cp
i
k
v
k
i
1: ( ) d t
(1 ) :1 d
cp
v
cp
i
k
v
k
i
vp
i
vp
v
(b) Boost
Table 3-2
k
v and
k
i
Converter
k
v
k
i
Buck 2
1
( )
s L
o
in o
Lf i
v
V v d

2
0
( )
2
in L
s
d
V v di
Lf

Boost
( )
0
2
1
s L
in
in
Lf i
V v
V d

2
2
in L
s
d
V di
Lf

Buck-Boost 2
1
s L
o
in
Lf i
v
V d

2
2
in L
s
d
V di
Lf

Chapter 4 Designing Feedback Controllers in Switch-Mode DC Power
Supplies
4-1 Objectives of Feedback Control
4-2 Review of the Linear Control Theory
4-3 Linearization of Various Transfer Function Blocks
4-4 Feedback Controller Design in Voltage-Mode Control
4-5 Peak-Current Mode Control
4-6 Feedback Controller Design in DCM
References
Problems
Appendix 4A Bode Plots of Transfer Functions
Appendix 4B Transfer Functions in CCM
Appendix 4C Derivation of Controller Transfer Functions
OBJECTIVES OF FEEDBACK CONTROL
zero steady state error
fast response
low overshoot
low noise susceptibility.
Controller
in
V
o
V
*
o
V
DC-DC
Converter
Controller
in
V
o
V
*
o
V
DC-DC
Converter
Figure 4-1 Regulated dc power supply.
Controller
in
V
o
V
*
o
V
DC-DC
Converter
Controller
in
V
o
V
*
o
V
DC-DC
Converter
Figure 4-1 Regulated dc power supply.
The steps in designing the feedback controller:
Linearize the system for small changes around the dc steady state operating point
Design the feedback controller using linear control theory
Confirm and evaluate the system response by simulations for large disturbances
REVIEW OF LINEAR CONTROL THEORY
( ) ( )
( ) ( )
( ) ( )
o o o
c c c
v t V v t
d t D d t
v t V v t
= +
= +
= +
Small signal representation:

Figure 4-2 Feedback control.
+
o
v
*
FB o
k V
PWM-IC
c
v
d
Controller
Pulse Width
Modulation
Power Stage
and Load
FB
k
+
o
v
*
FB o
k V
PWM-IC
c
v
d
Controller
Pulse Width
Modulation
Power Stage
and Load
FB
k
+ ( )
o
v s ( )
c
v s
( ) d s
( )
C
G s ( )
PWM
G s ( )
PS
G s
*
( ) 0
FB o
k v s =
FB
k
A
B
Controller
Pulse-
Width
Modulator
Power Stage
+
Output Filter
+ ( )
o
v s ( )
c
v s
( ) d s
( )
C
G s ( )
PWM
G s ( )
PS
G s
*
( ) 0
FB o
k v s =
FB
k
A
B
Controller
Pulse-
Width
Modulator
Power Stage
+
Output Filter
Figure 4-3 Small signal control system representation.

( ) ( ) ( ) ( )
L C PWM PS FB
G s G s G s G s k =
Phase Margin:
0 0
( 180 ) 180
c c
PM L L
f f
= = +
10
0
10
1
10
2
10
3
10
4
-100
-50
0
50
L
o
o
p
G
a
in
M
a
g
n
i
tu
d
e
(
d
B
)
Gain Margin
f
c
10
0
10
1
10
2
10
3
10
4
-270
-180
-90
0
Frequency (Hz)
L
o
o
p
G
a
in
P
h
a
s
e

(
o
)
Phase Margin
c
f
10
0
10
1
10
2
10
3
10
4
-100
-50
0
50
L
o
o
p
G
a
in
M
a
g
n
i
tu
d
e
(
d
B
)
Gain Margin
f
c
10
0
10
1
10
2
10
3
10
4
-270
-180
-90
0
Frequency (Hz)
L
o
o
p
G
a
in
P
h
a
s
e

(
o
)
Phase Margin
10
0
10
1
10
2
10
3
10
4
-100
-50
0
50
L
o
o
p
G
a
in
M
a
g
n
i
tu
d
e
(
d
B
)
Gain Margin
f
c
10
0
10
1
10
2
10
3
10
4
-270
-180
-90
0
Frequency (Hz)
L
o
o
p
G
a
in
P
h
a
s
e

(
o
)
Phase Margin
c
f
Figure 4-4 Definitions of crossover frequency, gain margin and phase margin.
10
0
10
1
10
2
10
3
10
4
-100
-50
0
50
L
o
o
p
G
a
in
M
a
g
n
i
tu
d
e
(
d
B
)
Gain Margin
f
c
10
0
10
1
10
2
10
3
10
4
-270
-180
-90
0
Frequency (Hz)
L
o
o
p
G
a
in
P
h
a
s
e

(
o
)
Phase Margin
c
f
10
0
10
1
10
2
10
3
10
4
-100
-50
0
50
L
o
o
p
G
a
in
M
a
g
n
i
tu
d
e
(
d
B
)
Gain Margin
f
c
10
0
10
1
10
2
10
3
10
4
-270
-180
-90
0
Frequency (Hz)
L
o
o
p
G
a
in
P
h
a
s
e

(
o
)
Phase Margin
10
0
10
1
10
2
10
3
10
4
-100
-50
0
50
L
o
o
p
G
a
in
M
a
g
n
i
tu
d
e
(
d
B
)
Gain Margin
f
c
10
0
10
1
10
2
10
3
10
4
-270
-180
-90
0
Frequency (Hz)
L
o
o
p
G
a
in
P
h
a
s
e

(
o
)
Phase Margin
c
f
Figure 4-4 Definitions of crossover frequency, gain margin and phase margin.
Loop Transfer Function:
LINEARIZATION OF VARIOUS
TRANSFER FUNCTION BLOCKS
Linearizing the PWM Controller IC
( )
( )
c
r
v t
d t
V
=
( ) d s
( )
c
v s
1
r
V
PWM IC
(c) (b)
r
V
( )
c
v t
( ) q t
s
dT
s
T
r
v
0
0
1
c
v
r
v
( ) q t
(a)
t
t
( ) d s
( )
c
v s
1
r
V
PWM IC
(c) (b)
r
V
( )
c
v t
( ) q t
s
dT
s
T
r
v
0
0
1
c
v
r
v
( ) q t
(a)
t
t
Figure 4-5 PWM waveforms.
( ) d s
( )
c
v s
1
r
V
PWM IC
(c) (b)
r
V
( )
c
v t
( ) q t
s
dT
s
T
r
v
0
0
1
c
v
r
v
( ) q t
(a)
t
t
( ) d s
( )
c
v s
1
r
V
PWM IC
(c) (b)
r
V
( )
c
v t
( ) q t
s
dT
s
T
r
v
0
0
1
c
v
r
v
( ) q t
(a)
t
t
Figure 4-5 PWM waveforms.
( ) 1
( )
( )
PWM
c r
d s
G s
v s V
= =
( ) ( )
c c c
v t V v t = +

( )
( ) ( )
( )

c c
r r
D d t
V t v t
d t
V V
= +

Example 4-1 In PWM-ICs, there is usually a dc voltage offset in the ramp voltage,
and instead of as shown in Fig. 4-5b, a typical Valley-to-Peak value of the ramp signal is
defined. In the PWM-IC UC3824, this valley-to-peak value is 1.8 V. Calculate the
linearized transfer function associated with this PWM-IC.
Solution The dc offset in the ramp signal does not change its small signal transfer
function. Hence, the peak-to-valley voltage can be treated as
r
V . Using Eq. 4-7

1 1
( )
1.8
PWM
r
G s
V
= = =0.556 (4-8)
Linearizing the Power Stage of DC-DC
Converters in CCM
( ) ( )
( ) ( )
( ) ( )
( ) ( )
( ) ( )
vp vp vp
cp cp cp
vp vp vp
cp cp cp
d t D d t
v t V v t
v t V v t
i t I i t
i t I i t
= +
= +
= +
= +
= +
( )
vp
i t
( )
cp
i t
( )
vp
v t ( )
cp
v t
( ) d t 1
( )
vp
i t
( )
cp
i t
( )
vp
v t ( )
cp
v t D 1
vp
dV
cp
dI
( ) a ( ) b
( )
vp
i t
( )
cp
i t
( )
vp
v t ( )
cp
v t
( ) d t 1
( )
vp
i t
( )
cp
i t
( )
vp
v t ( )
cp
v t D 1
vp
dV
cp
dI
( ) a ( ) b
( )
vp
i t
( )
cp
i t
( )
vp
v t ( )
cp
v t
( ) d t 1
( )
vp
i t
( )
cp
i t
( )
vp
v t ( )
cp
v t D 1
vp
dV
cp
dI
( ) a ( ) b
Figure 4-6 Linearizing the switching power-pole.
( )
vp
i t
( )
cp
i t
( )
vp
v t ( )
cp
v t
( ) d t 1
( )
vp
i t
( )
cp
i t
( )
vp
v t ( )
cp
v t D 1
vp
dV
cp
dI
( ) a ( ) b
( )
vp
i t
( )
cp
i t
( )
vp
v t ( )
cp
v t
( ) d t 1
( )
vp
i t
( )
cp
i t
( )
vp
v t ( )
cp
v t D 1
vp
dV
cp
dI
( ) a ( ) b
( )
vp
i t
( )
cp
i t
( )
vp
v t ( )
cp
v t
( ) d t 1
( )
vp
i t
( )
cp
i t
( )
vp
v t ( )
cp
v t D 1
vp
dV
cp
dI
( ) a ( ) b
Figure 4-6 Linearizing the switching power-pole.
Linearizing single-switch converters
1-1.1.1.1.1.1.1.1 Figure 4-7 Linearizing single-switch converters in CCM.
L
i
in
V
+
o
v
+
1: D
in
dV
L
dI
vp
i
vp
v
+
cp
v
+
L
i
o
v
+
1: ( ) d t
in
V
+
o
v
+
(1 ) :1 D
o
dV
L
dI
L
i
vp
v
+
cp
v
+
o
v
+
(1 ( )) :1 d t
(a) (b)
L
i
in
V
+
o
v
+
1: D
( )
in o
d V V +
L
dI
vp
i
vp
v
+
cp
v
+
L
i
o
v
+
1: ( ) d t
Buck
Boost
Buck-Boost
0
in
v =
0
in
v =
0
in
v =
r
r
r
L
i
L
i
in
V
+
o
v
+
o
v
+
1: D
in
dV
L
dI
vp
i
vp
v
+
cp
v
+
L
i
o
v
+
o
v
+
1: ( ) d t
in
V
+
o
v
+
(1 ) :1 D
o
dV
L
dI
L
i
vp
v
+
cp
v
+
o
v
+
o
v
+
(1 ( )) :1 d t
(a) (b)
L
i
in
V
+
o
v
+
o
v
+
1: D
( )
in o
d V V +
L
dI
vp
i
vp
v
+
cp
v
+
L
i
o
v
+
o
v
+
1: ( ) d t
Buck
Boost
Buck-Boost
0
in
v =
0
in
v =
0
in
v =
r
r
r
L
i

2
1
1 1
o in
v V srC
r LC d
s s
RC L LC
+
=

+ + +

( )
2
2
1
1
1 1 1
o in e
e
e e
v V L srC
s
R d
D r
L C s s
RC L L C
+
=

+ + +

Small signal equivalent circuit for Buck, Boost

and Buck-Boost converters
(Buck)
e
L L =
eq
v
R
e
L
+
o
v
+
1
sC
r
eq
v
R
e
L
+
o
v
+
1
sC
r
Figure 4-8 Small signal equivalent circuit for Buck, Boost and Buck-Boost converters.
eq
v
R
e
L
+
o
v
+
1
sC
r
eq
v
R
e
L
+
o
v
+
1
sC
r
Figure 4-8 Small signal equivalent circuit for Buck, Boost and Buck-Boost converters.
( )
2
2
1
1
1 1 1
o in e
e
e e
v V DL srC
s
R d
D r
L C s s
RC L L C
+
=

+ + +

2
= (Boost and Buck-Boost)
(1 )
e
L
L
D
(Boost)
(Buck)
(Buck-Boost)
Using Computer Simulation to Obtain
the transfer function Bode Plots
Example 4-2 A Buck converter has the following parameters and is operating in
CCM: 100 L H = , 697 C F = , 0.1 r = , 100
s
f kHz = , 30
in
V V = , and 36
o
P W = .
The duty-ratio D is adjusted to regulate the output voltage 12
o
V V = . Obtain both the
gain and the phase of the power stage ( )
PS
G s for the frequencies ranging from 1 Hz to
100 kHz.
Ideal Transformer
duty-ratio D
d
Ideal Transformer
duty-ratio D
d
Ideal Transformer
duty-ratio D
d
Figure 4-9 PSpice Circuit model for a Buck converter.

Ideal Transformer
duty-ratio D
d
Ideal Transformer
duty-ratio D
d
Ideal Transformer
duty-ratio D
d
Figure 4-9 PSpice Circuit model for a Buck converter.

PSpice Modeling: C:\FirstCourse_PE_Book07\buck_conv_avg.sch
Frequency
1.0Hz 3.0Hz 10Hz 30Hz 100Hz 300Hz 1.0KHz 3.0KHz 10KHz 30KHz 100KHz
P(V(V_out))
-150d
-100d
-50d
-0d
DB(V(V_out))
-40
0
40
SEL>>
Simulation Results
.
Frequency
30Hz 100Hz 300Hz 1.0KHz 3.0KHz 10KHz 30KHz
P(V(V_out))
-150d
-100d
-50d
0d
DB(V(V_out))
-20
0
20
40
SEL>>
24.66dB
( )
PS
dB
G s
( )
PS
G s
0
138
Frequency
P(V(V_out))
-150d
-100d
-50d
0d
DB(V(V_out))
-20
0
20
40
SEL>>
24.66dB
( )
PS
dB
G s
( )
PS
G s
0
138
Figure 4-10 The gain and the phase of the power stage
Frequency
P(V(V_out))
-150d
-100d
-50d
0d
DB(V(V_out))
-20
0
20
40
SEL>>
24.66dB
( )
PS
dB
G s
( )
PS
G s
0
138
Frequency
P(V(V_out))
-150d
-100d
-50d
0d
DB(V(V_out))
-20
0
20
40
SEL>>
24.66dB
( )
PS
dB
G s
( )
PS
G s
0
138
Figure 4-10 The gain and the phase of the power stage
FEEDBACK CONTROLLER DESIGN IN
VOLTAGE-MODE CONTROL
1. The crossover frequency
c
f of the open-loop gain is as high as possible to result
in a fast response of the closed-loop system.
2. The phase angle of the open-loop transfer function has the specified phase
margin, typically
0
60 at the crossover frequency so that the response in the
closed-loop system settles quickly without oscillations.
3. The phase angle of the open-loop transfer function should not drop below
0
180
at frequencies below the crossover frequency.
Example 4-3 Design the feedback controller for the Buck converter described in
Example 4-2. The PWM-IC is as described in Example 4-1. The output voltage-sensing
network in the feedback path has a gain 0.2
FB
k = . The steady state error is required to
be zero and the phase margin of the loop transfer function should be
0
60 at as high a
crossover frequency as possible.
( )
( )
2
2
1 /
( )
1 /
z c
c
p
s k
G s
s
s

+
=
+
Figure 4-11 Bode plot of ( )
C
G s in Eq. 4-18.

Frequency
10Hz 30Hz 100Hz 300Hz 1.0KHz 3.0KHz 10KHz 30KHz 100KHz
P(V(v_out)) -90
-100
-50
0
50
boost
( )
C dB
G s
( )
C
G s
0
90
( )
c
C f
G s
z
f
c
f
p
f
Frequency
P(V(v_out)) -90
-100
-50
0
50
Frequency
P(V(v_out)) -90
-100
-50
0
50
boost
( )
C dB
G s
( )
C
G s
0
90
( )
c
C f
G s
z
f
c
f
p
f
Step 1: Choose the Crossover Frequency. Choose
c
f to be slightly beyond the L-C
resonance frequency 1/(2 ) LC , which in this example is approximately 600 Hz.
Therefore, we will choose 1 kHz
c
f = . This ensures that the phase angle of the loop
remains greater than
0
180 at all frequencies.
Step 2: Calculate the needed Phase Boost. The desired phase margin is specified as
0
60
PM
= .
The required phase boost
boost
at the crossover frequency is calculated as follows, noting that
PWM
G and
FB
k produce zero phase shift:
( ) ( ) ( )
c c c
L PS C
f f f
G s G s G s = + (from Eq. 4-2) (4-19)
( ) 180
c
o
L PM
f
G s = + (from Eq. 4-3) (4-20)
( ) 90
c
o
C boost
f
G s = + (from Fig. 4-11) (4-21)
Substituting Eqs. 4-20 and 4-21 into Eq. 4-19,
90 ( )
c
o
boost PM PS
f
G s = + (4-22)
In Fig. 4-10,
0
( ) 138
c
PS
f
G s = , substituting which in Eq. 4-22 yields the required phase boost
108
o
boost
= .
Step 3: Calculate the Controller Gain at the Crossover Frequency. From Eq. 4-2 at the
crossover frequency
c
f
( ) ( ) ( ) ( ) 1
c c c c
L C PWM PS FB
f f f f
G s G s G s G s k = = (4-23)
In Fig. 4-10, at 1
c
f kHz = ,
1
( ) 24.66 17.1
c
PS
f kHz
G s dB
=
= = . Therefore in Eq. 4-23, using
the gain of the PWM block calculated in Example 4-1,

( ) ( )
( ) 0.556 17.1 0.2 1
c
FB PWM PS f f c c
C
f
k G s G s
G s = (4-24)
or
( ) 0.5263
c
C
f
G s = (4-25)
( )
( )
2
2
1 /
( )
1 /
z c
c
p
s k
G s
s
s

+
=
+
p
boost
z
K

= tan 45
4
o boost
boost
K

= +

c
z
boost
f
f
K
=
p boost c
f K f =
( )
c
z
c C
f
boost
k G s
K
+ ( )
o
v s ( )
c
v s ( ) d s
( )
C
G s ( )
PWM
G s ( )
PS
G s
*
( ) 0
o
v s =
FB
k
A
B
Controller
Pulse-
Width
Modulator
Power Stage
+
Output Filter
+ ( )
o
v s ( )
c
v s ( ) d s
( )
C
G s ( )
PWM
G s ( )
PS
G s
*
( ) 0
o
v s =
FB
k
A
B
Controller
Pulse-
Width
Modulator
Power Stage
+
Output Filter
+ ( )
o
v s ( )
c
v s ( ) d s
( )
C
G s ( )
PWM
G s ( )
PS
G s
*
( ) 0
o
v s =
FB
k
A
B
Controller
Pulse-
Width
Modulator
Power Stage
+
Output Filter
+ ( )
o
v s ( )
c
v s ( ) d s
( )
C
G s ( )
PWM
G s ( )
PS
G s
*
( ) 0
o
v s =
FB
k
A
B
Controller
Pulse-
Width
Modulator
Power Stage
+
Output Filter

Implementation of the controller by an op-amp
1
R
3
R
2
R
2
C
1
C
3
C
*
o
v
o
v
c
v
1
R
3
R
2
R
2
C
1
C
3
C
*
o
v
o
v
c
v
Figure 4-12 Implementation of the controller by an op-amp.
1
R
3
R
2
R
2
C
1
C
3
C
*
o
v
o
v
c
v
1
R
3
R
2
R
2
C
1
C
3
C
*
o
v
o
v
c
v
Figure 4-12 Implementation of the controller by an op-amp.
( )
2 1
1 2
2 1
3 1
3 3
/( )
/ 1
1/( )
/( / 1)
1/( )
z c p
p z
z
p z
p
C k R
C C
R C
R R
C R

=
=
=
=
=
( )
( )
2
2
1 /
( )
1 /
z c
c
p
s k
G s
s
s

+
=
+
In this numerical example with 1 kHz
c
f = , 108
o
boost
= , and ( ) 0.5263
c
C
f
G s = , we can
calculate 3.078
boost
K = in Eq. 4-27. Using Eqs. 4-27 through 4-30, 324.9
z
f Hz = ,
3078
p
f Hz = , and 349.1
c
k = . For the op-amp implementation, we will select
1
100 R k = . From Eq. 4-30,
2
3.0 C nF = ,
1
25.6 C nF = ,
2
19.1 R k = ,
3
11.8 R k = ,
and
3
4.4 C nF = .
PSpice model of the Buck converter with voltage-mode control
Figure 4-13 PSpice average model of the Buck converter with voltage-mode control.
Figure 4-14 Response to a step-change in load.
Time
0s 5ms 10ms
V(V_out)
11.6V
11.8V
12.0V
12.2V
PSpice Modeling: C:\FirstCourse_PE_Book07\buck_conv_avg_fb_ctrl_op.sch
Simulation Results
Time
0s 0.5ms 1.0ms 1.5ms 2.0ms 2.5ms 3.0ms 3.5ms 4.0ms 4.5ms 5.0ms 5.5ms 6.0ms
V(V_out)
11.7V
11.8V
11.9V
12.0V
12.1V
PEAK-CURRENT MODE CONTROL
Peak-Current-Mode Control, and
Average-Current-Mode Control.
Figure 4-15 Peak current mode control.
in
V
o
v
+
vp
i
vp
v
+
cp
v
+
L
i
Q S
R
Flip-flop
Slope
Compensation
Controller
*
o
v
c
i
Clock
*
L
i
Comparator
+
in
V
o
v
+
vp
i
vp
v
+
cp
v
+
L
i
Q S
R
S
R
Flip-flop
Slope
Compensation
Controller
*
o
v
c
i
Clock
*
L
i
Comparator
+

Figure 4-16 Peak-current-mode control with slope compensation.
L
i
Clock
c
i
1
s
s
T
f
=
t
t
*
L
i
( ) a
Peak Current
Mode
Controller
+
( )
o
v s
*
( )
L
i s
( )
L
i s
( )
C
G s 1
*
( ) 0
o
v s =
Power Stage Controller
( ) b
0
slope compensation
L
i
Clock
c
i
1
s
s
T
f
=
t
t
*
L
i
( ) a
Peak Current
Mode
Controller
+
( )
o
v s
*
( )
L
i s
( )
L
i s
( )
C
G s 1
*
( ) 0
o
v s =
Power Stage Controller
( ) b
0
slope compensation
Example 4-4 In this example, we will design a peak-current-mode controller for a
Buck-Boost converter that has the following parameters and operating conditions:
100 H L = , 697 F C = , 0.01 r = , 100 kHz
s
f = , 30V
in
V = . The output power
18W
o
P = in CCM and the duty-ratio D is adjusted to regulate the output voltage
12V
o
V = . The phase margin required for the voltage loop is
0
60 . Assume that in the
voltage feedback network, 1
FB
k = .
Figure 4-17 PSpice circuit for the Buck-Boost converter.
.
Figure 4-18 Bode plot of /
o L
v i
.
Frequency
P(V(V_out)/ I(L1))
-100d
-50d
0d
SEL>>
DB(V(V_out)/I(L1))
-40
-20
0
20
( )
PS dB
G s
deg
( ) |
PS
G s
29.33dB
0
90
5
c
f kHz =
Frequency
P(V(V_out)/ I(L1))
-100d
-50d
0d
SEL>>
DB(V(V_out)/I(L1))
-40
-20
0
20
( )
PS dB
G s
deg
( ) |
PS
G s
29.33dB
0
90
5
c
f kHz =
As shown in Fig. 4-18, the phase angle of the power-stage transfer function levels off at
approximately
0
90 at ~1kHz . The crossover frequency is chosen to be 5
c
f kHz = , at
which in Fig. 4-18,
0
( ) 90
c
PS
f
G s = . As explained in the Appendix on the
accompanying CD, the power-stage transfer function ( ) / ( )
o L
v s i s
of Buck-Boost
converters contains a right-half-plane zero in CCM. The crossover frequency is chosen
well below the frequency of the right-half-plane zero for reasons discussed in the
Appendix.
PSpice Modeling: C:\FirstCourse_PE_Book07\Buck-Boost_Freq_Analysis.sch
Simulation Results
Frequency
P(V(V_out)/I(L1))
-100d
-50d
0d
DB(V(V_out)/I(L1))
-40
-20
0
20
SEL>>
( )
( )
1 /
( )
1 /
z c
c
p
s k
G s
s s

+
=
+
tan 45
2
o boost
boost
K

= +

c
z
boost
f
f
K
=
p boost c
f K f =
( )
c
c z C
f
k G s =
At the crossover frequency, as shown in Fig. 4-18, the power stage transfer function has a
gain ( ) 29.33
c
PS
f
G s dB = . Therefore, at the crossover frequency, by definition, in Fig.
4-16b
( ) ( ) 1
c c
C PS
f f
G s G s = (4-37)
Hence,
( ) 29.33 29.27
c
C
f
G s dB = = (4-38)
Using the equations above for 5
c
f kHz = ,
0
60
boost
= , and ( ) 29.27
c
C
f
G s = ,
3.732
boost
K = in Eq. 4-32. Therefore, the parameters in the controller transfer function
of Eq. 4-31 are calculated as 1340
z
f Hz = , 18660
p
f Hz = , and
3
246.4 10
c
k = .
Figure 4-19 Implementation of controller in Eq. 4-32 by an op-amp circuit.
1
R
2
R
2
C
1
C
*
o
v
o
v
c
v
1
R
2
R
2
C
1
C
*
o
v
o
v
c
v
( )
2
1
1 2
2 1
30 F
/ 1 380 F
1/( ) 315
z
p c
p z
z
C p
R k
C C p
R C k
= =
= =
= =
1
10 R k =
Figure 4-20 PSpice simulation diagram of the peak-current-mode control.
Figure 4-21 Peak current mode control: Output voltage waveform.
Time
2.50ms 2.75ms 3.00ms 3.25ms 3.50ms
AVGX(V(Vo),10u) V(Vo)
11.92
11.96
12.00
12.04
( )
o
v t
( )
o
v t
Time
2.50ms 2.75ms 3.00ms 3.25ms 3.50ms
AVGX(V(Vo),10u) V(Vo)
11.92
11.96
12.00
12.04
( )
o
v t
( )
o
v t
PSpice Modeling: C:\FirstCourse_PE_Book07\bboost_conv_curr_mode_ctrl_opamp.sch
Time
V(Vo)
11.92V
11.94V
11.96V
11.98V
12.00V
12.02V
Simulation Results
FEEDBACK CONTROLLER DESIGN IN DCM
PSpice Modeling: C:\FirstCourse_PE_Book07\Buck-Boost_CCM_DCM_Freq_Analysis.sch
Frequency
P(V(V_out))
-200d
-100d
0d
DB(V(V_out))
-40
0
40
80
SEL>>
CCM
CCM
DCM
DCM
Simulation Results
APPENDIX 4A BODE PLOTS OF TRANSFER FUNCTIONS
WITH POLES AND ZEROS
4A-1 A Pole in a Transfer Function
1
( )
1 /
p
T s
s
=
+
10
20log ( ) T s
0
10
20
0
45
90
p
10
p
10
p
10
log
( ) T s
10
20log ( ) T s
0
10
20
0
45
90
0
45
90
p
10
p
10
p
10
log
( ) T s
Fig. 4A-1 Gain and phase plots of a pole.
4A-2 A Zero in a Transfer Function
( ) 1 /
z
T s s = +
10
20log ( ) T s
0
10
20
0
45
90
z
10
z
10
z
10
log
( ) T s
10
20log ( ) T s
0
10
20
0
45
90
z
10
z
10
z
10
log
( ) T s
Fig. 4A-2 Gain and phase plots of a zero.
4A-3 A Right-Hand-Plane (RHP) Zero in a Transfer Function
( ) 1
z
s
T s
=
0
45
90
10
20log ( ) T s
0
10
20
z
10
z
10
z
10
log
( ) T s
0
45
90
0
45
90
10
20log ( ) T s
0
10
20
0
10
20
z
10
z
10
z
10
z
10
z
10
log
( ) T s
Fig. 4A-3 Gain and phase plots of a right-hand side zero.
4A-4 A Double Pole in a Transfer Function
2
1
( )
1
o
T s
s
s
=

+ +

1 0
1
1 0
2
1 0
3
1 0
4
1 0
5
- 8 0
- 6 0
- 4 0
- 2 0
0
2 0
1 0
1
1 0
2
1 0
3
1 0
4
1 0
5
- 1 8 0
- 9 0
0
0 . 0 5 =
0 . 2 5 =
0 . 5 =
0 . 8 0 =
1 . 0 0 =
0 . 0 5 =
0 . 2 5 =
0 . 5 =
0 . 8 0 =
1 . 0 0 =
Fig.4A-4 Gain and phase plots of a double-pole.
Chapter 5 Rectification of Utility Input Using Diode Rectifiers
5-1 Introduction
5-2 Distortion and Power Factor
5-3 Classifying the Front-End of Power Electronic Systems
5-4 Diode-Rectifier Bridge Front-Ends
5-5 Means to Avoid Transient Inrush Currents at Starting
5-6 Front-Ends with Bi-Directional Power Flow
References
Problems
Figure 5-1 Block diagram of power electronic systems.
Converter
Controller
Source Load
Converter
Controller
Source Load
Linear and
Nonlinear Loads
Linear Load
cos
s s
P V I =
cos
s s
P
PF
V I
= =
s
s
P
I
V PF
=
Figure 5-2 Voltage and current phasors in simple R-L circuit.

s
I
s
V
i
s
v
s
+
( ) a
( ) b
s
I
s
V
i
s
v
s
+
i
s
v
s
+
( ) a
( ) b
Nonlinear
Loads
Non-linear Loads
Total Harmonic Distortion:
1
% 100
distortion
s
I
THD x
I
=
Displacement Power Factor:
1
cos DPF =
1
2
( )
1
s
s
I DPF
PF DPF
I
THD
= =
+
Figure 5-3 Current drawn by power electronics equipment with diode-bridge front-end.
t
( )
distortion s s1
i i i =
t 0
/
1

s1
i
i
s
v
s
1
T
0
( ) a
( ) b
t
( )
distortion s s1
i i i =
t 0
/
1

s1
i
i
s
v
s
1
T
0
( ) a
( ) b
Nonlinear loads reduce power factor
Obtaining Harmonic Components by Fourier Analysis
{ }
0 0
1 1
( ) ( ) cos( ) sin( )
h h h
h h
g t G g t G a h t b h t

= =
= + = + +

2
0
0
1
( ) ( )
2
G g t d t
2
0
1
( ) cos( ) ( ) 1, 2,...,
h
a g t h t d t h
= =
2
0
1
( )sin( ) ( ) 1, 2,...,
h
b g t h t d t h
= =
h h h
G G =
2 2
2
h h
h
a b
G
+
=
tan
h
h
h
b
a

=
2 2
0
1
h
h
G G G
=
= +

1
T
s
i
t
I
I
0
s1
i
t 0
I
I
/ 4I
t
distortion
i
0
( ) c
( ) b
( ) a
1
T
s
i
t
I
I
0
s1
i
t 0
I
I
/ 4I
t
distortion
i
0
( ) c
( ) b
( ) a
Harmonic Currents Lower Power Factor
PF
DPF
%THD
0 50 100 150 200 250 300
1
. 0 9
. 0 8
. 0 7
. 0 6
. 0 5
. 0 4
Ratio of actual power factor to displacement power factor decreases with
increasing THD
Harmonic Guidelines
/
SC 1
I I
Odd HarmonicOrder h
35 h 23 h 35 17 h 23 11 h 17 h 11 <
. 15 0
. 12 0
. 10 0
. 7 0
. 4 0
. 7 0
. 5 5
. 4 5
. 3 5
. 2 0
. 6 0
. 5 0
. 4 0
. 2 5
. 1 5
. 2 5
. 2 0
. 1 5
. 1 0
. 0 6
. 1 4
. 1 0
. 0 7
. 0 5
. 0 3
. 20 0
. 15 0
. 12 0
. 8 0
. 5 0
Distortion(%)
Harmonic
Total
1000 >
100 1000
50 100
20 50
20 <
IEEE 519
Limits on allowable harmonic currents drawn by loads of various relative magnitudes
Relative magnitude of load currents is based on Short Circuit Ratio (SCR)
1

sc
s
I
SCR
I
=
Where I
sc
is the short circuit current and I
s1
is the fundamental
current of the load
+
sc
I
Z
s
V
s
+
Z
s
V
s
(a) (b)
Figure 5-6 (a) Utility supply; (b) short circuit current.
+
sc
I
Z
s
V
s
+
Z
s
V
s
+
Z
s
V
s
(a) (b)
Figure 5-6 (a) Utility supply; (b) short circuit current.
sc
I Short-Circuit Current:
Types of Electric Drive Front-Ends
Diode-bridge rectifiers
Switch-mode converters
Thyristor converter
Figure 5-7 Front-end of power electronics equipment.
( ) a ( ) b ( ) c ( ) a ( ) b ( ) c
Single-Phase, Diode-
Bridge Rectifier
Power levels up to several kW
Current drawn from utility in short pulses
Figure 5-8 Full-bridge diode rectifier.
v
d eq
R
d
C
4
3
2
1
s
L
i
s
( )
s
v t
+
s
R
dr
i
d
i
( ) a ( ) b
dr
i
v
d
+
( )
s
v t
+
i
s
4
2
1
3
v
d eq
R
d
C
4
3
2
1
s
L
i
s
( )
s
v t
+
s
R
dr
i
d
i
( ) a ( ) b
dr
i
v
d
+
( )
s
v t
+
i
s
4
2
1
3
Fig. 5-9 Full-bridge diode rectifier with resistive load.
s
v
0
t
( ) a
d s
v v =
,
s dr
i i
dr
i
( ) b
dr
i
d
R
+
s
v
i
s
4
2
1
3
+
v
d
Full-bridge diode rectifier with resistive load
Fig. 5-10 Full-bridge diode rectifier with an inductive load where ( )
dr dr
i t I = (dc).
( ) a
dr
i
d R
+
s
v
i
s
4
2
1
3
+
v
d
s
v
0
t
d s
v v =
( )
s dr
i I =
( ) b
d R
d L
( )
s dr
i I =
Full-bridge diode rectifier with an inductive load where ( )
dr dr
i t I = (dc).
Peak-Charging Circuit
Current pulses widen as L
s
is increased
Figure 5-11 Waveforms for the full-bridge diode rectifier with a dc-bus capacitor.
t
3
t
2
t
1
v
d
i
dr
i
dr
v
s
t
0
i
s i
s
t
3
t
2
t
1
v
d
i
dr
i
dr
v
s
t
0
i
s i
s
Figure 5-12 Single-phase diode-bridge rectification for two values of
s
L .
Time
115ms 120ms 125ms 130ms 135ms 140ms 145ms 150ms
V(Ls:1) I(Ls)*3 V(R1:2,C1:2)
-200
-100
0
100
200
s
v
d
v
s
i
Time
115ms 120ms 125ms 130ms 135ms 140ms 145ms 150ms
V(Ls:1) I(Ls)*3 V(R1:2,C1:2)
-200
-100
0
100
200
s
v
d
v
s
i
PSpice Modeling: C:\FirstCourse_PE_Book07\DBrect1ph.sch
Time
0s 5ms 10ms 15ms 20ms 25ms 30ms 35ms 40ms 45ms 50ms
V(Ls:1) I(Ls)*3 V(R1:2,C1:2)
-200
-100
0
100
200
Simulation Results
Three-Phase, Diode- Bridge Rectifier
Figure 5-13 Three-phase diode bridge rectifier.
1
2
3
4
5
6
+
C
d
R
eq
v
d
+
v
a
v
b
v
c
L
s
L
s
L
s
+
+
i
dr
N
1
2
3
4
5
6
P
+
v
a
v
b
v
c
L
s
L
s
L
s
+
+
i
dr
( ) a
( ) b
a
i
1
2
3
4
5
6
+
C
d
R
eq
v
d
+
v
a
v
b
v
c
L
s
L
s
L
s
+
+
i
dr
N
1
2
3
4
5
6
P
+
v
a
v
b
v
c
L
s
L
s
L
s
+
+
i
dr
( ) a
( ) b
a
i
Voltage and Current Without C
d
v
P
follows whichever phase voltage is most positive at any moment
v
N
follows whichever phase voltage is most negative at any moment
Without C
d
, phase currents flow for a full 120 duration
Figure 5-14 Waveforms in a three-phase rectifier (a constant
dr
i ).
t
0
c
v
b
v
a
v
(a)
a
i
0
o
120
o
60 t
b
i
0
c
i
0
N
v
P
v
(c)
t
d
V
LL
2V d
v
0
(b)
t
t
t
0
c
v
b
v
a
v
(a)
a
i
0
o
120
o
60 t
b
i
0
c
i
0
N
v
P
v
(c)
t
d
V
LL
2V d
v
0
(b)
t
t
PSpice Modeling: C:\FirstCourse_PE_Book07\DBrect3_ph.sch
Time
60ms 65ms 70ms 75ms 80ms 85ms 90ms 95ms 100ms
I(L1)*5 V(L1:1) V(Vd,R7:2)
-200
-100
0
100
200
300
Simulation Results
Figure 5-15 Effect of
s
L variation (a) 0.1
s
L mH = ; (b) 3
s
L mH = .
Time
65ms 70ms 75ms 80ms 85ms 90ms 95ms
I(L1)*3 V(L1:1)
-200
-100
0
100
200
Time
I(L1)*3 V(L1:1)
-200
-100
0
100
200
s
v
s
i
s
v
s
i
( ) a
( ) b
Time
I(L1)*3 V(L1:1)
-200
-100
0
100
200
Time
I(L1)*3 V(L1:1)
-200
-100
0
100
200
s
v
s
i
s
v
s
i
( ) a
( ) b
Avoiding Large Inrush Currents
Resistor limits inrush current at startup
Resistor switched out during operation
Figure 5-16 Means to avoid inrush current.
( ) a ( ) b ( ) a ( ) b
Chapter 6 Power-Factor-Correction (PFC) Circuits and Designing the
Feedback Controller
6-1 Introduction
6-2 Single-Phase PFCs
6-3 Control of PFCs
6-4 Designing the Inner Average-Current-Control Loop
6-5 Designing the Outer Voltage Loop
6-6 Example of Single-Phase PFC Systems
6-7 Simulation Results
6-8 Feedforward of the Input Voltage
References
Problems
Appendix 6A Proving that
,3 ,2

/ 1/ 2
s L
I I =
Appendix 6B Deriving
~
( ) / ( )
d L
v s I s
Implementation of PFC
Figure 6-2 Average model and waveforms.
s
v
+
d
L
( )
L
i t
(1 ) d
1
d
C
r
R
d
v
+
( )
d
i t
( ) a ( ) b
0
t
t
d
V
s
v
L
i
0
( ) d t
1
1
t
+
+

L
I
s
v
+
d
L
( )
L
i t
(1 ) d
1
d
C
r
R
d
v
+
( )
d
i t
( ) a ( ) b
0
t
t
d
V
s
v
L
i
0
( ) d t
1
1
t
+
+

L
I
Figure 6-1 PFC circuit and waveforms.
s
i
+
0
L
i
+
d
V
+
s
v
d
L
( ) q t
d
C
R
( ) a ( ) b
s
v
s
v
L
i
s
i
L
I
d
i
s
i
+
0
L
i
+
d
V
+
s
v
d
L
( ) q t
d
C
R
( ) a ( ) b
s
v
s
v
L
i
s
i
L
I
d
i
Use a boost dc-dc converter to shape the rectified current
V
v d t
d t
V t
V
o
s
s
o
=
( )=
1
1
1
( )
`
sin a f
d s
V V >
Figure 6-3 Current division in the output stage.
d
i
2 d
i d
I
+
d
v
d
i
2 d
i d
I
+
d
v
2
( )

1 1

cos2
2 2
d d
s s
d L L
d d
I i t
V V
i I I t
V V
=
_ _
2
2

1
cos2 ( ) sin2
2 4
d
s L s L
d
d d
V
V I V I
v t d t t
C V CV

= =

_
2

4
s L
d
d
V I
V
C V
=
Figure 6-2 Average model and waveforms.
s
v
+
d
L
( )
L
i t
(1 ) d
1
d
C
r
R
d
v
+
( )
d
i t
( ) a ( ) b
0
t
t
d
V
s
v
L
i
0
( ) d t
1
1
t
+
+

L
I
s
v
+
d
L
( )
L
i t
(1 ) d
1
d
C
r
R
d
v
+
( )
d
i t
( ) a ( ) b
0
t
t
d
V
s
v
L
i
0
( ) d t
1
1
t
+
+

L
I
( )
( )
sin
1
s
o
V t
d t
V

=
Example 6-1 Derive ( )
d
i t in Eq. 6-5 by equating input and output powers.
Solution Assume that
sin
s s
v V t = and
sin
s s
i I t = . Therefore, the input power
2

( ) sin
in s s s s
P t v i V I t = = . Recognizing that
2
1 1
sin cos2
2 2
t t = , the input power is
2
1 1

( ) sin cos2
2 2
in s s s s s s
P t V I t V I V I t = = . The output power ( )
o d d
p t V i = . Equating
( ) ( )
in o
p t p t = ,

2
( )

1 1
cos2
2 2
d d
s s s s
d
d d
I i t
V I V I
i t
V V
=
_ _
(6-6)
As Eq. 6-5, Eq. 6-6 shows that the average current to the output stage consists of a dc
component
d
I and a component
2
( )
d
i t at the second-harmonic component.

Figure 6-3 Current division in the output stage.
d
i
2 d
i d
I
+
d
v
d
i
2 d
i d
I
+
d
v
2 2
1
( ) ( )
d d
v t i d t
C

2
2

1
cos2 sin2
2 4
d
L s L s
d
d d
V
I V I V
v t dt t
C V CV

= =

_
2
Calculationof
d
V
Example 6-2 Calculate
2
d
V at full-load and the nominal input voltage, for the
parameters and operating values of a PFC given in Table 6-1 on page
6-9. Ignore the capacitor ESR.
Solution Assuming the PFC to be lossless,
s s o
V I P = . Therefore, using the values given
in Table 6-1,

2 2.946
o
L s
s
P
I I A
V
= = = .
2 120 169.7
s
V V = = . Therefore, From Eq.
6-9, the peak value of the second-harmonic voltage is
2

6
4
L s
d
d
I V
V V
C V
= = .

CONTROL OF PFCs
Figure 6-4 PFC control loops.
*
d
V
Voltage
Controller
*
L
I
sin t
*
( )
L
i t
Current
Controller
r
v
( )
c
v t
( ) q t
Power
Stage
d
v
L
i
Current Loop
*
d
V
Voltage
Controller
*
L
I
sin t
*
( )
L
i t
Current
Controller
r
v
( )
c
v t
( ) q t
Power
Stage
d
v
L
i
Current Loop
( ) 1
( )
c r
d s
v s V
=
( )
( )
d L
d
V i s
sL d s
=
DESIGNING INNER AVERAGE-CURRENT-CONTROL LOOP

tan(45 )
2
o boost
boost
K

= +
PWM-IC:
Power-Stage:
phase boost
1 /
( )
1 /
c z
i
p
k s
G s
s s

+
=
+
_
Controller:
ci
z
boost
f
f
K
=
p boost ci
f K f = ( )
c
c z C
f
k G s =
Figure 6-5 PFCcurrent loop.
Current
Controller
*
( )
L
i t
L
i
d
v
Power
Stage
( ) d t ( )
c
v t
PWM
IC
( ) a
( )
i
G s
*
( )
L
i s
( )
L
i s
Power
Stage
( ) d s
( )
c
v s
1
r
V
Current
Controller
PWM
IC
d
d
V
sL
( ) b
+
Current
Controller
*
( )
L
i t
L
i
d
v
Power
Stage
( ) d t ( )
c
v t
PWM
IC
Current
Controller
*
( )
L
i t
L
i
d
v
Power
Stage
( ) d t ( )
c
v t
PWM
IC
( ) a
( )
i
G s
*
( )
L
i s
( )
L
i s
Power
Stage
( ) d s
( )
c
v s
1
r
V
Current
Controller
PWM
IC
d
d
V
sL
( ) b
+

DESIGNING THE OUTER VOLTAGE LOOP
( )
1 /
v
v
cv
k
G s
s
=
+
2
2 (2 120)
1 /
v L
cv d s j
k I
s V
=
=
+
Figure 6-6 Voltage control loop.
( ) b
( ) a
*
d
V
d
v
Closed
Current
Loop
L
I
Power
Stage
*
L
I
Voltage
Controller
*
d
V
d
v
Closed
Current
Loop
L
I
Power
Stage
*
L
I
Voltage
Controller
Voltage
Controller
*
( )
L
i s
*
( ) 0
d
v s =
( )
L
i s
1
( )
v
G s
1 / 2
2 1 ( / 2)
s
d
V R
V s R C +
( )
d
v s
Closed
Current
Loop
Power
Stage
(2 )
1 / 2
1
1 / 2 1 ( / 2)
cv
v s
cv d
s j f
k V R
s V s R C

=
=
+ +
EXAMPLE OF SINGLE-PHASE PFC SYSTEMS
Table 6-1
Parameters and Operating Values
Nominal input ac source voltage,
, s rms
V 120V
Line frequency, f 60 Hz
Output Voltage,
d
V 250V (dc)
Maximum Power Output 250W
Switching Frequency,
s
f 100kHz
Output Filter capacitor, C 220 F
ESR of the Capacitor, r 100m
Inductor,
d
L 1mH
Full-Load Equivalent Resistance, R 250

Design of the Current Loop
1
r
V =
4
2 10
ci
=
0
60
PM
=
4212
c
k =
4
1.68 10 /
z
rad s =
5
2.34 10 /
p
rad s =
phase boost
1 /
( )
1 /
c z
i
p
k s
G s
s s

+
=
+
_
DESIGNING THE OUTER VOLTAGE LOOP
( )
1 /
v
v
cv
k
G s
s
=
+
In this example at full-load, the plant transfer function given by Eq. 6-15 has a pole at the
frequency of 36.36 rad/s (5.79 Hz). At full-load,
2.946
L
I A = , and in Eq. 6-8,
2
6.029
d
V V = . Based on the previous discussion, the second-harmonic component is
limited to 1.5 percent of
L
I , such that
2
0.0442
L
I A = . Using these values, from Eq. 6-17
and 6-18, the parameters in the voltage controller transfer function of Eq. 6-16 are
calculated: 0.0754
v
k = , and 73.7 /
cv
rad s = (11.73 Hz). This transfer function is
realized by an op-amp circuit shown in Fig. 6-7, where
1
2
1
100
7.54
1.8 F
R k
R k
C
=
=
=

Figure 6-7 Op-amp circuit to implement transfer function ( )
v
G s .
in
1
R 2
R
1
C
1
R
1
R
out
+
+
in
1
R 2
R
1
C
1
R
1
R
out
+
+
( )
1 /
v
v
cv
k
G s
s
=
+
1
2
1
100
7.54
1.8 F
R k
R k
C
=
=
=
PSpice Modeling: C:\FirstCourse_PE_Book07\pfc__Avg_opm.sch
Time
0s 20ms 40ms 60ms 80ms 100ms 120ms 140ms 160ms 180ms 200ms
V(R2:2) I(L1)*50
0
50
100
150
200
250
Simulation Results
FEEDFORWARD OF THE INPUT VOLTAGE
Figure 6-10 Feedforward of the input voltage.
*
d
V
Voltage
Controller
,
s
s nom
V
V
sin t
*
( )
L
i t
Current
Controller
r
v
( )
c
v t
( ) q t
Power
Stage
d
v
L
i
Current Loop
*
L
I N
D
*
d
V
Voltage
Controller
,
s
s nom
V
V
sin t
*
( )
L
i t
Current
Controller
r
v
( )
c
v t
( ) q t
Power
Stage
d
v
L
i
Current Loop
*
L
I N
D
186
Chapter 7 Magnetic Circuit Concepts
7-1 Ampere-Turns and Flux
7-2 Inductance L
7-3 Faradays Law: Induced Voltage in a Coil due to Time-Rate of Change of Flux Linkage
7-4 Leakage and Magnetizing Inductances
7-5 Transformers
References
Problems
AMPERE-TURNS AND FLUX
g
/
m g
= =
i
Figure 7-1 Magnetic structure with air gap.
W
d
Ni
=
m g
= +

( )
m
g
g
m
m m g o
Ni
A A

+ =
/
/
m m g g
H H Ni + = / /
INDUCTANCE
2
m
m
m m
N
L
A
=
/
m
( ) N
m
( )
m
A ( )
m

m
B
m
H
m
N

/
i
Figure 7-2 Coil Inductance.
(a) (b)
m
m
A
i
N
m m m
N L i = =
Energy Storage due to Magnetic Fields
2
1
[ ]
2
m
W L i J =
2
3
1
[ / ]
2
B
w J m
=
FARADAYS LAW: INDUCED VOLTAGE IN A COIL
DUE TO TIME-RATE OF CHANGE OF FLUX LINKAGE
( ) ( ) ( )
d d
e t t N t
dt dt
= =
( ) i t
( ) t
( ) e t
+
N
Figure 7-3 Voltage polarity and direction of flux and current.
0
1
( ) (0) ( )
t
t e d
N
= +

LEAKAGE AND MAGNETIZING INDUCTANCES
(a) (b)
i
+
e
i
+
e
m
Figure 7-4 (a) Magnetic and leakage fluxes; (b) equivalent representation of magnetic and
leakage fluxes.
( ) v t
+
R
m
l
L
( ) i t
( )
m
e t ( ) e t
+
l
di
L
dt
( )
m
e t ( ) e t
+
+
( ) i t
m
L
l
L
Figure 7-5 (a) Circuit representation;
(b) leakage inductance separated from the core.
(a)
(b)
TRANSFORMERS
Figure 7-6 Transformer with three windings.
1
i
3
i
2
i
1
e
+
-
3
e
+
-
2
e + -
1
N 3
N
2
N
m
1
i
3
i
2
i
1
e
+
-
3
e
+
-
2
e + -
1
N 3
N
2
N
m
1 1
m
d
e N
dt
=
2 2
m
d
e N
dt
=
3 3
m
d
e N
dt
=
3 1 2
1 2 3
m
d e e e
dt N N N
= = =
1 1 2 2 3 3
m
m
N i N i N i
+ +
=
1 2 3
1 2 3
1 1 1
m
e dt e dt e dt
N N N
= = =


Transformer Equivalent Circuit
Figure 7-7 Equivalent circuits of transformers: (a) ideal, and (b) actual.
1
e 2
e
3
e
+
+
+
1
i
2
i
3
i
( ) a
1
i
2
i
3
i
1
e
+
2
e
+
3
e
+
1 m
i
1
i
1 m
L
( ) b
1
e 2
e
3
e
+
+
+
1
i
2
i
3
i
( ) a
1
i
2
i
3
i
1
e
+
2
e
+
3
e
+
1 m
i
1
i
1 m
L
1
i
2
i
3
i
1
e
+
2
e
+
3
e
+
1 m
i
1
i
1 m
L
( ) b
194
Chapter 8 Switch-Mode DC Power Supplies
8-1 Applications of Switch-Mode DC Power Supplies
8-2 Need for Electrical Isolation
8-3 Classification of Transformer-Isolated DC-DC Converters
8-4 Flyback Converters
8-5 Forward Converters
8-6 Full-Bridge Converters
8-7 Half-Bridge and Push-Pull Converters
8-8 Practical Considerations
References
Problems
SWITCH-MODE DC POWER SUPPLIES
Figure 8-1 Block diagram of switch-mode dc power supplies.
60Hz
ac
input
rectifier
topology to convert
dc to dc with isolation
Feedback
controller
HF transformer
dc to HF ac
Output in
V
+
*
o
V
o
V
60Hz
ac
input
rectifier
topology to convert
dc to dc with isolation
Feedback
controller
HF transformer
dc to HF ac
Output in
V
+
*
o
V
o
V
NEED FOR ELECTRICAL ISOLATION
CLASSIFICATION
Flyback converters derived from Buck-Boost dc-dc converters
Forward converter derived from Buck dc-dc converters
Full-Bridge and Half-Bridge converters derived from Buck dc-dc converters
FLYBACK CONVERTERS
Figure 8-2 Buck-Boost and the Flyback converters.
in
V
in
i
o
V
+
in
V
L
i
o
V
+
out
i
( ) a ( ) b
in
V
+
o
V
+
( ) c
in
i
out
i
1
N
2
N
in
V
in
i
o
V
+
in
V
L
i
o
V
+
out
i
( ) a ( ) b
in
V
+
o
V
+
( ) c
in
i
out
i
in
V
in
i
o
V
+
in
V
L
i
o
V
+
out
i
( ) a ( ) b
in
V
+
o
V
+
( ) c
in
i
out
i
1
N
2
N
Figure 8-3 Flyback converter waveforms.
DT
s
- p p

( )
m
t
0
0
0
t
t
t
in
i
(0)
in
I
in
I
out
i
out
I
(0)
m
T
s
DT
s
DT
s
- p p

( )
m
t
0
0
0
t
t
t
in
i
(0)
in
I
in
I
out
i
out
I
(0)
m
T
s
DT
s
1 2
(1 )
in o
p p s s
V V
DT D T
N N

= =
2
1
1
o
in
V N D
V N D

=


Example 8-1 In a Flyback converter shown in Fig. 8-2c, 48
in
V V = , 5
o
V V = ,
1 2
/ 6 N N = , and the magnetizing inductance
1
150
m
L H = . This converter is operating
in equivalent CCM with a switching frequency 200
s
f kHz = and supplying an output
load 30
o
P W = . Assuming this converter to be lossless, calculate the waveforms
associated with it.
Solution From Eq. 8-8, the duty-ratio 0.385 D = , where 5
s
T s = . The average
currents are 0.625
in
I A = and 6
out
I A = . In Fig. 8-3, the rise in current during the on-
interval
s
DT can be calculated as
1
( )
(0) 0.616
in s
in in
m
V DT
I I A
L
= = .
From the waveforms of Fig. 8-3, the average input current can be calculated as follows:

(0)
0.625
2
in in
in
I I
I D A
+
= = ;
(0) 3.247
in in
I I A + =
From equations above, in Fig. 8-3,
1.93
in
I A = and (0) 1.315
in
I A = . The output current
has a peak value
1
2

11.58
out in
N
I I A
N
= = and
1
2
(0) (0) 7.89
out in
N
I I A
N
= = .

PSpice Modeling: C:\FirstCourse_PE_Book07\flyback.sch
Time
I(S1) I(D1)
0A
2A
4A
6A
8A
10A
12A
Simulation Results
FORWARD CONVERTERS
2
1
o in
N
V DV
N

=

Figure 8-4 Buck and Forward converters.
in
V
+
-
o
V
+
-
2
D
1
D
3
D
1
N
2
N
3
N
in
V
+
-
o
V
+
-
L
i
+
A
v
( ) b ( ) a
( ) q t
( ) q t
L
i
+
1
v
3
i
1
i
in
V
+
-
o
V
+
-
2
D
1
D
3
D
1
N
2
N
3
N
in
V
+
-
o
V
+
-
L
i
+
A
v
( ) b ( ) a
( ) q t
( ) q t
L
i
+
1
v
3
i
1
i
Figure 8-5 Forward converter operation.
A
v
0
2 1
( / )
in
N N V
s
DT
s
T
t
2 1
( / )
in
N N DV
A
v
0
2 1
( / )
in
N N V
s
DT
s
T
t
2 1
( / )
in
N N DV
Fig. 8-6 Forward converter core flux.
s
DT
s
T
demag
T
m
t
0
s
DT
s
T
demag
T
m
t
0
Figure 8-4 Buck and Forward converters.
in
V
+
-
o
V
+
-
2
D
1
D
3
D
1
N
2
N
3
N
in
V
+
-
o
V
+
-
L
i
+
A
v
( ) b ( ) a
( ) q t
( ) q t
L
i
+
1
v
3
i
1
i
in
V
+
-
o
V
+
-
2
D
1
D
3
D
1
N
2
N
3
N
in
V
+
-
o
V
+
-
L
i
+
A
v
( ) b ( ) a
( ) q t
( ) q t
L
i
+
1
v
3
i
1
i
Example 8-2 In a Forward converter shown in Fig. 8-4b, 48
in
V V = , 5
o
V V = ,
1 2
/ 3.5 N N = ,
1 3
/ 1 N N = , and the magnetizing inductance
1
150
m
L H = . This converter
is operating in equivalent CCM with a switching frequency 200
s
f kHz = and supplying
an output load 60
o
P W = . Assume the filter inductor current
L
i to be ripple-free.
Assuming this converter to be lossless, calculate the waveforms associated with it.
s
T s = . The average
currents are 1.25
in
I A = and 12
out
I A = . The voltage waveforms are shown in Fig. 8-7,
where the output current reflected to the primary side is ( )
2 1
/ 3.43
out
N N I A = . The peak
of the magnetizing current during the on-interval
s
DT can be calculated as
1
( )
0.5
in s
m
m
V DT
I A
L
= = .
During the transistor off-interval, this magnetizing current, flowing through the diode D3,
decreases and comes to zero after 1.825
demag s
T DT s = = , as shown in Fig. 8-7.
Figure 8-7 Waveforms in the Forward converter of Example 8-2.
0
0
0
0
t
t
t
t
A
v
1
v
1
i
3
i
s DT
demag T
s T
48V
48V
3.43A
3.93A
0.5 A
0
0
0
0
t
t
t
t
A
v
1
v
1
i
3
i
s DT
demag T
s T
48V
48V
3.43A
3.93A
0.5 A
PSpice Modeling: C:\FirstCourse_PE_Book07\forward.sch
Time
0s 2us 4us 6us 8us 10us 12us 14us 16us 18us 20us
I(D_Pwr3) I(D_Pwr2)
0A
1.0A
2.0A
3.0A
4.0A
5.0A
Simulation Results
Two-Switch Forward Converters
Figure 8-8 Two-switch Forward converter.
( ) q t
in
V
+
1
T
2
T
2
D
1
D
o
D
F
D
L
i
( ) q t
in
V
+
1
T
2
T
2
D
1
D
o
D
F
D
L
i
FULL-BRIDGE CONVERTERS
Pulse-Width Modulated (PWM), and
Phase-Shift Modulated (PSM)
Figure 8-9 Full-Bridge converter.
in
V
T
1
T
3
T
2
T
4
D
1
D
2
i
L
o
V
+
-
v
1
1 N
2 N
2 N
+
-
+
A
v
+
in
V
T
1
T
3
T
2
T
4
D
1
D
2
i
L
o
V
+
-
v
1
1 N
2 N
2 N
+
-
+
A
v
+
Figure 8-10 Full-Bridge converter waveforms.

s
DT
s
T
s
DT
1
v
0
in
V
( )
in
V
t
s
DT
s
T
s
DT
1
v
0
in
V
( )
in
V
t
PWM Control
Figure 8-11 PWM-IC and control signals for transistors.
v
c
r
v
to T and T
1 2
to T and T
3 4
T , T
on
1 2 T , T
on
3 4 all
off
all
off
all
off
T , T
on
1 2
r
v
0
v
c
( ) a
( ) b
v
c
r
v
to T and T
1 2
to T and T
3 4
T , T
on
1 2 T , T
on
3 4 all
off
all
off
all
off
T , T
on
1 2
r
v
0
v
c
( ) a
( ) b
Figure 8-12 Full-Bridge: sub-circuits.
+
-
+
-
A
v
2
1
in
N
V
N
+
-
1
D
1
i
o
V
1
v
L
i / 2
L
i
/ 2
L
i
2
v
+
-
2
v
+
-
1
v
+
-
o
V
+
-
L
i
L
i
( ) b
( ) a
+
-
0
A
v = +
-
+
-
A
v
2
1
in
N
V
N
+
-
1
D
1
i
o
V
1
v
L
i / 2
L
i
/ 2
L
i
2
v
+
-
2
v
+
-
1
v
+
-
o
V
+
-
L
i
L
i
( ) b
( ) a
+
-
0
A
v =
2
1
2
o
in
V N
D
V N

=

Figure 8-13 Full-Bridge converter waveforms.
1
v
0
0 t
t
A
v
1 2
, T T
s
DT
s
T
/ 2
s
T
3 4
, T T
2
1
in
N
V
N
2
1
2
A o in
N
V V DV
N
= =
1
v
0
0 t
t
A
v
1 2
, T T
s
DT
s
T
/ 2
s
T
3 4
, T T
2
1
in
N
V
N
2
1
2
A o in
N
V V DV
N
= =
Example 8-3 In a Full-bridge converter shown in Fig. 8-9, 48
in
V V = , 5
o
V V = , and
1 2
/ 6 N N = . This converter is operating in CCM with a switching frequency
200
s
f kHz = and supplying an output load 100
o
P W = . The filter inductor has an
inductance of 0.25 L H = . Assuming this converter to be lossless, calculate the
waveforms associated with it.
s
T s = . The average
currents are 2.083
in
I A = and 20
out
I A = . The voltage waveforms are shown in Fig. 8-
14. The peak-peak-ripple in the filter inductor current
L
i can be calculated from the
voltage waveforms in Fig. 8-14
,
( )( )
18.75
A o s
L p p
v V DT
I A
L
= = .
Therefore,
L
i waveform is as shown in Fig. 8-14, with a minimum of
,
, min
10.625
2
L p p
L out
I
I I A
= = and a maximum of
,
, max
29.375
2
L p p
L out
I
I I A
= + = .
Taking the transformer turns-ratio into account, the primary current
1
i and the input
current
in
i ramp from 1.77 A to 4.896 A, and are zero when all the transistors are off.
Figure 8-14 Waveforms of the Full-Bridge converter of Example 8-3.
0
0
0
0
0
t
t
t
t
t
1
v
A
v
A o
V V =
L
i
1
i
in
i
s
DT
/ 2
s
T
48V
8V
5V
10.625 A
29.375 A
1.77 A
4.896 A
1.77 A
4.896 A
0
0
0
0
0
t
t
t
t
t
1
v
A
v
A o
V V =
L
i
1
i
in
i
0
0
0
0
0
t
t
t
t
t
1
v
A
v
A o
V V =
L
i
1
i
in
i
s
DT
/ 2
s
T
48V
8V
5V
10.625 A
29.375 A
1.77 A
4.896 A
1.77 A
4.896 A
PSpice Modeling: C:\FirstCourse_PE_Book07\fbsmps.sch
Time
V(R1:2,D2:2)
-200V
-100V
0V
100V
200V
Simulation Results
Half-Bridge and Push-Pull Converters
Figure 8-15 Half-Bridge and Push-Pull converters.
D
2
2
in
V
2
in
V
T
1
T
2
D
1
+
-
in
V
A
v
i
L
+
+
+
T
1
T
2
+
-
i
L
in
V
A
v
+
( ) a
( ) b
2 N
2 N
+
-
V
O
+
-
V
O
D
2
D
1
1 N
1 N
1 N
2 N
2 N
D
2
2
in
V
2
in
V
T
1
T
2
D
1
+
-
in
V
A
v
i
L
+
+
+
T
1
T
2
+
-
i
L
in
V
A
v
+
T
1
T
2
+
-
i
L
in
V
A
v
+
( ) a
( ) b
2 N
2 N
+
-
V
O
+
-
V
O
D
2
D
1
1 N
1 N
1 N
2 N
2 N
Chapter 9 Design of High-Frequency Inductors and Transformers
9-1 Introduction
9-2 Basics of Magnetic Design
9-3 Inductor and Transformer Construction
9-4 Area-Product Method
9-5 Design Example of an Inductor
9-6 Design Example of a Transformer for a Forward Converter
9-7 Thermal Considerations
References
Problems
218
BASICS OF MAGNETIC DESIGN
The peak flux density
max
B in the magnetic core to limit core losses, and
The peak current density
max
J in the winding conductors to limit conduction
losses
INDUCTOR AND TRANSFORMER CONSTRUCTION
Figure 9-1 Cross-sections.
window
A
core
A
cond
A
( ) a
window
A
core
A
( ) b
window
A
core
A
cond
A
( ) a
window
A
core
A
cond
A
( ) a
window
A
core
A
( ) b
window
A
core
A
( ) b
AREA-PRODUCT METHOD
Core WindowArea
window
A
( )
,
1
window y cond y
y w
A N A
k
=

,
,
max
rms y
cond y
I
A
J
=
( )
,
max
y rms y
y
window
w
N I
A
k J
=

Core Cross-Sectional Area
core
A
inductor:
max
core
A
B
LI
N
=
1
conv in
s
k V
N f
=
transformer:
Figure9-2Waveforms inatransformer for aForwardconverter.
1 v
t
t
in V
( ) in V
0
0
s T s DT
1 v
t
t
in V
( ) in V
0
0
s T s DT
max
core
LI
A
NB
=
max
conv y
core
y s
k V
A
N f B
=
Core Area-Product ( )
p core window
A A A =
p core window
A A A =
inductor:
max max
rms
p
w
LII
A
k J B
=
transformer:
,
max max
conv y y rms
p
w s
k V I
A
k B J f
=

Design Procedure Based on Area-Product
p
A
max
core
LI
N
B A
=
max
conv y
y
core s
k V
N
A f B
=
2
g
N
L
=
g
g
o core
A
/
=
2
o core
g
N A
L
= /
inductor:
transformer:
DESIGN EXAMPLE OF AN INDUCTOR
In this example, we will discuss the design of an inductor that has an inductance
100 L H = . The worst-case current through the inductor is shown in Fig. 9-3, where the
average current 5.0 I A = , and the peak-peak ripple 0.75 I A = at the switching
frequency 100
s
f kHz = . We will assume the following maximum values for the flux
density and the current density:
max
0.25 B T = , and
2
max
6.0 / J A mm = (for larger cores,
this is typically in a range of 3 to
2
4 / A mm ). The window fill factor is assumed to be
0.5
w
k = .
Figure9-3Inductor current waveforms.
I
I
t
L
i
I
I
t
L
i
5.375
2
I
I I A
= + =
2 2
1
5.0
12
rms
I I I A = + =
6
12 4
6
100 10 5.375 5
10 3587
0.5 0.25 6 10
p
A mm

= =

From the Magnetics, Inc. catalog [2], we will select a P-type material, which has the
saturation flux density of 0.5T and is quite suitable for use at the switching frequency of
100kHz . A pot core 2616, which is shown in Fig. 9-4 for a laboratory experiment, has
the core Area
2
93.1
core
A mm = and the window Area
2
39
window
A mm = . Therefore, we
will select this core, which has an Area-Product
4
93.1 39 3631
p
A mm = = .
Winding wire cross sectional area
2
max
/ 5.0/6.0 0.83
cond rms
A I J mm = = = . We will use
five strands of American Wire Gauge AWG25 wires [3], each with a cross-sectional area
of
2
0.16mm , in parallel.
6
100 5.375
23
0.25 93.1 10
N

=

=
2 7 6
23 4 10 93.1 10
0.62
100
g
mm

= / =
Figure 9-4 Pot core mounted on a plug-in board.
DESIGN EXAMPLE OF A TRANSFORMER FOR A FORWARD CONVERTER
The required electrical specifications for the transformer in a Forward converter are as
follows: 100
s
f kHz = and
1 2 3
30 V V V V = = = . Assume the rms value of the current in
each winding to be 2.5 A . We will choose the following values for this design:
max
0.25T B = and
2
max
5A/mm J = .
For the pot core 2213 [2],
2
63.9 mm
core
A = ,
2
29.2 mm
window
A = , and therefore
4
1866mm
p
A = .
0.5
w
k = 0.5
conv
k =
4
y ,
max max
1800 mm
conv
p rms y
y w s
k
A V I
k f B J
= =
1, 2
,1
max
2.5
0.5 mm
5
rms
cond
I
A
J
= = =
We will use three strands of AWG25 wires [3], each with a cross-sectional area of
2
0.16mm , in parallel for each winding.
( ) ( )
1
6 3
0.5 30
10
63.9 10 100 10 0.25
N

=

=
1 2 3
10 N N N = = =
9-7 THERMAL CONSIDERATIONS
Designs presented here do not include eddy current losses in the windings, which can be
very substantial due to proximity effects. These proximity losses in a conductor are due
to the high-frequency magnetic field generated by other conductors in close proximity.
To minimize these proximity losses suggests inductors with a single-layer construction.
In transformers, windings can be interleaved to minimize these losses, as described in
detail in [1]. Therefore, the area-product method discussed in this chapter is a good
starting point, but the designs must be evaluated for temperature rise due to additional
losses.
227
Chapter 10 Soft-Switching In DC-DC Converters And Inverters For Induction
Heating And Compact Fluorescent Lamps
10-1 Introduction
10-2 Hard-Switching In the Switching Power-Poles
10-3 Soft-Switching In the Switching Power-Poles
10-4 Inverters for Induction Heating and Compact Fluorescent Lamps
References
Problems
HARD-SWITCHING IN SWITCHING POWER-POLES
Figure 10-1 Hard switching in a power-pole.
( ) b
0
t
o
I DS
v
, c on
t
ri
t
fv
t
0
t
D
i
in
V
, c off
t
rv
t
fi
t
DS
v
in
V
D
i
, c on
t
, c off
t
sw
p
in o
V I
in o
V I
sw
p
(a)
in
V
+
D
i
o
I
GG
R
+
DS
v
( ) b
0
t
o
I DS
v
, c on
t
ri
t
fv
t
0
t
D
i
in
V
, c off
t
rv
t
fi
t
DS
v
in
V
D
i
, c on
t
, c off
t
sw
p
in o
V I
in o
V I
sw
p
0
t
o
I DS
v
, c on
t
ri
t
fv
t
0
t
D
i
in
V
, c off
t
rv
t
fi
t
DS
v
in
V
D
i
, c on
t
, c off
t
sw
p
in o
V I
in o
V I
sw
p
(a)
in
V
+
D
i
o
I
GG
R
+
DS
v
(a)
in
V
+
D
i
o
I
GG
R
+
DS
v
( )
( ) ( ) sw s c on c off
P f t t +
SOFT-SWITCHING IN SWITCHING POWER-POLES
Zero Voltage Switching (ZVS)
Figure 10-2 ZVS in a MOSFET.
( ) a ( ) b ( ) a ( ) b
- ZVS (zero voltage switching), and
- ZCS (zero current switching)
Synchronous Buck Converter with ZVS
Figure 10-3 Synchronous-rectified Buck converter.
in
V
o
V
A
v
T
+
T
q
+
q
L
i
q
+
q
A
v
L
i
t
t
t
L
I
0 t =
s
DT
s
T
in
V
o
V 0
0
0
0
L
I
( ) a
( ) b
in
V
o
V
A
v
T
+
T
q
+
q
L
i
q
+
q
A
v
L
i
t
t
t
L
I
0 t =
s
DT
s
T
in
V
o
V 0
0
0
0
L
I
( ) a
( ) b
Figure 10-4 Synchronous-rectified Buck converter with ZVS.
in
V
o
V
T
+
T
q
+
q
L
i
C
C
+
q
+
q
0 t =
delay
t
1
0
0
1
( ) a ( ) b
in
V
o
V
T
+
T
q
+
q
L
i
C
C
+
q
+
q
0 t =
delay
t
1
0
0
1
( ) a ( ) b
in
C C
v v V
+
+ =
0
C C
d d
C v C v
dt dt
+
+ =
0
C C
i i
+
+ =
C C
i i
+
=
2
L
C C
I
i i
+
= =
Fig. 10-5 Transition in synchronous-rectified Buck converter with ZVS.
in
V
L
I
T
+
T
0 q
+
=
0 q
=
C
C
+
C
i +
C
i
D
D
+
C
v
C
v +
_
+
_
+
( ) a
in
V
L
I
T
+
T
0 q
+
=
q
( ) b
in
V
L
I
T
+
T
0 q
+
=
0 q
=
C
C
+
C
i +
C
i
D
D
+
C
v
C
v +
_
+
_
+
( ) a
in
V
L
I
T
+
T
0 q
+
=
q
( ) b
in
V
L
I
T
+
T
0 q
+
=
q
( ) b
PSpice Modeling: C:\FirstCourse_PE_Book07\zvscv.sch
Time
0s 5us 10us 15us 20us 25us 30us
V(GA2) V(GA1) I(L1)
-1.0
0
1.0
2.0
3.0
Simulation Results
Phase-Shift Modulated (PSM) DC-DC Converter
Figure 10-6 Phase-Shift Modulated (PSM) DC-DCConverter.
T
A
+
T
A
T
B
T
B
+
D
b
+
D
b
D
a
D
a
+
+
2
d
V
o
I
A
B
a
b
+
2
d
V
D
A
+
D
A
D
B
D
B
+
lT
L
0 ficticious
L
i
(a)
+
in
V
AB
i
+
AB
v
AB
v
B
v
A
v
AB
i
t
(b)
T
A
+
T
A
T
B
T
B
+
D
b
+
D
b
D
a
D
a
+
+
2
d
V
o
I
A
B
a
b
+
2
d
V
D
A
+
D
A
D
B
D
B
+
lT
L
0 ficticious
L
i
T
A
+
T
A
T
B
T
B
+
D
b
+
D
b
D
a
D
a
+
+
2
d
V
o
I
A
B
a
b
+
2
d
V
D
A
+
D
A
D
B
D
B
+
lT
L
0 ficticious
L
i
(a)
+
in
V
AB
i
+
AB
v
AB
v
B
v
A
v
AB
i
t
(b)
(a)
+
in
V
AB
i
+
AB
v
AB
v
B
v
A
v
AB
i
t
AB
v
B
v
A
v
AB
i
t
(b)
Figure 10-7 Asuperior hybrid topology to achieve ZVSdown to no load [3-5].
Q1
Q2
Q3
Q4
+
V
in
+
Q5
Q6
_ _
uncontrolledfull bridge phase modulated full bridge
V
o
Q1
Q2
Q3
Q4
+
V
in
+
Q5
Q6
_ _
uncontrolledfull bridge phase modulated full bridge
V
o
Hybrid Topology
R. Ayyanar, N. Mohan, Zero voltage switching DC-DC converter,
US patent 6,310,785, 2001.
236
Chapter 11 Applications of Switch-Mode Power Electronics in Motor
Drives, Uninterruptible Power Supplies and Power Systems
11-1 Introduction
11-2 Electric Motor Drives
11-3 Uninterruptible Power Supplies
11-4 Utility Applications
References
Problems
Figure 11-1 Block diagramof an electric drive system.
Power
Processing
Unit fixed
form
ElectricSource
(utility)
Controller
ElectricDrive
adjustable
form
Sensors
input command
(speed/ position)
Motor
speed/
position
Load
Power
Processing
Unit fixed
form
ElectricSource
(utility)
Controller
ElectricDrive
adjustable
form
Sensors
input command
(speed/ position)
Motor
speed/
position
Load
DC MOTORS
Figure 11-2 Exploded view of a dc motor [Source: Electro-Craft Corporation].
stator
magnets
rotor
winding
stator
magnets
rotor
winding
Operating Principles of DC Machines
T em a
T k i =
E a
=
m
e k
T E
k k =
DC-Machine Equivalent Circuit
Figure 11-3 DC motor equivalent circuit.
PPU
em
a
T
T
i
k
=
a
R
a
L
a E m
e k =
+
+
a
V
PPU
em
a
T
T
i
k
=
a
R
a
L
a E m
e k =
+
+
a
V
i
a
a a a a a
di
v e R L
dt
= + +
1
( )
m
em L
eq
d
T T
dt J
=
Torque-Speed Characteristics
( )
em L
a
T
T T
I
k
=
=
( ) /
a a em T a a a a
m
E E E
V R T k E V R I
k k k

= = =
Figure 11-4 (a) Torque-Speed characteristics, and (b)
a
V versus
m
.
0
constant at its rated value
f
a1 a2 a3 a4
V V V V > > >
rated
a1
V =
a2
V
a3
V
a4
V
rated
, m rated
em
T m
a
V
( ) a ( ) b
0
0
constant at its rated value
f
a1 a2 a3 a4
V V V V > > >
rated
a1
V =
a2
V
a3
V
a4
V
rated
, m rated
em
T m
a
V
( ) a ( ) b
0
PERMANENT-MAGNET AC MACHINES
Figure 11-5 Two-pole PMAC machine.
axis c
axis a
axis b
N
S
b
i
a
i
c
i
m
( )
m
t
( )
r
B t
,
axis a
( ) a
( ) b
axis c
axis a
axis b
N
S
b
i
a
i
c
i
m
axis c
axis a
axis b
N
S
b
i
a
i
c
i
m
( )
m
t
( )
r
B t
,
axis a
( )
m
t
( )
r
B t
,
axis a
( ) a
( ) b
Figure 11-6 Block diagram of a PMAC machine.
Power
Processing
Unit
Utility
Control
input
Sinusoidal
PMAC
motor
Position
sensor
Load
Controller
a
b
c
i
i
i
( )
m
t
Power
Processing
Unit
Utility
Control
input
Sinusoidal
PMAC
motor
Position
sensor
Load
Controller
a
b
c
i
i
i
( )
m
t
Figure 11-7 Equivalent circuit diagram and the phasor diagram of PMAC (2 pole).
PPU
+
a
V
, 0
,
0
em phase
a
T phase
T
I
k
=
s
R
s
L
0
,
0
ma E phase m
E k =

+
( ) a
( ) b
a
I
ma
E
m s a
j L I
a
V
PPU
+
a
V
, 0
,
0
em phase
a
T phase
T
I
k
=
s
R
s
L
0
,
0
ma E phase m
E k =

+
( ) a
( ) b
a
I
ma
E
m s a
j L I
a
V
PMAC Torque-Speed Characteristics
Figure 11-8 Torque-speed characteristics and the voltage versus frequency in PMAC.
m
0
em
T
1
f
1 2 3 4
f f f f > > >
2
m
f

=
a
V
0
( ) a ( ) b
2
f
3
f
4
f
m
0
em
T
1
f
1 2 3 4
f f f f > > >
2
m
f

=
a
V
0
( ) a ( ) b
2
f
3
f
4
f
Induction Machines
Figure 11-9 (a) Three-phase stator; (b) squirrel-cage rotor.
axis a
axis b
axis c
/ 2 3
/ 2 3
/ 2 3
b
i
a
i
c
i
( ) a
( ) b
axis a
axis b
axis c
/ 2 3
/ 2 3
/ 2 3
b
i
a
i
c
i
axis a
axis b
axis c
/ 2 3
/ 2 3
/ 2 3
b
i
a
i
c
i
( ) a
( ) b
I 90 , I 210 , and I 330
o o o
ma m mb m mc m
I I I = = =
2
syn
f =
2
for a -pole machine
/ 2
syn
f
p
p
=
Principles of Induction Motor Operation
0 , 120 , and 240
o o o
a rms b rms c rms
V V V V V V = = =
slip syn m
slip speed =
slip
slip
syn
slip frequency f f
=
Figure 11-10 Induction machine: applied voltages and magnetizing currents.
mc
I
mb
I
ma
I
c
V
b
V
a
V
a
i
b
i
c
i
c
v
b
v
a
v
b
v
c
v
n +
+
+
+
+
a
v
( ) a ( ) b
mc
I
mb
I
ma
I
c
V
b
V
a
V
a
i
b
i
c
i
c
v
b
v
a
v
b
v
c
v
n +
+
+
+
+
a
v
a
i
b
i
c
i
c
v
b
v
a
v
b
v
c
v
n +
+
+
+
+
a
v
( ) a ( ) b
Per-Phase Equivalent Circuit of Induction Machines
Figure 11-11 Induction motor equivalent circuit and phasor diagram.
PPU
a
I
+
a
V
0
0
ra ra
I I =
+
ra E slip
V k =
r
R
0
0
a E m
E k =
0
0
a ma E syn
V E k = =
ma
I
m
L
( ) a
( ) b
a
I
a
E
r ra
R I
a
V
ma
I
ra
I
PPU
a
I
+
a
V
0
0
ra ra
I I =
+
ra E slip
V k =
r
R
0
0
a E m
E k =
0
0
a ma E syn
V E k = =
ma
I
m
L
( ) a
( ) b
a
I
a
E
r ra
R I
a
V
ma
I
ra
I
Figure 11-12 Induction motors: Torque-speed characteristics and voltage vs. frequency.
m
0
em
T
2
syn
f

=
a
V
0
( ) a ( ) b
1 2 3 4
f f f f > > >
1
f
2
f
3
f
4
f
m
0
em
T
2
syn
f

=
a
V
0
( ) a ( ) b
1 2 3 4
f f f f > > >
1
f
2
f
3
f
4
f
1
f
2
f
3
f
4
f
UNINTERRUPTIBLE POWER SUPPLIES (UPS)
Fig. 11-13 CBEMA curve.
Figure 11-14 Block diagram of UPS.
Rectifier Inverter Filter
Critical
Load
Energy
Storage
Critical
Load
Energy
Storage
UTILITY APPLICATIONS OF SWITCH-MODE
POWER ELECTRONICS
Figure 11-15 Interaction of the switch-mode converter with the ac utility system.
d
V
+
conv
v
s
v
i
d
V
+
conv
v
s
v
i
Figure 11-16 Per-phase equivalent circuit and the phasor diagram.
+
conv
V
s
V
I
+
jX
( ) a ( ) b
s
V
jXI
I
conv
V
Re
+
conv
V
s
V
I
+
jX
( ) a ( ) b
s
V
jXI
I
conv
V
Re
254
Chapter 12 Synthesis of DC and Low-Frequency Sinusoidal AC Voltages for
Motor Drives and UPS
12-1 Introduction
12-2 Bi-Directional Switching Power-Pole as the Building Block
12-3 Converters for DC-Motor Drives
12-4 Synthesis of Low-Frequency AC
12-5 Single-Phase Inverters
12-6 Three-Phase Inverters
12-7 Multi-Level Inverters
12-8 Converters for Bi-Directional Power Flow
12-9 Matrix Converters
References
Problems
Figure 12-1 Voltage-link system.
conv1 conv2
controller
utility Load
conv1 conv2
controller
utility Load
Figure 12-2 Converters for dc and ac motor drives.
+
-
v
A
v
B
v
C
i
A
acmotor
A
B
C
V
d
n
( ) b
+
-
V
d v
o
i
o
dcmotor
A
B
+
e
a
+
( ) a
+
-
v
A
v
B
v
C
i
A
acmotor
A
B
C
V
d
n
( ) b
+
-
V
d v
o
i
o
dcmotor
A
B
+
e
a
+
( ) a
+
-
V
d v
o
i
o
dcmotor
A
B
+
e
a
+
( ) a
SWITCHING POWER-POLE AS THE BUILDING BLOCK
Figure 12-3 Bi-directional power flow through a switching power-pole.
q
d
V
L
i
Buck Boost
(1 ) q q
=
d
V
q
1 q =
0 q =
Buck
1 q =
0 q =
d
V
Boost
(a) (b) i
L
= positive (c) i
L
= negative
q
q
q
q
d
V
L
i
Buck Boost
(1 ) q q
=
d
V
q
1 q =
0 q =
Buck
1 q =
0 q =
d
V
Boost
(a) (b) i
L
= positive (b) i
L
= positive (c) i
L
= negative (c) i
L
= negative
q
q
q

Figure 12-4 Bidirectional Switching power-pole.
q
d
V
L
i
d
V
1 q =
d
V
(a)
0 q =
(b) 1 q = (c) 0 q =
q
d
V
L
i
d
V
1 q =
d
V
(a)
0 q =
(b) 1 q = (b) 1 q = (c) 0 q = (c) 0 q =
Figure 12-5 switching-cycle averaged representation of the bi-directional power-pole.
a
q
+
d
V
da
i
a
i
a
N
+
aN
v
(a) (b)
1:
a
d
a
i
d
V
da
i
+
aN
v
a
q
+
d
V
da
i
a
i
a
N
+
aN
v
(a) (b)
1:
a
d
a
i
d
V
da
i
+
aN
v
Figure 12-6 Waveforms for PWM in a switching power-pole.
tri
V
0
0
0
t
t
t
tri
v
, cntrl a
v
a
q
aN
v
a
d
a d
d V
d
V
2
s
T
2
s
a
T
d
tri
v
tri
V
0
0
0
t
t
t
tri
v
, cntrl a
v
a
q
aN
v
a
d
a d
d V
d
V
2
s
T
2
s
a
T
d
tri
v
Pulse-Width-Modulation (PWM) of the Bi-Directional
Switching Power-Pole
Figure 12-7 Switching power-pole and its duty-ratio control.
d
V
+
tri
V
, cntrl a
v
a
d
aN
v
+
a
q
+
d
V
da
i
a
i
a
N
+
aN
v
(a)
tri
v
, cntrl a
v
(b)
a
i
da
i
d
V
+
tri
V
, cntrl a
v
a
d
aN
v
+
a
q
+
d
V
da
i
a
i
a
N
+
aN
v
(a)
tri
v
, cntrl a
v
(b)
a
i
da
i
Figure 12-8 Harmonics in the output of a switching power-pole.
1
f
s
f 2
s
f 3
s
f 4
s
f
1 2 1 s
k f k f + ( ) b
h
V
s
f 2
s
f 3
s
f 4
s
f
h
V
0
( ) a
1
f
s
f 2
s
f 3
s
f 4
s
f
1 2 1 s
k f k f + ( ) b
h
V
1
f
s
f 2
s
f 3
s
f 4
s
f
1 2 1 s
k f k f + ( ) b
1
f
s
f 2
s
f 3
s
f 4
s
f
1 2 1 s
k f k f + ( ) b
h
V
s
f 2
s
f 3
s
f 4
s
f
h
V
0
( ) a
s
f 2
s
f 3
s
f 4
s
f
h
V
0
( ) a
1 2 1
sidebands
h s
f k f k f =
Figure 12-9 Converter for dc-motor drive.
a
q
+
d
V
a
N
(a)
b
q
n
b +
+
an
v
bn
v
+
o
v
(b)
N
2
d
V
2
d
V
2
o
an
v
v =
2
o
bn
v
v =
a
+
an
v
bn
v
+
o
v
+
n
a
q
+
d
V
a
N
(a)
b
q
n
b +
+
an
v
bn
v
+
o
v
(b)
N
2
d
V
2
d
V
2
o
an
v
v =
2
o
bn
v
v =
a
+
an
v
bn
v
+
o
v
+
n
DC-MOTOR DRIVES
Figure 12-10 switching-cycle averaged representation of the converter for dc drives.
1/
tri
V
1/
tri
V
cntrl
v
tri
v
d
V
+
d
i
da
i
db
i
o
i
+
o
v
1:
a
d 1:
b
d
b
d
a
d
, cntrl a
v
, cntrl b
v
a
i
b
i
1/
tri
V
1/
tri
V
cntrl
v
tri
v
d
V
+
d
i
da
i
db
i
o
i
+
o
v
1:
a
d 1:
b
d
b
d
a
d
, cntrl a
v
, cntrl b
v
a
i
b
i
Figure 12-11 Gain of the converter for dc drives.
cntrl
v
o
v
PWM
k
cntrl
v
o
v
PWM
k
Figure 12-12 Switching voltage waveforms in a converter for dc drive.
tri
V
, cntrl a
v
, cntrl b
v
0
0
0
0
t
t
t
t
, a aN
q v
, b bN
q v
0
v
0
v
/ 2
s
T
/ 2
a s
d T
/ 2
b s
d T
tri
V
, cntrl a
v
, cntrl b
v
0
0
0
0
t
t
t
t
, a aN
q v
, b bN
q v
0
v
0
v
/ 2
s
T
/ 2
a s
d T
/ 2
b s
d T
Figure 12-13 Currents defined in the converter for dc-motor drives.
+
-
d
V
v
o
i
o
dc motor
a
b
+
e
a
+
da
i
db
i
d
i
a
i
b
i
+
-
d
V
v
o
i
o
dc motor
a
b
+
e
a
+
da
i
db
i
d
i
a
i
b
i
Fig. 12-14 Superposition of dc and ripple-frequency variables.
( ) a ( ) b
+
+ + +

o
v
a
e , o ripple
v
a
R
a
L
o
i , o ripple
i
( ) a ( ) b
+
+ + +

o
v
a
e , o ripple
v
a
R
a
L
o
i , o ripple
i
Example 12-3
Example 12-3 continued
Figure 12-15 Switching current waveforms in Example 12-3.
4.5 A
3.5A
4.5A
3.5 A
112V
238
o
v V =
350V
350V
0
/
s
t T
/
s
t T
/
s
t T
/
s
t T
/
s
t T
/
s
t T
/
s
t T
0
0
0
0
0
0
1
tri
V V =
,
0.84
control a
v V =
,
0.16
control b
v V =
0 / 2
b
d / 2
a
d
1
2
1
aN
v
bN
v
o
v
, o ripple
v
4
o
i A =
o
i
d
i
350V
238
o
v V =
( 238)V
0.34
2
a b
d d
=
2.72
d
i A =
4.5 A
3.5A
4.5A
3.5 A
112V
238
o
v V =
350V
350V
0
/
s
t T
/
s
t T
/
s
t T
/
s
t T
/
s
t T
/
s
t T
/
s
t T
0
0
0
0
0
0
1
tri
V V =
,
0.84
control a
v V =
,
0.16
control b
v V =
0 / 2
b
d / 2
a
d
1
2
1
aN
v
bN
v
o
v
, o ripple
v
4
o
i A =
o
i
d
i
350V
238
o
v V =
( 238)V
0.34
2
a b
d d
=
2.72
d
i A =
Figure 12-16 Waveforms of a switching power-pole to synthesize low-frequency ac.
aN
v
0 t
d
V
aN
v
aN
v
aN
v
0
0
s
T
aN
v
0 t
d
V
aN
v
aN
v
aN
v
0
0
s
T
Synthesis of Low-Frequency AC
Figure 12-17 Single-phase uninterruptible power supply.
d
V
+
d
i
a
i
b
i
+
o
v
Critical
Load
a
q
b
q
( ) a
d
V
+
d
i
a
i
b
i
+
o
v Critical
Load
a
d
( ) b
o
i o
i
1:
a
d 1:
a
d 1:
a
d 1:
b
d
d
V
+
d
i
a
i
b
i
+
o
v
Critical
Load
a
q
b
q
( ) a
d
V
+
d
i
a
i
b
i
+
o
v Critical
Load
a
d
( ) b
o
i o
i
1:
a
d 1:
a
d 1:
a
d 1:
b
d
Single-Phase Inverters -
UNINTERRUPTIBLE POWER SUPPLIES (UPS)
Figure 12-18 Switching-cycle averaged voltages in a single-phase UPS.
d
V
0.5
com d
v V =
0
aN
v
bN
v
o
v
t
an
v
d
V
0.5
com d
v V =
0
aN
v
bN
v
o
v
t
an
v
Figure 12-19 Output voltage and current.
0
1
t
o
v
o
i
1
0
1
t
o
v
o
i
1

Figure 12-20 Waveforms in the UPS of Example 12-4.
tri
V
, cntrl a
v
, cntrl b
v
0
0
0
0
t
t
t
t
, a aN
q v
, b bN
q v
0
v
0
v
/ 2
s
T
/ 2
a s
d T
/ 2
b s
d T
tri
V
, cntrl a
v
, cntrl b
v
0
0
0
0
t
t
t
t
, a aN
q v
, b bN
q v
0
v
0
v
/ 2
s
T
/ 2
a s
d T
/ 2
b s
d T
Example 12-4
Three-Phase Inverters
Figure 12-21 Three-phase converter.
( ) a ( ) b
+
d
V
+
d
V
a
q
b
q
c
q
N
a
b
c
n
a
b
c
1:
a
d 1:
b
d 1:
c
d
N
Superposition -
Figure 12-22 switching-cycle averaged output voltages in a three-phase converter.
( ) a
( ) b
an
v
bn
v
cn
v
N
n
com
v
com
v
com
v
com
v
com
v
com
v
n
N
i
i
i
a
b
c
aN
v
+
+ an
v
Sine PWM
Figure 12-23 switching-cycle averaged voltages due to Sine-PWM.
t 0
2
d
V
d
V
aN
v
bN
v
cN
v
an
v
Example 12-5
Figure 12-24 Switching waveforms in Example 12-5.
0
0
0
0
tri
V
, cntrl a
v
, cntrl b
v
, cntrl c
v
aN
v
bN
v
cN
v
aN
v
bN
v
cN
v
/ 2
s
T
t
t
t
t
2
s
a
T
d
2
s
b
T
d
2
s
c
T
d
PSpice Modeling: C:\FirstCourse_PE_Book07\PWMinv3.sch
PSpice Modeling: C:\FirstCourse_PE_Book07\pwninv3ph_avg.sch
Time
I(L3) I(L2) I(L1)
-20A
-10A
0A
10A
20A
Simulation Results
aN
v
bN
v
cN
v
d
V
2
d
V
0
1
t
t
aN
v
bN
v
cN
v
d
V
2
d
V
0
1
t
t
Figure 12-25 Three-phase voltages to be synthesized.
SV-PWM
Figure 12-26 Waveforms in sector 1 of Fig. 12-25
tt
aN
v
bN
v
cN
v
d
V
/ 2
d
V
0
d
V
+
( )
aN
v t
+
1: ( )
a
d t
+
( )
cN
v t
1: ( )
c
d t
a
c
N
( ) a ( ) b
tt
aN
v
bN
v
cN
v
d
V
/ 2
d
V
0
tt
aN
v
bN
v
cN
v
d
V
/ 2
d
V
0
d
V
+
( )
aN
v t
+
1: ( )
a
d t
+
( )
cN
v t
1: ( )
c
d t
a
c
d
V
+
( )
aN
v t
+
1: ( )
a
d t
+
( )
cN
v t
1: ( )
c
d t
a
c
N
( ) a ( ) b
SV-PWM: Sector 1
Figure 12-27 Duty-ratio
a
d in Sine-PWM and SV-PWM for the same phase output.
1
0
0.5
Sine-PWM
SV-PWM
t
,
ctrl aN
aN
tri
v
d
V
=
, , ctrl com SV PWM
v

1
0
0.5
Sine-PWM
SV-PWM
t
,
ctrl aN
aN
tri
v
d
V
=
, , ctrl com SV PWM
v

0.5
k
d
v
V
+
a
d
1
0
0.5
Sine-PWM
SV-PWM
t
,
ctrl aN
aN
tri
v
d
V
=
, , ctrl com SV PWM
v

1
0
0.5
Sine-PWM
SV-PWM
t
,
ctrl aN
aN
tri
v
d
V
=
, , ctrl com SV PWM
v

0.5
k
d
v
V
+
a
d
0.5
k
d
v
V
+
a
d
SV-PWM versus Sine-PWM
Figure 12-28 Square-wave (six-step) waveforms.
bN
v
aN
v
cN
v
ab
v
0
0
0
0
t
t
t
t
2 0
1 ab
v
d
V
2 / 3 5 / 3 0
/ 3 4 / 3 0
2
0
1.1
d
V
bN
v
aN
v
cN
v
ab
v
0
0
0
0
t
t
t
t
2 0
1 ab
v
d
V
2 / 3 5 / 3 0
/ 3 4 / 3 0
2
0
1.1
d
V
Square-Wave (Six-Step) Operation
Figure 12-29 Three-level Inverters.
0
+
a b c
d
V
1 a
S
+
2 a
S
+
2 a
S
1 a
S
1
C
2
C
0
+
a b c
d
V
1 a
S
+
2 a
S
+
2 a
S
1 a
S
1
C
2
C
Three-Level Inverter
Figure 12-30 Voltage-link structure for bi-directional power flow.
AC motor
Rectifier
Inverter
P
P
motoring
mode
regenerative
braking mode
( ) i t
a ( ) v t
sa
( )
A
i t
n
ac motor

_
+
c b a
c
d
b
d a
d
C
d B
d A
d
A B C
+
d
V
+
( )
A
e t
a1
V
A
E V
sa1
+
An1
V
+
A1
I
a1
I
sinusoidal
( ) i t
a ( ) v t
a
+
+
d
V
( )
A
i t
+
( )
A
e t
n
s
L eq
L
s
L
eq
L
( ) c
( ) b
( ) a
AC motor
Rectifier
Inverter
P
P
motoring
mode
regenerative
braking mode
AC motor
Rectifier
Inverter
P
P
motoring
mode
regenerative
braking mode
( ) i t
a ( ) v t
sa
( )
A
i t
n
ac motor

_
+
c b a
c
d
b
d a
d
C
d B
d A
d
A B C
+
d
V
+
( )
A
e t
a1
V
A
E V
sa1
+
An1
V
+
A1
I
a1
I
sinusoidal
( ) i t
a ( ) v t
a
+
+
d
V
( )
A
i t
+
( )
A
e t
n
s
L eq
L
s
L
eq
L
( ) c
( ) b
( ) a
VOLTAGE-LINK STRUCTURE WITH
BI-DIRECTIONAL POWER FLOW
Figure 12-31 Matrix Converter.
v
C
v
B
v
A
v
c
v
b
v
a
i
a
d
aA
d
bA
d
cA
d
aB
d
aC
d
bB
d
bC
d
cB
d
cC
( ) a ( ) b
v
C
v
B
v
A
v
c
v
b
v
a
i
a
d
aA
d
bA
d
cA
d
aB
d
aC
d
bB
d
bC
d
cB
d
cC
v
C
v
B
v
A
v
c
v
b
v
a
i
a
d
aA
d
bA
d
cA
d
aB
d
aC
d
bB
d
bC
d
cB
d
cC
( ) a ( ) b
Matrix Converter
Figure 12-32 Matrix Converter switching-cycled averaged representation.
aA
d
bA
d
cA
d
aB
d
bB
d
cB
d
aC
d
bC
d
cC
d
A
i
B
i
C
i
a
i
b
i
c
i
a
v
b
v
c
v
A
v
B
v
C
v
aA
d
bA
d
cA
d
aB
d
bB
d
cB
d
aC
d
bC
d
cC
d
A
i
B
i
C
i
a
i
b
i
c
i
a
v
b
v
c
v
A
v
B
v
C
v
Figure 12-33 Common-mode offsets to ensure the realizable range of duty-ratios.
a aA
d D +
a aB
d D +
a aC
d D +
A
i
B
i
C
i
a
i
b
i
c
i
a
v
b
v
c
v
A
v
B
v
C
v
b bA
d D +
b bB
d D +
b bC
d D +
c cA
d D +
c cB
d D +
c cC
d D +
a aA
d D +
a aB
d D +
a aC
d D +
A
i
B
i
C
i
a
i
b
i
c
i
a
v
b
v
c
v
A
v
B
v
C
v
b bA
d D +
b bB
d D +
b bC
d D +
c cA
d D +
c cB
d D +
c cC
d D +
Figure 12-34 Modification of common-mode offsets to provide current path.

0.5
( )
a
D t ( )
b
D t ( )
c
D t
( ) ( ) ( ) a b c D t D t D t + +
t
1.0
( )
b
D t ( )
c
D t ( )
a
D t
( ) a
( ) b
aA a
d D + +
A
i
B
i
C
i
a
i
b
i
c
i
a
v
b
v
c
v
A
v
B
v
C
v
aB a
d D + + aC a
d D + +
bA b
d D + +
bB b
d D + + bC b
d D + +
cA c
d D + +
cB c
d D + + cC c
d D + +

0.5
( )
a
D t ( )
b
D t ( )
c
D t
( ) ( ) ( ) a b c D t D t D t + +
t
1.0
( )
b
D t ( )
c
D t ( )
a
D t
( ) a

0.5
( )
a
D t ( )
b
D t ( )
c
D t
( ) ( ) ( ) a b c D t D t D t + +
t
1.0
( )
b
D t ( )
c
D t ( )
a
D t
( ) a
( ) b
aA a
d D + +
A
i
B
i
C
i
a
i
b
i
c
i
a
v
b
v
c
v
A
v
B
v
C
v
aB a
d D + + aC a
d D + +
bA b
d D + +
bB b
d D + + bC b
d D + +
cA c
d D + +
cB c
d D + + cC c
d D + +
Figure 12-35 Generation of switching signals.

d aA
d aA + d bA
d aA
d aA + d bA
0
= 1 d aA + d bA d aA + d bA + d cA + d cA
q aA q aA
q bA q bA
q cA q cA
292
Chapter 13 Thyristor Converters
13-1 Introduction
13-2 Thyristors (SCRs)
13-3 Single-Phase, Phase-Controlled Thyristor Converters
13-4 Three-Phase, Full-Bridge Thyristor Converters
13-5 Current-Link Systems
References
Problems
Thyristors (SCRs)
Figure 13-1 Thyristors.
K
A
G
P
N
P
N
A
G
pn1
pn2
pn3
K
(a) (b)
K
A
G
K
A
G
P
N
P
N
A
G
pn1
pn2
pn3
K
P
N
P
N
A
G
pn1
pn2
pn3
K
(a) (b)
Figure 13-2 A simple thyristor circuit with a resistive load.
( ) b
t
t
t
0
0
0

d
v
d
V
s
v s
i
G
i
0 t =
( ) a
s
i
R
+
d
v
s
v
( ) b
t
t
t
0
0
0

d
v
d
V
s
v s
i
G
i
0 t =
( ) b
t
t
t
0
0
0

d
v
d
V
s
v s
i
G
i
0 t =
( ) a
s
i
R
+
d
v
s
v
( ) a
s
i
R
+
d
v
s
v
Figure 13-3 Thyristor circuit with a resistive load and a series inductance.
( ) b
t
t
t
0
0
0

d
v
d
V
s
v s
i
G
i
0 t =
( ) a
s
i
s
L
+
d
v s
v
R
( ) b
t
t
t
0
0
0

d
v
d
V
s
v s
i
G
i
0 t =
( ) b
t
t
t
0
0
0

d
v
d
V
s
v s
i
G
i
0 t =
( ) a
s
i
s
L
+
d
v s
v
R
( ) a
s
i
s
L
+
d
v s
v
R
Single-Phase, Phase-Controlled Thyristor Converters
Figure 13-4 Full-Bridge, single-phase thyristor converter.
(a)
s
v
+
s
L
s
i
4 2
3 1
d
i
d
v
a
e
+
s
v
+
4 2
3
1
d
v
+
d
I
s
i
(b) (a)
s
v
+
s
L
s
i
4 2
3 1
d
i
d
v
a
e
+
s
v
+
4 2
3
1
d
v
+
d
I
s
i
(b)
( ) ( ) and ( )
d s s d
v t v t i t I = = t < +
( ) ( ) and ( )
d s s d
v t v t i t I = = 2 t + < +
1 2

sin ( ) cos
d s s
V V t d t V

+
= =
1
4
s d
I I
=
1
1

cos
2
s s
P V I =
Figure 13-5 Single-phase thyristor converter waveforms.
d
I
d
I
G
i
0
0
0
s
v
d
v
d
V
t
t
t
s
v
1 s
i
s
i
0
( ) +
, 3 4 , 1 2 , 3 4
d
I
d
I
G
i
0
0
0
s
v
d
v
d
V
t
t
t
s
v
1 s
i
s
i
0
( ) +
, 3 4 , 1 2 , 3 4
1, 2 1, 2 3, 4
d
I
d
I
G
i
0
0
0
s
v
d
v
d
V
t
t
t
s
v
1 s
i
s
i
0
( ) +
, 3 4 , 1 2 , 3 4
d
I
d
I
G
i
0
0
0
s
v
d
v
d
V
t
t
t
s
v
1 s
i
s
i
0
( ) +
, 3 4 , 1 2 , 3 4
1, 2 1, 2 3, 4
Fig. 13-6 Effect of the delay angle .
(b)
(a)
0
o
150
o
180 o
90
d
V Rectifier
d d
P V I = = +
d
I
d
V
Inverter
d d
P V I = =
(b)
(a)
0
o
150
o
180 o
90
d
V
0
o
150
o
180 o
90
d
V Rectifier
d d
P V I = = +
d
I
d
V
Inverter
d d
P V I = =
Rectifier
d d
P V I = = +
d
I
d
V
Inverter
d d
P V I = =
Example 13-1 Draw the waveforms for the full-bridge thyristor converter of
Fig. 13-4b if its operating in an inverter mode with the delay angle equal to
0
150 .
Solution Since now equals
0
150 , in comparison to Fig. 13-5 the
s
i waveform is
shifted by
0
150 with respect to
s
v waveform as shown in Fig. 13-7.
Figure 13-7 Single-phase thyristor converter in an inverter mode with
0
150 = .
t
t
t
0
0
0

s
v
s
v
s
i
G
i
0 t =
d
V
d
I
d
I
d
v
1, 2 1, 2 3, 4
t
t
t
0
0
0

s
v
s
v
s
i
G
i
0 t =
d
V
d
I
d
I
d
v
1, 2 1, 2 3, 4
The Effect of
s
L on Current Commutation
( ) ( ) (2 )
d
d
I u u
s
L s s s s d
I
di
v d t L d t L di L I
dt

+ +
= = =

2
d s d
V L I
=
2 2
cos
d s s d
V V L I

=
Figure 13-8 Effect of
s
L on Current Commutation.
+
+
L
v d
I
d
v
+
4
3
2
1
1
i
2
i
3
i
4
i
s
v
s
L
s
i
(b) (a)
d
I
d
I
u s d
A 2 L I =
G
i
d
v
d
V
t
t
t
s
v
s
v
u
s
i
0
0
s1
i
+
+
L
v d
I
d
v
+
4
3
2
1
1
i
2
i
3
i
4
i
s
v
s
L
s
i
+
+
L
v d
I
d
v
+
4
3
2
1
1
i
2
i
3
i
4
i
s
v
s
L
s
i
(b) (a)
d
I
d
I
u s d
A 2 L I =
G
i
d
v
d
V
t
t
t
s
v
s
v
u
s
i
0
0
s1
i
1, 2 3, 4
1
+
+
L
v d
I
d
v
+
4
3
2
1
1
i
2
i
3
i
4
i
s
v
s
L
s
i
(b) (a)
d
I
d
I
u s d
A 2 L I =
G
i
d
v
d
V
t
t
t
s
v
s
v
u
s
i
0
0
s1
i
+
+
L
v d
I
d
v
+
4
3
2
1
1
i
2
i
3
i
4
i
s
v
s
L
s
i
+
+
L
v d
I
d
v
+
4
3
2
1
1
i
2
i
3
i
4
i
s
v
s
L
s
i
(b) (a)
d
I
d
I
u s d
A 2 L I =
G
i
d
v
d
V
t
t
t
s
v
s
v
u
s
i
0
0
s1
i
1, 2 3, 4
1

PSpice Modeling: C:\FirstCourse_PE_Book07\Thyrect1ph.sch
Time
0s 5ms 10ms 15ms 20ms 25ms 30ms
V(Ld:1,SCR2:A) I(Ls2)*5
-200
-100
0
100
200
300
Simulation Results
THREE-PHASE, FULL-BRIDGE THYRISTOR CONVERTERS
Figure 13-9 Three-phase Full-Bridge thyristor converter.
(a)
d
i
6
5
4 2
1 3
cn
v
+
+
+
an
v
bn
v
s
L
a
i
+
+
an
v
a
i
d
I
+
d
v
N
P
1
3
5
4
6
2
(b)
n n
(a)
d
i
6
5
4 2
1 3
cn
v
+
+
+
an
v
bn
v
s
L
a
i
+
+
an
v
a
i
d
I
+
d
v
N
P
1
3
5
4
6
2
(b)
n n
+
d
v
(a)
d
i
6
5
4 2
1 3
cn
v
+
+
+
an
v
bn
v
s
L
a
i
+
+
an
v
a
i
d
I
+
d
v
N
P
1
3
5
4
6
2
(b)
n n
(a)
d
i
6
5
4 2
1 3
cn
v
+
+
+
an
v
bn
v
s
L
a
i
+
+
an
v
a
i
d
I
+
d
v
N
P
1
3
5
4
6
2
(b)
n n
+
d
v
/ 6
/ 6
1 3

cos ( )
/ 3
do LL LL
V V t d t V
= =
0
1 3

sin ( ) (1 cos )
/ 3
LL LL
A
V V t d t V

= =
_
Figure 13-10 Waveforms with 0
s
L = .
0
0
0
0
t
t
t
t
an
v
bn
v cn
v Pn
v
Nn
v
A
a
i
b
i
c
i
1
4
3
6 6
1
5 5
2
4
0
0
0
0
t
t
t
t
an
v
bn
v cn
v Pn
v
Nn
v
A
a
i
b
i
c
i
1
4
3
6 6
1
5 5
2
4

Example 13-3 Three-phase thyristor converter of Fig. 13-9b is operating in its
inverter mode with
0
150 = . Draw waveforms similar to Fig. 13-10 for this operating
condition.
Solution These waveforms for
0
150 = in the inverter mode are shown in Fig. 13-11.
Figure 13-11 Waveforms in the inverter mode.
0
0
0
0
t
t
t
t
an
v
bn
v
cn
v
Pn
v
Nn
v
a
i
b
i
c
i
1
4
3
6
1
5
2
4
3
2
0
0
0
0
t
t
t
t
an
v
bn
v
cn
v
Pn
v
Nn
v
a
i
b
i
c
i
1
4
3
6
1
5
2
4
3
2
Effect of
s
L
0
( )
d
I u
u L s s s d
A v d t L di L I

+
= = =

3
/ 3
u
u s d
A
V L I

= =
Figure 13-12 Commutation of current from thyristor 5 to thyristor 1.
( ) a
n
P
N
d
I
s
L
s
L
s
L bn
v
+
+
6
5
cn
v
an
v
+
1
+
L
v
0 t =
t
t
0
0
an
v
cn
v
bn
v
u
A
u
1
i
5
i
Pn
v
( ) b
Pn
v
Pn
v
( ) a
n
P
N
d
I
s
L
s
L
s
L bn
v
+
+
6
5
cn
v
an
v
+
1
+
L
v
n
P
N
d
I
s
L
s
L
s
L bn
v
+
+
6
5
cn
v
an
v
+
1
+
L
v
0 t =
t
t
0
0
an
v
cn
v
bn
v
u
A
u
1
i
5
i
Pn
v
( ) b
Pn
v
Pn
v
d do u
V V V V
=
3 3
cos
d LL s d
V V L I

=
Figure 13-13 Waveforms with
s
L .
0
0
t
t
an
v
bn
v
cn
v Pn
v
Nn
v
u
A
a
i
1
4
1
4
u
0
0
t
t
an
v
bn
v
cn
v Pn
v
Nn
v
u
A
a
i
1
4
1
4
u
1 1 1 1
3 3
cos
d LL s d
V V L I

=
2 2 2 2
3 3
cos
d LL s d
V V L I

=
1 2 d d
d
d
V V
I
R
+
=
Figure 13-14 Block diagramof current-link systems.
d
i
+
1 d
v
+
2 d
v
AC1 AC2 AC1 AC2
d
R
d
L
d
i
+
1 d
v
+
2 d
v
AC1 AC2 AC1 AC2
d
R
d
L
Chapter 14 Utility Applications of Power Electronics
14-1 Introduction
14-2 Power Semiconductor Devices and Their Capabilities
14-3 Categorizing Power Electronic Systems
14-4 Distributed Generation (DG) Applications
14-5 Power Electronic Loads
14-6 Power Quality Solutions
14-7 Transmission and Distribution (T&D) Applications
References
Problems
310
INTRODUCTION
Distributed Generation (DG)
- Renewable Resources (Wind, Photovoltaic, etc.)
- Fuel Cells and Micro-Turbines
- Storage - Batteries, Super-conducting Magnetic Storage, Flywheels
Power Electronic Loads - Adjustable Speed Drives
Power Quality Solutions
- Dual Feeders
- Uninterruptible Power Supplies
- Dynamic Voltage Restorers
Transmission and Distribution (T&D)
- High Voltage DC (HVDC) and HVDC-Light
- Flexible AC Transmission (FACTS)
Shunt Compensation
Series Compensation
Static Phase Angle Control and Unified Power Flow Controllers
POWER SEMICONDUCTOR DEVICES
AND THEIR CAPABILITIES
Figure 14-1 Power semiconductor devices.
(a)
10
1
10
2
10
3
10
4
10
2
10
4
10
6
10
8
T
h
y
r
i
s
t
o
r
IGBT
MOSFET
P
o
w
e
r

(
V
A
)
IGCT
(b)
(a)
(a)
10
1
10
2
10
3
10
4
10
2
10
4
10
6
10
8
T
h
y
r
i
s
t
o
r
IGBT
MOSFET
P
o
w
e
r

(
V
A
)
IGCT
(b)
10
1
10
2
10
3
10
4
10
2
10
4
10
6
10
8
T
h
y
r
i
s
t
o
r
IGBT
MOSFET
P
o
w
e
r

(
V
A
)
IGCT
10
1
10
2
10
3
10
4
10
2
10
4
10
6
10
8
T
h
y
r
i
s
t
o
r
IGBT
MOSFET
P
o
w
e
r

(
V
A
)
IGCT
(b)
CATEGORIZING POWER ELECTRONIC SYSTEMS
Solid-State Switches
( ) a

Deviceblockingvoltage[V]
D
e
v
i
c
e

c
u
r
r
e
n
t

[
A
]
10
4
10
3
10
2
10
1
10
4
10
3
10
2
10
1
10
0
HVDC
Traction
Motor
Drive
Power
Supply
Auto-
motive
Lighting
FACTS
D
e
v
i
c
e

c
u
r
r
e
n
t

[
A
]
10
4
10
3
10
2
10
1
10
4
10
3
10
2
10
1
10
0
D
e
v
i
c
e

c
u
r
r
e
n
t

[
A
]
10
4
10
3
10
2
10
1
10
4
10
3
10
2
10
1
10
0
HVDC
Traction
Motor
Drive
Power
Supply
Auto-
motive
Lighting
FACTS
( ) b ( ) a

D
e
v
i
c
e

c
u
r
r
e
n
t

[
A
]
10
4
10
3
10
2
10
1
10
4
10
3
10
2
10
1
10
0
HVDC
Traction
Motor
Drive
Power
Supply
Auto-
motive
Lighting
FACTS
D
e
v
i
c
e

c
u
r
r
e
n
t

[
A
]
10
4
10
3
10
2
10
1
10
4
10
3
10
2
10
1
10
0
D
e
v
i
c
e

c
u
r
r
e
n
t

[
A
]
10
4
10
3
10
2
10
1
10
4
10
3
10
2
10
1
10
0
HVDC
Traction
Motor
Drive
Power
Supply
Auto-
motive
Lighting
FACTS
( ) b
Solid-State Switches
Figure 14-3 Back-to-back thyristors to act as a solid-state switch.
Converters as an Interface
Figure 14-4 Power electronics interface.
Converter
Controller
Source Load
Converter
Controller
Source Load
Voltage-Link Systems
Fig. 14-5 Block diagram of the voltage-link systems.
AC1 AC2
+
AC1 AC2 AC1 AC2 AC1 AC2
+
Figure 14-6 Block diagramof the current-link systems.
AC1 AC2 AC1 AC2 AC1 AC2 AC1 AC2
DISTRIBUTED GENERATION (DG) APPLICATIONS
Figure 14-7 Distributed utility structure of tomorrow [source: ABB].
Wind-Electric Systems
Figure 14-8 Doubly-fed induction generators for wind-electric systems.
AC
DC
DC
AC
Wound rotor
Induction Generator
Generator-side
Converter
Grid-side
Converter
Wind
Turbine
AC
DC
DC
AC
Wound rotor
Induction Generator
Generator-side
Converter
Grid-side
Converter
Wind
Turbine
AC
DC
DC
AC
Wound rotor
Induction Generator
Generator-side
Converter
Grid-side
Converter
Wind
Turbine
AC
DC
DC
AC
Wound rotor
Induction Generator
Generator-side
Converter
Grid-side
Converter
Wind
Turbine
Figure 14-9 Wind-resource map of the United States [source: www.nrel.gov].
Photovoltaic (PV) Systems
Figure 14-10 Photovoltaic systems.
Isolated
DC-DC
Converter
PWM
Converter
Max. Power-
point Tracker
Utility
1
Isolated
DC-DC
Converter
PWM
Converter
Max. Power-
point Tracker
Utility
1
Figure 14-11 Arooftop PVsystem[source: www.NREL.gov].
Fuel Cell Systems
Figure 14-12 Fuel cell v-i relationship and cell power [source: www.NETL.DOE.gov].
1.4 -
1.2 -
1 -
0.8 -
0.6 -
0.4 -
0.2 -
0 - - 0
- 200
- 400
- 600
- 800
- 1000
- 1200
|
0
|
500
|
1000
|
1500
|
2000
Maximum Theoretical Voltage
Current Density ( i in mA/cm
2
)
Activation
Losses
Ohmic Losses
Mass
Transport
Losses
Open
Circuit
Voltage
C
e
l
l

P
o
w
e
r

(

P
C
in
m
W
)
C
e
l
l

V
o
l
t
a
g
e

(

V
C
in
V
o
l
t
s

)
- g
E =
2 F
Cell Power
P
C
= V
C
x i
1.4 -
1.2 -
1 -
0.8 -
0.6 -
0.4 -
0.2 -
0 -
1.4 -
1.2 -
1 -
0.8 -
0.6 -
0.4 -
0.2 -
0 - - 0
- 200
- 400
- 600
- 800
- 1000
- 1200
- 0
- 200
- 400
- 600
- 800
- 1000
- 1200
|
0
|
500
|
1000
|
1500
|
2000
|
0
|
500
|
1000
|
1500
|
2000
Maximum Theoretical Voltage
Current Density ( i in mA/cm
2
)
Activation
Losses
Ohmic Losses
Mass
Transport
Losses
Open
Circuit
Voltage
C
e
l
l

P
o
w
e
r

(

P
C
in
m
W
)
C
e
l
l

V
o
l
t
a
g
e

(

V
C
in
V
o
l
t
s

)
- g
E =
2 F
- g
E =
2 F
Cell Power
P
C
= V
C
x i
Micro-Turbines
Energy Storage Systems
Figure 14-13 Flywheel storage system.
Machine-side
Converter
Grid-side
Converter
AC
DC
DC
AC
Flywheel
Machine-side
Converter
Grid-side
Converter
AC
DC
DC
AC
AC
DC
DC
AC
Flywheel
POWER ELECTRONIC LOADS
Figure 14-14 Adjustable-speed drive.
Controller
Motor
Utility
Rectifier
Switch-mode
Converter
Controller
Motor
Utility
Rectifier
Switch-mode
Converter
POWER QUALITY SOLUTIONS
Dual Feeders
Uninterruptible Power Supplies
Dynamic Voltage Restorers
Figure 14-15 Dual-feeders.
Load
Feeder 1
Feeder 2
Load
Feeder 1
Feeder 2
Figure 14-16 Uninterruptible power supplies.
Critical
Load
Energy
Storage
Critical
Load
Energy
Storage
Critical
Load
Energy
Storage
Figure 14-17 Dynamic voltage restorers.
Power Electronic
Interface
Load s
v
+
+ inj
v
Power Electronic
Interface
Load
Power Electronic
Interface
Load s
v
+
+ inj
v
TRANSMISSION AND DISTRIBUTION (T&D) APPLICATIONS
High Voltage DC (HVDC) Transmission
AC1 AC2 AC1 AC2
HVDC Transmission System using Voltage-Link IGBT-based Converters
Figure 14-20 Block diagram HVDC transmission using a voltage-link-system.
AC1 AC2
+
AC1 AC2 AC1 AC2 AC1 AC2
+
Flexible AC Transmission Systems (FACTS)
1 2
sin
E E
P
X
=
Figure 14-22 Power flowon a transmission line.
AC1 AC2
jX
1
0 E
2
E
AC1 AC2
jX
1
0 E
2
E
Shunt-Connected Devices to Control the Bus Voltage Magnitude
Figure 14-23 Shunt-connected devices for voltage control.
Utility
STATCOM
jX
( ) a ( ) b ( ) c
Utility
STATCOM
jX
Utility
STATCOM
jX
( ) a ( ) b ( ) c
Series-Connected Devices to Control the Effective Series Reactance
( ) a
( ) b
( ) a
( ) b
Unified Power Flow Controller (UPFC)
1. controlling the voltage magnitude E
2. changing the line reactance X, and/or
3. changing the power angle .
1 3 2
E E E + =
*
1 3
3Re( ) P E I =
*
1 3
3Im( ) Q E I =
2 1
P P =
2 1
Q Q
Figure 14-25 UPFC.
+ -
3
E
1
E
2
E
Shunt
converter
Series
converter
I
1
E
2
E
3
E
( ) a
( ) b
1 2
1 1
, P Q 2 2
, P Q
sub-station
+ -
3
E
1
E
2
E
Shunt
converter
Series
converter
I
1
E
2
E
3
E
( ) a
( ) b
1 2
1 1
, P Q 2 2
, P Q
sub-station
Figure 14-26 UPFC combines many functions [source: Siemens].

Power Electronics: First Course On

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Power Electronics: First Course On

Uploaded by

Copyright:

Available Formats

Copyright Ned Mohan 2007 1

Figure 1-14 Power output capability as a function of efficiency.

Copyright Ned Mohan 2007 18

(a) (c) (b)

Copyright Ned Mohan 2007 63

Figure 3-15 SEPIC converter.

Figure 3-16 Cuk converter.

Copyright Ned Mohan 2007 96

Copyright Ned Mohan 2007 99

Small signal representation:

Figure 4-3 Small signal control system representation.

Copyright Ned Mohan 2007 109

Copyright Ned Mohan 2007 112

Small signal equivalent circuit for Buck, Boost

Figure 4-9 PSpice Circuit model for a Buck converter.

Figure 4-9 PSpice Circuit model for a Buck converter.

Figure 4-3 Small signal control system representation.

Figure 4-3 Small signal control system representation.

Copyright Ned Mohan 2007 129

Figure 5-2 Voltage and current phasors in simple R-L circuit.

Copyright Ned Mohan 2007 152

Copyright Ned Mohan 2007 174

Copyright Ned Mohan 2007 176

DESIGNING INNER AVERAGE-CURRENT-CONTROL LOOP

Copyright Ned Mohan 2007 178

Copyright Ned Mohan 2007 191

Copyright Ned Mohan 2007 193

Copyright Ned Mohan 2007 199

Copyright Ned Mohan 2007 200

Figure 8-10 Full-Bridge converter waveforms.

Copyright Ned Mohan 2007 221

Copyright Ned Mohan 2007 257

Copyright Ned Mohan 2007 273

Copyright Ned Mohan 2007 301

Copyright Ned Mohan 2007 305

You might also like