Hardware Description COPYRIGHT INTEL CORPORATION 1996 Order Number 270252-006 8051 8052 and 80C51 Hardware Description CONTENTS PAGE INTRODUCTION 1 Special Function Registers 1 PORT STRUCTURES AND OPERATION 4 IO Configurations 5 Writing to a Port 5 Port Loading and Interfacing 6 Read-Modify-Write Feature 7 ACCESSING EXTERNAL MEMORY 7 TIMERCOUNTERS 7 Timer 0 and Timer 1 8 Timer 2 10 SERIAL INTERFACE 11 Multiprocessor Communications 12 Serial Port Control Register 12 Baud Rates 13 More About Mode 0 15 More About Mode 1 15 More About Modes 2 and 3 18 CONTENTS PAGE INTERRUPTS 21 Priority Level Structure 22 How Interrupts Are Handled 22 External Interrupts 23 Response Time 23 SINGLE-STEP OPERATION 24 RESET 24 POWER-ON RESET 25 POWER-SAVING MODES OF OPERATION 25 CHMOS Power Reduction Modes 25 EPROM VERSIONS 27 Exposure to Light 27 Program Memory Locks 27 ONCE Mode 28 THE ON-CHIP OSCILLATORS 28 HMOS Versions 28 CHMOS Versions 30 INTERNAL TIMING 31 8051 8052 AND 80C51 HARDWARE DESCRIPTION INTRODUCTION This chaptei piesents a compiehensive desciiption of the on-chip haidwaie featuies of the MCS-51 micio- contioIIeis. IncIuded in this desciiption aie The poit diiveis and how they function both as poits and, foi Poits 0 and 2, in bus opeiations The Timei/Counteis The SeiiaI Inteiface The Inteiiupt System Reset The Reduced Powei Modes in the CHMOS devices The FPROM veisions of the 8051AH, 8052AH and 80C51BH The devices undei consideiation aie Iisted in TabIe 1. As it becomes unwieIdy to be constantIy iefeiiing to each of these devices by theii individuaI names, we wiII adopt a convention of iefeiiing to them geneiicaIIy as 8051s and 8052s, unIess a specific membei of the gioup is being iefeiied to, in which case it wiII be specificaIIy named. The 8051s incIude the 8051AH, 80C51BH, and theii ROMIess and FPROM veisions. The 8052s aie the 8052AH, 8032AH and 8752BH. Figuie 1 shows a functionaI bIock diagiam of the 8051s and 8052s. Table 1 The MCS-51 Family of Microcontrollers Device ROMless EPROM ROM RAM 16-bit Ckt Name Version Version Bytes Bytes Timers Type 8051AH 8031AH 8751H 8751BH 4K 128 2 HMOS 8052AH 8032AH 8752BH 8K 256 3 HMOS 80C51BH 80C31BH 87C51 4K 128 2 CHMOS Special Function Registers A map of the on-chip memoiy aiea caIIed SFR (SpeciaI Function Registei) space is shown in Figuie 2. SFRs maiked by paientheses aie iesident in the 8052s but not in the 8051s. 1 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 2702521 Figure 1 MCS-51 Architectural Block Diagram 2 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 8 Bytes F8 FF F0 B F7 E8 EF E0 ACC E7 D8 DF D0 PSW D7 C8 (T2CON) (RCAP2L) (RCAP2H) (TL2) (TH2) CF C0 C7 B8 IP BF B0 P3 B7 A8 IE AF A0 P2 A7 98 SCON SBUF 9F 90 P1 97 88 TCON TMOD TL0 TL1 TH0 TH1 8F 80 P0 SP DPL DPH PCON 87 Figure 2 SFR Map ( ) Indicates Resident in 8052s not in 8051s Note that not aII of the addiesses aie occupied. Unoc- cupied addiesses aie not impIemented on the chip. Read accesses to these addiesses wiII in geneiaI ietuin iandom data, and wiite accesses wiII have no effect. Usei softwaie shouId not wiite 1s to these unimpIe- mented Iocations, since they may be used in futuie MCS-51 pioducts to invoke new featuies. In that case the ieset oi inactive vaIues of the new bits wiII aIways be 0, and theii active vaIues wiII be 1. The functions of the SFRs aie outIined beIow. ACCUMULATOR ACC is the AccumuIatoi iegistei. The mnemonics foi AccumuIatoi-Specific instiuctions, howevei, iefei to the AccumuIatoi simpIy as A. B REGISTER The B iegistei is used duiing muItipIy and divide opei- ations. Foi othei instiuctions it can be tieated as anoth- ei sciatch pad iegistei. PROGRAM STATUS WORD The PSW iegistei contains piogiam status infoimation as detaiIed in Figuie 3. STACK POINTER The Stack Pointei Registei is 8 bits wide. It is incie- mented befoie data is stoied duiing PUSH and CALL executions. WhiIe the stack may ieside anywheie in on- chip RAM, the Stack Pointei is initiaIized to 07H aftei a ieset. This causes the stack to begin at Iocation 08H. DATA POINTER The Data Pointei (DPTR) consists of a high byte (DPH) and a Iow byte (DPL). Its intended function is to hoId a 16-bit addiess. It may be manipuIated as a 16-bit iegistei oi as two independent 8-bit iegisteis. PORTS 0 TO 3 P0, P1, P2 and P3 aie the SFR Iatches of Poits 0, 1, 2 and 3, iespectiveIy. SERIAL DATA BUFFER The SeiiaI Data Buffei is actuaIIy two sepaiate iegis- teis, a tiansmit buffei and a ieceive buffei iegistei. When data is moved to SBUF, it goes to the tiansmit buffei wheie it is heId foi seiiaI tiansmission. (Moving a byte to SBUF is what initiates the tiansmission.) When data is moved fiom SBUF, it comes fiom the ieceive buffei. TIMER REGISTERS Registei paiis (TH0, TL0), (TH1, TL1), and (TH2, TL2) aie the 16-bit Counting iegisteis foi Timei/Coun- teis 0, 1, and 2, iespectiveIy. CAPTURE REGISTERS The iegistei paii (RCAP2H, RCAP2L) aie the Cap- tuie iegisteis foi the Timei 2 Captuie Mode. In this mode, in iesponse to a tiansition at the 8052s T2FX pin, TH2 and TL2 aie copied into RCAP2H and RCAP2L. Timei 2 aIso has a 16-bit auto-ieIoad mode, and RCAP2H and RCAP2L hoId the ieIoad vaIue foi this mode. Moie about Timei 2s featuies in a Iatei section. CONTROL REGISTERS SpeciaI Function Registeis IP, IF, TMOD, TCON, T2CON, SCON, and PCON contain contioI and status bits foi the inteiiupt system, the Timei/Counteis, and the seiiaI poit. They aie desciibed in Iatei sections. 3 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 (MSB) (LSB) CY AC F0 RS1 RS0 OV P Symbol Position Name and Significance CY PSW7 Carry flag AC PSW6 Auxiliary Carry flag (For BCD operations) F0 PSW5 Flag 0 (Available to the user for general purposes) RS1 PSW4 Register bank select control bits 1 RS0 PSW3 0 Setcleared by software to determine working register bank (see Note) Symbol Position Name and Significance OV PSW2 Overflow flag PSW1 User definable flag P PSW0 Parity flag Setcleared by hardware each instruction cycle to indicate an odd even number of one bits in the Accumulator ie even parity NOTE The contents of (RS1 RS0) enable the working register banks as follows (00)Bank 0 (00H07H) (01)Bank 1 (08H0FH) (10)Bank 2 (10H17H) (11)Bank 3 (18H1FH) Figure 3 PSW Program Status Word Register 2702522 A Port 0 Bit 2702524 C Port 2 Bit 2702523 B Port 1 Bit 2702525 D Port 3 Bit Figure 4 8051 Port Bit Latches and IO Buffers See Figuie 5 foi detaiIs of the inteinaI puIIup. PORT STRUCTURES AND OPERATION AII foui poits in the 8051 aie bidiiectionaI. Fach con- sists of a Iatch (SpeciaI Function Registeis P0 thiough P3), an output diivei, and an input buffei. The output diiveis of Poits 0 and 2, and the input buff- eis of Poit 0, aie used in accesses to exteinaI memoiy. In this appIication, Poit 0 outputs the Iow byte of the exteinaI memoiy addiess, time-muItipIexed with the byte being wiitten oi iead. Poit 2 outputs the high byte of the exteinaI memoiy addiess when the addiess is 16 bits wide. Otheiwise the Poit 2 pins continue to emit the P2 SFR content. AII the Poit 3 pins, and (in the 8052) two Poit 1 pins aie muItifunctionaI. They aie not onIy poit pins, but aIso seive the functions of vaiious speciaI featuies as Iisted on the foIIowing page. 4 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 Port Pin Alternate Function P10 T2 (TimerCounter 2 external input) P11 T2EX (TimerCounter 2 CaptureReload trigger) P30 RXD (serial input port) P31 TXD (serial output port) P32 INT0 (external interrupt) P33 INT1 (external interrupt) P34 T0 (TimerCounter 0 external input) P35 T1 (TimerCounter 1 external input) P36 WR (external Data Memory write strobe) P37 RD (external Data Memory read strobe) P1.0 and P1.1 seive these aIteinate functions onIy on the 8052. The aIteinate functions can onIy be activated if the coi- iesponding bit Iatch in the poit SFR contains a 1. Oth- eiwise the poit pin is stuck at 0. IO Configurations Figuie 4 shows a functionaI diagiam of a typicaI bit Iatch and I/O buffei in each of the foui poits. The bit Iatch (one bit in the poits SFR) is iepiesented as a Type D fIip-fIop, which wiII cIock in a vaIue fiom the inteinaI bus in iesponse to a wiite to Iatch signaI fiom the CPU. The Q output of the fIip-fIop is pIaced on the inteinaI bus in iesponse to a iead Iatch signaI fiom the CPU. The IeveI of the poit pin itseIf is pIaced on the inteinaI bus in iesponse to a iead pin signaI fiom the CPU. Some instiuctions that iead a poit acti- vate the iead Iatch signaI, and otheis activate the iead pin signaI. Moie about that Iatei. As shown in Figuie 4, the output diiveis of Poits 0 and 2 aie switchabIe to an inteinaI ADDR and ADDR/ DATA bus by an inteinaI CONTROL signaI foi use in exteinaI memoiy accesses. Duiing exteinaI memoiy ac- cesses, the P2 SFR iemains unchanged, but the P0 SFR gets 1s wiitten to it. AIso shown in Figuie 4, is that if a P3 bit Iatch contains a 1, then the output IeveI is contioIIed by the signaI IabeIed aIteinate output function. The actuaI P3.X pin IeveI is aIways avaiIabIe to the pins aIteinate input function, if any. Poits 1, 2, and 3 have inteinaI puIIups. Poit 0 has open diain outputs. Fach I/O Iine can be independentIy used as an input oi an output. (Poits 0 and 2 may not be used as geneiaI puipose I/O when being used as the ADDR/DATA BUS). To be used as an input, the poit bit Iatch must contain a 1, which tuins off the output diivei FFT. Then, foi Poits 1, 2, and 3, the pin is puIIed high by the inteinaI puIIup, but can be puIIed Iow by an exteinaI souice. Poit 0 diffeis in not having inteinaI puIIups. The puIIup FFT in the P0 output diivei (see Figuie 4) is used onIy when the Poit is emitting 1s duiing exteinaI memoiy accesses. Otheiwise the puIIup FFT is off. Consequent- Iy P0 Iines that aie being used as output poit Iines aie open diain. Wiiting a 1 to the bit Iatch Ieaves both output FFTs off, so the pin fIoats. In that condition it can be used a high-impedance input. Because Poits 1, 2, and 3 have fixed inteinaI puIIups they aie sometimes caIIed quasi-bidiiectionaI poits. When configuied as inputs they puII high and wiII souice cuiient (IIL, in the data sheets) when exteinaIIy puIIed Iow. Poit 0, on the othei hand, is consideied tiue bidiiectionaI, because when configuied as an in- put it fIoats. AII the poit Iatches in the 8051 have 1s wiitten to them by the ieset function. If a 0 is subsequentIy wiitten to a poit Iatch, it can be ieconfiguied as an input by wiiting a 1 to it. Writing to a Port In the execution of an instiuction that changes the vaI- ue in a poit Iatch, the new vaIue aiiives at the Iatch duiing S6P2 of the finaI cycIe of the instiuction. How- evei, poit Iatches aie in fact sampIed by theii output buffeis onIy duiing Phase 1 of any cIock peiiod. (Dui- ing Phase 2 the output buffei hoIds the vaIue it saw duiing the pievious Phase 1). ConsequentIy, the new vaIue in the poit Iatch wont actuaIIy appeai at the output pin untiI the next Phase 1, which wiII be at S1P1 of the next machine cycIe. See Figuie 39 in the InteinaI Timing section. If the change iequiies a 0-to-1 tiansition in Poit 1, 2, oi 3, an additionaI puIIup is tuined on duiing S1P1 and S1P2 of the cycIe in which the tiansition occuis. This is done to inciease the tiansition speed. The extia puIIup can souice about 100 times the cuiient that the noimaI puIIup can. It shouId be noted that the inteinaI puIIups aie fieId-effect tiansistois, not Iineai iesistois. The puII- up aiiangements aie shown in Figuie 5. In HMOS veisions of the 8051, the fixed pait of the puIIup is a depIetion-mode tiansistoi with the gate wiied to the souice. This tiansistoi wiII aIIow the pin to souice about 0.25 mA when shoited to giound. In paiaIIeI with the fixed puIIup is an enhancement-mode tiansistoi, which is activated duiing S1 whenevei the poit bit does a 0-to-1 tiansition. Duiing this inteivaI, if the poit pin is shoited to giound, this extia tiansistoi wiII aIIow the pin to souice an additionaI 30 mA. 5 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 2702526 A HMOS Configuration The enhancement mode transistor is turned on for 2 osc periods after Q makes a 0-to-1 transition 2702527 B CHMOS Configuration pFET 1 is turned on for 2 osc periods after Q makes a 0-to-1 transition During this time pFET 1 also turns on pFET 3 through the inverter to form a latch which holds the 1 pFET 2 is also on Figure 5 Ports 1 And 3 HMOS And CHMOS Internal Pullup Configurations Port 2 is Similar Except That It Holds The Strong Pullup On While Emitting 1s That Are Address Bits (See Text Accessing External Memory) In the CHMOS veisions, the puIIup consists of thiee pFFTs. It shouId be noted that an n-channeI FFT (nFFT) is tuined on when a IogicaI 1 is appIied to its gate, and is tuined off when a IogicaI 0 is appIied to its gate. A p-channeI FFT (pFFT) is the opposite: it is on when its gate sees a 0, and off when its gate sees a 1. pFFT1 in Figuie 5 is the tiansistoi that is tuined on foi 2 osciIIatoi peiiods aftei a 0-to-1 tiansition in the poit Iatch. WhiIe its on, it tuins on pFFT3 (a weak puII- up), thiough the inveitei. This inveitei and pFFT foim a Iatch which hoId the 1. Note that if the pin is emitting a 1, a negative gIitch on the pin fiom some exteinaI souice can tuin off pFFT3, causing the pin to go into a fIoat state. pFFT2 is a veiy weak puIIup which is on whenevei the nFFT is off, in tiaditionaI CMOS styIe. Its onIy about the stiength of pFFT3. Its function is to iestoie a 1 to the pin in the event the pin had a 1 and Iost it to a gIitch. Port Loading and Interfacing The output buffeis of Poits 1, 2, and 3 can each diive 4 LS TTL inputs. These poits on HMOS veisions can be diiven in a noimaI mannei by any TTL oi NMOS cii- cuit. Both HMOS and CHMOS pins can be diiven by open-coIIectoi and open-diain outputs, but note that 0- to-1 tiansitions wiII not be fast. In the HMOS device, if the pin is diiven by an open-coIIectoi output, a 0-to-1 tiansition wiII have to be diiven by the ieIativeIy weak depIetion mode FFT in Figuie 5(A). In the CHMOS device, an input 0 tuins off puIIup pFFT3, Ieaving onIy the veiy weak puIIup pFFT2 to diive the tiansition. In exteinaI bus mode, Poit 0 output buffeis can each diive 8 LS TTL inputs. As poit pins, they iequiie extei- naI puIIups to diive any inputs. 6 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 Read-Modify-Write Feature Some instiuctions that iead a poit iead the Iatch and otheis iead the pin. Which ones do which! The instiuc- tions that iead the Iatch iathei than the pin aie the ones that iead a vaIue, possibIy change it, and then iewiite it to the Iatch. These aie caIIed iead-modify-wiite in- stiuctions. The instiuctions Iisted beIow aie iead-mod- ify-wiite instiuctions. When the destination opeiand is a poit, oi a poit bit, these instiuctions iead the Iatch iathei than the pin: ANL (IogicaI AND, e.g., ANL P1, A) ORL (IogicaI OR, e.g., ORL P2, A) XRL (IogicaI FX-OR, e.g., XRL P3, A) JBC (jump if bit e 1 and cIeai bit, e.g., JBC P1.1, LABFL) CPL (compIement bit, e.g., CPL P3.0) INC (inciement, e.g., INC P2) DFC (deciement, e.g., DFC P2) DJNZ (deciement and jump if not zeio, e.g., DJNZ P3, LABFL) MOV, PX.Y, C (move caiiy bit to bit Y of Poit X) CLR PX.Y (cIeai bit Y of Poit X) SFTB PX.Y (set bit Y of Poit X) It is not obvious that the Iast thiee instiuctions in this Iist aie iead-modify-wiite instiuctions, but they aie. They iead the poit byte, aII 8 bits, modify the addiessed bit, then wiite the new byte back to the Iatch. The ieason that iead-modify-wiite instiuctions aie di- iected to the Iatch iathei than the pin is to avoid a possibIe misinteipietation of the voItage IeveI at the pin. Foi exampIe, a poit bit might be used to diive the base of a tiansistoi. When a 1 is wiitten to the bit, the tiansistoi is tuined on. If the CPU then ieads the same poit bit at the pin iathei than the Iatch, it wiII iead the base voItage of the tiansistoi and inteipiet it as a 0. Reading the Iatch iathei than the pin wiII ietuin the coiiect vaIue of 1. ACCESSING EXTERNAL MEMORY Accesses to exteinaI memoiy aie of two types: accesses to exteinaI Piogiam Memoiy and accesses to exteinaI Data Memoiy. Accesses to exteinaI Piogiam Memoiy use signaI PSFN (piogiam stoie enabIe) as the iead stiobe. Accesses to exteinaI Data Memoiy use RD oi WR (aIteinate functions of P3.7 and P3.6) to stiobe the memoiy. Refei to Figuies 36 thiough 38 in the InteinaI Timing section. Fetches fiom exteinaI Piogiam Memoiy aIways use a 16-bit addiess. Accesses to exteinaI Data Memoiy can use eithei a 16-bit addiess (MOVX
DPTR) oi an 8-bit addiess (MOVX
Ri). Whenevei a 16-bit addiess is used, the high byte of the addiess comes out on Poit 2, wheie it is heId foi the duiation of the iead oi wiite cycIe. Note that the Poit 2 diiveis use the stiong puIIups duiing the entiie time that they aie emitting addiess bits that aie 1s. This is duiing the execution of a MOVX
DPTR instiuction. Duiing this time the Poit 2 Iatch (the SpeciaI Function Registei) does not have to contain 1s, and the contents of the Poit 2 SFR aie not modified. If the exteinaI memoiy cycIe is not immediateIy foIIowed by anothei exteinaI memoiy cycIe, the undistuibed contents of the Poit 2 SFR wiII ieappeai in the next cycIe. If an 8-bit addiess is being used (MOVX
Ri), the contents of the Poit 2 SFR iemain at the Poit 2 pins thioughout the exteinaI memoiy cycIe. This wiII faciIi- tate paging. In any case, the Iow byte of the addiess is time-muIti- pIexed with the data byte on Poit 0. The ADDR/ DATA signaI diives both FFTs in the Poit 0 output buffeis. Thus, in this appIication the Poit 0 pins aie not open-diain outputs, and do not iequiie exteinaI puII- ups. SignaI ALF (Addiess Latch FnabIe) shouId be used to captuie the addiess byte into an exteinaI Iatch. The addiess byte is vaIid at the negative tiansition of ALF. Then, in a wiite cycIe, the data byte to be wiitten appeais on Poit 0 just befoie WR is activated, and ie- mains theie untiI aftei WR is deactivated. In a iead cycIe, the incoming byte is accepted at Poit 0 just be- foie the iead stiobe is deactivated. Duiing any access to exteinaI memoiy, the CPU wiites 0FFH to the Poit 0 Iatch (the SpeciaI Function Regis- tei), thus obIiteiating whatevei infoimation the Poit 0 SFR may have been hoIding. If the usei wiites to Poit 0 duiing an exteinaI memoiy fetch, the incoming code byte is coiiupted. Theiefoie, do not wiite to Poit 0 if exteinaI piogiam memoiy is used. FxteinaI Piogiam Memoiy is accessed undei two con- ditions: 1) Whenevei signaI FA is active, oi 2) Whenevei the piogiam countei (PC) contains a numbei that is Iaigei than 0FFFH (1FFFH foi the 8052). This iequiies that the ROMIess veisions have FA wiied Iow to enabIe the Iowei 4K (8K foi the 8032) piogiam bytes to be fetched fiom exteinaI memoiy. When the CPU is executing out of exteinaI Piogiam Memoiy, aII 8 bits of Poit 2 aie dedicated to an output function and may not be used foi geneiaI puipose I/O. Duiing exteinaI piogiam fetches they output the high byte of the PC. Duiing this time the Poit 2 diiveis use the stiong puIIups to emit PC bits that aie 1s. TIMERCOUNTERS The 8051 has two 16-bit Timei/Countei iegisteis: Tim- ei 0 and Timei 1. The 8052 has these two pIus one 7 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 moie: Timei 2. AII thiee can be configuied to opeiate eithei as timeis oi event counteis. In the Timei function, the iegistei is inciemented eveiy machine cycIe. Thus, one can think of it as count- ing machine cycIes. Since a machine cycIe consists of 12 osciIIatoi peiiods, the count iate is of the osciIIatoi fiequency. In the Countei function, the iegistei is inciemented in iesponse to a 1-to-0 tiansition at its coiiesponding exteinaI input pin, T0, T1 oi (in the 8052) T2. In this function, the exteinaI input is sampIed duiing S5P2 of eveiy machine cycIe. When the sampIes show a high in one cycIe and a Iow in the next cycIe, the count is incie- mented. The new count vaIue appeais in the iegistei duiing S3P1 of the cycIe foIIowing the one in which the tiansition was detected. Since it takes 2 machine cycIes (24 osciIIatoi peiiods) to iecognize a 1-to-0 tiansition, the maximum count iate is of the osciIIatoi fie- quency. Theie aie no iestiictions on the duty cycIe of the exteinaI input signaI, but to ensuie that a given IeveI is sampIed at Ieast once befoie it changes, it shouId be heId foi at Ieast one fuII machine cycIe. In addition to the Timei oi Countei seIection, Timei 0 and Timei 1 have foui opeiating modes fiom which to seIect. Timei 2, in the 8052, has thiee modes of opeiation: Captuie, Auto-ReIoad and baud iate geneiatoi. Timer 0 and Timer 1 These Timei/Counteis aie piesent in both the 8051 and the 8052. The Timei oi Countei function is seIect- ed by contioI bits C/T in the SpeciaI Function Registei TMOD (Figuie 6). These two Timei/Counteis have foui opeiating modes, which aie seIected by bit-paiis (M1, M0) in TMOD. Modes 0, 1, and 2 aie the same foi both Timei/Counteis. Mode 3 is diffeient. The foui opeiating modes aie desciibed in the foIIowing text. MODE 0 Fithei Timei in Mode 0 is an 8-bit Countei with a divide-by-32 piescaIei. This 13-bit timei is MCS-48 compatibIe. Figuie 7 shows the Mode 0 opeiation as it appIies to Timei 1. In this mode, the Timei iegistei is configuied as a 13-Bit iegistei. As the count ioIIs ovei fiom aII 1s to aII 0s, it sets the Timei inteiiupt fIag TF1. The counted input is enabIed to the Timei when TR1 e 1 and eithei OATF e 0 oi INT1 e 1. (Setting OATF e 1 aIIows the Timei to be contioIIed by exteinaI input INT1, to faciIitate puIse width measuiements.) TR1 is a contioI bit in the SpeciaI Function Registei TCON (Figuie 8). OATF is in TMOD. The 13-Bit iegistei consists of aII 8 bits of TH1 and the Iowei 5 bits of TL1. The uppei 3 bits of TL1 aie inde- teiminate and shouId be ignoied. Setting the iun fIag (TR1) does not cIeai the iegisteis. Mode 0 opeiation is the same foi Timei 0 as foi Timei 1. Substitute TR0, TF0 and INT0 foi the coiiespond- ing Timei 1 signaIs in Figuie 7. Theie aie two diffeient OATF bits, one foi Timei 1 (TMOD.7) and one foi Timei 0 (TMOD.3). MODE 1 Mode 1 is the same as Mode 0, except that the Timei iegistei is being iun with aII 16 bits. (MSB) (LSB) GATE CT M1 M0 GATE CT M1 M0 X YX Y Timer 1 Timer 0 GATE Gating control when set TimerCounter x is enabled only while INTx pin is high and TRx control pin is set When cleared Timer x is enabled whenever TRx control bit is set CT Timer or Counter Selector cleared for Timer operation (input from internal system clock) Set for Counter operation (input from Tx input pin) M1 M0 Operating Mode 0 0 8-bit TimerCounter THx with TLx as 5-bit prescaler 0 1 16-bit TimerCounter THx and TLx are cascaded there is no prescaler 1 0 8-bit auto-reload TimerCounter THx holds a value which is to be reloaded into TLx each time it overflows 1 1 (Timer 0) TL0 is an 8-bit TimerCounter controlled by the standard Timer 0 control bits TH0 is an 8-bit timer only controlled by Timer 1 control bits 1 1 (Timer 1) TimerCounter 1 stopped Figure 6 TMOD TimerCounter Mode Control Register 8 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 2702529 Figure 7 TimerCounter 1 Mode 0 13-Bit Counter (MSB) (LSB) TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Symbol Position Name and Significance TF1 TCON7 Timer 1 overflow Flag Set by hardware on TimerCounter overflow Cleared by hardware when processor vectors to interrupt routine TR1 TCON6 Timer 1 Run control bit Setcleared by software to turn TimerCounter on off TF0 TCON5 Timer 0 overflow Flag Set by hardware on TimerCounter overflow Cleared by hardware when processor vectors to interrupt routine TR0 TCON4 Timer 0 Run control bit Setcleared by software to turn TimerCounter on off Symbol Position Name and Significance IE1 TCON3 Interrupt 1 Edge flag Set by hardware when external interrupt edge detected Cleared when interrupt processed IT1 TCON2 Interrupt 1 Type control bit Set cleared by software to specify falling edgelow level triggered external interrupts IE0 TCON1 Interrupt 0 Edge flag Set by hardware when external interrupt edge detected Cleared when interrupt processed IT0 TCON0 Interrupt 0 Type control bit Set cleared by software to specify falling edgelow level triggered external interrupts Figure 8TCON TimerCounter Control Register MODE 2 Mode 2 configuies the Timei iegistei as an 8-bit Coun- tei (TL1) with automatic ieIoad, as shown in Figuie 9. OveifIow fiom TL1 not onIy sets TF1, but aIso ieIoads TL1 with the contents of TH1, which is pieset by soft- waie. The ieIoad Ieaves TH1 unchanged. Mode 2 opeiation is the same foi Timei/Countei 0. MODE 3 Timei 1 in Mode 3 simpIy hoIds its count. The effect is the same as setting TR1 e 0. Timei 0 in Mode 3 estabIishes TL0 and TH0 as two sepaiate counteis. The Iogic foi Mode 3 on Timei 0 is shown in Figuie 10. TL0 uses the Timei 0 contioI bits: C/T, OATF, TR0, INT0, and TF0. TH0 is Iocked into a timei function (counting machine cycIes) and takes ovei the use of TR1 and TF1 fiom Timei 1. Thus, TH0 now contioIs the Timei 1 inteiiupt. Mode 3 is piovided foi appIications iequiiing an extia 8-bit timei oi countei. With Timei 0 in Mode 3, an 8051 can Iook Iike it has thiee Timei/Counteis, and an 8052, Iike it has foui. When Timei 0 is in Mode 3, Timei 1 can be tuined on and off by switching it out of and into its own Mode 3, oi can stiII be used by the seiiaI poit as a baud iate geneiatoi, oi in fact, in any appIication not iequiiing an inteiiupt. 9 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 27025210 Figure 9 TimerCounter 1 Mode 2 8-Bit Auto-Reload 27025211 Figure 10 TimerCounter 0 Mode 3 Two 8-Bit Counters Timer 2 Timei 2 is a 16-bit Timei/Countei which is piesent onIy in the 8052. Like Timeis 0 and 1, it can opeiate eithei as a timei oi as an event countei. This is seIected by bit C/T2 in the SpeciaI Function Registei T2CON (Figuie 11). It has thiee opeiating modes: captuie, auto-Ioad and baud iate geneiatoi, which aie se- Iected by bits in T2CON as shown in TabIe 2. Table 2 Timer 2 Operating Modes RCLK a TCLK CPRL2 TR2 Mode 0 0 1 16-bit Auto-Reload 0 1 1 16-bit Capture 1 X 1 Baud Rate Generator X X 0 (off) 10 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 (MSB) (LSB) TF2 EXF2 RCLK TCLK EXEN2 TR2 CT2 CPRL2 Symbol Position Name and Significance TF2 T2CON7 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software TF2 will not be set when either RCLK e 1 or TCLK e 1 EXF2 T2CON6 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 e 1 When Timer 2 interrupt is enabled EXF2 e 1 will cause the CPU to vector to the Timer 2 interrupt routine EXF2 must be cleared by software RCLK T2CON5 Receive clock flag When set causes the serial port to use Timer 2 overflow pulses for its receive clock in Modes 1 and 3 RCLK e 0 causes Timer 1 overflow to be used for the receive clock TCLK T2CON4 Transmit clock flag When set causes the serial port to use Timer 2 overflow pulses for its transmit clock in modes 1 and 3 TCLK e 0 causes Timer 1 overflows to be used for the transmit clock EXEN2 T2CON3 Timer 2 external enable flag When set allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port EXEN2 e 0 causes Timer 2 to ignore events at T2EX TR2 T2CON2 Startstop control for Timer 2 A logic 1 starts the timer CT2 T2CON1 Timer or counter select (Timer 2) 0 e Internal timer (OSC12) 1 e External event counter (falling edge triggered) CPRL2 T2CON0 CaptureReload flag When set captures will occur on negative transitions at T2EX if EXEN2 e 1 When cleared auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX when EXEN2 e 1 When either RCLK e 1 or TCLK e 1 this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow Figure 11 T2CON TimerCounter 2 Control Register In the Captuie Mode theie aie two options which aie seIected by bit FXFN2 in T2CON. If FXFN2 e 0, then Timei 2 is a 16-bit timei oi countei which upon oveifIowing sets bit TF2, the Timei 2 oveifIow bit, which can be used to geneiate an inteiiupt. If FXFN2 e 1, then Timei 2 stiII does the above, but with the added featuie that a 1-to-0 tiansition at exteinaI input T2FX causes the cuiient vaIue in the Timei 2 iegisteis, TL2 and TH2, to be captuied into iegisteis RCAP2L and RCAP2H, iespectiveIy. (RCAP2L and RCAP2H aie new SpeciaI Function Registeis in the 8052.) In addition, the tiansition at T2FX causes bit FXF2 in T2CON to be set, and FXF2, Iike TF2, can geneiate an inteiiupt. The Captuie Mode is iIIustiated in Figuie 12. In the auto-ieIoad mode theie aie again two options, which aie seIected by bit FXFN2 in T2CON. If FXFN2 e 0, then when Timei 2 ioIIs ovei it not onIy sets TF2 but aIso causes the Timei 2 iegisteis to be ieIoaded with the 16-bit vaIue in iegisteis RCAP2L and RCAP2H, which aie pieset by softwaie. If FXFN2 e 1, then Timei 2 stiII does the above, but with the added featuie that a 1-to-0 tiansition at exteinaI input T2FX wiII aIso tiiggei the 16-bit ieIoad and set FXF2. The auto-ieIoad mode is iIIustiated in Figuie 13. The baud iate geneiatoi mode is seIected by RCLK e 1 and/oi TCLK e 1. It wiII be desciibed in conjunc- tion with the seiiaI poit. SERIAL INTERFACE The seiiaI poit is fuII dupIex, meaning it can tiansmit and ieceive simuItaneousIy. It is aIso ieceive-buffeied, meaning it can commence ieception of a second byte befoie a pieviousIy ieceived byte has been iead fiom the ieceive iegistei. (Howevei, if the fiist byte stiII hasnt been iead by the time ieception of the second byte is compIete, one of the bytes wiII be Iost). The seiiaI poit ieceive and tiansmit iegisteis aie both ac- cessed at SpeciaI Function Registei SBUF. Wiiting to SBUF Ioads the tiansmit iegistei, and ieading SBUF accesses a physicaIIy sepaiate ieceive iegistei. 11 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 27025212 Figure 12 Timer 2 in Capture Mode The seiiaI poit can opeiate in 4 modes: Mode 0 SeiiaI data enteis and exits thiough RXD. TXD outputs the shift cIock. 8 bits aie tiansmitted/ie- ceived: 8 data bits (LSB fiist). The baud iate is fixed at 1/12 the osciIIatoi fiequency. Mode 1 10 bits aie tiansmitted (thiough TXD) oi ie- ceived (thiough RXD): a stait bit (0), 8 data bits (LSB fiist), and a stop bit (1). On ieceive, the stop bit goes into RB8 in SpeciaI Function Registei SCON. The baud iate is vaiiabIe. Mode 2 11 bits aie tiansmitted (thiough TXD) oi ie- ceived (thiough RXD): a stait bit (0), 8 data bits (LSB fiist), a piogiammabIe 9th data bit, and a stop bit (1). On Tiansmit, the 9th data bit (TB8 in SCON) can be assigned the vaIue of 0 oi 1. Oi, foi exampIe, the paiity bit (P, in the PSW) couId be moved into TB8. On ie- ceive, the 9th data bit goes into RB8 in SpeciaI Functon Registei SCON, whiIe the stop bit is ignoied. The baud iate is piogiammabIe to eithei oi the osciIIatoi fiequency. Mode 3 11 bits aie tiansmitted (thiough TXD) oi ie- ceived (thiough RXD): a stait bit (0), 8 data bits (LSB fiist), a piogiammabIe 9th data bit and a stop bit (1). In fact, Mode 3 is the same as Mode 2 in aII iespects except the baud iate. The baud iate in Mode 3 is vaii- abIe. In aII foui modes, tiansmission is initiated by any in- stiuction that uses SBUF as a destination iegistei. Re- ception is initiated in Mode 0 by the condition RI e 0 and RFN e 1. Reception is initiated in the othei modes by the incoming stait bit if RFN e 1. Multiprocessor Communications Modes 2 and 3 have a speciaI piovision foi muItipio- cessoi communications. In these modes, 9 data bits aie ieceived. The 9th one goes into RB8. Then comes a stop bit. The poit can be piogiammed such that when the stop bit is ieceived, the seiiaI poit inteiiupt wiII be activated onIy if RB8 e 1. This featuie is enabIed by setting bit SM2 in SCON. A way to use this featuie in muItipiocessoi systems is as foIIows. When the mastei piocessoi wants to tiansmit a bIock of data to one of seveiaI sIaves, it fiist sends out an ad- diess byte which identifies the taiget sIave. An addiess byte diffeis fiom a data byte in that the 9th bit is 1 in an addiess byte and 0 in a data byte. With SM2 e 1, no sIave wiII be inteiiupted by a data byte. An addiess byte, howevei, wiII inteiiupt aII sIaves, so that each sIave can examine the ieceived byte and see if it is being addiessed. The addiessed sIave wiII cIeai its SM2 bit and piepaie to ieceive the data bytes that wiII be com- ing. The sIaves that weient being addiessed Ieave theii SM2s set and go on about theii business, ignoiing the coming data bytes. SM2 has no effect in Mode 0, and in Mode 1 can be used to check the vaIidity of the stop bit. In a Mode 1 ieception, if SM2 e 1, the ieceive inteiiupt wiII not be activated unIess a vaIid stop bit is ieceived. Serial Port Control Register The seiiaI poit contioI and status iegistei is the SpeciaI Function Registei SCON, shown in Figuie 14. This iegistei contains not onIy the mode seIection bits, but aIso the 9th data bit foi tiansmit and ieceive (TB8 and RB8), and the seiiaI poit inteiiupt bits (TI and RI). 12 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 27025213 Figure 13 Timer 2 in Auto-Reload Mode (MSB) (LSB) SM0 SM1 SM2 REN TB8 RB8 TI RI Where SM0 SM1 specify the serial port mode as follows SM0 SM1 Mode Description Baud Rate 0 0 0 shift register f osc 12 0 1 1 8-bit UART variable 1 0 2 9-bit UART f osc 64 or f osc 32 1 1 3 9-bit UART variable SM2 enables the multiprocessor communication feature in Modes 2 and 3 In Mode 2 or 3 if SM2 is set to 1 then RI will not be activated if the received 9th data bit (RB8) is 0 In Mode 1 if SM2 e 1 then RI will not be activated if a valid stop bit was not received In Mode 0 SM2 should be 0 REN enables serial reception Set by software to enable reception Clear by software to disable reception TB8 is the 9th data bit that will be transmitted in Modes 2 and 3 Set or clear by software as desired RB8 in Modes 2 and 3 is the 9th data bit that was received In Mode 1 if SM2 e 0 RB8 is the stop bit that was received In Mode 0 RB8 is not used TI is transmit interrupt flag Set by hardware at the end of the 8th bit time in Mode 0 or at the beginning of the stop bit in the other modes in any serial transmission Must be cleared by software RI is receive interrupt flag Set by hardware at the end of the 8th bit time in Mode 0 or halfway through the stop bit time in the other modes in any serial reception (except see SM2) Must be cleared by software Figure 14 SCON Serial Port Control Register Baud Rates The baud iate in Mode 0 is fixed: Mode 0 Baud Rate e OsciIIatoi Fiequency 12 The baud iate in Mode 2 depends on the vaIue of bit SMOD in SpeciaI Function Registei PCON. If SMOD e 0 (which is the vaIue on ieset), the baud iate the osciIIatoi fiequency. If SMOD e 1, the baud iate is the osciIIatoi fiequency. Mode 2 Baud Rate e 2 SMOD 64 c (OsciIIatoi Fiequency) In the 8051, the baud iates in Modes 1 and 3 aie detei- mined by the Timei 1 oveifIow iate. In the 8052, these baud iates can be deteimined by Timei 1, oi by Timei 2, oi by both (one foi tiansmit and the othei foi ie- ceive). 13 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 Using Timer 1 to Generate Baud Rates When Timei 1 is used as the baud iate geneiatoi, the baud iates in Modes 1 and 3 aie deteimined by the Timei 1 oveifIow iate and the vaIue of SMOD as foI- Iows: Modes 1, 3 Baud Rate e 2 SMOD 32 c (Timei 1 OveifIow Rate) The Timei 1 inteiiupt shouId be disabIed in this appIi- cation. The Timei itseIf can be configuied foi eithei timei oi countei opeiation, and in any of its 3 iunning modes. In the most typicaI appIications, it is configuied foi timei opeiation, in the auto-ieIoad mode (high nibbIe of TMOD e 0010B). In that case, the baud iate is given by the foimuIa Modes 1, 3 Baud Rate e 2 SMOD 32 c OsciIIatoi Fiequency 12x 256 b (TH1) One can achieve veiy Iow baud iates with Timei 1 by Ieaving the Timei 1 inteiiupt enabIed, and configuiing the Timei to iun as a 16-bit timei (high nibbIe of TMOD e 0001B), and using the Timei 1 inteiiupt to do a 16-bit softwaie ieIoad. Figuie 15 Iists vaiious commonIy used baud iates and how they can be obtained fiom Timei 1. Timer 1 Baud Rate f OSC SMOD CT Mode Reload Value Mode 0 Max 1 MHZ 12 MHZ X X X X Mode 2 Max 375K 12 MHZ 1 X X X Modes 1 3 625K 12 MHZ 1 0 2 FFH 192K 11059 MHZ 1 0 2 FDH 96K 11059 MHZ 0 0 2 FDH 48K 11059 MHZ 0 0 2 FAH 24K 11059 MHZ 0 0 2 F4H 12K 11059 MHZ 0 0 2 E8H 1375 11986 MHZ 0 0 2 1DH 110 6 MHZ 0 0 2 72H 110 12 MHZ 0 0 1 FEEBH Figure 15 Timer 1 Generated Commonly Used Baud Rates Using Timer 2 to Generate Baud Rates In the 8052, Timei 2 is seIected as the baud iate geneia- toi by setting TCLK and/oi RCLK in T2CON (Figuie 11). Note then the baud iates foi tiansmit and ieceive can be simuItaneousIy diffeient. Setting RCLK and/oi TCLK puts Timei 2 into its baud iate geneiatoi mode, as shown in Figuie 16. 27025214 Figure 16 Timer 2 in Baud Rate Generator Mode 14 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 The baud iate geneiatoi mode is simiIai to the auto-ie- Ioad mode, in that a ioIIovei in TH2 causes the Timei 2 iegisteis to be ieIoaded with the 16-bit vaIue in iegisteis RCAP2H and RCAP2L, which aie pieset by softwaie. Now, the baud iates in Modes 1 and 3 aie deteimined by Timei 2s oveifIow iate as foIIows: Modes 1, 3 Baud Rate e Timei 2 OveifIow Rate 16 The Timei can be configuied foi eithei timei oi countei opeiation. In the most typicaI appIications, it is configuied foi timei opeiation (C/T2 e 0). Tim- ei opeiation is a IittIe diffeient foi Timei 2 when its being used as a baud iate geneiatoi. NoimaIIy, as a timei it wouId inciement eveiy machine cycIe (thus at the osciIIatoi fiequency). As a baud iate geneiatoi, howevei, it inciements eveiy state time (thus at the osciIIatoi fiequency). In that case the baud iate is given by the foimuIa Modes 1, 3 Baud Rate e OsciIIatoi Fiequency 32x 65536 b (RCAP2H, RCAP2L) wheie (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit unsigned in- tegei. Timei 2 as a baud iate geneiatoi is shown in Figuie 16. This Figuie is vaIid onIy if RCLK a TCLK e 1 in T2CON. Note that a ioIIovei in TH2 does not set TF2, and wiII not geneiate an inteiiupt. Theiefoie, the Timei 2 inteiiupt does not have to be disabIed when Timei 2 is in the baud iate geneiatoi mode. Note too, that if FXFN2 is set, a 1-to-0 tiansition in T2FX wiII set FXF2 but wiII not cause a ieIoad fiom (RCAP2H, RCAP2L) to (TH2, TL2). Thus when Timei 2 is in use as a baud iate geneiatoi, T2FX can be used as an extia exteinaI inteiiupt, if desiied. It shouId be noted that when Timei 2 is iunning (TR2 e 1) in timei function in the baud iate geneiatoi mode, one shouId not tiy to iead oi wiite TH2 oi TL2. Undei these conditions the Timei is being inciemented eveiy state time, and the iesuIts of a iead oi wiite may not be accuiate. The RCAP iegisteis may be iead, but shouIdnt be wiitten to, because a wiite might oveiIap a ieIoad and cause wiite and/oi ieIoad eiiois. Tuin the Timei off (cIeai TR2) befoie accessing the Timei 2 oi RCAP iegisteis, in this case. More About Mode 0 SeiiaI data enteis and exits thiough RXD. TXD out- puts the shift cIock. 8 bits aie tiansmitted/ieceived: 8 data bits (LSB fiist). The baud iate is fixed at the osciIIatoi fiequency. Figuie 17 shows a simpIified functionaI diagiam of the seiiaI poit in Mode 0, and associated timing. Tiansmission is initiated by any instiuction that uses SBUF as a destination iegistei. The wiite to SBUF signaI at S6P2 aIso Ioads a 1 into the 9th position of the tiansmit shift iegistei and teIIs the TX ContioI bIock to commence a tiansmission. The inteinaI timing is such that one fuII machine cycIe wiII eIapse between wiite to SBUF, and activation of SFND. SFND enabIes the output of the shift iegistei to the aIteinate output function Iine of P3.0, and aIso enabIes SHIFT CLOCK to the aIteinate output function Iine of P3.1. SHIFT CLOCK is Iow duiing S3, S4, and S5 of eveiy machine cycIe, and high duiing S6, S1 and S2. At S6P2 of eveiy machine cycIe in which SFND is active, the contents of the tiansmit shift iegistei aie shifted to the iight one position. As data bits shift out to the iight, zeioes come in fiom the Ieft. When the MSB of the data byte is at the output position of the shift iegistei, then the 1 that was initiaI- Iy Ioaded into the 9th position, is just to the Ieft of the MSB, and aII positions to the Ieft of that contain zeioes. This condition fIags the TX ContioI bIock to do one Iast shift and then deactivate SFND and set TI. Both of these actions occui at S1P1 of the 10th machine cycIe aftei wiite to SBUF. Reception is initiated by the condition RFN e 1 and R1 e 0. At S6P2 of the next machine cycIe, the RX ContioI unit wiites the bits 11111110 to the ieceive shift iegistei, and in the next cIock phase activates RF- CFIVF. RFCFIVF enabIes SHIFT CLOCK to the aIteinate output function Iine of P3.1. SHIFT CLOCK makes tiansitions at S3P1 and S6P1 of eveiy machine cycIe. At S6P2 of eveiy machine cycIe in which RFCFIVF is active, the contents of the ieceive shift iegistei aie shift- ed to the Ieft one position. The vaIue that comes in fiom the iight is the vaIue that was sampIed at the P3.0 pin at S5P2 of the same machine cycIe. As data bits come in fiom the iight, 1s shift out to the Ieft. When the 0 that was initiaIIy Ioaded into the iight- most position aiiives at the Ieftmost position in the shift iegistei, it fIags the RX ContioI bIock to do one Iast shift and Ioad SBUF. At S1P1 of the 10th machine cycIe aftei the wiite to SCON that cIeaied RI, RF- CFIVF is cIeaied and RI is set. More About Mode 1 Ten bits aie tiansmitted (thiough TXD), oi ieceived (thiough RXD): a stait bit (0), 8 data bits (LSB fiist), and a stop bit (1). On ieceive, the stop bit goes into RB8 in SCON. In the 8051 the baud iate is deteimined by the Timei 1 oveifIow iate. In the 8052 it is detei- mined eithei by the Timei 1 oveifIow iate, oi the Timei 2 oveifIow iate, oi both (one foi tiansmit and the othei foi ieceive). Figuie 18 shows a simpIified functionaI diagiam of the seiiaI poit in Mode 1, and associated timings foi tians- mit ieceive. 15 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 27025215 Figure 17 Serial Port Mode 0 16 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 27025216 Figure 18 Serial Port Mode 1 TCLK RCLK and Timer 2 are Present in the 80528032 Only Tiansmission is initiated by any instiuction that uses SBUF as a destination iegistei. The wiite to SBUF signaI aIso Ioads a 1 into the 9th bit position of the tiansmit shift iegistei and fIags the TX ContioI unit that a tiansmission is iequested. Tiansmission actuaIIy commences at S1P1 of the machine cycIe foIIowing the next ioIIovei in the divide-by-16 countei. (Thus, the bit times aie synchionized to the divide-by-16 countei, not to the wiite to SBUF signaI). The tiansmission begins with activation of SFND, which puts the stait bit at TXD. One bit time Iatei, DATA is activated, which enabIes the output bit of the tiansmit shift iegistei to TXD. The fiist shift puIse oc- cuis one bit time aftei that. 17 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 As data bits shift out to the iight, zeioes aie cIocked in fiom the Ieft. When the MSB of the data byte is at the output position of the shift iegistei, then the 1 that was initiaIIy Ioaded into the 9th position is just to the Ieft of the MSB, and aII positions to the Ieft of that contain zeioes. This condition fIags the TX ContioI unit to do one Iast shift and then deactivate SFND and set TI. This occuis at the 10th divide-by-16 ioIIovei aftei wiite to SBUF. Reception is initiated by a detected 1-to-0 tiansition at RXD. Foi this puipose RXD is sampIed at a iate of 16 times whatevei baud iate has been estabIished. When a tiansition is detected, the divide-by-16 countei is imme- diateIy ieset, and 1FFH is wiitten into the input shift iegistei. Resetting the divide-by-16 countei aIigns its ioIIoveis with the boundaiies of the incoming bit times. The 16 states of the countei divide each bit time into 16ths. At the 7th, 8th, and 9th countei states of each bit time, the bit detectoi sampIes the vaIue of RXD. The vaIue accepted is the vaIue that was seen in at Ieast 2 of the 3 sampIes. This is done foi noise iejection. If the vaIue accepted duiing the fiist bit time is not 0, the ieceive ciicuits aie ieset and the unit goes back to Iook- ing foi anothei 1-to-0 tiansition. This is to piovide ie- jection of faIse stait bits. If the stait bit pioves vaIid, it is shifted into the input shift iegistei, and ieception of the iest of the fiame wiII pioceed. As data bits come in fiom the iight, 1s shift out to the Ieft. When the stait bit aiiives at the Ieftmost position in the shift iegistei, (which in mode 1 is a 9-bit iegis- tei), it fIags the RX ContioI bIock to do one Iast shift, Ioad SBUF and RB8, and set RI. The signaI to Ioad SBUF and RB8, and to set RI, wiII be geneiated if, and onIy if, the foIIowing conditions aie met at the time the finaI shift puIse is geneiated. 1) RI e 0 and 2) Either SM2 e 0 or the received stop bit e 1 If eithei of these two conditions is not met, the ieceived fiame is iiietiievabIy Iost. If both conditions aie met, the stop bit goes into RB8, the 8 data bits go into SBUF, and RI is activated. At this time, whethei the above conditions aie met oi not, the unit goes back to Iooking foi a 1-to-0 tiansition in RXD. More About Modes 2 and 3 FIeven bits aie tiansmitted (thiough TXD), oi ieceived (thiough RXD): a stait bit (0), 8 data bits (LSB fiist), a piogiammabIe 9th data bit, and a stop bit (1). On tians- mit, the 9th data bit (TB8) can be assigned the vaIue of 0 oi 1. On ieceive, the 9th data bit goes into RB8 in SCON. The baud iate is piogiammabIe to eithei oi the osciIIatoi fiequency in Mode 2. Mode 3 may have a vaiiabIe baud iate geneiated fiom eithei Timei 1 oi 2 depending on the state of TCLK and RCLK. Figuies 19 and 20 show a functionaI diagiam of the seiiaI poit in Modes 2 and 3. The ieceive poition is exactIy the same as in Mode 1. The tiansmit poition diffeis fiom Mode 1 onIy in the 9th bit of the tiansmit shift iegistei. Tiansmission is initiated by any instiuction that uses SBUF as a destination iegistei. The wiite to SBUF signaI aIso Ioads TB8 into the 9th bit position of the tiansmit shift iegistei and fIags the TX ContioI unit that a tiansmission is iequested. Tiansmission com- mences at S1P1 of the machine cycIe foIIowing the next ioIIovei in the divide-by-16 countei. (Thus, the bit times aie synchionized to the divide-by-16 countei, not to the wiite to SBUF signaI.) The tiansmission begins with activation of SFND, which puts the stait bit at TXD. One bit time Iatei, DATA is activated, which enabIes the output bit of the tiansmit shift iegistei to TXD. The fiist shift puIse oc- cuis one bit time aftei that. The fiist shift cIocks a 1 (the stop bit) into the 9th bit position of the shift iegis- tei. Theieaftei, onIy zeioes aie cIocked in. Thus, as data bits shift out to the iight, zeioes aie cIocked in fiom the Ieft. When TB8 is at the output position of the shift iegistei, then the stop bit is just to the Ieft of TB8, and aII positions to the Ieft of that contain zeioes. This condition fIags the TX ContioI unit to do one Iast shift and then deactivate SFND and set TI. This occuis at the 11th divide-by-16 ioIIovei aftei wiite to SBUF. Reception is initiated by a detected 1-to-0 tiansition at RXD. Foi this puipose RXD is sampIed at a iate of 16 times whatevei baud iate has been estabIished. When a tiansition is detected, the divide-by-16 countei is imme- diateIy ieset, and 1FFH is wiitten to the input shift iegistei. At the 7th, 8th and 9th countei states of each bit time, the bit detectoi sampIes the vaIue of RXD. The vaIue accepted is the vaIue that was seen in at Ieast 2 of the 3 sampIes. If the vaIue accepted duiing the fiist bit time is not 0, the ieceive ciicuits aie ieset and the unit goes back to Iooking foi anothei 1-to-0 tiansition. If the stait bit pioves vaIid, it is shifted into the input shift iegistei, and ieception of the iest of the fiame wiII pio- ceed. 18 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 27025217 Figure 19 Serial Port Mode 2 19 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 27025218 Figure 20 Serial Port Mode 3 TCLK RCLK and Timer 2 are Present in the 80528032 Only 20 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 As data bits come in fiom the iight, 1s shift out to the Ieft. When the stait bit aiiives at the Ieftmost position in the shift iegistei (which in Modes 2 and 3 is a 9-bit iegistei), it fIags the RX ContioI bIock to do one Iast shift, Ioad SBUF and RB8, and set RI. The signaI to Ioad SBUF and RB8, and to set RI, wiII be geneiated if, and onIy if, the foIIowing conditions aie met at the time the finaI shift puIse is geneiated: 1) RI e 0 and 2) Either SM2 e 0 or the received 9th data bit e 1 If eithei of these conditions is not met, the ieceived fiame is iiietiievabIy Iost, and RI is not set. If both conditions aie met, the ieceived 9th data bit goes into RB8, and the fiist 8 data bits go into SBUF. One bit time Iatei, whethei the above conditions weie met oi not, the unit goes back to Iooking foi a 1-to-0 tiansition at the RXD input. Note that the vaIue of the ieceived stop bit is iiieIevant to SBUF, RB8, oi RI. INTERRUPTS The 8051 piovides 5 inteiiupt souices. The 8052 pio- vides 6. These aie shown in Figuie 21. The FxteinaI Inteiiupts INT0 and INT1 can each be eithei IeveI-activated oi tiansition-activated, depending on bits IT0 and IT1 in Registei TCON. The fIags that actuaIIy geneiate these inteiiupts aie bits IF0 and IF1 in TCON. When an exteinaI inteiiupt is geneiated, the fIag that geneiated it is cIeaied by the haidwaie when the seivice ioutine is vectoied to onIy if the inteiiupt 27025219 Figure 21 MCS-51 Interrupt Sources was tiansition-activated. If the inteiiupt was IeveI-acti- vated, then the exteinaI iequesting souice is what con- tioIs the iequest fIag, iathei than the on-chip haidwaie. The Timei 0 and Timei 1 Inteiiupts aie geneiated by TF0 and TF1, which aie set by a ioIIovei in theii ie- spective Timei/Countei iegisteis (except see Timei 0 in Mode 3). When a timei inteiiupt is geneiated, the fIag that geneiated it is cIeaied by the on-chip haidwaie when the seivice ioutine is vectoied to. The SeiiaI Poit Inteiiupt is geneiated by the IogicaI OR of RI and TI. Neithei of these fIags is cIeaied by haid- waie when the seivice ioutine is vectoied to. In fact, the seivice ioutine wiII noimaIIy have to deteimine whethei it was RI oi TI that geneiated the inteiiupt, and the bit wiII have to be cIeaied in softwaie. In the 8052, the Timei 2 Inteiiupt is geneiated by the IogicaI OR of TF2 and FXF2. Neithei of these fIags is cIeaied by haidwaie when the seivice ioutine is vec- toied to. In fact, the seivice ioutine may have to detei- mine whethei it was TF2 oi FXF2 that geneiated the inteiiupt, and the bit wiII have to be cIeaied in soft- waie. AII of the bits that geneiate inteiiupts can be set oi cIeaied by softwaie, with the same iesuIt as though it had been set oi cIeaied by haidwaie. That is, inteiiupts can be geneiated oi pending inteiiupts can be canceIed in softwaie. (MSB) (LSB) EA ET2 ES ET1 EX1 ET0 EX0 Enable Bit e 1 enables the interrupt Enable Bit e 0 disables it Symbol Position Function EA IE7 disables all interrupts If EA e 0 no interrupt will be acknowledged If EA e 1 each interrupt source is individually enabled or disabled by setting or clearing its enable bit IE6 reserved ET2 IE5 Timer 2 interrupt enable bit ES IE4 Serial Port interrupt enable bit ET1 IE3 Timer 1 interrupt enable bit EX1 IE2 External interrupt 1 enable bit ET0 IE1 Timer 0 interrupt enable bit EX0 IE0 External interrupt 0 enable bit User software should never write 1s to unimplemented bits since they may be used in future MCS-51 products Figure 22 IE Interrupt Enable Register 21 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 Fach of these inteiiupt souices can be individuaIIy en- abIed oi disabIed by setting oi cIeaiing a bit in SpeciaI Function Registei IF (Figuie 22). IF contains aIso a gIobaI disabIe bit, FA, which disabIes aII inteiiupts at once. Note in Figuie 22 that bit position IF.6 is unimpIe- mented. In the 8051s, bit position IF.5 is aIso unimpIe- mented. Usei softwaie shouId not wiite 1s to these bit positions, since they may be used in futuie MCS-51 pioducts. Priority Level Structure Fach inteiiupt souice can aIso be individuaIIy pio- giammed to one of two piioiity IeveIs by setting oi cIeaiing a bit in SpeciaI Function Registei IP (Figuie 23). A Iow-piioiity inteiiupt can itseIf be inteiiupted by a high-piioiity inteiiupt, but not by anothei Iow-pii- oiity inteiiupt. A high-piioiity inteiiupt cant be intei- iupted by any othei inteiiupt souice. (MSB) (LSB) PT2 PS PT1 PX1 PT0 PX0 Priority bit e 1 assigns high priority Priority bit e 0 assigns low priority Symbol Position Function IP7 reserved IP6 reserved PT2 IP5 Timer 2 interrupt priority bit PS IP4 Serial Port interrupt priority bit PT1 IP3 Timer 1 interrupt priority bit PX1 IP2 External interrupt 1 priority bit PT0 IP1 Timer 0 interrupt priority bit PX0 IP0 External interrupt 0 priority bit User software should never write 1s to unimplemented bits since they may be used in future MCS-51 products Figure 23 IP Interrupt Priority Register If two iequests of diffeient piioiity IeveIs aie ieceived simuItaneousIy, the iequest of highei piioiity IeveI is seiviced. If iequests of the same piioiity IeveI aie ie- ceived simuItaneousIy, an inteinaI poIIing sequence de- teimines which iequest is seiviced. Thus within each piioiity IeveI theie is a second piioiity stiuctuie detei- mined by the poIIing sequence, as foIIows: Source Priority Within Level 1 IE0 (highest) 2 TF0 3 IE1 4 TF1 5 RI a TI 6 TF2 a EXF2 (lowest) Note that the piioiity within IeveI stiuctuie is onIy used to iesoIve simultaneous requests of the same priori- ty level The IP iegistei contains a numbei of unimpIemented bits. IP.7 and IP.6 aie vacant in the 8052s, and in the 8051s these and IP.5 aie vacant. Usei softwaie shouId not wiite 1s to these bit positions, since they may be used in futuie MCS-51 pioducts. How Interrupts Are Handled The inteiiupt fIags aie sampIed at S5P2 of eveiy ma- chine cycIe. The sampIes aie poIIed duiing the foIIow- ing machine cycIe. The 8052s Timei 2 inteiiupt cycIe is diffeient, as desciibed in the Response Time Section. If one of the fIags was in a set condition at S5P2 of the pieceding cycIe, the poIIing cycIe wiII find it and the inteiiupt system wiII geneiate an LCALL to the appio- piiate seivice ioutine, piovided this haidwaie-geneiat- ed LCALL is not bIocked by any of the foIIowing con- ditions: 1. An inteiiupt of equaI oi highei piioiity IeveI is aI- ieady in piogiess. 2. The cuiient (poIIing) cycIe is not the finaI cycIe in the execution of the instiuction in piogiess. 3. The instiuction in piogiess is RFTI oi any wiite to the IF oi IP iegisteis. Any of these thiee conditions wiII bIock the geneiation of the LCALL to the inteiiupt seivice ioutine. Condi- tion 2 ensuies that the instiuction in piogiess wiII be 27025220 This is the fastest possible response when C2 is the final cycle of an instruction other than RETI or an access to IE or IP Figure 24 Interrupt Response Timing Diagram 22 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 compIeted befoie vectoiing to any seivice ioutine. Con- dition 3 ensuies that if the instiuction in piogiess is RFTI oi any access to IF oi IP, then at Ieast one more instiuction wiII be executed befoie any inteiiupt is vec- toied to. The poIIing cycIe is iepeated with each machine cycIe, and the vaIues poIIed aie the vaIues that weie piesent at S5P2 of the pievious machine cycIe. Note then that if an inteiiupt fIag is active but not being iesponded to foi one of the above conditions, and is not still active when the bIocking condition is iemoved, the denied inteiiupt wiII not be seiviced. In othei woids, the fact that the inteiiupt fIag was once active but not seiviced is not iemembeied. Fveiy poIIing cycIe is new. The poIIing cycIe/LCALL sequence is iIIustiated in Figuie 24. Note that if an inteiiupt of highei piioiity IeveI goes active piioi to S5P2 of the machine cycIe IabeIed C3 in Figuie 24, then in accoidance with the above iuIes it wiII be vectoied to duiing C5 and C6, without any in- stiuction of the Iowei piioiity ioutine having been exe- cuted. Thus the piocessoi acknowIedges an inteiiupt iequest by executing a haidwaie-geneiated LCALL to the ap- piopiiate seivicing ioutine. In some cases it aIso cIeais the fIag that geneiated the inteiiupt, and in othei cases it doesnt. It nevei cIeais the SeiiaI Poit oi Timei 2 fIags. This has to be done in the useis softwaie. It cIeais an exteinaI inteiiupt fIag (IF0 oi IF1) onIy if it was tiansition-activated. The haidwaie-geneiated LCALL pushes the contents of the Piogiam Countei onto the stack (but it does not save the PSW) and ie- Ioads the PC with an addiess that depends on the souice of the inteiiupt being vectoied to, as shown be- Iow. Source Vector Address IE0 0003H TF0 000BH IE1 0013H TF1 001BH RI a TI 0023H TF2 a EXF2 002BH Fxecution pioceeds fiom that Iocation untiI the RFTI instiuction is encounteied. The RFTI instiuction in- foims the piocessoi that this inteiiupt ioutine is no Iongei in piogiess, then pops the top two bytes fiom the stack and ieIoads the Piogiam Countei. Fxecution of the inteiiupted piogiam continues fiom wheie it Ieft off. Note that a simpIe RFT instiuction wouId aIso have ietuined execution to the inteiiupted piogiam, but it wouId have Ieft the inteiiupt contioI system thinking an inteiiupt was stiII in piogiess. External Interrupts The exteinaI souices can be piogiammed to be IeveI-ac- tivated oi tiansition-activated by setting oi cIeaiing bit IT1 oi IT0 in Registei TCON. If ITx e 0, exteinaI inteiiupt x is tiiggeied by a detected Iow at the INTx pin. If ITx e 1, exteinaI inteiiupt x is edge-tiiggeied. In this mode if successive sampIes of the INTx pin show a high in one cycIe and a Iow in the next cycIe, inteiiupt iequest fIag IFx in TCON is set. FIag bit IFx then iequests the inteiiupt. Since the exteinaI inteiiupt pins aie sampIed once each machine cycIe, an input high oi Iow shouId hoId foi at Ieast 12 osciIIatoi peiiods to ensuie sampIing. If the exteinaI inteiiupt is tiansition-activated, the exteinaI souice has to hoId the iequest pin high foi at Ieast one machine cycIe, and then hoId it Iow foi at Ieast one machine cycIe to ensuie that the tiansition is seen so that inteiiupt iequest fIag IFx wiII be set. IFx wiII be automaticaIIy cIeaied by the CPU when the seivice ioutine is caIIed. If the exteinaI inteiiupt is IeveI-activated, the exteinaI souice has to hoId the iequest active untiI the iequested inteiiupt is actuaIIy geneiated. Then it has to deacti- vate the iequest befoie the inteiiupt seivice ioutine is compIeted, oi eIse anothei inteiiupt wiII be geneiated. Response Time The INT0 and INT1 IeveIs aie inveited and Iatched into the inteiiupt fIags IF0 and IF1 at S5P2 of eveiy machine cycIe. SimiIaiIy, the Timei 2 fIag FXF2 and the SeiiaI Poit fIags RI and TI aie set at S5P2. The vaIues aie not actuaIIy poIIed by the ciicuitiy untiI the next machine cycIe. The Timei 0 and Timei 1 fIags, TF0 and TF1, aie set at S5P2 of the cycIe in which the timeis oveifIow. The vaIues aie then poIIed by the ciicuitiy in the next cycIe. Howevei, the Timei 2 fIag TF2 is set at S2P2 and is poIIed in the same cycIe in which the timei oveifIows. If a iequest is active and conditions aie iight foi it to be acknowIedged, a haidwaie subioutine caII to the ie- quested seivice ioutine wiII be the next instiuction to be executed. The caII itseIf takes two cycIes. Thus, a mini- mum of thiee compIete machine cycIes eIapse between activation of an exteinaI inteiiupt iequest and the be- ginning of execution of the fiist instiuction of the seiv- ice ioutine. Figuie 24 shows inteiiupt iesponse timings. A Iongei iesponse time wouId iesuIt if the iequest is bIocked by one of the 3 pieviousIy Iisted conditions. If an inteiiupt of equaI oi highei piioiity IeveI is aIieady in piogiess, the additionaI wait time obviousIy depends on the natuie of the othei inteiiupts seivice ioutine. If the instiuction in piogiess is not in its finaI cycIe, the additionaI wait time cannot be moie than 3 cycIes, since the Iongest instiuctions (MUL and DIV) aie onIy 4 23 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 cycIes Iong, and if the instiuction in piogiess is RFTI oi an access to IF oi IP, the additionaI wait time can- not be moie than 5 cycIes (a maximum of one moie cycIe to compIete the instiuction in piogiess, pIus 4 cycIes to compIete the next instiuction if the instiuction is MUL oi DIV). Thus, in a singIe-inteiiupt system, the iesponse time is aIways moie than 3 cycIes and Iess than 9 cycIes. SINGLE-STEP OPERATION The 8051 inteiiupt stiuctuie aIIows singIe-step execu- tion with veiy IittIe softwaie oveihead. As pieviousIy noted, an inteiiupt iequest wiII not be iesponded to whiIe an inteiiupt of equaI piioiity IeveI is stiII in piog- iess, noi wiII it be iesponded to aftei RFTI untiI at Ieast one othei instiuction has been executed. Thus, once an inteiiupt ioutine has been enteied, it cannot be ie-enteied untiI at Ieast one instiuction of the inteiiupt- ed piogiam is executed. One way to use this featuie foi singIe-stop opeiation is to piogiam one of the exteinaI inteiiupts (say, INT0) to be IeveI-activated. The seivice ioutine foi the inteiiupt wiII teiminate with the foIIow- ing code: JNB P32$ Wait Here Till INT0 Goes High JB P32$ Now Wait Here Till it Goes Low RETI Go Back and Execute One Instruction Now if the INT0 pin, which is aIso the P3.2 pin, is heId noimaIIy Iow, the CPU wiII go iight into the FxteinaI Inteiiupt 0 ioutine and stay theie untiI INT0 is puIsed (fiom Iow to high to Iow). Then it wiII execute RFTI, go back to the task piogiam, execute one instiuction, and immediateIy ie-entei the FxteinaI Inteiiupt 0 iou- tine to await the next puIsing of P3.2. One step of the task piogiam is executed each time P3.2 is puIsed. RESET The ieset input is the RST pin, which is the input to a Schmitt Tiiggei. A ieset is accompIished by hoIding the RST pin high foi at Ieast two machine cycIes (24 osciIIatoi peiiods), while the oscillator is running The CPU iesponds by geneiating an inteinaI ieset, with the timing shown in Figuie 25. The exteinaI ieset signaI is asynchionous to the inteinaI cIock. The RST pin is sampIed duiing State 5 Phase 2 of eveiy machine cycIe. The poit pins wiII maintain theii cuiient activities foi 19 osciIIatoi peiiods aftei a Iogic 1 has been sampIed at the RST pin, that is, foi 19 to 31 osciIIatoi peiiods aftei the exteinaI ieset signaI has been appIied to the RST pin. WhiIe the RST pin is high, ALF and PSFN aie weakIy puIIed high. Aftei RST is puIIed Iow, it wiII take 1 to 2 machine cycIes foi ALF and PSFN to stait cIocking. Foi this ieason, othei devices can not be synchionized to the inteinaI timings of the 8051. Diiving the ALF and PSFN pins to 0 whiIe ieset is active couId cause the device to go into an indeteimi- nate state. The inteinaI ieset aIgoiithm wiites 0s to aII the SFRs except the poit Iatches, the Stack Pointei, and SBUF. The poit Iatches aie initiaIized to FFH, the Stack Pointei to 07H, and SBUF is indeteiminate. TabIe 3 Iists the SFRs and theii ieset vaIues. The inteinaI RAM is not affected by ieset. On powei up the RAM content is indeteiminate. 27025233 Figure 25 Reset Timing 24 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 Table 3 Reset Values of the SFRs SFR Name Reset Value PC 0000H ACC 00H B 00H PSW 00H SP 07H DPTR 0000H P0P3 FFH IP (8051) XXX00000B IP (8052) XX000000B IE (8051) 0XX00000B IE (8052) 0X000000B TMOD 00H TCON 00H TH0 00H TL0 00H TH1 00H TL1 00H TH2 (8052) 00H TL2 (8052) 00H RCAP2H (8052) 00H RCAP2L (8052) 00H SCON 00H SBUF Indeterminate PCON (HMOS) 0XXXXXXXB PCON (CHMOS) 0XXX0000B 27025221 Figure 26 Power on Reset Circuit POWER-ON RESET Foi HMOS devices when V CC is tuined on an automat- ic ieset can be obtained by connecting the RST pin to V CC thiough a 10 mF capacitoi and to V SS thiough an 8.2 KX iesistoi (Figuie 26). The CHMOS devices do not iequiie this iesistoi aIthough its piesence does no haim. In fact, foi CHMOS devices the exteinaI iesistoi can be iemoved because they have an inteinaI puIIdown on the RST pin. The capacitoi vaIue couId then be ie- duced to 1 mF. When powei is tuined on, the ciicuit hoIds the RST pin high foi an amount of time that depends on the capaci- toi vaIue and the iate at which it chaiges. To ensuie a vaIid ieset the RST pin must be heId high Iong enough to aIIow the osciIIatoi to stait up pIus two machine cycIes. On powei up, V CC shouId iise within appioximateIy ten miIIiseconds. The osciIIatoi stait-up time wiII de- pend on the osciIIatoi fiequency. Foi a 10 MHz ciystaI, the stait-up time is typicaIIy 1 ms. Foi a 1 MHz ciystaI, the stait-up time is typicaIIy 10 ms. With the given ciicuit, ieducing V CC quickIy to 0 caus- es the RST pin voItage to momentaiiIy faII beIow 0V. Howevei, this voItage is inteinaIIy Iimited and wiII not haim the device. NOTE The poit pins wiII be in a iandom state untiI the osciIIatoi has staited and the inteinaI ieset aIgoiithm has wiitten 1s to them. Poweiing up the device without a vaIid ieset couId cause the CPU to stait executing instiuctions fiom an indeteiminate Iocation. This is because the SFRs, spe- cificaIIy the Piogiam Countei, may not get piopeiIy initiaIized. POWER-SAVING MODES OF OPERATION Foi appIications wheie powei consumption is ciiticaI the CHMOS veision piovides powei ieduced modes of opeiation as a standaid featuie. The powei down mode in HMOS devices is no Iongei a standaid featuie and is being phased out. CHMOS Power Reduction Modes CHMOS veisions have two powei-ieducing modes, IdIe and Powei Down. The input thiough which back- up powei is suppIied duiing these opeiations is VCC. Figuie 27 shows the inteinaI ciicuitiy which impIe- ments these featuies. In the IdIe mode (IDL e 1), the osciIIatoi continues to iun and the Inteiiupt, SeiiaI Poit, and Timei bIocks continue to be cIocked, but the 25 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 cIock signaI is gated off to the CPU. In Powei Down (PD e 1), the osciIIatoi is fiozen. The IdIe and Powei Down modes aie activated by setting bits in SpeciaI Function Registei PCON. The addiess of this iegistei is 87H. Figuie 28 detaiIs its contents. In the HMOS devices the PCON iegistei onIy contains SMOD. The othei foui bits aie impIemented onIy in the CHMOS devices. Usei softwaie shouId nevei wiite 1s to unimpIemented bits, since they may be used in futuie MCS-51 pioducts. IDLE MODE An instiuction that sets PCON.0 causes that to be the Iast instiuction executed befoie going into the IdIe mode. In the IdIe mode, the inteinaI cIock signaI is gated off to the CPU, but not to the Inteiiupt, Timei, and SeiiaI Poit functions. The CPU status is pieseived in its entiiety: the Stack Pointei, Piogiam Countei, Piogiam Status Woid, AccumuIatoi, and aII othei ieg- isteis maintain theii data duiing IdIe. The poit pins hoId the IogicaI states they had at the time IdIe was activated. ALF and PSFN hoId at Iogic high IeveIs. Theie aie two ways to teiminate the IdIe. Activation of any enabIed inteiiupt wiII cause PCON.0 to be cIeaied by haidwaie, teiminating the IdIe mode. The inteiiupt wiII be seiviced, and foIIowing RFTI the next instiuc- tion to be executed wiII be the one foIIowing the in- stiuction that put the device into IdIe. 27025222 Figure 27 Idle and Power Down Hardware (MSB) (LSB) SMOD - - - GF1 GF0 PD IDL Symbol Position Name and Function SMOD PCON7 Double Baud rate bit When set to a 1 and Timer 1 is used to generate baud rate and the Serial Port is used in modes 1 2 or 3 PCON6 (Reserved) PCON5 (Reserved) PCON4 (Reserved) GF1 PCON3 General-purpose flag bit GF0 PCON2 General-purpose flag bit PD PCON1 Power Down bit Setting this bit activates power down operation IDL PCON0 Idle mode bit Setting this bit activates idle mode operation If 1s are written to PD and IDL at the same time PD takes precedence The reset value of PCON is (0XXX0000) In the HMOS devices the PCON register only contains SMOD The other four bits are implemented only in the CHMOS devices User software should never write 1s to unimplemented bits since they may be used in future MCS-51 products Figure 28 PCON Power Control Register The fIag bits OF0 and OF1 can be used to give an indication if an inteiiupt occuiied duiing noimaI opei- ation oi duiing an IdIe. Foi exampIe, an instiuction that activates IdIe can aIso set one oi both fIag bits. When IdIe is teiminated by an inteiiupt, the inteiiupt seivice ioutine can examine the fIag bits. The othei way of teiminating the IdIe mode is with a haidwaie ieset. Since the cIock osciIIatoi is stiII iun- ning, the haidwaie ieset needs to be heId active foi onIy two machine cycIes (24 osciIIatoi peiiods) to compIete the ieset. The signaI at the RST pin cIeais the IDL bit diiectIy and asynchionousIy. At this time the CPU iesumes piogiam execution fiom wheie it Ieft off, that is, at the instiuction foIIowing the one that invoked the IdIe Mode. As shown in Figuie 25, two oi thiee machine cycIes of piogiam execution may take pIace befoie the inteinaI ieset aIgoiithm takes contioI. On-chip haid- waie inhibits access to the inteinaI RAM duiing this time, but access to the poit pins is not inhibited. To eIiminate the possibiIity of unexpected outputs at the poit pins, the instiuction foIIowing the one that invokes IdIe shouId not be one that wiites to a poit pin oi to exteinaI Data RAM. POWER DOWN MODE An instiuction that sets PCON.1 causes that to be the Iast instiuction executed befoie going into the Powei Down mode. In the Powei Down mode, the on-chip osciIIatoi is stopped. With the cIock fiozen, aII func- 26 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 Table 4 EPROM Versions of the 8051 and 8052 Device EPROM EPROM Ckt VPP Time Required to Name Version Bytes Type Program Entire Array 8051AH 8751H8751BH 4K HMOS 210V1275V 4 minutes 80C51BH 87C51 4K CHMOS 1275V 13 seconds 8052AH 8752BH 8K HMOS 1275V 26 seconds tions aie stopped, but the on-chip RAM and SpeciaI Function Registeis aie heId. The poit pins output the vaIues heId by theii iespective SFRs. ALF and PSFN output Iows. The onIy exit fiom Powei Down foi the 80C51 is a haidwaie ieset. Reset iedefines aII the SFRs, but does not change the on-chip RAM. In the Powei Down mode of opeiation, VCC can be ieduced to as Iow as 2V. Caie must be taken, howevei, to ensuie that VCC is not ieduced befoie the Powei Down mode is invoked, and that VCC is iestoied to its noimaI opeiating IeveI, befoie the Powei Down mode is teiminated. The ieset that teiminates Powei Down aIso fiees the osciIIatoi. The ieset shouId not be activated befoie VCC is iestoied to its noimaI opeiating IeveI, and must be heId active Iong enough to aIIow the osciI- Iatoi to iestait and stabiIize (noimaIIy Iess than 10 msec). EPROM VERSIONS The FPROM veisions of these devices aie Iisted in Ta- bIe 4. The 8751H piogiams at VPP e 21V using one 50 msec PROO puIse pei byte piogiammed. This ie- suIts in a totaI piogiamming time (4K bytes) of appiox- imateIy 4 minutes. The 8751BH, 8752BH and 87C51 use the fastei Quick-PuIse piogiamming aIgoiithm. These devices piogiam at VPP e 12.75V using a seiies of twenty-five 100 ms PROO puIses pei byte piogiammed. This iesuIts in a totaI piogiamming time of appioxi- mateIy 26 seconds foi the 8752BH (8 Kbytes) and 13 seconds foi the 87C51 (4 Kbytes). DetaiIed pioceduies foi piogiamming and veiifying each device aie given in the data sheets. Exposure to Light It is good piactice to covei the FPROM window with an opaque IabeI when the device is in opeiation. This is not so much to piotect the FPROM aiiay fiom inad- veitent eiasuie, but to piotect the RAM and othei on- chip Iogic. AIIowing Iight to impinge on the siIicon die whiIe the device is opeiating can cause IogicaI maIfunc- tion. Program Memory Locks In some miciocontioIIei appIications it is desiiabIe that the Piogiam Memoiy be secuie fiom softwaie piiacy. InteI has iesponded to this need by impIementing a Piogiam Memoiy Iocking scheme in some of the MCS- 51 devices. WhiIe it is impossibIe foi anyone to guaian- tee absoIute secuiity against aII IeveIs of technoIogicaI sophistication, the Piogiam Memoiy Iocks in the MCS- 51 devices wiII piesent a substantiaI baiiiei against iIIe- gaI ieadout of piotected softwaie. One Lock Bit Scheme on 8751H The 8751H contains a Iock bit which, once pio- giammed, denies eIectiicaI access by any exteinaI means to the on-chip Piogiam Memoiy. The effect of this Iock bit is that whiIe it is piogiammed the inteinaI Piogiam Memoiy can not be iead out, the device can not be fuithei piogiammed, and it can not execute ex- ternal Program Memory. Fiasing the FPROM aiiay deactivates the Iock bit and iestoies the devices fuII functionaIity. It can then be ie-piogiammed. The pioceduie foi piogiamming the Iock bit is detaiIed in the 8751H data sheet. Two Program Memory Lock Schemes The 8751BH, 8752BH and 87C51 contain two Piogiam Memoiy Iocking schemes: Fnciypted Veiify and Lock Bits. Encryption Array Within the FPROM is an aiiay of enciyption bytes that aie initiaIIy unpiogiammed (aII 1s). The usei can piogiam the aiiay to enciypt the code bytes duiing FPROM veiification. The veiifica- tion pioceduie sequentiaIIy XNORs each code byte with one of the key bytes. When the Iast key byte in the aiiay is ieached, the veiify ioutine staits ovei with the fiist byte of the aiiay foi the next code byte. If the key bytes aie unpiogiammed, the XNOR piocess Ieaves the code byte unchanged. With the key bytes piogiammed, the code bytes aie enciypted and can be iead coiiectIy onIy if the key bytes aie known in theii piopei oidei. TabIe 6 Iists the numbei of enciyption bytes avaiIabIe on the vaiious pioducts. When using the enciyption aiiay, one impoitant factoi shouId be consideied. If a code byte has the vaIue 27 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 0FFH, veiifying the byte wiII pioduce the enciyption byte vaIue. If a Iaige bIock of code is Ieft unpio- giammed, a veiification ioutine wiII dispIay the enciyp- tion aiiay contents. Foi this ieason aII unused code bytes shouId be piogiammed with some vaIue othei than 0FFH, and not aII of them the same vaIue. This wiII ensuie maximum piogiam piotection. Program Lock Bits AIso incIuded in the Piogiam Lock scheme aie Lock Bits which can be enabIed to piovide vaiying degiees of piotection. TabIe 5 Iists the Lock Bits and theii coiiesponding effect on the micio- contioIIei. Refei to TabIe 6 foi the Lock Bits avaiIabIe on the vaiious pioducts. Fiasing the FPROM aIso eiases the Fnciyption Aiiay and the Lock Bits, ietuining the pait to fuII functionaIi- ty. Table 5 Program Lock Bits and their Features Program Lock Bits Protection Type LB1 LB2 LB3 1 U U U No program lock features enabled (Code verify will still be encrypted by the encryption array if programmed) 2 P U U MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory EA is sampled and latched on reset and further programming of the EPROM is disabled 3 P P U Same as 2 also verify is disabled 4 P P P Same as 3 also external execution is disabled P-Programmed U-Unprogrammed Any othei combination of the Lock Bits is not defined. Table 6 Program Protection Device Lock Bits Encrypt Array 8751BH LB1 LB2 32 Bytes 8752BH LB1 LB2 32 Bytes 87C51 LB1 LB2 LB3 64 Bytes When Lock Bit 1 is piogiammed, the Iogic IeveI at the FA pin is sampIed and Iatched duiing ieset. If the de- vice is poweied up without a ieset, the Iatch initiaIizes to a iandom vaIue, and hoIds that vaIue untiI ieset is activated. It is necessaiy that the Iatched vaIue of FA be in agieement with the cuiient Iogic IeveI at that pin in oidei foi the device to function piopeiIy. ROM PROTECTION The 8051AHP and 80C51BHP aie ROM Piotected veisions of the 8051AH and 80C51BH, iespectiveIy. To incoipoiate this Piotection Featuie, piogiam veiifica- tion has been disabIed and exteinaI memoiy accesses have been Iimited to 4K. Refei to the data sheets on these paits foi moie infoimation. ONCE Mode The ONCF (on-ciicuit emuIation) mode faciIitates testing and debugging of systems using the device with- out the device having to be iemoved fiom the ciicuit. The ONCF mode is invoked by: 1. PuII ALF Iow whiIe the device is in ieset and PSFN is high, 2. HoId ALF Iow as RST is deactivated. WhiIe the device is in ONCF mode, the Poit 0 pins go into a fIoat state, and the othei poit pins and ALF and PSFN aie weakIy puIIed high. The osciIIatoi ciicuit iemains active. WhiIe the device is in this mode, an emuIatoi oi test CPU can be used to diive the ciicuit. NoimaI opeiation is iestoied aftei a noimaI ieset is appIied. THE ON-CHIP OSCILLATORS HMOS Versions The on-chip osciIIatoi ciicuitiy foi the HMOS (HMOS-I and HMOS-II) membeis of the MCS-51 fam- iIy is a singIe stage Iineai inveitei (Figuie 29), intended foi use as a ciystaI-contioIIed, positive ieactance osciI- Iatoi (Figuie 30). In this appIication the ciystaI is opei- ated in its fundamentaI iesponse mode as an inductive ieactance in paiaIIeI iesonance with capacitance extei- naI to the ciystaI. 28 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 27025223 Figure 29 On-Chip Oscillator Circuitry in the HMOS Versions of the MCS-51 Family 27025224 Figure 30 Using the HMOS On-Chip Oscillator The ciystaI specifications and capacitance vaIues (C1 and C2 in Figuie 30) aie not ciiticaI. 30 pF can be used in these positions at any fiequency with good quaIity ciystaIs. A ceiamic iesonatoi can be used in pIace of the ciystaI in cost-sensitive appIications. When a ce- iamic iesonatoi is used, C1 and C2 aie noimaIIy seIect- ed to be of somewhat highei vaIues, typicaIIy, 47 pF. The manufactuiei of the ceiamic iesonatoi shouId be consuIted foi iecommendations on the vaIues of these capacitois. In geneiaI, ciystaIs used with these devices typicaIIy have the foIIowing specifications: FSR (FquivaIent Seiies Resistance) see Figuie 31 C O (Shunt Capacitance) 7.0 pF max. C L (Load Capacitance) 30 pF g3 pF Diive LeveI 1 mW 27025234 Figure 31 ESR vs Frequency 29 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 Fiequency, toIeiance and tempeiatuie iange aie detei- mined by the system iequiiements. A moie in-depth discussion of ciystaI specifications, ce- iamic iesonatois, and the seIection of vaIues foi C1 and C2 can be found in AppIication Note AP-155, OsciIIa- tois foi MiciocontioIIeis, which is incIuded in the Embedded Applications Handbook. To diive the HMOS paits with an exteinaI cIock souice, appIy the exteinaI cIock signaI to XTAL2, and giound XTAL1, as shown in Figuie 32. A puIIup iesis- toi may be used (to inciease noise maigin), but is op- tionaI if VOH of the diiving gate exceeds the VIH MIN specification of XTAL2. 27025225 Figure 32 Driving the HMOS MCS-51 Parts with an External Clock Source CHMOS Versions The on-chip osciIIatoi ciicuitiy foi the 80C51BH, shown in Figuie 33, consists of a singIe stage Iineai inveitei intended foi use as a ciystaI-contioIIed, posi- tive ieactance osciIIatoi in the same mannei as the HMOS paits. Howevei, theie aie some impoitant dif- feiences. One diffeience is that the 80C51BH is abIe to tuin off its osciIIatoi undei softwaie contioI (by wiiting a 1 to the PD bit in PCON). Anothei diffeience is that in the 80C51BH the inteinaI cIocking ciicuitiy is diiven by the signaI at XTAL1, wheieas in the HMOS veisions it is by the signaI at XTAL2. The feedback iesistoi R f in Figuie 33 consists of paiaI- IeIed n- and p- channeI FFTs contioIIed by the PD bit, such that R f is opened when PD e 1. The diodes D1 and D2, which act as cIamps to VCC and VSS, aie paiasitic to the R f FFTs. The osciIIatoi can be used with the same exteinaI com- ponents as the HMOS veisions, as shown in Figuie 34. TypicaIIy, C1 e C2 e 30 pF when the feedback eIe- ment is a quaitz ciystaI, and C1 e C2 e 47 pF when a ceiamic iesonatoi is used. To diive the CHMOS paits with an exteinaI cIock souice, appIy the exteinaI cIock signaI to XTAL1, and Ieave XTAL2 fIoat, as shown in Figuie 35. 27025226 Figure 33 On-Chip Oscillator Circuitry in the CHMOS Versions of the MCS-51 Family 30 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 27025227 Figure 34 Using the CHMOS On-Chip Oscillator 27025228 Figure 35 Driving the CHMOS MCS-51 Parts with an External Clock Source The ieason foi this change fiom the way the HMOS pait is diiven can be seen by compaiing Figuies 29 and 33. In the HMOS devices the inteinaI timing ciicuits aie diiven by the signaI at XTAL2. In the CHMOS devices the inteinaI timing ciicuits aie diiven by the signaI at XTAL1. INTERNAL TIMING Figuies 36 thiough 39 show when the vaiious stiobe and poit signaIs aie cIocked inteinaIIy. The figuies do not show iise and faII times of the signaIs, noi do they show piopagation deIays between the XTAL signaI and events at othei pins. Rise and faII times aie dependent on the exteinaI Ioad- ing that each pin must diive. They aie often taken to be something in the neighboihood of 10 nsec, measuied between 0.8V and 2.0V. Piopagation deIays aie diffeient foi diffeient pins. Foi a given pin they vaiy with pin Ioading, tempeiatuie, VCC, and manufactuiing Iot. If the XTAL wavefoim is taken as the timing iefeience, piop deIays may vaiy fiom 25 to 125 nsec. The AC Timings section of the data sheets do not iefei- ence any timing to the XTAL wavefoim. Rathei, they ieIate the ciiticaI edges of contioI and input signaIs to each othei. The timings pubIished in the data sheets incIude the effects of piopagation deIays undei the specified test conditions. 31 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 27025229 Figure 36 External Program Memory Fetches 27025230 Figure 37 External Data Memory Read Cycle 32 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 27025231 Figure 38 External Data Memory Write Cycle 27025232 Figure 39 Port Operation 33 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 ADDITIONAL REFERENCES The foIIowing appIication notes and aiticIes aie found in the Embedded Applications handbook. (Oidei Numbei: 270648) 1. AP-125 Designing MiciocontioIIei Systems foi FIectiicaIIy Noisy Fnviionments. 2. AP-155 OsciIIatois foi MiciocontioIIeis. 3. AP-252 Designing with the 80C51BH. 4. AR-517 Using the 8051 MiciocontioIIei with Resonant Tiansduceis. 34