Current-Mode Digital Gates and Circuits: Concept, Design and Verification

Oleg Maslennikow, Piotr Pawlowski, Przemyslaw Soltan and Robert Berezowski

Technical University of Koszalin, POLAND, e-mail: olen@,ie.tu.koszalin.pl
ABSTRACT The paper deals with the problem of design and FPGAbased realization of digital circuits with the current-mode gates - novel digital gates operating with constant, continuous power supply current. The purpose is the provision of a high level of noise immunity of chips, which contain both analog and digital circuits. Using proposed approach to design digital current-mode circuits, current-mode prototypes of several digital circuits and similar to Spartan I1 slice are designed. Obtained circuits are characterized by smaller hardware overheads and switching noise levels in comparison with the similar circuits based on the classical voltage type of gates. It indicates the possibility of realization of field programmable mixed analog-digital array on a single die. type gates. Moreover, based on the current-mode gates, several digital circuits were designed, which are characterized by smaller number of gates in comparison with their prototypes constructed with classical voltage CMOS-type gates [4, 51. Note that the physical and logical properties of the current-mode gates differ from corresponding properties of classical voltage-mode gates. Therefore, in this paper, we use approaches proposed in ref. [4] to design current-mode digital circuits to perform a prototype of the basic block of Xilinx FPGA cells - the Spartan I1 FPGAs slice. For the verification of the designed current-mode circuits at the logical level, the VHDL language was used. To do this, new logical levels (and new resolution table) were introduced in the element std-logic 1 164 of Active-HDL@ library IEEE 1 164. A new library of current-mode gates was created. In this paper, we also propose the approach for automatic implementation of the target digital circuits in the current-mode FPGA chip. The paper purpose is an investigation of the possibility of design and realization of the whole programmable mixed analog-digital system on a single die.
2. CURRENT-MODE GATES AND OPERATIONS OVERVIEW

1. INTRODUCTION

Modern application specific systems (for example, signal processing systems) contain both digital and analog parts, where the first part usually is the specialized parallel processor, while the latter is the preprocessing and interface unit between digital part and external world [l]. Advances of the modem VLSI technology allow us to implement such mixed systems on a single die. Moreover, the general trend is toward solutions that guarantee high density and easy design. Reconfigurable arrays, as i.e. field programmable gate arrays (FPGA) [1, 21 and analog arrays (FPAA) [3] are examples of these solutions. This allows to design and to implement an entirely programmable specialized mixed analog-digital system (FPMA) on a common semiconductor substrate. However, the problem of influence of digital part on the analog part of such a system-on-chip must be solved during system design. Switching transients (noise) of the digital part can perturb the analog part of a system owing to the coupling through the substrate. There are several known solutions for substrate interference reduction - the use of physical separation of analog and digital circuits, guard rings, and a low inductance substrate bias. Each of these methods has its own advantages and drawbacks. Another alternative approach for minimizing substrate crosstalk, is based on the implementation of the digital part of the mixed system with the current mode gates [4]. Due to the nearly constant value of the power supply current at different gate states, the level of its noise is essentially lower in comparison with the classical voltage 0-7803-7596-3/02/$17.00 02002 IEEE

Fig. 1 represents a basic concept of a current-mode gate [4]. This circuit operates with a continuous, constant current drawn from the power supply and generates low values of current and voltage signals, which fulfill the requirements for minimizing the substrate interferences. Using a simple saturation-mode transistor model, the equation for the output current may be represented by the following form:
Io=Zq-Kz

(K

-+VT,-VTz-V]2;

where: V,., ,V, - threshold voltages of nMOS transistors. In this case, the output current f, = f q means the logical ,,l at the output ,,out. Logical ,,l at the input corresponds to the value:
I, 2 K ,

.(.+E)

623

Then the output current I, = 0 means the logical ,,O on the output of the gate. Therefore, the circuit in Fig.la performs logical inversion (NOT-operation). Note, that when more than one excitation of value, which can fulfill equation (2) is given, then circuit in Fig. 1 performs logical negation of alternative (NOR-operation). Details of current-mode gate concept and electronic parameters of several current-mode gates are represented in the ref. [4,51.

operation corresponds, at the physical level, to the addition of currents, each of which represents the value of the corresponding operand. On the functional level this means an association of all operand lines into the one node. Similarly, an arithmetic subtraction operation in this technique, on the physical level, is performed by the subtraction of currents. On the functional level, this means (for example, for expression (X-r)) the association of the line of the operand X with the output of the antiinverter gate connected to the line of the operand Y, where Y E {O,l}. Examples of realization of operations (X+Y) and ( X Y ) are shown in Fig. 3.

Fig. 2. Current-mode gate with four different output types Fig. 1. Basic concept of the current-mode gate There are four types of gates in the current-mode gate technique. The gate of the first type is named an inverter. It implements the logical function Y,= X of the inversion, according to the following expression:
0 if X = 1,2,3,...

Fig. 3. Realization of addition and subtraction operations in the current-mode technique It follows from the expressions (3) - (6) that arbitrary logical variable in this logic is (in a general case) a multivalued one. Moreover, the value of the variable (or function) which appears on any gate output belongs to the set {-1, 0, l}, while the value of the variable on any gate input (for example, as a result of an addition or subtraction operations) belongs to the set of integer numbers from the range ]-oo,oo[. Due to such logical properties, the Boolean algebra identities are not suitable for the current-mode algebra. Therefore, in ref. [4,5], we propose several approaches to design digital circuits with current-mode gates. Using proposed approaches functional schemes of the several current-mode digital circuits - adders, decoders, multiplexers, triggers, counters and some others were designed. The obtained circuits are characterized by smaller (up to 35%) hardware overheads in comparison with the similar circuits based on the classical voltage type gates. As an example, the current-mode version of one-bit adder is presented in Fig.4, where outputs of sum s, and output carry bit c , + ~are the following logic functions:
_

(3)

Gates of the second type are named the anti-inverters. They implement the logical function Y, = 2 of the antiinversion, according to the following expression:
-- 1 if

X = l,2,3,...

(4)

The third type of the current-mode gate is named an inverter-inverter (or double-inverter). Its carried out is represented below: logical function Y,=

The fourth type of the current-mode gate is named an inverter-anti-inverter. It implements the logical function

Y, =

x ,which is represented by the expression (6).

0 if X = 1,2,3,...

(6)
-

cI+,= a,
A

+ b, + ?,

and
(7)

Moreover, all current-mode gates have only one input, while an arbitrary gate may contain several outputs, even of a different type. For example, the graphical representation of the current-mode gate with four different types of output (inverter q , anti-inverter

s, =

+ ( a , + b, + t,)+ a, + b, + c, .
CI+1

Y,, double inverter Y, and inverter-anti-inverter Y,) is

shown in the Fig.2. Therefore, there are only four types of elementary operations in the current mode logic inversion and double-inversion (scallion) operations. The addition 624 Fig. 4. The 6-gate version of the one-bit adder The results of simulation of this adder in the ActiveHDL v.4.1 environment are presented in ref. [6].

3. DESIGN OF CURRENT-MODE PROTOTYPE OF THE SPARTAN I1 FPGAs SLICE

The Spartan @ -11 Field-Programmable Gate Array family has a regular, flexible, programmable architecture of Configurable Logic Blocks (CLBs), surrounded by a perimeter of programmable Input/Output Blocks (IOBs). The basic building block of the Spartan-I1 CLB is the logic cell (LC). An LC includes a 4-input function generator, carry logic, and a storage element. Each Spartan-I1 CLB contains four LCs organized in two similar slices; a single slice is shown in Fig. 5. In addition to the four basic LCs, the Spartan-I1 CLB contains logic that combines function generators to provide functions of five or six inputs.

Spartan-I1 function generators are implemented as 4input look-up tables (LUTs). Four independent inputs are connected to each of two function generators of the single slice (Fl-F4 and Gl-G4). Each of these function generators (with outputs labeled 0) are capable to implement any arbitrary defined Boolean function of four inputs. The propagation delay is therefore independent of the implemented function. In addition, to operate as a function generator, each LUT can provide a 16 x 1-bit synchronous RAM or ROM. Furthermore, the Spartan-I1 function generator can also provide a 16-bit shift register that is ideal for capturing high-speed or burst-mode data. Analysis of the function generator operation shows that it may be composed of 2" cells one-bit FIFO-buffer

BX m

CIN

Fig. 5. Simplified block diagram of Spartan I1 FPGA slice (where n is the number of LUT inputs, n=4 for F' and G' generators), 4-input write decoder, 2"- input multiplexer and some logic controlled by corresponding mode bits FIFO, RAM, ROM, LUT of the configuration memory. The example of such function generator realization is represented in the Fig. 6.
I
In FIFO RAM
Config memow ROM LUTl

G G

Out

G G

Thus, in order to elaborate a current-mode prototype of this function generator circuit, current-mode prototypes of its blocks such as D-trigger (see Fig.7), decoder and multiplexer circuit were designed (presented in [4]) using proposed approaches to design binary current-mode circuits. The current-mode prototype of the whole function generator circuit is presented in the Fig. 8. The current-mode prototypes of other SPARTAN 11 slice blocks, from S1 to S5, are shown in the Fig. 9a - Fig. 9e respectively. Proposed slice may be used as the main block of a current-mode FPGA chip, in which configuration memory is realized with the classical voltage-mode CMOS gates.

cu<
Fig. 6. Simplified block diagram of Spartan I1 series function generator 625

;ml

Fig. 7. Current-mode low-level sensitive D-trigger

4. AUTOMATED IMPLEMENTATION OF CURRENT-MODE CIRCUITS IN FPGA CHIP

In order to implement digital circuits in the current-mode FPGA chip, a simple approach is proposed. It consists of the following steps (see fig. 8.): 0 Design of the VHDL-model of the target circuit in the classical voltage technique and its verification using arbitrary taken VHDL simulator.

The result of this step is the .ncd file and next the .xdl file (when Xilinx Foundation environment is used), which includes information about used slices, inlout blocks, switches, etc. and describes their interconnections. 0 Analysis of the obtained .xdl file and its conversion to the similar file for selected current-mode FPGA chip based on current-mode blocks library. To realize it, the appropriate program-converter is used, which also allows generating the VHDL description of the target circuit in the current-mode technique. This enables to .. simulate the obtained VDHL-model in the arbitrary VHDL simulator (for example, Active-HDL environment), in which current-mode table of resolution and current-mode gates libraries were included. 5. CONCLUSIONS Using proposed approaches to current-mode circuits design, the current-mode prototypes of several digital circuits, as well as the Spartan I1 FPGA's slice have been designed. The obtained circuits are characterized by smaller hardware overheads in comparison with the similar circuits based on the classical voltage type of gates. For the verification of the designed current-mode circuits, the VHDL language has been used. Moreover, the approach to automatic implementation of the target digital circuits in the current-mode FPGA chip has been proposed. It proved the possibility of realization of field programmable mixed analog-digital array on a single die, by the use of specially elaborated current-mode digital circuits.

Fig. 8. Realization of the current-mode 4-input LUT a)

6. REFERENCES
[ I ] G.R. Goslin. A Guide to Using Field Programmable Gate Arrays (FPGAs) for Application-Spec@ Digital Signal Processing Performance. Xilinx, Inc., 1995.

[2] The Programmable Logic Data Book. Xilinx, Inc., 2000. [3] Introducing Motorola's Field Programmable Analog Array, Motorola Inc.. 1997.

T e d
T3

,,I

[4] A. Guzinski, P. Pawlowski, D. Czwyrow, J. Kaniewski, 0. Maslennikow, N. Maslennikowa, D. Rataj, "Design of Digital f the Polish Circuits with Current-Mode Gates," Bulletin o Academy of Sciences, Technical Sciences, vol. 48, no. 1, pp.7391, 2000. [5] 0. Maslennikow "Approaches to Designing and Examples of Digital Circuits Based on the Current-Mode Gates," Datu Recording, Storage & Processing, vol. 3 , no. 2, pp.84-98,2001.

e)
GSR SR

3TY
626

Fig. 9. Current-mode prototypes of slice components S1-S5

0

[6] D. Gretkowski, A. Guzinski, J. Kaniewski, 0. Maslennikow, "VHDL models of digital combinatorical circuits on the current-mode gates," in Proc. 6-th Int. Conf Mixed Design of Integrated Circuits, MIXDES'99, Krakow, Poland, pp.253-258, 1999.

Synthesis of the verified model (mapping, placement and routing procedures) in the selected FPGA chip.

The work is supported by the grant KBN 7T11B 004 20.