SHASTRA MICRO SYSTTEMS - M.

TECH VLSI PROJECTS

CODE MTLD01

LOGIC-DESIGN PROJECT TITLES

YEAR 2013Transaction

Design and Implementation of an On-Chip Permutation Network for multiprocessor System-On-Chip

MTLD02

CORDIC Designs for Fixed Angle of Rotation Low-Cost FIR Filter Designs Based on Faithfully Rounded Truncated Multiple Constant Multiplication/Accumulation An Energy-Efficient L2 Cache Architecture Using Way Tag Information Under Write-Through Policy Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool An Area Efficient Carry select Adder Design by Sharing the Common Boolean logic Term Test Patterns of Multiple SIC Vectors: Theory and Application in BIST Schemes Symmetric Transparent Online BIST for Arrays of Word Organized RAMs Multi-Sized Output Cache Controllers Area Efcient ROM-Embedded SRAM Cache Thread Row Buffers: Improving Memory Performance Isolation and Through put in Multi programmed Environments PROGRAMMABLE DDRX CONTROLLERS Parallelization of Radix-2 Montgomery Multiplication on Multicore Platform A Novel Hardware Efficient FIR Filter for Wireless Sensor Networks New modified Reconfigurable Architectures for Implementing FIR Filters with Low Complexity

2013Transaction 2013Transaction

MTLD03

MTLD04

2013Transaction

MTLD05

2013Transaction

MTLD06

2013Transaction

MTLD07

2013Transaction

MTLD08

2013Transaction

MTLD09

2013

MTLD10 MTLD11 MTLD12

2013 2013Transaction 2013Transaction

MTLD13 MTLD14

2013 2013Transaction

MTLD15 MTLD16

2013 2013

MTLD17

A Configurable Bus-Tracer for Error Reproduction in Post-Silicon Validation* ASIC Implementation of DDR SDRAM Memory Controller A Novel Approach for Assertion Based Verification of DDR Memory Protocols A Fast-Locking All-Digital Deskew Buffer WithDuty-Cycle Correction Design and Verification of a MAC Controller Based on AXI Bus A High Performance Video Transform Engine by Using Space-Time Scheduling Strategy low cost self test technics for small RAM in SOC Using Enhance IEEE 1500 Test wrapper Efficient built-in self-repair strategy for embedded SRAM with selectable redundancy. A High Speed FIR Filter Architecture Based on Novel Higher Radix Algorithm VHDL Implementation of UART with Status Register selected High speed signed multiplier for Digital Signal Processing applications .A Novel Approach for Parallel CRC Generation for High Speed Application. Error-Correcting Unordered Codes and Hardware Support for Robust Asynchronous Global Communication Implementation Of Bist controller For Fault Detection In CLB of FPGA Research and Design of CRT Controller Based on CPLD CIARP: Crypto Instruction-Aware RISC Processor Data Transactions on System-on-Chip Bus Using AXI4 Protocol An efficient FPGA implementation of the Advanced Encryption Standard algorithm High Speed Signed Multiplier for Digital Signal Processing Applications An OCP-AHB Bus Wrapper with Built-in ICE Support for SOC Integration

2013

MTLD18 MTLD19

2013 2013

MTLD20 MTLD21 MTLD22

2013 2013 2012

MTLD23

2012

MTLD24

2012

MTLD25

2012

MTLD26 MTLD27 MTLD28

2012 2012 2012

MTLD29

2012Transaction

MTLD30 MTLD31 MTLD32 MTLD33 MTLD34

2012 2012 2012 2011 2012

MTLD35

2012

MTLD36

2012

MTLD37 MTLD38 MTLD39

Optimal implementation of UART-spi interface in soc Accumulator Based 3-Weight Pattern Generation Low-Power and Area-Efficient Carry Select Adder

2012 2012 2012

MTLD40

EFFICIENT and high performance parallel hardware architectures for AES-GCM Design and Implementation of Low power digital FIR filters based on a low power multipliers and adders on Xilinx FPGA Area optimized Low power arithmetic and logic unit A novel area-throughput optimized architecture for AES FPGA implementation of AES (Advance encryption standards) A FPGA design of AES core architecture for Portable hard disk Memory BIST(Built in self test) with address programmability Modified-DES Encryption Algorithm with Improved BER Performance in Wireless Communication Design and Implementation of APB Bridge based on AMBA(Advanced micro controller bus architecture) 4.0 Pre-fetch-Aware Memory Controllers Building an AMBA AHB compliant Memory Controller

2012Transaction

MTLD41

2011

MTLD42 MTLD43 MTLD44 MTLD45 MTLD46 MTLD47

2011 2011 2011 2011 2011 2011

MTLD48

2011Transaction

MTLD49 MTLD50

2011 2011

MTLD51 MTLD52

An interconnect interface for reconfigurable multimedia system FPGA Implementation of Real-time Ethernet Communication Using RMII Interface Efficient CODEC Designs for Crosstalk on Numeral Systems Avoidance Codes Based

2011 2011

MTLD53

2011

MTLD54 MTLD55

BIST-Based Fault Diagnosis for Read-Only Memories Efficient Linear Feedback Shift Register design for Pseudo Exhaustive Test Generation in BIST Optimizing Memory BIST Address Generator Implementations Design and Implementation of High Performance Reconfigurable Arbiter for On chip Bus Architecture

2011 2011

MTLD56 MTLD57

2011 2011

MTLD58

An On-Chip AHB Bus Tracer With Real-Time Compression and Dynamic Multi resolution Supports for SoC A New Architecture of Test Response AnalyzerBased on the Berlekamp Massey Algorithm for BIST Design of a Random Testing Circuit Based on LFSR for the External Memory Interface A design of the PLB to AHB Bus bridge VHDL implementation of high performance RC6 algorithm using ancient vedic algorithm Accumulator Based 3-Weight Pattern Generation Architecture of faster ram controller design with in-built memory Reconfigurable router for low power and high performance A Reduced-Complexity Architecture for LDPC (low density parity check) Layered Decoding Schemes FPGA implementation RS 232 to USB Converter VLSI Implementation Non-Linear Variable Cut-off H.P.F algorithm Systematic Design of RSA Processors Based on High-Radix Montgomery Multipliers Systematic RSA Design and Realization of an Optimized Memory Access Scheduler

2011Transaction

MTLD59

2011Transaction

MTLD60

2011

MTLD61 MTLD62

2011 2011

MTLD63 MTLD64 MTLD65 MTLD66

2011 2010 2010 2010Transaction

MTLD67 MTLD68 MTLD69

2010 2010 2010Transaction

MTLD70

2010

MTLD71 MTLD72 MTLD73

AXI Compliant DDR3 Controller A Novel BIST Scheme for Low Power Testing A Concurrent B1ST architecture based on Monitoring Square Windows Optimized Design of UART IP Soft Core based on DMA Mode Design of Hybrid Encoded Booth Multiplier with Reduced Switching Activity Technique and Low Power 0.13m Adder for DSP Block in Wireless Sensor Node Design and implementation for MD5-based data integrity checking system Energy Efficient Spatial Coding Technique for Low Power VLSI Applications

2010 2010 2010

MTLD74 MTLD75

2010 2010

MTLD76

2010

MTLD77

2010

MTLD78

Implementation of pipelined 2D DCT and quantization architecture for JPEG image compression

2010Transaction

MTLD79

Implementation of a Self-Motivated Arbitration Scheme for theMultilayer AHB Busmatrix ReBISR: A Reconfigurable Built-In Self-Repair Scheme for Random Access Memories in SOCs A new approach to lut-based design and memory based realization of FIR filter Power Optimization of Linear Feedback Shift Register (LFSR) for Low Power BIST Built In self Test Applicability for the Non Linear Operations of Advanced Encryption Standard The data and read/write controller for March-based8SRAM diagnostic algorithm MBIST Hardware Design of the H.264/AVC Variable Block Size Motion Estimation for Real-Time 1080HD Video Encoding LOW power lossless compression of video using Mpeg4 Reduction of discrete cosine transform/quantization/inverse quantization/inverse discrete cosine transform computational complexity in H.264 video encoding by using an efficient prediction algorithm Very Fast Pipelined RSA Architecture Based on Montgomerys Algorithm High Throughput Pipelined Implementation of AES on FPGA Efficient Technique for the FPGA Implementation of the AES Mix Columns Transformation Architecture Design of High Efficient and Non-Memory AES Crypto Core for WPAN FPGA Implementation of AES Encryption and Decryption A Reverse-Encoding-based on-chip AHB Bus Tracer for Efficient Circular Buffer Utilization AMBA AHB Bus Protocol Checker with Efficient Debugging Mechanism

2010Transaction

MTLD80

2010Transaction

MTLD81

2010Transaction

MTLD82

2009

MTLD83

2009

MTLD84

2009

MTLD85

2009

MTLD85 MTLD86

2009 2009

MTLD87

2009

MTLD88 MTLD89

2009 2009

MTLD90

2009

MTLD91 MTLD92

2009 2009

MTLD93

2008

MTLD94

Design and Implementation of an Advanced DMA Controller on AMBA-Based SoC Improving Memory Bank-Level Parallelism in the Presence of Prefetching Design and Implementation of a Low-power Cryptosystem Soc

2009

MTLD95

2009

MTLD96

2009

MTLD97

32-bit RISC CPU Based on MIPS (Instruction Fetch Module Design)

2009

MTLD98

A Micro programmable Memory Controller for High-Performance Dataflow Applications BIST Approach for testing Embedded Memory Blocks in System-onChips Low Area FSM-Based Memory BIST for Synchronous Asynchronous computing in sense amplifier based pass transitor logic Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication Efficient On-Chip Crosstalk Avoidance CODEC Design Design and Implementation of a Field Programmable CRC Circuit Architecture Design of a multi channel UART controller based on FIFO technique and FPGA The Design and Implementation of AMBA Interfaced HighPerformance SDRAM Controller for HDTV SoC A Multi-resolution AHB Bus Tracer for Real-time Compression of Forward/Backward Traces in a Circular Buffer Low-Power Mixed Signal CVNS-Based 64-Bit Adder for Media Signal Processing An Embedded Multi-resolution AMBA Trace Analyzer for Microprocessor-based SoC Integration Design and Implementation of a Schedulable DMAC on an AMBABased SOPC Platform A VHDL Implementation of UART with BIST capability

2009

MTLD99

2009

MTLD100 MTLD101 MTLD102

2009 2009Transaction 2009

MTLD103 MTLD104

2009 2009

MTLD105

2009Transaction

MTLD106

2009

MTLD107

2009

MTLD108

2009Transaction

MTLD109

2008

MTLD110

2008

MTLD112

2008

MTLD113

A DSP embedded system. Application to digital communication systems

2008

Physical Design-Projects

MTPD01 MTPD02

Design Flow for Flip Folp Grouping in Data Driven Clock Gating Symmetrical Buffered Clock-Tree Synthesis with Supply-voltage Alignment ASIC Clock Tree Estimation in Design Planning Stable matching based metal-only ECO synthesis. An efficient clock tree synthesis method in physical design. Clock mesh frame work Thermal aware timing budget for buffer insertion in early stage of physical design ASIC Clock Tree Estimation in Design Planning A technique to eliminate glitch power consumption at P.D stage in CMOS ckt's Low Complexity Design of Ripple Carry and BrentKung Adders in QCA

2013 2013

MTPD03 MTPD04 MTPD05 MTPD06 MTPD07

2013 2012 2012 2012 2012

MTPD08 MTPD09

2012 2012

MTPD10

2012

LAYOUT DESIGN PROJECTS

MTLO01

Low Power Sequential Circuit Using Clocked Pair Shared Flip flop

2013

MTLO02

A High speed low power CAM with Bit and Power Gated ML Sensing. Constant Delay Logic Style

2013Transaction

MTLO03

2013Transaction

MTLO04

Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops Glitch-Free NAND-Based Digitally Controlled Delay-Lines

2013Transaction

MTLO05

2013Transaction

MTLO06

CMOS full adder for energy efficient arithmetic design

2013

MTLO07

An All-Digital Read Stability and Write Margin Characterization Scheme for CMOS 6T SRAM Array

2012

MTLO08

Design and Analysis of Low Power Full Adder Using Adiabatic Technique Comparison of Transistor count Optimized Full adders with modified CMOS Full adders
area_optimized_low_power_alu A CMOS Single Stage Fully Differential Folded Cascode Amplifier Employing Gain Boosting Technique An improved Phase/Frequency Detector and a glitch-suppression Charge Pump design for PLL Applications

2012

MTLO09

2012

MTLO10 MTLO11

2011 2011

MTLO12

2011

MTLO13

Design of a Multiplexer In Multiple Logic Styles for Low Power VLSI LFSR Counter Implementation in CMOS VLSI
LOW POWER-AREA DESIGNS OF 1BIT FULL ADDER IN CADENCE VIRTUOSO PLATFORM

MTLO14

MTLO15

MTLO16

A Competent Design of 2:1 Multiplexer and Its Application in 1-Bit Full Adder Cell Area, Delay and Power Comparison of Adder Topologies

MTLO17