A LOW COST GSM/GPRS BASED WIRELESS HOME SECURITY SYSTEM

(ABSTRACT) AIM: The main aim of the project is to design A LOW COST GSM/GPRS BASED WIRELESS HOME SECURITY SYSTEM. COMPONENTS: S3C2440 Micro Controller, LCD, GP S Modem, Mo!ile, smo"e sensor, temperat#re sensor$ ABSTRACT: Sec#rit% is a prime concern in o#r da%&toda% life$ '(er%one )ants to !e as m#ch sec#re as possi!le$ *n access control for doors forms a (ital lin" in a sec#rit% chain$ The microcontroller !ased )ireless digital loc" for is an access control s%stem that allo)s onl% a#thori+ed persons to enter a partic#lar room$ ,t is a lo) cost so that the concept is implemented !% #sing micro controller$ ,n this project )e are #sing * M !ased microcontroller for controlling the e-#ipments in the home$ GSM modem is #sed to comm#nicate and respond to the remote commands and those commands are sent to the processor$ The s%stem has a "e% pad !% )hich the pass)ord can !e entered thro#gh it$ .hen the entered pass)ord e-#als )ith the pass)ord stored in the memor% then the GSM modem sends a message to the #ser$ Then the #ser sends an SMS to the em!edded s%stem then the rela% )ill !e on the door )ill !e opened$ 'ntering pass)ord sho#ld !e displa%ed on the li-#id cr%stal displa% and the GSM$ ,f the sending pass)ord thro#gh the GSM is also correct, then the loc" )ill !e opened other)ise the loc" )ill not !e opened$ This s%stem also contains m#ltiple sensors )hich are #sed as sec#rit% p#rpose, alert signal is pro(ided to o)ner of home #sing GSM modem and !#++er to alert s#rro#ndings$

BLOCK DIAGRAM:

REGULATED POWER SUPPLY

TEMPERATURE SENSOR MICRO CONTROLLER SMOKE SENSOR

LCD UNIT

GPRS MODULE

RELAY

MOBILE

IMPLEMENTATION:

OPERATING SYSTEM: Lin#/ Ported into controller$ TARGET DEVICE: S3C2440 01riendl% * M2$ APPLICATION LANGUAGE: C34 5C663 DRIVERS: 7S8 Dri(ers, Displa% Dri(ers$ APPLICATIONS: 7sed for 9ome and office sec#rit% s%stem$ ADVANTAGES: Po)er cons#mption$ REFERENCE: :$ The ;0<: micro controller and em!edded s%stems !% Ma+idi$ 2$ Datasheets and the #ser man#als of S3C2440$ Lo) cost, eas% to implement, a#tomated operation, and Lo)

S C!""#A MICROCONTROLLER:

S*MS7=G>s S3C2440* :?432&!it ,SC microprocessor$ S*MS7=G3s S3C2440* is designed to pro(ide hand&held de(ices and general applications )ith lo)&po)er, and high&performance microcontroller sol#tion in small die si+e$ To red#ce total s%stem cost, the S3C2440* incl#des the follo)ing components$ The S3C2440* is de(eloped )ith * M@20T core, 0$:3#m CMAS standard cells and a memor% complier$ ,ts lo) po)er, simple, elegant and f#ll% static design is partic#larl% s#ita!le for cost& and po)er&sensiti(e applications$ ,t adopts a ne) !#s architect#re "no)n as *d(anced Micro controller 8#s *rchitect#re 0*M8*2$ The S3C2440* offers o#tstanding feat#res )ith its CP7 core, a :?432&!it * M@20T ,SC processor designed !% *d(anced ,SC Machines, Ltd$ The * M@20T implements MM7, *M8* 87S, and 9ar(ard cache architect#re )ith separate :?B8 instr#ction and :?B8 data caches, each )ith an ;&)ord line length$ 8% pro(iding a complete set of common s%stem peripherals, the S3C2440* minimi+es o(erall s%stem costs and eliminates the need to config#re additional components$ The integrated on&chip f#nctions that are descri!ed in this doc#ment incl#deC *ro#nd :$2D internal, :$;D42$<D43$3D memor%, 3$3D e/ternal ,4A microprocessor )ith :?B8 ,&Cache4:?B8 D&Cache4MM7 '/ternal memor% controller 0SD *M Control and Chip Select logic2 LCD controller 0#p to 4B color ST= and 2<?B color T1T2 )ith LCD&dedicated DM* 4&ch DM* controllers )ith e/ternal re-#est pins 3&ch 7* Ts 0,rD*:$0, ?4&8%te T/ 1,1A, and ?4&8%te / 1,1A2 2&ch SP, ,,C !#s interface 0m#lti&master s#pport2 ,,S *#dio CAD'C interface *C3@E CAD'C interface

 SD 9ost interface (ersion :$0 F MMC Protocol (ersion 2$:: compati!le 2&ch 7S8 9ost controller 4 :&ch 7S8 De(ice controller 0(er :$:2 4&ch P.M timers 4 :&ch ,nternal timer 4 .atch Dog Timer ;&ch :0&!it *DC and To#ch screen interface TC )ith calendar f#nction

Camera interface 0Ma/$ 40@? / 40@? pi/els inp#t s#pport$ 204; / 204; pi/el inp#t s#pport for scaling2 :30 General P#rpose ,4A ports 4 24&ch e/ternal interr#pt so#rce Po)er controlC =ormal, Slo), ,dle and Sleep mode An&chip cloc" generator )ith PLL

F$%&'(. S C!""#A B)*+, D$-%'-.

FEATURES: ARCHITECTURE: ,ntegrated s%stem for hand&held de(ices and General em!edded applications$ :?432&8it ,SC architect#re and po)erf#l ,nstr#ction set )ith * M@20T CP7 core$ 'nhanced * M architect#re MM7 to s#pport .inC', 'PAC 32 and Lin#/$ ,nstr#ction cache, data cache, )rite !#ffer and Ph%sical address T*G *M to red#ce the effect of main memor% !and)idth and latenc% on Performance$ * M@20T CP7 core s#pports the * M de!#g *rchitect#re$ ,nternal *d(anced Microcontroller 8#s *rchitect#re 0*M8*2 0*M8*2$0, *984*P82$ SYSTEM MANAGER Little48ig 'ndean s#pport$ S#pport 1ast !#s mode and *s%nchrono#s !#s mode$ *ddress spaceC :2;M !%tes for each !an" 0total :G !%tes2$ S#pports programma!le ;4:?432&!it data !#s )idth for each !an"$ 1i/ed !an" start address from !an" 0 to !an" ?$ Programma!le !an" start address and !an" si+e for !an" E$ 'ight memor% !an"sC Si/ memor% !an"s for AM, S *M, and others$ T)o memor% !an"s for AM4S *M4S%nchrono#s D *M$ Complete Programma!le access c%cles for all memor% !an"s$

 S#pports e/ternal )ait signals to e/pand the !#s c%cle$ S#pports self&refresh mode in SD *M for po)er do)n$ S#pports (ario#s t%pes of AM for !ooting 0=A 4=*=D 1lash, ''P AM, and others2$ NAND F)-/0 B**1 L*-2(' S#pports !ooting from =*=D flash memor%$ 4B8 internal !#ffer for !ooting$ S#pports storage memor% for =*=D flash memor% after !ooting$ S#pports *d(anced =*=D flash C-+0( M(.*'3 ?4&)a% set&associati(e cache )ith ,&Cache 0:?B82 and D&Cache 0:?B82$ ;)ords length per line )ith one (alid !it and t)o dirt% !its per line$ Pse#do random or ro#nd ro!in replacement algorithm$ .rite&thro#gh or )rite&!ac" cache operation to #pdate the main memor%$ The )rite !#ffer can hold :? )ords of data and fo#r addresses$ CLOCK 4 POWER MANAGER An&chip MPLL and 7PLLC 7PLL generates the cloc" to operate 7S8 9ost4De(ice$ MPLL generates the cloc" to operate MC7 at ma/im#m 400M9+ G :$3D$ Cloc" can !e fed selecti(el% to each f#nction !loc" !% soft)are$ P*5(' .*2(C =ormal, Slo), ,dle, and Sleep mode o N*'.-) .*2(C =ormal operating mode o S)*5 .*2(C Lo) fre-#enc% cloc" )itho#t PLL o I2)( .*2(C The cloc" for onl% CP7 is stopped$

o S)((6 .*2(C The Core po)er incl#ding all peripherals is sh#t do)n$ .o"en #p !% ',=TH:<C0I or TC alarm interr#pt from Sleep mode INTERRUPT CONTROLLER ?0 ,nterr#pt so#rces 0Ane .atch dog timer, < timers, @ 7* Ts, 24 e/ternal interr#pts, 4 DM*, 2 TC, 2 *DC, : ,,C, 2 SP,, : SD,, 2 7S8, : LCD, : 8atter% 1a#lt, : =*=D and 2 Camera2, : *C@E Le(el4'dge mode on e/ternal interr#pt so#rce Programma!le polarit% of edge and le(el S#pports 1ast ,nterr#pt re-#est 01,J2 for (er% #rgent interr#pt re-#est TIMER WITH PULSE WIDTH MODULATION (PWM) 4&ch :?&!it Timer )ith P.M 4 :&ch :?&!it internal timer )ith DM*&!ased or interr#pt&!ased operation Programma!le d#t% c%cle, fre-#enc%, and polarit% Dead&+one generation S#pports e/ternal cloc" so#rces RTC (REAL TIME CLOCK) 1#ll cloc" feat#reC millisecond, second, min#te, ho#r, date, da%, month, and %ear 32$E?; B9+ operation *larm interr#pt Time tic" interr#pt GENERAL PURPOSE INPUT/OUTPUT PORTS 24 e/ternal interr#pt ports :30 M#ltiple/ed inp#t4o#tp#t ports DMA CONTROLLER

 4&ch DM* controller S#pports memor% to memor%, ,A to memor%, memor% to ,A, and ,A to ,A transfers 8#rst transfer mode to enhance the transfer rate LCD CONTROLLER STN LCD DISPLAYS FEATURE S#pports 3 t%pes of ST= LCD panelsC 4&!it d#al scan, 4&!it single scan, ;&!it single scan displa% t%pe S#pports monochrome mode, 4 gra% le(els, :? gra% le(els, 2<? colors and 40@? colors for ST= LCD S#pports m#ltiple screen si+e o T%pical act#al screen si+eC ?40/4;0, 320/240, :?0/:?0, and others$ o Ma/im#m frame !#ffer si+e is 4 M!%tes$ o Ma/im#m (irt#al screen si+e in 2<? color o modeC 40@?/:024, 204;/204;, :024/40@? and others TFT(THIN FILM TRANSISTOR) COLOR DISPLAYS FEATURE S#pports :, 2, 4 or ; 8PP 0!it&per&pi/el2 palette color displa%s for color T1T S#pports :?, 24 8PP non&palette tr#e&color displa%s for color T1T S#pports ma/im#m :?M color T1T at 24 8PP mode LPC3?00 Timing controller em!edded for LTS3<0J:&PD:420S*MS7=G 3$<K Portrait 4 2<?Bcolor4 eflecti(e a&Si T1T LCD2 LCC3?00 Timing controller em!edded for LTS3<0J:&P':420S*MS7=G 3$<K Portrait 4 2<?Bcolor4Transflecti(e a&Si T1T LCD2 S#pports m#ltiple screen si+e o T%pical act#al screen si+eC ?40/4;0, 320/240, :?0/:?0, and others$ o Ma/im#m frame !#ffer si+e is 4M!%tes$

o Ma/im#m (irt#al screen si+e in ?4B color o modeC 204;/:024, and others UART 3&channel 7* T )ith DM*&!ased or interr#pt !ased operation S#pports <&!it, ?&!it, E&!it, or ;&!it serial data transmit4recei(e 0T/4 /2 S#pports e/ternal cloc"s for the 7* T operation 07'LTCLB2 Programma!le !a#d rate S#pports ,rD* :$0 Loop!ac" mode for testing 'ach channel has internal ?4&!%te T/ 1,1A and ?4&!%te / 1,1A$ A/D CONVERTER 4 TOUCH SCREEN INTERFACE ;&ch m#ltiple/ed *DC Ma/$ <00BSPS and :0&!it esol#tion ,nternal 1'T for direct To#ch screen interface WATCHDOG TIMER :?&!it .atchdog Timer ,nterr#pt re-#est or s%stem reset at time&o#t IIC7BUS INTERFACE :&ch M#lti&Master ,,C&8#s Serial, ;&!it oriented and !i&directional data transfers can !e made at #p to :00 B!it4s in Standard mode or #p to 400 B!it4s in 1ast mode$ IIS7BUS INTERFACE :&ch ,,S&!#s for a#dio interface )ith DM*&!ased operation Serial, ;&4:?&!it per channel data transfers

 :2; 8%tes 0?4&8%te 6 ?4&8%te2 1,1A for T/4 / S#pports ,,S format and MS8&j#stified data format AC89 AUDIO7CODEC INTERFACE S#pport :?&!it samples :&ch stereo PCM inp#ts4 :&ch stereo PCM o#tp#ts :&ch M,C inp#t USB HOST 2&port 7S8 9ost Complies )ith A9C, e($ :$0 Compati!le )ith 7S8 Specification (ersion :$: USB DEVICE :&port 7S8 De(ice < 'ndpoints for 7S8 De(ice Compati!le )ith 7S8 Specification (ersion :$: SD HOST INTERFACE =ormal, ,nterr#pt and DM* data transfer mode 0!%te, half )ord, )ord transfer2 DM* !#rst4 access s#pport 0onl% )ord transfer2 Compati!le )ith SD Memor% Card Protocol (ersion :$0 Compati!le )ith SD,A Card Protocol (ersion :$0 ?4 8%tes 1,1A for T/4 / Compati!le )ith M#ltimedia Card Protocol (ersion 2$:: SPI INTERFACE Compati!le )ith 2&ch Serial Peripheral ,nterface Protocol (ersion 2$:: 2/; !its Shift register for T/4 /

 DM*&!ased or interr#pt&!ased operation CAMERA INTERFACE ,T7& 8T ?0:4?<? ;&!it mode s#pport DM, 0Digital Moom ,n2 capa!ilit% Programma!le polarit% of (ideo s%nc signals Ma/$ 40@? / 40@? pi/els inp#t s#pport 0204; / 204; pi/el inp#t s#pport for scaling2 ,mage mirror and rotation 0L&a/is mirror, N&a/is mirror, and :;0O rotation2 Camera o#tp#t format 0 G8 :?424&!it and NC!Cr 4C2C044C2C2 format2 O6('-1$:% V*)1-%( R-:%( CoreC :$20D for 300M9+ :$30D for 400M9+ Memor%C :$;D4 2$<D43$0D43$3D ,4AC 3$3D O6('-1$:% F'(;&(:+3 1cl" 7p to 400M9+ 9cl" 7p to :3?M9+ Pcl" 7p to ?;M9+ P-+,-%( 2;@&18G*

ARM 4 ITS ARCHITECTURE:

ARM H$/1*'3 The ARM 0A+*': RISC M-+0$:(2 architect#re is de(eloped at *corn Comp#ter Limited of Cam!ridge, 'ngland !et)een:@;3&:@;<$ * M Limited fo#nded in :@@0$ ARM !ecame as the A2<-:+(2 RISC M-+0$:( is a 32& !it ,SC processor architect#re that is )idel% #sed in em!edded designs$ ARM cores licensed to semicond#ctor partners )ho fa!ricate and sell to their c#stomers$ * M does not fa!ricate silicon itself 8eca#se of their po)er sa(ing feat#res, * M CP7s are dominant in the mo!ile electronics mar"et, )here lo) po)er cons#mption is a critical design goal$ *s of 200E, a!o#t @; percent of the more than a !illion mo!ile phones sold each %ear #se at least one * M CP7$ Toda%, the * M famil% acco#nts for appro/imatel% E<P of all em!edded 32&!it ,SC CP7s ma"ing it the most )idel% #sed 32&!it architect#re$

* M CP7s are fo#nd in most corners of cons#mer electronics, from porta!le de(ices 0PD*s, mo!ile phones, iPods and other digital media and m#sic pla%ers, handheld gaming #nits, and calc#lators2 to comp#ter peripherals 0hard dri(es, des"top ro#ters2$ * M does not man#fact#re the CP7 itself, !#t licenses it to other man#fact#rers to integrate them into their o)n s%stem$

ARM -'+0$1(+1&'( RISC: ,SC, or Reduced Instruction Set Computer is a t%pe of microprocessor architect#re that #tili+es a small, highl%&optimi+ed set of instr#ctions, rather than a more speciali+ed set of instr#ctions often fo#nd in other t%pes of architect#res$ H$/1*'3: The first ,SC projects came from ,8M, Stanford, and 7C&8er"ele% in the late E0s and earl% ;0s$ The ,8M ;0:, Stanford M,PS, and 8er"ele% ,SC : and 2 )ere all designed )ith a similar philosoph% )hich has !ecome "no)n as ,SC$ Certain design feat#res ha(e !een characteristic of most ,SC processorsC

One cycle execution time: ,SC processors ha(e a CP, 0cloc" per instr#ction2 of one c%cle$ This is d#e to the optimi+ation of each instr#ction on the CP7 and a techni-#e called Q

Pipelining : a techni-#e that allo)s for sim#ltaneo#s e/ec#tion of parts, or

stages, of instr#ctions to more efficientl% process instr#ctionsQ

Large number of registers : the ,SC design philosoph% generall% incorporates a larger n#m!er of registers to pre(ent in large amo#nts of interactions )ith memor%

C,SC Price4Performance Strategies PriceC mo(e comple/it% from soft)are to hard)are$ PerformanceC ma"e tradeoffs in fa(or of decreased code si+e, at the e/pense of a higher CP,$ Design Decisions

,SC

PriceC mo(e comple/it% from hard)are to soft)are PerformanceC ma"e tradeoffs in fa(or of a lo)er CP,, at the e/pense of increased code si+e$

'/ec#tion of instr#ctions ta"es man% c%cles Design r#les are simple th#s core operates at higher cloc" fre-#encies Memor%&to&memor% addressing modes$

Simple, single&c%cle instr#ctions that perform onl% !asic f#nctions$ *ssem!ler instr#ctions correspond to microcode instr#ctions on a C,SC machine$ Design r#les are more comple/ and

* microcode control #nit$ Spend fe)er transistors on registers$

operates at lo)er cloc" fre-#encies Simple addressing modes that allo) onl% LA*D and STA ' to access memor%$ *ll operations are register& to&register$

Direct e/ec#tion control #nit$ Spend more transistors on m#ltiple !an"s of registers$ 7se pipelined e/ec#tion to lo)er CP,$

8ased #pon ,SC *rchitect#re )ith enhancements to meet re-#irements of em!edded applications * M is ha(ing :$ * large #niform register file 2$ Load&store architect#re ,)here data processing operations operate on register contents onl% 3$ 7niform and fi/ed length instr#ctions 4$ 32 &!it processor <$ ,nstr#ctions are 32&!it long ?$ Good Speed4Po)er Cons#mption atio E$ 9igh Code Densit% H-'<-'2 -'+0$1(+1&'( has separate data and instr#ction !#sses, allo)ing transfers to !e performed sim#ltaneo#sl% on !oth !#sses$ Greater amo#nt of instr#ction parallelism is possi!le in this architect#re$ Most DSPs #se 9ar(ard architect#re for streaming data$ The onl% difference in 9ar(ard architect#re to that of V*:7 N(&.-:: -'+0$1(+1&'( is that the program and data memories are

separat(2 -:2 &/( 603/$+-))3 /(6-'-1( 1'-:/.$//$*: 6-10/ . E:-=)(/ 10( .-+0$:( 1* 1'-:/>(' $:/1'&+1$*:/ -:2 2-1- /$.&)1-:(*&/)3 (:0-:+(/ 6('>*'.-:+(. H-'<-'2 -'+0$1(+1&'( $/ .*'( +*..*:)3 &/(2 $: /6(+$-)$?(2 .$+'*6'*+(//*'/ >*' '(-)71$.( -:2 (.=(22(2 -66)$+-1$*:. H*5(<('@ *:)3 10( (-')3 DSP +0$6/ &/( 10( H-'<-'2 -'+0$1(+1&'( =(+-&/( *> 10( +*/1. T0( %'(-1(/1 2$/-2<-:1-%( *> 10( H-'<-'2 -'+0$1(+1&'( $/ 50$+0 :((2/ 15$+( -/ .-:3 -22'(// -:2 2-1- 6$:/ *: 10( +0$6/ V*:7N(&.-:: -'+0$1(+1&'( )ill store program and data in the same memor% area )ith a single !#s$ So this !#s onl% is #sed for !oth data transfers and instr#ction fetches, and therefore data transfers and instr#ction fetches m#st !e sched#led & the% cannot !e performed at the same time$ Most of the general& p#rpose microprocessors li"e Motorola ?;000 and ,ntel ;0/;? #ses this sort of architect#re$ ,t is simple in hard)are implementation, !#t the data and program are re-#ired to share a single !#s$ ARM P'*+(//*' C*'(:

The fig#re sho)s the * M core dataflo) model$ ,n )hich the * M core as f#nctional #nits connected !% data !#ses$ *nd the arro)s represent the flo) of data, the lines represent the !#ses, and !o/es represent either an operation #nit or a

storage area$ The fig#re sho)s not onl% the flo) of data !#t also the a!stract components that ma"e #p an * M core$ 1igC * M core dataflo) model

,n the a!o(e fig#re the D-1- enters the processor core thro#gh the Data !#s$ The data ma% !e an instr#ction to e/ec#te or a data item$ This * M core represents the V*: N(&.-:: implementation of the * M data items and

instr#ctions share the same !#s$ ,n contrast, 9ar(ard implementations of the * M #se t)o different !#ses$ The $:/1'&+1$*: 2(+*2(' translates instr#ctions !efore the% are e/ec#ted$ 'ach instr#ction e/ec#ted !elongs to a partic#lar instr#ction set$ The * M processor, li"e all ,SC processors, #ses load-store architecture. This means it has t)o instr#ction t%pes for transferring data in and o#t of the processorC load instr#ctions cop% data from memor% to registers in the core, and con(ersel% the store instr#ctions cop% data from registers to memor%$ There are no data processing instr#ctions that directl% manip#late data in memor%$ Th#s, data processing is carried o#t solel% in registers$ Data items are placed in the '(%$/1(' >$)( a storage !an" made #p of 32&!it registers$ Since the * M core is a 32& !it processor, most instr#ctions treat the registers as holding signed or #nsigned 32&!it (al#es$ The /$%: (A1(:2 hard)are con(erts signed ;&!it and :?&!it n#m!ers to 32& !it (al#es as the% are read from memor% and placed in a register$ The *L7 0arithmetic logic #nit2 or M*C 0m#ltipl% R acc#m#late #nit2 ta"es the register (al#es Rn and Rm from the * and 8 !#ses and comp#tes a res#lt$ Data processing instr#ctions )rite the res#lt in Rd directl% to the register file$ Load and store instr#ctions #se the *L7 to generate an address to !e held in the address register and !roadcast on the *ddress !#s$ Ane important feat#re of the * M is that register Rm alternati(el% can !e preprocessed in the !arrel shifter !efore it enters the *L7$ Together the !arrel shifter and *L7 can calc#late a )ide range of e/pressions and addresses$ *fter passing thro#gh the f#nctional #nits, the res#lt in Rd is )ritten !ac" to the register file #sing the Result !#s$ 1or load and store instr#ctions the incremented #pdates the address register !efore the core reads or )rites the ne/t register (al#e from or to the ne/t se-#ential memor% location$ The processor

contin#es e/ec#ting instr#ctions #ntil an e/ception or interr#pt changes the normal e/ec#tion flo)$ BARM B&/ T(+0:*)*%3: 'm!edded s%stems #se different !#s technologies$ Most common PC !#s technolog% is the Peripheral Component ,nterconnect 0PC,2 !#s .hich connects de(ices s#ch as (ideo card and dis" controllers to the L ;? processor !#ses$ This t%pe of technolog% is called '/ternal or off chip !#s technolog%$ 'm!edded de(ices #se an on&chip !#s that is internal to the chip and allo)s different peripheral de(ices to !e inter connected )ith an * M core$ There are t)o different t%pes of de(ices connected to the !#s :$ 8#s Master 2$ 8#s Sla(e

:$ B&/ M-/1(': * logical de(ice capa!le of initiating a data transfer )ith another de(ice across the same !#s 0* M processor core is a !#s Master2$ 2$ B&/ S)-<( : * logical de(ice capa!le onl% of responding to a transfer re-#est from a !#s master de(ice 0 Peripherals are !#s sla(es 2 Generall% a 8#s has t)o architect#re le(els P03/$+-) )(<(': .hich co(ers electrical characteristics an !#s )idth 0:?, 32, ?4 !#s2$ P'*1*+*) )(<(): )hich deals )ith protocol =AT'C & * M is primaril% a design compan%$ ,t seldom implements the electrical characteristics of the !#s, !#t it ro#tinel% specifies the !#s protocol AMBA (A2<-:+(2 M$+'*+*:1'*))(' B&/ A'+0$1(+1&'() B&/ 6'*1*+*):

*M8* 8#s )as introd#ced in :@@? and has !een )idel% adopted as the An Chip !#s architect#re #sed for * M processors$ The first *M8* !#ses )ere :$ * M S%stem 8#s 0 *S8 2 2$ * M Peripheral 8#s 0 *P8 2 Later * M introd#ced another !#s design called the * M 9igh performance 8#s 0*982 7sing *M8* i$ Peripheral designers can re#se the same design on m#ltiple projects ii$ * Peripheral can simpl% !e !olted on the An Chip !#s )itho#t ha(ing to redesign an interface for different processor architect#re$ This pl#g&and&pla% interface for hard)are de(elopers impro(es a(aila!ilit% and time to mar"et$ *98 pro(ides higher data thro#ghp#t than *S8 !eca#se it is !ased on centrali+ed m#ltiple/ed !#s scheme rather than the *S8 !idirectional !#s design$ This change allo)s the *98 !#s to r#n at )idths of ?4 !its and :2; !its * M introd#ced t)o (ariations on the *98 !#s :$ M#lti&la%er *98 2$ *98&Lite ,n contrast to the original *98, )hich allo)s a single !#s master to !e acti(e on the !#s at an% time, the M#lti&la%er *98 !#s allo)s m#ltiple acti(e !#s masters$ *98& Lite is a s#!set of the *98 !#s and it is limited to a single !#s master$ This !#s )as de(eloped for designs that do not re-#ire the f#ll feat#res of the standard *98 !#s$ *98 and M#ltiple&la%er *98 s#pport the same protocol for master and sla(e !#t ha(e different interconnects$ The ne) interconnects in M#lti&la%er *98

are good for s%stems )ith m#ltiple processors$ The% permit operations to occ#r in parallel and allo) for higher thro#ghp#t rates$ ARCHITECTURE R(<$/$*:/: '(er% * M processor implementation e/ec#tes a specific instruction set architecture 0,S*2, altho#gh an ,S* re(ision ma% ha(e more than one processor implementation The ,S* has e(ol(ed to "eep #p )ith the demands of the em!edded mar"et$ This e(ol#tion has !een caref#ll% managed !% * M, so that code )ritten to e/ec#te on an earlier architect#re re(ision )ill also e/ec#te on a later re(ision of the architect#re$ The nomenclat#re identifies indi(id#al processors and pro(ides !asic information a!o#t the feat#re set$ NOMENCLATUREC * M #ses the nomenclat#re sho)n !elo) is to descri!e the processor implementations$ The letters and n#m!ers after the )ord S* MK indicate the feat#res a processor ma% ha(e$ ARM C A DC 3 DC ? DC T DC D DC M DC I DC E DCE DC F DC 7S D / T famil% % T memor% management 4 protection #nit + T cache T T Th#m! :? !it decoder

D T UT*G de!#g M T fast m#ltiplier , T 'm!edded ,C' macro cell ' T enhanced instr#ction 0ass#mes TDM,2 U T Ua+elle 1 T (ector floating&point #nit S T s%nthesi+a!le (ersion

*ll * M cores after the * METDM, incl#de the TDM, feat#res e(en tho#gh the% ma% not incl#de those letters after the S * M K la!el

The processor famil% is a gro#p of processor implementations that share the same hard)are characteristics$ 1or e/ample, the * METDM,, * ME40T, and * ME20T all share the same famil% characteristics and !elong to the * ME famil%

JTAG is descri!ed !% ,''' ::4@$: standard Test *ccess Port and !o#ndar% scan architect#re$ ,t is a serial protocol #sed !% * M to send and recei(e de!#g information !et)een the processor core and test e-#ipment

Embedded ICE macro cell is the de!#g hard)are !#ilt into the processor that allo)s !rea"points and )atch points to !e set

Synthesizable means that the processor core is s#pplied as so#rce code that can !e compiled into a form easil% #sed !% 'D* tools

I:1'*2&+1$*: 1* ARM9TDMI +*'(

The * METDM, core is a 32&!it em!edded

,SC processor deli(ered as a hard

macro cell optimi+ed to pro(ide the !est com!ination of performance, po)er and area characteristics$ The * METDM, core ena!les s%stem designers to !#ild em!edded de(ices re-#iring small si+e, lo) po)er and high performance$ ARM9TDMI F(-1&'(/

324:?&!it ,SC architect#re 0* M (4T2 32&!it * M instr#ction set for ma/im#m performance and fle/i!ilit% :?&!it Th#m! instr#ction set for increased code densit% 7nified !#s interface, 32&!it data !#s carries !oth instr#ctions and data Three&stage pipeline 32&!it *L7 Der% small die si+e and lo) po)er cons#mption 1#ll% static operation Coprocessor interface '/tensi(e de!#g facilities 0'm!edded ,C' de!#g #nit accessi!le (ia UT*G interface #nit2

B(:(>$1/

Generic la%o#t can !e ported to specific process technologies 7nified memor% !#s simplifies SoC integration process * M and Th#m! instr#ctions sets can !e mi/ed )ith minimal o(erhead to s#pport application re-#irements for speed and code densit% Code )ritten for * METDM,&S is !inar%&compati!le )ith other mem!ers of the * ME 1amil% and for)ards compati!le )ith * M@, * M@' and * M:0 families, th#s it>s -#ite eas% to port %o#r design to higher le(el

microcontroller or microprocessor

Static design and lo)er po)er cons#mption are essential for !atter% &po)ered de(ices ,nstr#ction set can !e e/tended for specific re-#irements #sing coprocessors 'm!edded ,C'& T and optional 'TM #nits ena!le e/tensi(e, real&time de!#g facilities

ARM9TDMI M$+'*+*:1'*))('/: :$ *(aila!le * METDM, Microcontrollers 2$ *nalog De(ices *D#C E/// 3$ *tmel *T@:S*ME 4$ 1ree scale M*CE:00 <$ =LP4Philips LPC2000 ?$ ST ST E:0 E$ Te/as ,nstr#ments TMS4E0

ARM R(%$/1(' >$)( 4 .*2(/ *> *6('-1$*: R(%$/1('/: General P#rpose registers hold either data or address and the% are identified )ith the letter r prefi/ed to the register n#m!er$ *ll registers are of 32 !its$

ARM 0-/ 9 '(%$/1('/ $: 1*1-)@ -)) *> 50$+0 -'( !7=$1/ )*:%. : dedicated program co#nter : dedicated c#rrent program stat#s register < dedicated sa(ed program stat#s registers 30 general p#rpose registers 9o)e(er these are arranged into se(eral !an"s, )ith the accessi!le !an" !eing go(erned !% the processor mode$ 'ach mode can access a partic#lar set of r0&r:2 registers, a partic#lar r:3 0the stac" pointer2 and r:4 0lin" register2, r:< 0the program co#nter2, cpsr 0the c#rrent program stat#s register2 *nd pri(ileged modes can also access a partic#lar spsr 0sa(ed program stat#s register2$ ,n #ser mode :? data registers and 2 stat#s registers are (isi!le$ Depending #pon conte/t, register r:3 and r:4 can also !e #sed as General P#rpose egisters$ ,n * M state the registers r0 to r:3 are Orthogonal that means & an% instr#ction )hich #se r0 can as )ell !e #sed )ith an% other General P#rpose egister 0r:&r:32$ The * M processor has three registers assigned to a partic#lar tas" or special f#nctionC r:3, r:4 and r:<$ The% are fre-#entl% gi(en different la!els to differentiate them from the other registers$

egister r ! is traditionall% #sed as the stac" pointer 0sp2 and stores the head of the stac" in the c#rrent processor mode

egister r " is called the lin" register 0lr # and is )here the core p#ts the ret#rn address )hene(er it calls a s#!ro#tine$

egister r $ is the program co#nter 0 pc 2 and contains the address of the ne/t instr#ction to !e fetched !% the processor

The register file contains all the registers a(aila!le to a programmer$ .hich

registers are (isi!le to the programmer depend #pon the c#rrent mode of the processor$ C&''(:1 6'*%'-. /1-1&/ '(%$/1('/: The * M core #ses the cpsr to monitor and control internal operations$ The cpsr is a dedicated 32&!it register and resides in the register file$ The follo)ing fig#re sho)s the generic program stat#s register$

1igC Program Stat#s egister The control !it field contains the processor mode, state, and interr#pt mas" !its 0,,12$ eser(ed !its are allocated for the f#t#re (ersions p#rpose$ The =, M, C and D are condition code flags )ill !e changed as a res#lt of arithmetic and logical operations in the processor =C =egati(e$ MC Mero$ CC Carr%$ DC A(erflo) The , and 1 !its are the interr#pt disa!le !its The M0, M:, M2, M3 and M4 !its are the mode !its

P'*+(//*' M*2(/: Processor modes determine )hich register are acti(e, and access rights to CPS register itself$ 'ach processor mode is either pri(ileged or =on&pri(ileged$ * M has se(en modes$ These E modes are di(ided into t)o t%pes$

P'$<$)(%(2: 7 1#ll read&)rite access to the CPS $ 7nder this )e are ha(ing A=*'1@ F-/1 $:1(''&61 '(;&(/1@ I:1(''&61 '(;&(/1@ S&6('<$/*'@ S3/1(. -:2 U:2(>$:(2 A=*'1 (F#FFF): .hen there is a failed attempt to access memor% F-/1 $:1(''&61 R(;&(/1 (FIG (F###F)) 4 $:1(''&61 '(;&(/1 (F##F#): Correspond to interr#pt le(els a(aila!le on * M S&6('<$/*' .*2( (F##FF)C State after reset and generall% the mode in )hich AS "ernel e/ec#tes S3/1(. .*2( (FFFFF): Special (ersion of #ser mode that allo)s f#ll read&)rite access of CPS U:2(>$:(2 (FF#FF)C .hen processor enco#nters an #ndefined instr#ction N*:76'$<$)(%(2:7 Anl% read access to the control filed of CPS access to the condition flags$ U/(' (F####): 7ser mode is #ser for programs and applications$ *nd this the !#t read&)rite

normal mode B-:,(2 R(%$/1('/: egister file contains in all 3E registers$ 20 registers are hidden from program at different times$ These registers are called !an"ed registers$ 8an"ed registers are a(aila!le onl% )hen the processor is in a partic#lar mode$ Processor modes 0other than s%stem mode2 ha(e a set of associated !an"ed registers that are s#!set of :? register

egister 8an"

Indicates that the normal register used by User or System mode has been replaced by an alternative register specific to the exception mode

SPSR: 'ach pri(ileged mode 0e/cept s%stem mode2 has associated )ith it a Sa(e Program

Stat#s

egister, or SPS $ This SPS

is #sed to sa(e the state of CPS

0C#rrent

program stat#s egister2 )hen the pri(ileged mode is entered in order that the #ser state can !e f#ll% restored )hen the #ser processor is res#med M*2( C0-:%$:%: Mode changes !% )riting directl% to CPS responds to e/ception or interr#pt$ To ret#rn to #ser mode a special ret#rn instr#ction is #sed that instr#cts the core to restore the original CPS and !an"ed registers$ ARM I:/1'&+1$*: S(1 ,n this chapter )e are going to disc#ss a!o#t the most commonl% #sed ,nstr#ction Set of * M$ Different * M architect#res re(isions s#pport different instr#ctions$ 9o)e(er ne) re(isions #s#all% add instr#ctions and remain !ac")ardl% compati!le$ The follo)ing sho)s the t%pe of instr#ctions that * M s#pport$ ,$ Data Processing ,nstr#ctions ,,$ 8ranch ,nstr#ctions ,,,$Load&store ,nstr#ctions ,D$ Soft)are ,nterr#pt ,nstr#ction D$ Program Stat#s egister ,nstr#ctions or !% hard)are )hen the processor

I. D-1- P'*+(//$:% I:/1'&+1$*:/:7 The data processing instr#ctions manip#late data )ithin registers$ Most data processing instr#ctions can process one of their operands #sing the !arrel shifter$ ,f

)e #se the S s#ffi/ on a data processing instr#ction, then it #pdates the flags in the cpsr. Mo(e and logical operations #pdate the carr% flag C, negati(e flag =, and Mero flag M$ The carr% flag is set from the res#lt of the !arrel shift as the last !it shifted o#t$ The = flag is set to !it 3: of the res#lt$ The M flag is set if the res#lt is +ero$ The follo)ing instr#ctions are Data processing instr#ctions$ $). M*<( $:/1'&+1$*:/: This instr#ction is #sed to mo(e the content of one register to another register$ The !elo) instr#ctions are the Mo(e instr#ctions MOV: mo(e a 32&!it (al#e into a register dV S MOVN: mo(e the =AT of the 32 !it (al#e into a register dV W S $$). B-''() S0$>1(' :7 * #ni-#e and po)erf#l feat#re of * M processor is a!ilit% to shift the 32&!it !inar% pattern in one of the so#rce registers left or right !% a specific n#m!er of positions !efore it enters the *L7$ This is done !% #sing the 8arrel shifter$ This preprocessing or shift occ#rs )ithin the c%cle time of the instr#ction$ The fi(e different shift operations that )e can #se )ithin the !arrel shifter gi(en !elo)$ LSLC logical shift left LS C logical shift right *S C arithmetic right shift A C rotate right LC rotate right e/tended $$$. A'$10.(1$+ I:/1'&+1$*:/: The arithmetic instr#ctions implement and s#!traction of 32&!it signed and #nsigned (al#es$ Some of the instr#ctions of *rithmetic instr#ctions are gi(en !elo)$ *DDC add t)o 32&!it (al#es$

*DCC add t)o 32&!it (al#es and carr% S78C s#!tract t)o 32&!it (al#es S8CC s#!tract )ith carr% of t)o 32&!it (al#es S8C re(erse s#!tract of t)o 32&!it (al#es SCC re(erse s#!tract )ith carr% of t)o 32&!it (al#es $<. L*%$+-) I:/1'&+1$*:/: Performs the logical operations on t)o so#rce registers *=DC logical !it)ise *=D of t)o 32&!it (al#es A C logical !it)ise A of t)o 32&!it (al#es 'A C logical e/cl#si(e A of t)o 32&!it (al#es$ 8,CC Logical !it clear 0*=D =AT2 <. C*.6-'$/*: I:/1'&+1$*:/: The comparison instr#ctions are #sed to compare or test a register )ith a 32 !it (al#e$ The% #pdate the cpsr flag !its 0=, M, C, and D2 according to the res#lt, !#t do not affect other registers$ *fter the !its ha(e !een set, the information can then !e #sed to change program flo) !% #sing conditional e/ec#tion$ .e do not need to appl% the S s#ffi/ for comparison instr#ctions to #pdate the flag$ The follo)ing instr#ctions are !elong Comparison instr#ctions CMP 0compare2 C flags set as a res#lt of :& 2 :F 2 CM= 0compare negated2 C flags set as a res#lt of :6 2 TST 0test for e-#alit% of t)o 32&!it (al#es2 C flags set as a res#lt of T'J 0test for e-#alit% of t)o 32&!it (al#es2 C flags set as a res#lt of :X 2 <$. M&)1$6)3 I:/1'&+1$*:/: The m#ltipl% instr#ctions m#ltipl% the content of a pair of registers and, depending #pon the instr#ction, acc#m#late the res#lts in )ith another register$ The long m#ltiplies acc#m#late onto a pair of registers representing a ?4 !it (al#e$ The final res#lt is placed in a destination register or a

pair of registers$ M7LC m#ltipl% ML*C m#ltipl% and acc#m#late Long M#ltipl% ,nstr#ctionsC 0Prod#ce ?4 !it (al#es, res#lt )ill !e placed in t)o 32 !it (al#es2 SML*LC signed m#ltipl% acc#m#late long SM7LLC signed m#ltipl% acc#m#late 7ML*LC #nsigned m#ltipl% acc#m#late long 7M7LLC #nsigned m#ltipl% long II. B'-:+0 I:/1'&+1$*:/: 7 * !ranch instr#ction changes the flo) of e/ec#tion or is #sed to call a ro#tine$ This t%pe of instr#ction allo)s programs to ha(e s#!ro#tines, i%-then-else str#ct#res, and loops$ The change of e/ec#tion flo) forces the program co#nter pc to point to ne) address$ The !elo) sho)n instr#ctions are 8ranch instr#ctions$ 8C !ranch 8LC !ranch )ith lin" 8LC !ranch e/change 8LLC !ranch e/change )ith lin" III. L*-27/1*'( I:/1'&+1$*:/: 7 Load&store instr#ctions transfer data !et)een memor% and processor registers$ There are three t%pes of load&store instr#ctionsC i$ single register transferring ii$ M#ltiple register transfer iii$ S)ap

S$:%)( '(%$/1(' 1'-:/>(''$:%: 7 These instr#ctions are #sed for mo(ing a single data item in and o#t of a register$ The data t%pes s#pported are signed and #nsigned )ords 032&!it2, half&)ords 0:?&!it2, and !%tes$ The follo)ing instr#ctions are (ario#s load&store single&register transfer instr#ctions$ LD C load )ord into a register ST C sa(e !%te or )ord from a register LD 8C load !%te into a register ST 8C sa(e !%te from a register LD 9C load half&)ord into a register ST 9C sa(e half&)ord into a register LD S8C load signed !%te into a register LD S9C load signed half&)ord into a register M&)1$6)( '(%$/1(' 1'-:/>(': 7 Load&store m#ltiple instr#ctions can transfer m#ltiple registers !et)een memor% and the processor in a single instr#ction$ The transfer occ#rs from a !ase address register Rn pointing into memor%$ M#ltiple& register transfer instr#ctions are more efficient from single&register transfers for mo(ing !loc"s of data aro#nd memor% and sa(ing and restoring conte/t and stac"s$ ,f an interr#pt has !een raised, then it has no effect #ntil the load&store m#ltiple instr#ction is complete$ LDMC load m#ltiple registers STMC sa(e m#ltiple registers S5-6: 7 The s)ap instr#ction is a special case of a load&store instr#ction$ ,t s)aps the contents of memor% )ith the contents of a register$ This instr#ction is an atomic operation& it reads and )rites a location in the same !#s operation,

pre(enting an% other instr#ction from reading or )riting to that location #ntil it completes$ IV. S*>15-'( I:1(''&61 I:/1'&+1$*:: 7 * soft)are interr#pt instr#ction 0S&I# ca#ses a soft)are interr#pt e/ception, )hich pro(ides a mechanism for applications to call operating s%stem ro#tines$ The follo)ing instr#ction comes #nder soft)are interr#pt instr#ction$ S.,C soft)are interr#pt V. P'*%'-. S1-1&/ R(%$/1(' I:/1'&+1$*:/: 7 The * M instr#ction set pro(ides t)o instr#ctions to directl% control a program stat#s 0psr#$ M SC This instr#ction transfers the contents of either the cpsr or spsr into a register MS C This instr#ction transfers the content of a register into the cpsr or spsr Together the a!o(e t)o instr#ctions are #sed to read and )rite the cpsr or spsr

ARM8 -'+0$1(+1&'(
ARM8 is an * M architect#re 32&!it ,SC CP7 famil%$ .ith this design

generation, * M mo(ed from a (on =e#mann architect#re 0Princeton architect#re2 to a 9ar(ard architect#re )ith separate instr#ction and data !#sses 0and caches2, significantl% increasing its potential speed$ Most silicon chips integrating these cores )ill pac"age them as modified 9ar(ard architect#re chips, com!ining the t)o address !#sses on the other side of separated CP7 caches and tightl% co#pled memories$

There are t)o s#!families, implementing different * M architect#re (ersions$ C*:1(:1/ : Differences from * ME cores 2 * M@TDM, !ased cores 3 * M@' !ased cores D$>>('(:+(/ >'*. ARM9 +*'(/ Be% impro(ements o(er * ME cores, ena!led !% spending more transistors, incl#deC

Decreased heat prod#ction and lo)er o(erheating ris"$ Cloc" fre-#enc% impro(ements$ Shifting from a three stage pipeline to a fi(e stage one lets the cloc" speed !e appro/imatel% do#!led, on the same silicon fa!rication process$ C%cle co#nt impro(ements$ Man% #nmodified * ME !inaries )ere meas#red as ta"ing a!o#t 30P fe)er c%cles to e/ec#te on * M@ cores$ Be% impro(ements incl#de
o

1aster loads and storesQ man% instr#ctions no) cost j#st one c%cle$ This is helped !% !oth the modified 9ar(ard architect#re 0red#cing !#s and cache contention2 and the ne) pipeline stages$ '/posing pipeline interloc"s, ena!ling compiler optimi+ations to red#ce !loc"age !et)een stages$

*dditionall%, some * M@ cores incorporate Y'nhanced DSPY instr#ctions, s#ch as a m#ltipl%&acc#m#late, to s#pport more efficient implementations of digital signal processing algorithms$ S)itching to 9ar(ard architect#re entailed a non&#nified cache, so that instr#ction fetches do not e(ict data 0and (ice (ersa2$ * M@ cores ha(e separate data and address !#s signals, )hich chip designers #se in (ario#s )a%s$ ,n most cases the%

connect at least part of the address space in (on =e#mann st%le, #sed for !oth instr#ctions and data, #s#all% to an *98 interconnect connecting to a D *M interface and an '/ternal 8#s ,nterface #sa!le )ith =A h%!rids are no longer p#re 9ar(ard architect#re processors$ ARM8TDMI =-/(2 +*'(/ * M@TDM, is a s#ccessor to the pop#lar * METDM, core, and is also !ased on the * M(4T architect#re$ Cores !ased on it s#pport !oth 32&!it * M and :?&!it Th#m! instr#ction sets incl#deC

flash memor%$ S#ch

* M@20T )ith :?B8 each of ,4D cache and an MM7 * M@22T )ith ;B8 each of ,4D cache and an MM7 * M@40T )ith cache and a Memor% Protection 7nit 0MP72

A=*&1 10( ARM8!#T: The * M@20T processor is a mem!er of the * M@TDM, famil% of general& p#rpose microprocessors, )hich incl#desC

* M@TDM, 0core2 * M@40T 0core pl#s cache and protection #nit2 * M@20T 0core pl#s cache and MM72$

The * M@TDM, processor core is a 9ar(ard architect#re de(ice implemented #sing a fi(e&stage pipeline consisting of 1etch, Decode, '/ec#te, Memor%, and .rite stages$ ,t can !e pro(ided as a standalone core that can !e em!edded into more comple/ de(ices$ The standalone core has a simple !#s interface that allo)s %o# to design %o#r o)n caches and memor% s%stems aro#nd it$ The * M@TDM, famil% of microprocessors s#pports !oth the 32&!it * M and :?&!it Th#m! instr#ction sets, allo)ing %o# to trade off !et)een high performance and high code densit%$

The * M@20T processor is a 9ar(ard cache architect#re processor that is targeted at m#ltiprogrammer applications )here f#ll memor% management, high performance, and lo) po)er are all&important$ The separate instr#ction and data caches in this design are :?B8 each in si+e, )ith an ;&)ord line length$ The * M@20T processor implements an enhanced * M architect#re (4 MM7 to pro(ide translation and access permission chec"s for instr#ction and data addresses$ The * M@20T processor s#pports the * M de!#g architect#re and incl#des logic to assist in !oth hard)are and soft)are de!#g$ The * M@20T processor also incl#des s#pport for coprocessors, e/porting the instr#ction and data !#ses along )ith simple handsha"ing signals$ The * M@20T interface to the rest of the s%stem is o(er #nified address and data !#ses$ This interface ena!les implementation of either an Ad'anced (icrocontroller )us Architecture 0*M8*2 Ad'anced System )us 0*S82 or Ad'anced *i+h-per%ormance )us 0*982 !#s scheme either as a f#ll%&compliant *M8* !#s master, or as a sla(e for prod#ction test$ The * M@20T processor also has a Trac,in+ ICE mode )hich allo)s an approach similar to a con(entional ,C' mode of operation$ The * M@20T processor s#pports the addition of an Embedded Trace (acrocell 0'TM2 for real&time tracing of instr#ctions and data$ T0( ARM8!#TH: The * M@20T is a high&performance 32&!it com!ining an * M@TDM,Z processor core )ithC :$ :?B8 instr#ction and :?B8 data caches 2$ instr#ction and data (emory (ana+ement -nits 0MM7s2 3$ )rite !#ffer ,SC processor Macro cell

4$ an A()AZ 0*d(anced Microprocessor 8#s *rchitect#re2 !#s interface <$ *n Embedded Trace (acro cell 0'TM2 interface$ H$%0 6('>*'.-:+( The * M@20T pro(ides a high&performance processor sol#tion for open s%stems re-#iring f#ll (irt#al memor% management and sophisticated memor% protection$ *n enhanced * M[ architect#re (4 MM7 implementation pro(ides translation and access permission chec"s for instr#ction and data addresses$ The * M@20T high&performance processor sol#tion gi(es considera!le sa(ings in chip comple/it% and area, chip s%stem design, and po)er cons#mption$ C*.6-1$=)( 5$10 ARM9H -:2 S1'*:%7-'.I The * M@20T processor is :00P #ser code !inar% compati!le )ith * METDM,, and !ac")ards compati!le )ith the * ME Th#m![ 1amil% and the Strong * M processor families, gi(ing designers soft)are&compati!le processors )ith a range of price4performance points from ?0 M,PS to 2006M,PS$ S#pport for the * M architect#re toda% incl#desC :$ .indo)s C', S%m!ian AS, Lin#/, and J=L operating s%stems 2$ 406 eal Time Aperating S%stems 3$ co&sim#lation tools from leading 'D* (endors 4$ Dariet% of soft)are de(elopment tools$ A66)$+-1$*:/: :$ *pplications r#nning an Apen ASC - S%m!ian AS

- Lin#/, Palm AS - .inC' 2$ 9igh performance )ireless applicationsC - Smart phones - PD*s 3$ =et)or"ing applications 4$ Digital set top !o/es <$ ,maging ?$ *#tomoti(e control sol#tions E$ *#dio and (ideo encoding and decoding B(:(>$1/: :$ Designed specificall% for S%stem&on&Chip integration 2$ S#pports the Th#m! instr#ction set offering the same e/cellent code densit% as the * METDM, 3$ 9igh performance allo)s s%stem designers to integrate more f#nctionalit% into price and po)er&sensiti(e applications demanding more performance 4$ Cached processor )ith an eas% to #se lo)er fre-#enc% on&chip s%stem !#s interface$ ARM8!#T B)*+, 2$-%'-.:

ARM8!#T M-+'* +()):

The * M@20T macro cell is !ased on the * M@TDM, 9ar(ard architect#re processor core, )ith an efficient <&stage pipeline$ To red#ce the effect of main memor% !and)idth and latenc% on performance, the * M@20T incl#desC :$ instr#ction cache

2$ data cache 3$ MM7 4$ TL8s <$ )rite !#ffer ?$ Ph%sical address T*G *M$

C-+0(/ T)o :?B8 caches are implemented, one for instr#ctions, the other for data, !oth )ith an ;&)ord line si+e$ * 32&!it data !#s connects each cache to the * M@TDM, core allo)ing a 32&!it instr#ction to !e fetched and fed into the instr#ction Decode stage of the pipeline at the same time as a 32&!it data access for the Memor% stage of the pipeline$ C-+0( )*+,72*5: Cache loc"&do)n is pro(ided to allo) critical code se-#ences to !e loc"ed into the cache to ens#re predicta!ilit% for real&time code$ The cache replacement algorithm can !e selected !% the operating s%stem as either pse#do random or ro#nd&ro!in$ 8oth caches are ?4&)a% set associati(e$ Loc"&do)n operates on a per&set !asis$ W'$1( =&>>(' The * M@20T also incorporates a :?&entr% )rite !#ffer, to a(oid stalling the processor )hen )rites to e/ternal memor% are performed$ PATAG RAM The * M@20T implements P*T*G *M to perform )rite&!ac"s from the data cache$

The ph%sical address of all the lines held in the data cache is stored !% the P*T*G memor%, remo(ing the need for address translation )hen e(icting a line from the cache$ MMU/ The standard * M@20T implements an enhanced * M(4 MM7 to pro(ide translation and access$ Permission chec"s for the instr#ction and data address ports of the * M@TDM,$ T0( MMU >(-1&'(/ -'(: :$ standard * M(4 MM7 mapping si+es, domains, and access protection scheme 2$ mapping si+es are :M8 sections,?4B8 large pages, 4B8 small pages, and ne) :B8 tin% pages 3$ access permissions for sections 4$ access permissions for large pages and small pages can !e specified separatel% for each -#arter of the page 0these -#arters are called s#!pages2 <$ :? domains implemented in hard)are ?$ ?4&entr% instr#ction TL8 and ?4&entr% data TL8 E$ 9ard)are page ta!le )al"s$ ;$ o#nd&ro!in replacement algorithm 0also called c%clic2$

S3/1(. +*:1'*))(' The s%stem controller o(ersees the interaction !et)een the instr#ction and data caches and the 8#s ,nterface 7nit$ ,t controls internal ar!itration !et)een the !loc"s and stalls appropriate !loc"s )hen re-#ired$

The s%stem controller ar!itrates !et)een instr#ction and data access to sched#le single or sim#ltaneo#s re-#ests to the MM7s and the 8#s ,nterface 7nit$ The s%stem controller recei(es ac"no)ledgement from each reso#rce to allo) e/ec#tion to contin#e$ C*:1'*) +*6'*+(//*' (CPFJ) The CP:< allo)s config#ration of the caches, the )rite !#ffer, and other * M@20T options$ Se(eral registers )ithin CP:< are a(aila!le for program control, pro(iding access to feat#res s#ch asC :$ in(alidate )hole TL8 #sing CP:< 2$ in(alidate TL8 entr%, selected !% modified (irt#al address, #sing CP:< 3$ independent loc"&do)n of instr#ction TL8 and data TL8 #sing CP:< register :0 4$ !ig or little&endian operation <$ lo) po)er state ?$ memor% partitioning and protection E$ Page ta!le address cache and TL8 maintenance operations$

O6('-1$:% /3/1(.:
*n *6('-1$:% /3/1(. 0OS2 is soft)are, consisting of programs and data that r#ns on comp#ters and manages the comp#ter hard)are and pro(ides common ser(ices for efficient e/ec#tion of (ario#s application soft)are$ 1or hard)are f#nctions s#ch as inp#t and o#tp#t and memor% allocation, the operating s%stem acts as an intermediar% !et)een application programs and the comp#ter hard)are, altho#gh the application code is #s#all% e/ec#ted directl% !% the hard)are, !#t )ill fre-#entl% call the AS or !e interr#pted !% it$ Aperating s%stems are fo#nd on almost an% de(ice that contains a comp#ter\from cell#lar phones and (ideo game consoles to s#percomp#ters and )e! ser(ers$

K(':():
The ,ernel is a program that constit#tes the central core of a comp#ter operating s%stem$ ,t has complete control o(er e(er%thing that occ#rs in the s%stem$ * "ernel can !e contrasted )ith a shell 0s#ch as bash, csh or ,sh in 7ni/&li"e operating s%stems2, )hich is the o#termost part of an operating s%stem and a program that interacts )ith #ser commands$ The "ernel itself does not interact directl% )ith the #ser, !#t rather interacts )ith the shell and other programs as )ell as )ith the hard)are de(ices on the s%stem, incl#ding the processor 0also called the central processing #nit or CP72, memor% and dis" dri(es$ The "ernel is the first part of the operating s%stem to load into memor% d#ring bootin+ 0i$e$, s%stem start#p2, and it remains there for the entire d#ration of the comp#ter session !eca#se its ser(ices are re-#ired contin#o#sl%$ Th#s it is important for it to !e as small as possi!le )hile still pro(iding all the essential ser(ices needed !% the other parts of the operating s%stem and !% the (ario#s application programs$

8eca#se of its critical nat#re, the "ernel code is #s#all% loaded into a protected area of memor%, )hich pre(ents it from !eing o(er)ritten !% other, less fre-#entl% #sed parts of the operating s%stem or !% application programs$ The "ernel performs its tas"s, s#ch as e/ec#ting processes and handling interrupts, in ,ernel space, )hereas e(er%thing a #ser normall% does, s#ch as )riting te/t in a te/t editor or r#nning programs in a G7, 0graphical #ser interface2, is done in user space$ This separation is made in order to pre(ent #ser data and "ernel data from interfering )ith each other and there!% diminishing performance or ca#sing the s%stem to !ecome #nsta!le 0and possi!l% crashing2$ .hen a comp#ter crashes, it act#all% means the "ernel has crashed$ ,f onl% a single program has crashed !#t the rest of the s%stem remains in operation, then the "ernel itself has not crashed$ * crash is the sit#ation in )hich a program, either a #ser application or a part of the operating s%stem, stops performing its e/pected f#nction0s2 and responding to other parts of the s%stem$ The program might appear to the #ser to %reeze$ ,f s#ch program is a critical to the operation of the "ernel, the entire comp#ter co#ld stall or sh#t do)n$ The "ernel pro(ides !asic ser(ices for all other parts of the operating s%stem, t%picall% incl#ding memor% management, process management, file management and ,4A 0inp#t4o#tp#t2 management 0i$e$, accessing the peripheral de(ices2$ These ser(ices are re-#ested !% other parts of the operating s%stem or !% application programs thro#gh a specified set of program interfaces referred to as system calls$ Process management, possi!l% the most o!(io#s aspect of a "ernel to the #ser, is the part of the "ernel that ens#res that each process o!tains its t#rn to r#n on the processor and that the indi(id#al processes do not interfere )ith each other !% )riting to their areas of memor%$ * process, also referred to as a tas,, can !e defined as an e/ec#ting 0i$e$, r#nning2 instance of a program$

The contents of a "ernel (ar% considera!l% according to the operating s%stem, !#t the% t%picall% incl#de 0:2 a sched#ler, )hich determines ho) the (ario#s processes share the "ernel>s processing time 0incl#ding in )hat order2, 022 a s#per(isor, )hich grants #se of the comp#ter to each process )hen it is sched#led, 032 an interr#pt handler, )hich handles all re-#ests from the (ario#s hard)are de(ices 0s#ch as dis" dri(es and the "e%!oard2 that compete for the "ernel>s ser(ices and 042 a memor% manager, )hich allocates the s%stem>s address spaces 0i$e$, locations in memor%2 among all #sers of the "ernel>s ser(ices$ The "ernel sho#ld not !e conf#sed )ith the )I.S 08asic ,np#t4o#tp#t S%stem2$ The 8,AS is an independent program stored in a chip on the motherboard 0the main circ#it !oard of a comp#ter2 that is #sed d#ring the !ooting process for s#ch tas"s as initiali+ing the hard)are and loading the "ernel into memor%$ .hereas the 8,AS al)a%s remains in the comp#ter and is specific to its partic#lar hard)are, the "ernel can !e easil% replaced or #pgraded !% changing or #pgrading the operating s%stem or, in the case of Lin#/, !% adding a ne)er "ernel or modif%ing an e/isting "ernel$ Most "ernels ha(e !een de(eloped for a specific operating s%stem, and there is #s#all% onl% one (ersion a(aila!le for each operating s%stem$ 1or e/ample, the Microsoft .indo)s 2000 "ernel is the onl% "ernel for Microsoft .indo)s 2000 and the Microsoft .indo)s @; "ernel is the onl% "ernel for Microsoft .indo)s @;$ Lin#/ is far more fle/i!le in that there are n#mero#s (ersions of the Lin#/ "ernel, and each of these can !e modified in inn#mera!le )a%s !% an informed #ser$ * fe) "ernels ha(e !een designed )ith the goal of !eing s#ita!le for #se )ith an% operating s%stem$ The !est "no)n of these is the Mach "ernel, )hich )as de(eloped at Carnegie&Mellon 7ni(ersit% and is #sed in the Macintosh AS L operating s%stem$

,t is not necessar% for a comp#ter to ha(e a "ernel in order for it to !e #sa!le, the reason !eing that it is not necessar% for it to ha(e an operating s%stem$ That is, it is possi!le to load and r#n programs directl% on bare metal machines 0i$e$, comp#ters )itho#t an% operating s%stem installed2, altho#gh this is #s#all% not (er% practical$ ,n fact, the first generations of comp#ters #sed !are metal operation$ 9o)e(er, it )as e(ent#all% reali+ed that con(enience and efficienc% co#ld !e increased !% retaining small #tilit% programs, s#ch as program loaders and de!#ggers, in memor% !et)een applications$ These programs grad#all% e(ol(ed into operating s%stem "ernels$ The term ,ernel is fre-#entl% #sed in !oo"s and disc#ssions a!o#t Lin#/, )hereas it is #sed less often )hen disc#ssing some other operating s%stems, s#ch as the Microsoft .indo)s s%stems$ The reasons are that the "ernel is highl% config#ra!le in the case of Lin#/ and #sers are enco#raged to learn a!o#t and modif% it and to do)nload and install #pdated (ersions$ .ith the Microsoft .indo)s operating s%stems, in contrast, there is relati(el% little point in disc#ssing "ernels !eca#se the% cannot !e modified or replaced$ C-1(%*'$(/ *> K(':()/ Bernels can !e classified into fo#r !road categoriesC monolithic ,ernels, micro,ernels, hybrid ,ernels and e/o,ernels$ 'ach has its o)n ad(ocates and detractors$ Monolithic "ernels, )hich ha(e traditionall% !een #sed !% 7ni/&li"e operating s%stems, contain all the operating s%stem core f#nctions and the de'ice dri'ers 0small programs that allo) the operating s%stem to interact )ith hard)are de(ices, s#ch as dis" dri(es, (ideo cards and printers2$ Modern monolithic "ernels, s#ch as those of Lin#/ and 1ree8SD, !oth of )hich fall into the categor% of 7ni/&li"e operating s%stems, feat#re the a!ilit% to load modules at r#ntime, there!% allo)ing

eas% e/tension of the "ernel>s capa!ilities as re-#ired, )hile helping to minimi+e the amo#nt of code r#nning in "ernel space$ * micro"ernel #s#all% pro(ides onl% minimal ser(ices, s#ch as defining memor% address spaces, interprocess comm#nication 0,PC2 and process management$ *ll other f#nctions, s#ch as hard)are management, are implemented as processes r#nning independentl% of the "ernel$ '/amples of micro"ernel operating s%stems are *,L, 8eAS, 9#rd, Mach, Mac AS L, M,=,L and J=L$ 9%!rid "ernels are similar to micro"ernels, e/cept that the% incl#de additional code in "ernel space so that s#ch code can r#n more s)iftl% than it )o#ld )ere it in #ser space$ These "ernels represent a compromise that )as implemented !% some de(elopers !efore it )as demonstrated that p#re micro"ernels can pro(ide high performance$ 9%!rid "ernels sho#ld not !e conf#sed )ith monolithic "ernels that can load mod#les after !ooting 0s#ch as Lin#/2$ Most modern operating s%stems #se h%!rid "ernels, incl#ding Microsoft .indo)s =T, 2000 and LP$ Dragon1l% 8SD, a recent %or, 0i$e$, (ariant2 of 1ree8SD, is the first non&Mach !ased 8SD operating s%stem to emplo% a h%!rid "ernel architect#re$ '/o"ernels are a still e/perimental approach to operating s%stem design$ The% differ from the other t%pes of "ernels in that their f#nctionalit% is limited to the protection and m#ltiple/ing of the ra) hard)are, and the% pro(ide no hard)are a!stractions on top of )hich applications can !e constr#cted$ This separation of hard)are protection from hard)are management ena!les application de(elopers to determine ho) to ma"e the most efficient #se of the a(aila!le hard)are for each specific program$ '/o"ernels in themsel(es the% are e/tremel% small$ 9o)e(er, the% are accompanied !% library operatin+ systems, )hich pro(ide application de(elopers )ith the con(entional f#nctionalities of a complete operating s%stem$ * major

ad(antage of e/o"ernel&!ased s%stems is that the% can incorporate m#ltiple li!rar% operating s%stems, each e/porting a different *P, 0application programming interface2, s#ch as one for Lin#/ and one for Microsoft .indo)s, th#s ma"ing it possi!le to sim#ltaneo#sl% r#n !oth Lin#/ and .indo)s applications$ T0( M*:*)$10$+ V('/&/ M$+'* C*:1'*<('/3 ,n the earl% :@@0s, man% comp#ter scientists considered monolithic "ernels to !e o!solete, and the% predicted that micro"ernels )o#ld re(ol#tioni+e operating s%stem design$ ,n fact, the de(elopment of Lin#/ as a monolithic "ernel rather than a micro"ernel led to a famo#s %lame 0ar 0i$e$, a )ar of )ords on the ,nternet2 !et)een *ndre) Tanen!a#m, the de(eloper of the M,=,L operating s%stem, and Lin#/ Tor(alds, )ho originall% de(eloped Lin#/ !ased largel% on M,=,L$ Proponents of micro"ernels point o#t those monolithic "ernels ha(e the disad(antage that an error in the "ernel can ca#se the entire s%stem to crash$ 9o)e(er, )ith a micro"ernel, if a "ernel process crashes, it is still possi!le to pre(ent a crash of the s%stem as a )hole !% merel% restarting the ser(ice that ca#sed the error$ *ltho#gh this so#nds sensi!le, it is -#estiona!le ho) important it is in realit%, !eca#se operating s%stems )ith monolithic "ernels s#ch as Lin#/ ha(e !ecome e/tremel% sta!le and can r#n for %ears )itho#t crashing$ *nother disad(antage cited for monolithic "ernels is that the% are not portableQ that is, the% m#st !e re)ritten for each ne) architecture 0i$e$, processor t%pe2 that the operating s%stem is to !e #sed on$ 9o)e(er, in practice, this has not appeared to !e a major disad(antage, and it has not pre(ented Lin#/ from !eing ported to n#mero#s processors$ Monolithic "ernels also appear to ha(e the disad(antage that their source code can !ecome e/tremel% large$ So#rce code is the (ersion of so%t0are as it is originall% 0ritten 0i$e$, t%ped into a comp#ter2 !% a h#man in plain te/t 0i$e$, h#man reada!le

alphan#meric characters2 and !efore it is con(erted !% a compiler into ob1ect code that a comp#ter>s processor can directl% read and e/ec#te$ 1or e/ample, the so#rce code for the Lin#/ "ernel (ersion 2$4$0 is appro/imatel% :00M8 and contains nearl% 3$3; million lines, and that for (ersion 2$?$0 is 2:2M8 and contains <$@3 million lines$ This adds to the comple/it% of maintaining the "ernel, and it also ma"es it diffic#lt for ne) generations of comp#ter science st#dents to st#d% and comprehend the "ernel$ 9o)e(er, the ad(ocates of monolithic "ernels claim that in spite of their si+e s#ch "ernels are easier to design correctl%, and th#s the% can !e impro(ed more -#ic"l% than can micro"ernel&!ased s%stems$ Moreo(er, the si+e of the compiled "ernel is onl% a tin% fraction of that of the so#rce code, for e/ample ro#ghl% :$:M8 in the case of Lin#/ (ersion 2$4 on a t%pical ed 9at Lin#/ @ des"top installation$ Contri!#ting to the small si+e of the compiled Lin#/ "ernel is its a!ilit% to d%namicall% load mod#les at r#ntime, so that the !asic "ernel contains onl% those components that are necessar% for the s%stem to start itself and to load mod#les$ The monolithic Lin#/ "ernel can !e made e/tremel% small not onl% !eca#se of its a!ilit% to d%namicall% load mod#les !#t also !eca#se of its ease of c#stomi+ation$ ,n fact, there are some (ersions that are small eno#gh to fit together )ith a large n#m!er of #tilities and other programs on a single flopp% dis" and still pro(ide a f#ll% f#nctional operating s%stem 0one of the most pop#lar of )hich is mu2inu/2$ This a!ilit% to miniat#ri+e its "ernel has also led to a rapid gro)th in the #se of Lin#/ in embedded systems 0i$e$, comp#ter circ#itr% !#ilt into other prod#cts2$ *ltho#gh micro"ernels are (er% small !% themsel(es, in com!ination )ith all their re-#ired a#/iliar% code the% are, in fact, often larger than monolithic "ernels$ *d(ocates of monolithic "ernels also point o#t that the t)o&tiered str#ct#re of micro"ernel s%stems, in )hich most of the operating s%stem does not interact

directl% )ith the hard)are, creates a not&insignificant cost in terms of s%stem efficienc%$

L$:&A
L$:&A refers to the famil% of 7ni/&li"e comp#ter operating s%stems #sing the Lin#/ "ernel$ Lin#/ can !e installed on a )ide (ariet% of comp#ter hard)are, ranging from mo!ile phones, ta!let comp#ters and (ideo game consoles, to mainframes and s#percomp#ters$ Lin#/ is the leading ser(er AS, acco#nting for more than <0P of installations$ Des"top #se of Lin#/ has increased in recent %ears, partl% o)ing to the pop#lar 7!#nt#, 1edora, and open 7S' distri!#tions and the emergence of net !oo"s and smart phones r#nning an em!edded Lin#/$ The name YLin#/Y comes from the Lin#/ "ernel, originall% )ritten in :@@: !% Lin#s Tor(alds$ The main s#pporting #ser space s%stem tools and li!raries from the G=7 Project 0anno#nced in :@;3 !% ichard Stallman2 are the !asis for the 1ree Soft)are 1o#ndation>s preferred name G3-42inu/$ The de(elopment of Lin#/ is one of the most prominent e/amples of free and open so#rce soft)are colla!orationQ t%picall% all the #nderl%ing so#rce code can !e #sed, freel% modified, and redistri!#ted, !oth commerciall% and non&commerciall%, !% an%one #nder licenses s#ch as the G=7 General P#!lic License$ T%picall% Lin#/ is pac"aged in a format "no)n as a 2inu/ distribution for des"top and ser(er #se$ Lin#/ distri!#tions incl#de the Lin#/ "ernel and all of the s#pporting soft)are re-#ired to r#n a complete s%stem, s#ch as #tilities and li!raries, the L .indo) S%stem, the G=AM' and BD' des"top en(ironments, and the *pache 9TTP Ser(er$ Commonl% #sed applications )ith des"top Lin#/ s%stems incl#de the Mo+illa 1irefo/ )e!&!ro)ser, the ApenAffice$org office application s#ite and the G,MP image editor$

F(-1&'(/ *> L$:&A: Lin#/ has e(ol(ed to ha(e the follo)ing feat#res as an o#tstanding operating s%stem )hich is strong in sec#rit% and net)or"ing$ ] M#ltitas"ingC Se(eral programs can r#n at the same time$ ]M#lti#serC Se(eral #sers can logon to the same machine at the same time There is no need to ha(e separate #ser licenses$ ] M#ltiplatformC Lin#/ r#ns on man% different CP7s, that means it s#pports m#ltiprocessor machine$ ] M#ltithreadingC Lin#/ has nati(e "ernel s#pport for m#ltiple independent threads of control )ithin a single process memor% space$ ]Crash proofC Lin#/ has memor% protection !et)een processes, so that one program can>t !ring the )hole s%stem do)n$ ]Demand loads e/ec#ta!lesC Lin#/ onl% reads from those parts of a program that are act#all% #sed on the dis"$ ]Shared cop%&on&)rite pages among e/ec#ta!lesC This means that m#ltiple processes can #se the same memor% to r#n in$ .hen one tries to )rite to that memor%, that page 0)ith 4B8 piece of memor%2 is copied some)here else$ Cop%& on&)rite has t)o !enefitsC increasing speed and decreasing memor% #se$ ] Dirt#al memor% #ses paging 0not s)apping )hole processes2 to dis" to a separate partition or a file in the file s%stem, or !oth, )ith the possi!ilit% of adding more s)apping areas d#ring r#ntime 0%es, the%>re still called s)apping areas2$ * total of :? of these :2; M8 02G8 in recent "ernels2 s)apping areas can !e #sed at the same time, for a theoretical total of 2 G8 of #sa!le s)ap space$ ,t is simple to increase this if necessar%, !% changing a fe) lines of so#rce code$

]Lin#/ has a #nified memor% pool for #ser programs and dis" cache, so that all free memor% can !e #sed for caching, and the cache can !e red#ced )hen r#nning large programs$ ] Lin#/ does core d#mps for post&mortem anal%sis, allo)ing the #se of a de!#gger on a program not onl% )hile it is r#nning !#t also after it has crashed$ ] Lin#/ is mostl% compati!le )ith PAS,L, S%stem D, and 8SD at the so#rce le(el$ ] Thro#gh an i8CS2&compliant em#lation mod#le, Lin#/ is mostl% compati!le )ith SCA, SD 3, and SD 4 at the !inar% le(el$ ] 1ree and Apen so#rce code for allC *ll so#rce code of Lin#/ is a(aila!le, incl#ding the )hole "ernel and all dri(ers, the de(elopment tools and all #ser programsQ also, all of it is freel% distri!#ta!le$ Plent% of commercial programs are !eing pro(ided for Lin#/ )itho#t so#rce, !#t e(er%thing that has !een free, incl#ding the entire !ase operating s%stem, is still free$ ] Lin#/ s#pports pse#do terminals 0pt%>s2 and m#ltiple (irt#al consolesC 8% se(eral independent login sessions thro#gh the console, %o# can s)itch !et)een !% pressing a hot&"e% com!ination 0not dependent on (ideo hard)are2$ These are d%namicall% allocatedQ %o# can #se #p to ?4$ ] Lin#/ s#pports se(eral common file s%stems, incl#ding mini/, Leni/, and all the common s%stem D file s%stems, and has an ad(anced file s%stem of its o)n, )hich offers file s%stems of #p to 4 T8, and names #p to 2<< characters long$ ] Lin#/ has a transparent access to MS&DAS partitions 0or AS42 1*T partitions2 (ia a special file s%stemC$No# don>t need an% special commands to #se the MS& DAS partition, it loo"s j#st li"e a normal 7ni/ file s%stem 0e/cept for f#nn% restrictions on file names, permissions, and so on2$ MS&DAS ? compressed partitions do not )or" at this time )itho#t a patch 0dmsdosfs2$ *lso D1*T 0.=T, .indo)s @<2 s#pport and 1*T&32 is a(aila!le in Lin#/ 2$0

] Lin#/ has CD& AM file s%stem )hich reads all standard formats of CD& AMs$ ] Lin#/ performs )ell )ith TCP4,P net)or"ing, incl#ding ftp, telnet, =1S, etc$ ] Lin#/ is #ser&friendl% as =et)are client and ser(er ] Lin#/ also r#ns as Lan Manager4.indo)s =ati(e 0SM82 client and ser(er ] ,t integrates man% net)or"ing protocolsC The !ase protocols a(aila!le in the latest de(elopment "ernels incl#de TCP, ,P(4, ,P(?, *L$2<, L$2<, ,PL, DDP 0*ppletal"2, =etrom, and others$ Sta!le net)or" protocols incl#ded in the sta!le "ernels c#rrentl% incl#de TCP, ,P(4, ,PL, DDP, and *L$2<$

RS! !
RS! ! (/('$-) 6*'1): S&232 0 ecommended Standard & 2322 is a telecomm#nications standard for !inar% serial comm#nications !et)een de(ices$ ,t s#pplies the roadmap for the )a% de(ices spea" to each other #sing serial ports$ The de(ices are commonl% referred to as a DT' 0data terminal e-#ipment2 and DC' 0data comm#nications e-#ipment2Q for e/ample, a comp#ter and modem, respecti(el%$ S232 is the most "no)n serial port #sed in transmitting the data in comm#nication and interface$ '(en tho#gh serial port is harder to program than the parallel port, this is the most effecti(e method in )hich the data transmission re-#ires less )ires that %ields to the less cost$ The S232 is the comm#nication line )hich ena!les the data transmission !% onl% #sing three )ire lin"s$ The three lin"s pro(ides 5transmit3, 5recei(e3 and common gro#nd$$$ The 5transmit3 and 5recei(e3 line on this connecter send and recei(e data !et)een the comp#ters$ *s the name indicates, the data is transmitted seriall%$ The t)o pins are TLD F LD$ There are other lines on this port as TS, CTS, DS , DT , and TS, ,$ The 5:3 and 503 are the data )hich defines a (oltage le(el of 3D to 2<D and &3D to &2<D respecti(el%$ he electrical characteristics of the serial port as per the ',* 0'lectronics ,nd#str% *ssociation2 S232C Standard specifies a ma/im#m !a#d rate of 20,000!ps, )hich is slo) compared to toda%3s standard speed$ 1or this reason, )e ha(e chosen the ne) S&232D Standard, )hich )as recentl% released$

The S&232D has e/isted in t)o t%pes$ i$e$, D&TNP' 2< pin connector and D& TNP' @ pin connector, )hich are male connectors on the !ac" of the PC$ No# need a female connector on %o#r comm#nication from 9ost to G#est comp#ter$ The pin o#ts of !oth D&@ F D&2< are sho) !elo) D&T%pe&@ pinD&T%pe&2< no$ 3 2 E ; ? < : 4 @ no$ 2 3 4 < ? E ; 20 22 D TD TS CTS DS SG DCD DT , ecei(e Data 0Serial data inp#t2 Transmit Data 0Serial data o#tp#t2 e-#est to send 0ac"no)ledge to modem that 7* T is read% to e/change data Clear to send 0i$e$Q modem is read% to e/change data2 Data read% state 07* T esta!lishes a lin"2 Signal gro#nd Data Carrier detect 0This line is acti(e )hen modem detects a carrier Data Terminal ead%$ ing ,ndicator 08ecomes acti(e )hen modem detects ringing signal from PST= pinPin o#ts 1#nction

R/! !

.hen comm#nicating )ith (ario#s micro processors one needs to con(ert the S232 le(els do)n to lo)er le(els, t%picall% 3$3 or <$0 D *)1/. 9ere is a cheap and simple )a% to do that$ S('$-) RS7! ! 0D$242 comm#nication )or"s )ith (oltages &:<D to 6:<D for high and lo)$ An the other hand, TTL logic operates !et)een 0D and 6<D $ Modern lo) po)er cons#mption logic operates in the range of 0D and 63$3D or e(en lo)er$

RS7! ! TTL L*%$+ &:<D ^ &3D 62D ^ 6<D 9igh 63D ^ 6:<D 0D ^ 60$;D Lo) Th#s the S&232 signal le(els are far too high TTL ()(+1'*:$+/@ and the negati(e S&232 (oltage for high can3t !e handled at all !% comp#ter logic$ To recei(e serial data from an S&232 interface the (oltage has to !e red#ced$ *lso the lo) and high (oltage le(el has to !e in(erted$ This le(el con(erter #ses a M-A! ! and fi(e +-6-+$1*'/$ The ma/232 is -#ite cheap 0less than < dollars2 or if %o#re l#c"% %o# can get a free sample from M-A$.. The M*L232 from M-A$. )as the first ,C )hich in one pac"age contains the necessar% dri(ers and recei(ers to adapt the S&232 signal (oltage le(els to TTL logic$ ,t !ecame pop#lar, !eca#se it j#st needs

one (oltage 06<D or 63$3D2 and generates the necessar%

S&232 (oltage le(els$

M*L 232 P,= D,*G *M 6&&&_4&&&6 : &`C:6 Dcc`& :? 2 &`D6 gnd`& :< 3 &`C:& T:A`& :4 4 &`C26 < &`C2& :,`& :3 :A`& :2

? &`D& T:,`& :: E &`T2A T2,`& :0 ; &` 2, 2A`& @ 6&&&&&&&&6 RS! ! INTERFACED TO MAK ! !

J2 # " ! 5 4 3 2 1 U3 1 )1, U ) )*+ $ 3 %1 (4 5' ( & % 51 u f ( & %1 u f & %1 u f (! & %1 u f - . *3232 15 2 13 " 1& 11 1 3 4 5 1 1 I0 1 2 I0 )2 I0 )1 I0 ( ( ( ( 12 13 22 23 /0+ 1 1, U ) 1 2, U ) )1, U ) )2, U ) 12 # 14 ! (1 1uf $ 3 %& 1 * + )1, U )

'2 '3

s232 is @ pin d! connector, onl% three pins of this are #sed ie 2,3,< the transmit pin of rs232 is connected to r/ pin of microcontroller M-A! ! $:1('>-+(2 1* .$+'*+*:1'*))('

'((

M*L232 is connected to the microcontroller as sho)n in the fig#re a!o(e ::, :2 pin are connected to the :0 and :: pin ie transmit and recei(e pin of microcontroller$

TEMPERATURE SENSOR F(-1&'(/

] Cali!rated directl% in O Celsi#s 0Centigrade2 ] Linear 6 :0$0 mD4OC scale factor ] 0$<OC acc#rac% g#aranteea!le 0at 62<OC2 ] ated for f#ll &<<O to 6:<0OC range ] S#ita!le for remote applications ] Lo) cost d#e to )afer&le(el trimming ] Aperates from 4 to 30 (olts ] Less than ?0 a* c#rrent drain ] Lo) self&heating, 0$0;OC in still air ] =onlinearit% onl% bcOC t%pical ] Lo) impedance o#tp#t, 0$: Ahm for : m* load Description The LM3< series are precision integrated&circ#it temperat#re sensors, )hose o#tp#t (oltage is linearl% proportional to the Celsi#s 0Centigrade2 temperat#re$ The LM3< th#s has an ad(antage o(er linear temperat#re sensors cali!rated in O Bel(in, as the #ser is not re-#ired to s#!tract a large constant (oltage from its o#tp#t to o!tain con(enient Centigrade scaling$ The LM3< does not re-#ire an% e/ternal cali!ration or trimming to pro(ide t%pical acc#racies of bcOC at room temperat#re and bdOC o(er a f#ll &<< to 6:<0OC temperat#re range$ Lo) cost is ass#red !% trimming and cali!ration at the )afer le(el$ The LM3<>s lo) o#tp#t impedance, linear o#tp#t, and precise inherent cali!ration ma"e interfacing to reado#t or control circ#itr% especiall% eas%$ ,t can !e #sed )ith single po)er s#pplies, or )ith pl#s and min#s s#pplies$ *s it dra)s onl% ?0 a* from its s#ppl%, it has (er% lo) self&heating, less than 0$:OC in still air$ The LM3< is rated to operate o(er a &<<O to 6:<0OC temperat#re range, )hile the LM3<C is rated for a &40O to 6::0OC range 0& :0O )ith impro(ed acc#rac%2$ Temperat#re sensorC

*n analog temperat#re sensor is prett% eas% to e/plain, its a chip that tells %o# )hat the am!ient temperat#re ise These sensors #se a solid&state techni-#e to determine the temperat#re$ That is to sa%, the% dont #se merc#r% 0li"e old thermometers2, !imetalic strips 0li"e in some home thermometers or sto(es2, nor do the% #se thermistors 0temperat#re sensiti(e resistors2$ ,nstead, the% #se the fact as temperat#re increases, the (otage across a diode increases at a "no)n rate$ 0Technicall%, this is act#all% the (oltage drop !et)een the !ase and emitter & the D!e & of a transistor$ 8% precisel% amplif%ing the (oltage change, it is eas% to genereate an analog signal that is directl% proportional to temperat#re$ Meas#ring temperat#re To con(ert the (oltage to temperat#re, simpl% #se the !asic form#laC Temp in OC V H0Do#t in mD2 & <00I 4 :0 So for e/ample, if the (oltage o#t is :D that means that the temperat#re is 00:000 mD & <002 4 :02 V <0 OC ,f %o#>re #sing a LM3< or similar, #se line >a> in the image a!o(e and the form#laC Temp in OC V 0Do#t in mD2 4 :0 Testing %o#r temperat#re sensor Testing these sensors is prett% eas% !#t %o#>ll need a !atter% pac" or po)er s#ppl%$ Connect a 2$E&<$<D po)er s#ppl% 02&4 ** !atteries )or" fantastic2 so that gro#nd is connected to pin 3 0right pin2, and po)er is connected to pin : 0left pin2$ Then connect %o#r m#ltimeter in DC (oltage mode to gro#nd and the remaining pin 2 0middle2$ ,f %o#>(e got a TMP3? and its a!o#t room temperat#re 02<OC2, the

(oltage sho#ld !e a!o#t 0$E<D$ =ote that if %o#>re #sing a LM3<, the (oltage )ill !e 0$2<D$ The sensor is indicating that the temperat#re is 2?$3OC also "no)n as E@$3O1$ No# can change the (oltage range !% pressing the plastic case of the sensor )ith %o#r fingers, %o# )ill see the temperat#re4(oltage rise$ .ith m% fingers on the sensor, heating it #p a little, the temperat#re reading is no) 2@$EOC 4 ;<$<O1 Ar %o# can to#ch the sensor )ith an ice c#!e, perferra!l% in a plastic !ag so it doesn>t get )ater on %o#r circ#it, and see the temperat#re4(oltage drop$ Connecting to %o#r temperat#re sensor These sensors ha(e little chips in them and )hile the%>re not that delicate, the% do need to !e handled properl%$ 8e caref#l of static electricit% )hen handling them and ma"e s#re the po)er s#ppl% is connected #p correctl% and is !et)een 2$E and <$<D DC & so don>t tr% to #se a @D !atter%e 8read !oarded to&@2$ The% come in a YTA&@2Y pac"age )hich means the chip is ho#sed in a plastic hemi&c%linder )ith three legs$ The legs can !e !ent easil% to allo) the sensor to !e pl#gged into a !read!oard$ No# can also solder to the pins to connect long )ires$ ,f %o# need to )aterproof the sensor, %o# can see !elo) for an ,nstr#cta!le for ho) to ma"e an e/cellent case$

SMOKE SENSOR

INTRODUCTION: * CA gas sensor according to the present in(ention incl#des a gas collecting container for collecting a meas#red gas thereinQ a detecting section pro(ided )ithin

the gas collecting container and ha(ing at least a pair of electrodes positioned thro#gh electrol%teQ and a (oltage appl%ing apparat#s for appl%ing (oltage to the detecting section$ Ane of the electrodes of the detecting section is a detection electrode ha(ing the capa!ilit% of adsor!ing at least one of h%drogeno#s gas and CA gas )hen a (oltage is applied and then o/idi+ing it$ 8% introd#cing a meas#red gas into a gas collecting container of the CA gas sensor and carr%ing o#t electrol%sis according to a potential s)eep method or a p#lse method )ith the meas#red gas !eing in contact )ith the detecting section, a CA gas concentration in the meas#red gas can !e meas#red !ased on an electrical c#rrent (al#e o!tained at the detecting section and changes of the electrical c#rrent )ith elapse of time$ *ccording to the CA gas sensor of the present in(ention, it is possi!le to acc#ratel% carr% o#t detection and meas#rement of the concentration of CA gas )hen CA gas is to !e detected or meas#red e(en in a gaseo#s atmosphere containing a relati(el% large amo#nt of h%drogen gas and CA2 gas$ D'SC ,PT,A=C 1,'LD A1 T9' ,=D'=T,A=

The present in(ention relates to a CA gas sensor for meas#ring the concentration of CA gas contained in a gaseo#s phase and to a method of meas#ring the concentration of CA gas, and in partic#lar relates to a CA gas sensor for meas#ring the concentration of CA gas in a gaseo#s atmosphere containing relati(el% high concentrations of h%drogen gas and car!on dio/ide gas, a f#el cell po)er generating apparat#s e-#ipped )ith s#ch CA gas sensor, and a method of meas#ring the concentration of CA gas$

8*CBG A7=D

* T

,n man% cases, h%drogen gas is #sed as a f#el gas for f#el cells$ *s s#ch h%drogen gas, a h%drogen gas rich reforming gas )hich is o!tained !% reforming methanol or the li"e is #sed$ .hen man#fact#ring s#ch a reforming gas, a tin% amo#nt of car!on mono/ide 0CA2, namel% se(eral tens ppm to se(eral h#ndred ppm, is present as imp#rities$ 1or this reason, )hen s#ch a reforming gas is #sed as a f#el gas for a f#el cell, the CA gas is adsor!ed on the s#rface of the platin#m catal%st of the f#el cell electrodes, th#s hindering ioni+ation of the h%drogen gas and lo)ering the o#tp#t of the f#el cell$ ,n order to ta"e appropriate meas#res to co#nter s#ch a pro!lem ca#sed !% the CA gas, it is necessar% to contin#o#sl% monitor the concentration of CA gas in the reforming gas #sed in the f#el cell$ Con(entionall%, as for the most commonl% #sed CA gas sensor, there are "no)n a controlled potential anal%sis t%pe CA gas sensor and a semicond#ctor t%pe CA gas sensor$ 9o)e(er, for the reasons gi(en !elo), neither of these CA gas sensors is appropriate for detecting CA gas in a reforming gas$

=amel%, the reforming gas contains h%drogen gas #sed as a f#el in the f#el cell for the amo#nt of a!o#t E<P thereof$ ,n comparison )ith this, the reforming gas contains a relati(el% tin% amo#nt of CA gas as descri!ed a!o(e$ Therefore, it !ecomes necessar% to detect or meas#re CA gas in a h%drogen gas atmosphere containing a relati(el% large amo#nt of h%drogen gas$ 9o)e(er, in the case )here the concentration of CA gas is meas#red in s#ch a h%drogen gas rich atmosphere #sing these CA gas sensors, there is a pro!lem that it is diffic#lt to acc#ratel% detect 0-#alitati(e anal%sis2 or meas#re 0-#antitati(e anal%sis2 s#ch CA gas )ith either t%pe of CA gas sensor d#e to infl#ence of the h%drogen gas rich atmosphere

in

)hich

interference

!%

h%drogen

gas

occ#rs$

,n (ie) of the pro!lem mentioned a!o(e, it is an o!ject of the present in(ention to pro(ide a CA gas sensor )hich can acc#ratel% carr% o#t detection 0-#alitati(e anal%sis2 and meas#rement 0-#antitati(e anal%sis2 of the concentration of CA gas )hen CA gas is detected or meas#red in a gaseo#s atmosphere containing a relati(el% large amo#nt of h%drogen gas and car!on dio/ide gas, a f#el cell po)er generating apparat#s e-#ipped )ith s#ch a CA gas sensor, and a method of meas#ring the concentration of CA gas$

RELAY
* rela% is an electrical s)itch that opens and closes #nder the control of another electrical circ#it$ ,n the original form, the s)itch is operated !% an electromagnet to open or close one or man% sets of contacts$ 8eca#se a rela% is a!le to control an o#tp#t circ#it of higher po)er than the inp#t circ#it, it can !e considered to !e, in a !road sense, a form of an electrical amplifier$

Small rela% as #sed in electronics * simple electromagnetic rela%, s#ch as the one ta"en from a car in the first pict#re, is an adaptation of an electromagnet$ ,t consists of a coil of )ire s#rro#nding a soft iron core, an iron %o"e, )hich pro(ides a lo) rel#ctance path for magnetic fl#/, a mo(ea!le iron armat#re, and a set, or sets, of contactsQ t)o in the rela% pict#red$ The armat#re is hinged to the %o"e and mechanicall% lin"ed to a mo(ing contact or contacts$ ,t is held in place !% a spring so that )hen the rela% is de&energi+ed there is an air gap in the magnetic circ#it$ ,n this condition, one of the t)o sets of contacts in the rela% pict#red is closed, and the other set is open$ Ather rela%s ma% ha(e more or fe)er sets of contacts depending on their f#nction$ The rela% in the pict#re also has a )ire connecting the armat#re to the %o"e$ This ens#res contin#it% of the circ#it !et)een the mo(ing contacts on the armat#re, and the circ#it trac" on the Printed Circ#it 8oard 0PC82 (ia the %o"e, )hich is soldered to the PC8$ .hen an electric c#rrent is passed thro#gh the coil, the res#lting magnetic field attracts the armat#re and the conse-#ent mo(ement of the mo(a!le contact or contacts either ma"es or !rea"s a connection )ith a fi/ed contact$ ,f the set of contacts )as closed )hen the rela% )as de&energi+ed, then the mo(ement opens the contacts and !rea"s the connection, and (ice (ersa if the contacts )ere open$ .hen the c#rrent to the coil is s)itched off, the armat#re is ret#rned !% a force, appro/imatel% half as strong as the magnetic force, to its rela/ed position$ 7s#all% this force is pro(ided !% a spring, !#t gra(it% is also #sed commonl% in ind#strial motor starters$ Most rela%s are man#fact#red to operate -#ic"l%$ ,n a lo) (oltage application, this is to red#ce noise$ ,n a high (oltage or high c#rrent application, this is to red#ce arcing$ ,f the coil is energi+ed )ith DC, a diode is fre-#entl% installed across the coil, to dissipate the energ% from the collapsing magnetic field at deacti(ation, )hich

)o#ld other)ise generate a (oltage spi"e dangero#s to circ#it components$ Some a#tomoti(e rela%s alread% incl#de that diode inside the rela% case$ *lternati(el% a contact protection net)or", consisting of a capacitor and resistor in series, ma% a!sor! the s#rge$ ,f the coil is designed to !e energi+ed )ith *C, a small copper ring can !e crimped to the end of the solenoid$ This Yshading ringY creates a small o#t&of&phase c#rrent, )hich increases the minim#m p#ll on the armat#re d#ring the *C c%cle$H:I 8% analog% )ith the f#nctions of the original electromagnetic de(ice, a solid&state rela% is made )ith a th%ristor or other solid&state s)itching de(ice$ To achie(e electrical isolation an optoco#pler can !e #sed )hich is a light&emitting diode 0L'D2 co#pled )ith a photo transistor$

T36(/ *> '()-3

Latching rela% * latching rela% has t)o rela/ed states 0!i sta!le2$ These are also called >"eep> or >sta%> rela%s$ .hen the c#rrent is s)itched off, the rela% remains in its last state$ This is achie(ed )ith a solenoid operating a ratchet and cam mechanism, or !% ha(ing t)o opposing coils )ith an o(er&center spring or permanent magnet to hold the armat#re and contacts in position )hile the coil is rela/ed, or )ith a remnant core$ ,n the ratchet and cam e/ample, the first p#lse to the coil t#rns the rela% on and the second p#lse t#rns it off$ ,n the t)o coil e/ample, a p#lse to one coil t#rns the rela% on and a p#lse to the opposite coil t#rns the rela% off$ This t%pe of rela% has the ad(antage that it cons#mes po)er onl% for an instant, )hile it is !eing s)itched, and it retains its last setting across a po)er o#tage$ R((2 '()-3 * reed rela% has a set of contacts inside a (ac##m or inert gas filled glass t#!e, )hich protects the contacts against atmospheric corrosion$ The contacts are closed

!% a magnetic field generated )hen c#rrent passes thro#gh a coil aro#nd the glass t#!e$ eed rela%s are capa!le of faster s)itching speeds than larger t%pes of rela%s, !#t ha(e lo) s)itch c#rrent and (oltage ratings$ See also reed s)itch$ M('+&'375(11(2 '()-3 * merc#r%&)etted reed rela% is a form of reed rela% in )hich the contacts are )etted )ith merc#r%$ S#ch rela%s are #sed to s)itch lo)&(oltage signals 0one (olt or less2 !eca#se of its lo) contact resistance, or for high&speed co#nting and timing applications )here the merc#r% eliminates contact !o#nce$ Merc#r% )etted rela%s are position&sensiti(e and m#st !e mo#nted (erticall% to )or" properl%$ 8eca#se of the to/icit% and e/pense of li-#id merc#r%, these rela%s are rarel% specified for ne) e-#ipment$ See also merc#r% s)itch$ P*)-'$?(2 '()-3 * Polari+ed ela% placed the armat#re !et)een the poles of a permanent magnet to increase sensiti(it%$ Polari+ed rela%s )ere #sed in middle 20th Cent#r% telephone e/changes to detect faint p#lses and correct telegraphic distortion$ The poles )ere on scre)s, so a technician co#ld first adj#st them for ma/im#m sensiti(it% and then appl% a !ias spring to set the critical c#rrent that )o#ld operate the rela%$ M-+0$:( 1**) '()-3 * machine tool rela% is a t%pe standardi+ed for ind#strial control of machine tools, transfer machines, and other se-#ential control$ The% are characteri+ed !% a large n#m!er of contacts 0sometimes e/tenda!le in the field2 )hich are easil% con(erted from normall%&open to normall%&closed stat#s, easil% replacea!le coils, and a form factor that allo)s compactl% installing man% rela%s in a control panel$ *ltho#gh s#ch rela%s once )ere the !ac"!one of a#tomation in s#ch ind#stries as a#tomo!ile assem!l%, the programma!le logic controller 0PLC2 mostl% displaced the machine tool rela% from se-#ential control applications$

 C*:1-+1*' '()-3 * contactor is a (er% hea(%&d#t% rela% #sed for s)itching electric motors and lighting loads$ 9igh&c#rrent contacts are made )ith allo%s containing sil(er$ The #na(oida!le arcing ca#ses the contacts to o/idi+e and sil(er o/ide is still a good cond#ctor$ S#ch de(ices are often #sed for motor starters$ * motor starter is a contactor )ith o(erload protection de(ices attached$ The o(erload sensing de(ices are a form of heat operated rela% )here a coil heats a !i&metal strip, or )here a solder pot melts, releasing a spring to operate a#/iliar% contacts$ These a#/iliar% contacts are in series )ith the coil$ ,f the o(erload senses e/cess c#rrent in the load, the coil is de&energi+ed$ Contactor rela%s can !e e/tremel% lo#d to operate, ma"ing them #nfit for #se )here noise is a chief concern$ S*)$27/1-1( '()-3 Solid state rela%, )hich has no mo(ing parts 2< amp or 40 amp solid state contactors * solid state rela% 0SS 2 is a solid state electronic component that pro(ides a similar f#nction to an electromechanical rela% !#t does not ha(e an% mo(ing components, increasing long&term relia!ilit%$ .ith earl% SS >s, the tradeoff came from the fact that e(er% transistor has a small (oltage drop across it$ This (oltage drop limited the amo#nt of c#rrent a gi(en SS co#ld handle$ *s transistors impro(ed, higher c#rrent SS >s, a!le to handle :00 to :,200 amps, ha(e !ecome commerciall% a(aila!le$ Compared to electromagnetic rela%s, the% ma% !e falsel% triggered !% transients$ S*)$2 /1-1( +*:1-+1*' '()-3 * solid state contactor is a (er% hea(%&d#t% solid state rela%, incl#ding the necessar% heat sin", #sed for s)itching electric heaters, small electric motors and lighting loadsQ )here fre-#ent on4off c%cles are re-#ired$ There are no mo(ing

parts to )ear o#t and there is no contact !o#nce d#e to (i!ration$ The% are acti(ated !% *C control signals or DC control signals from Programma!le logic controller 0PLCs2, PCs, Transistor&transistor logic 0TTL2 so#rces, or other microprocessor controls$ B&+00*)? '()-3 * 8#chhol+ rela% is a safet% de(ice sensing the acc#m#lation of gas in large oil& filled transformers, )hich )ill alarm on slo) acc#m#lation of gas or sh#t do)n the transformer if gas is prod#ced rapidl% in the transformer oil$ F*'+(27%&$2(2 +*:1-+1/ '()-3 * forced&g#ided contacts rela% has rela% contacts that are mechanicall% lin"ed together, so that )hen the rela% coil is energi+ed or de&energi+ed, all of the lin"ed contacts mo(e together$ ,f one set of contacts in the rela% !ecomes immo!ili+ed, no other contact of the same rela% )ill !e a!le to mo(e$ The f#nction of forced&g#ided contacts is to ena!le the safet% circ#it to chec" the stat#s of the rela%$ 1orced& g#ided contacts are also "no)n as Ypositi(e&g#ided contactsY, Ycapti(e contactsY, Yloc"ed contactsY, or Ysafet% rela%sY$ O<(')*-2 6'*1(+1$*: '()-3 Ane t%pe of electric motor o(erload protection rela% is operated !% a heating element in series )ith the electric motor $ The heat generated !% the motor c#rrent operates a !i&metal strip or melts solder, releasing a spring to operate contacts$ .here the o(erload rela% is e/posed to the same en(ironment as the motor, a #sef#l tho#gh cr#de compensation for motor am!ient temperat#re is pro(ided$

G(:('-) P-+,(1 R-2$* S('<$+(

G(:('-) 6-+,(1 '-2$* /('<$+( (GPRS) is a pac"et oriented mo!ile data ser(ice on the 2G and 3G cell#lar comm#nication s%stem>s glo!al s%stem for mo!ile comm#nications 0GSM2$ GP S )as originall% standardi+ed !% '#ropean Telecomm#nications Standards ,nstit#te 0'TS,2 in response to the earlier CDPD

and i&mode pac"et&s)itched cell#lar technologies$ ,t is no) maintained !% the 3rd Generation Partnership Project 03GPP2$ GP S #sage is t%picall% charged !ased on (ol#me of data$ This contrasts )ith circ#it s)itching data, )hich is t%picall% !illed per min#te of connection time, regardless of )hether or not the #ser transfers data d#ring that period$ GP S data is t%picall% s#pplied either as part of a !#ndle 0e$g$, < G8 per month for a fi/ed fee2 or on a pa%&as&%o#&#se !asis$ 7sage a!o(e the !#ndle cap is either charged per mega!%te or disallo)ed$ The pa%&as&%o#&#se charging is t%picall% per mega!%te of traffic$ GP S is a !est&effort ser(ice, impl%ing (aria!le thro#ghp#t and latenc% that depend on the n#m!er of other #sers sharing the ser(ice conc#rrentl%, as opposed to circ#it s)itching, )here a certain -#alit% of ser(ice 0JoS2 is g#aranteed d#ring the connection$ ,n 2G s%stems, GP S pro(ides data rates of <?R::4 "!it4second$ 2G cell#lar technolog% com!ined )ith GP S is sometimes descri!ed as 5.$G, that is, a technolog% !et)een the second 02G2 and third 03G2 generations of mo!ile telephon%$ ,t pro(ides moderate&speed data transfer, !% #sing #n#sed time di(ision m#ltiple access 0TDM*2 channels in, for e/ample, the GSM s%stem$ GP S is integrated into GSM elease @E and ne)er releases$ The GP S core net)or" allo)s 2G, 3G and .CDM* mo!ile net)or"s to transmit ,P pac"ets to e/ternal net)or"s s#ch as the ,nternet$ The GP S s%stem is an integrated part of the GSM net)or" s)itching s#!s%stem$

S('<$+(/ *>>('(2 GP S e/tends the GSM Pac"et circ#it s)itched data capa!ilities and ma"es the follo)ing ser(ices possi!leC

SMS messaging and !roadcasting Y*l)a%s onY internet access M#ltimedia messaging ser(ice 0MMS2 P#sh to tal" o(er cell#lar 0PoC2 ,nstant messaging and presence\)ireless (illage ,nternet applications for smart de(ices thro#gh )ireless application protocol 0.*P2 Point&to&point 0P2P2 ser(iceC inter&net)or"ing )ith the ,nternet 0,P2 Point&to&M#ltipoint 0P2M2 ser(iceC point&to&m#ltipoint m#lticast and point& to&m#ltipoint gro#p calls

,f SMS o(er GP S is #sed, an SMS transmission speed of a!o#t 30 SMS messages per min#te ma% !e achie(ed$ This is m#ch faster than #sing the ordinar% SMS o(er GSM, )hose SMS transmission speed is a!o#t ? to :0 SMS messages per min#te$ P'*1*+*)/ /&66*'1(2 GP S s#pports the follo)ing protocolsCHcitation neededI

,nternet protocol 0,P2$ ,n practice, !#ilt&in mo!ile !ro)sers #se ,P(4 since ,P(? )as not %et pop#lar$ Point&to&point protocol 0PPP2$ ,n this mode PPP is often not s#pported !% the mo!ile phone operator !#t if the mo!ile is #sed as a modem to the

connected comp#ter, PPP is #sed to t#nnel ,P to the phone$ This allo)s an ,P address to !e assigned d%namicall% to the mo!ile e-#ipment$

L$2< connections$ This is t%picall% #sed for applications li"e )ireless pa%ment terminals, altho#gh it has !een remo(ed from the standard$ L$2< can still !e s#pported o(er PPP, or e(en o(er ,P, !#t doing this re-#ires either a net)or" !ased ro#ter to perform encaps#lation or intelligence !#ilt in to the end&de(ice4terminalQ e$g$, #ser e-#ipment 07'2$

.hen TCP4,P is #sed, each phone can ha(e one or more ,P addresses allocated$ GP S )ill store and for)ard the ,P pac"ets to the phone e(en d#ring hando(er$ The TCP handles an% pac"et loss 0e$g$ d#e to a radio noise ind#ced pa#se2$ H-'25-'( De(ices s#pporting GP S are di(ided into three classesC Class * Can !e connected to GP S ser(ice and GSM ser(ice 0(oice, SMS2, #sing !oth at the same time$ S#ch de(ices are "no)n to !e a(aila!le toda%$ Class 8 Can !e connected to GP S ser(ice and GSM ser(ice 0(oice, SMS2, !#t #sing onl% one or the other at a gi(en time$ D#ring GSM ser(ice 0(oice call or SMS2, GP S ser(ice is s#spended, and then res#med a#tomaticall% after the GSM ser(ice 0(oice call or SMS2 has concl#ded$ Most GP S mo!ile de(ices are Class 8$ Class C *re connected to either GP S ser(ice or GSM ser(ice 0(oice, SMS2$ M#st !e s)itched man#all% !et)een one or the other ser(ice$

* tr#e Class * de(ice ma% !e re-#ired to transmit on t)o different fre-#encies at the same time, and th#s )ill need t)o radios$ To get aro#nd this e/pensi(e re-#irement, a GP S mo!ile ma% implement the d#al transfer mode 0DTM2 feat#re$ * DTM&capa!le mo!ile ma% #se sim#ltaneo#s (oice and pac"et data, )ith the net)or" coordinating to ens#re that it is not re-#ired to transmit on t)o different fre-#encies at the same time$ S#ch mo!iles are considered pse#do&Class *, sometimes referred to as Ysimple class *Y$ Some net)or"s s#pport DTM since 200E$ A22'(//$:% * GP S connection is esta!lished !% reference to its access point name 0*P=2$ The *P= defines the ser(ices s#ch as )ireless application protocol 0.*P2 access, short message ser(ice 0SMS2, m#ltimedia messaging ser(ice 0MMS2, and for ,nternet comm#nication ser(ices s#ch as email and .orld .ide .e! access$ ,n order to set #p a GP S connection for a )ireless modem, a #ser m#st specif% an *P=, optionall% a #ser name and pass)ord, and (er% rarel% an ,P address, all pro(ided !% the net)or" operator$

. DESIGN AND DEVEPLOPMENT OF HARDWARE.

M-$: C$'+&$1 D$-%'-. -:2 $1/ *<('-)) *6('-1$*::

". DEVELOPMENT OF SOFTWARE

!.F S3/1(. S(1&6 -:2 C*:>$%&'-1$*:/ B**1 O61$*:/:7

.e can select the !ooting mode !% toggling the s)itch S2$ .hen toggling the S2 s)itch to the S=or 1lashK side the s%stem )ill !oot from on !oard =or 1lash$ .hen toggling the S2 s)itch to the S=and 1lashK side the s%stem )ill !oot from on !oard =and 1lash$

C*::(+1$:% P('$60('-)/:7
Connect the M,=,2440 !oard3s serial port to a PC3s serial port$ Connect the <D po)er s#ppl% adapter to the <D po)er s#ppl% interface on the !oard$ Connect an LCD to#ch panel 0if the #ser has one2 to the LCD interface on the !oard follo)ing the data !#s3 arro)$ Connect the M,=,2440 !oard to a PC )ith a 7S8 ca!le$

S(11$:% &6 H36(' T('.$:-) :7

To connect the M,=,2440 !oard to a host PC (ia a serial ca!le, )e sho#ld #se a sim#lated terminal$ There are man% tools a(aila!le$ * most )idel% #sed one is the MS&.indo)s3 9%per terminal$ Go to S1-'1 &f A)) P'*%'-./ &f A++(//*'$(/ &fC*..&:$+-1$*:/. Clic" on H36(' T('.$:-) and a .indo) )ill pop #p as !elo)$ Clic" on the N* !#tton$

 Clic" on the SCancelK !#tton on the follo)ing )indo)$ Clic" on the SNesK !#tton and the SABK !#tton to the ne/t step$

* pop#p )indo) )ill re-#ire %o# to name this connection$ ,n this e/ample )e t%ped 113S#. .indo)s does not accept names li"e COMF that ha(e alread% !een #sed !% the s%stem$

 *fter naming this connection another )indo) )ill re-#ire %o# to select a serial port that )ill !e #sed to connect the M,=,2440 !oard$ 9ere )e selected CAM:C

Lastl%, also the most important step is to set #p the port properties$ =oteC %o# m#st select N* in the data flo) control field other)ise %o# )ill onl%

!e a!le to see o#tp#ts$ ,n addition the !its per second sho#ld !e set to ::<200$

E:1('$:% BIOS N*1(C 1or Loading the 8oot loader, Lin#/ "ernel ,mage, tool has to !e installed on )indo)s s%stem oot 1ile S%stem D=.

S1(6 FC P#sh the !otton to the =or flash side, select !ooting from the =or flash$
$

S1(6 !C Po)er #p the !oard, %o# can enter into the 8,AS men# as follo)sC

I:/1-))$:% B**1 )*-2(':7

Start the D=. applicationQ connect the M,=,2440 !oard to a host PC (ia a 7S8 ca!le$ ,f the D=.3s title !ar sho)s USB:OK@ it indicates that the 7S8 connection is a s#ccess$ Select item L<M to start do)nloading a s#per(i(i$

Go to S7S8 PortK &f ST'-:/.$1/R(/1*'(, select a s#per(i(i

 Ance the do)nload is finished, 8,AS )ill a#tomaticall% )rite this s#per(i(i to =and 1lash3s corresponding section and ret#rn to the main men#

I:/1-))$:% L$:&A K(':():7

,n the 8,AS main men#, select item H"I to do)nload a Lin#/ "ernel

+,mage

 Go to S7S8 PortK &f STransmit4 estoreK, select a +,mage file according to AS that )e )ant to load into the M,=, 2440

I:/1-))$:% R**1 F$)( S3/1(. :7

,n the 8,AS main men# select item H%I to start do)nloading a %affs root file s%stem image$ Go to S7S8 PortK &f STransmit4 estoreK, select a file s%stem image file and start to do)nload$

 *fter the do)nload is done, 8,AS )ill a#tomaticall% )rite it in =and 1lash3s corresponding section and ret#rn to the main men#C *fter the do)nload is done, please disconnect the 7S8 connection, other)ise it co#ld ca#se s%stem crash on reset or po)er&on$ ,n the 8,AS main men#, select item H!I to re!oot the !oard ,f the !oot mode is s)itched to the =and 1lash side, the s%stem )ill a#tomaticall% !oot on po)er on$

M$:$!""# D(<()*6.(:1 B*-'2

Mini24440 is a practical lo)&cost * M@ de(elopment !oard, is c#rrentl% the highest in a cost&effecti(e learning !oard$ ,t is for the Sams#ng S3C2440 processor and the #se of professional po)er sta!le core CP7 chip to chip and reset sec#rit% permit s%stem sta!ilit%$ The mini2440 ,mmersion Gold PC8 #sing the 4& la%er !oard design process, professional, s#ch as long&)iring to ens#re that the "e% signal lines of signal integrit%, the prod#ction of SMT machine, mass prod#ctionQ the factor% ha(e !een a strict -#alit% control, )ith (er% detailed in this man#al can help %o# -#ic"l% master the de(elopment of em!edded Lin#/ and .inC' process, as long as there is C lang#age !ased on the general entr% to t)o )ee"s$

Mini2440 Development Board:-

M$:$!""# D(<()*6.(:1 B*-'2 H-'25-'( R(/*&'+(/ F(-1&'(/:

CPU P'*+(//*' & Sams#ng S3C2440*, fre-#enc% 400 M9+, the highest <33 M9+ SDRAM M(.*'3 & An&!oard ?4M8 SD *M & 32&!it data !#s & SD *M cloc" fre-#enc% #p to :00 M9+ FLASH M(.*'3 & An&!oard ?4 M8 =*=D flash, Po)er&do)n non&(olatile & An&!oard 2 M8 =A flash, Po)er&do)n non&(olatile, 8,AS has !een installed LCD D$/6)-3 & An&!oard integrated 4&)ire resisti(e to#ch screen interface, %o# can directl% connect 4&)ire resisti(e to#ch screen & S#pport for !lac" and )hite, 4 gra%&scale, :? gra%&scale, 2<?&color, 40@?&color ST= LCD screen si+e from 3$<Q to :2$:Q, :024/E?; pi/els screen resol#tion can !e achie(ed & S#pport for !lac" and )hite, 4 gra%&scale, :? gra%&scale, 2<?&color, ?4B&color, Tr#e Color T1T LCD screen si+e from 3$<Q to :2$:Q, :024/E?; pi/els screen resol#tion can !e achie(ed$ & Standard config#ration for the ='C 2<?B&color 240/32043$<Q T1T Tr#e Color LCD Screen )ith to#ch screen$ & Leads to a :2 D po)er s#ppl% on&!oard interface, for the large&si+e T1T LCD :2 D CC1L !ac"light mod#le 0in(erting2 po)er s#ppl% I:1('>-+(/ -:2 R(/*&'+(/ & : :00 M!ps 1ast 'thernet U&4< interface 0#sed net)or" chips DM@0002 & 3 Serial ports & : 7S8 host & : 7S8 sla(e 08&t%pe interface2 & : SD card storage interface & : channel stereo a#dio o#tp#t interface, all the )a% microphone interface

& : 2$0mm pitch :0&pin UT*G interface & 4 7ser L'Ds & ? 7ser !#ttons 0)ith lead !loc"s2 & : !#++er P.M control & : adj#sta!le resistor, analog&to&digital con(erter for *4D test & : ,2C&!#s *T24C0; chip for ,2C&!#s test & : 2$0 mm pitch 20&pin camera interface & An&!oard real&time cloc" !atter% & Po)er interface 0< D2, )ith po)er s)itch and indicator light S3/1(. C)*+, S*&'+( & :2 M9+ passi(e cr%stal R(-)7T$.( C)*+, & ,nternal real&time cloc" 0)ith lithi#m !atter% !ac"&#p2 EA6-:/$*: I:1('>-+( & : 34&pin 2$0 mm GP,A interface & : 40&pin 2$0 mm s%stem !#s interface D$.(:/$*: & :00 mm / :00 mm O6('-1$:% S3/1(. S&66*'1 & Lin#/ 2$?$2@ & .indo)s C' $='T <$0

I:1('>-+(/ -:2 E&.6('/ L-3*&1:7

E&.6(' D(/+'$61$*: There is onl% one de(elopment of on&!oard j#mper U2, it is #sed to select the inp#t panel LCD dri(e (oltage, in the standard config#ration, the access for ='C 3$<g LCD, (oltage selection for < D$ I:1('>-+(/ L-3*&1

Mini2440 interface la%o#t is sho)n !elo) it in a (er% compact area of :00 mm / :00 mm delicate arrangement of open made from a (ariet% of commonl% #sed interface, and also leads to the need for de(elopment and testing of the s#rpl#s of the ,4A ports and !#s interfaces$

D(<()*6.(:1 B*-'2 /(1/ &6 -:2 +*::(+1/:7

S1-'1&6 M*2( S()(+1$*: To choose the de(elopment !oard start#p mode, S2 D,P&s)itch is determined, Depending on the target !oard tips$ S)itch S2 to h=A Y side logo, the s%stem )ill start )ith the =A flash$ S)itch S2 to h=*=DY side logo, the s%stem )ill start )ith the =*=D 1lash$ The =A 1lash and =*=D 1lash of the de(elopment !oard has !een !#rned into the Same 8,AS from factor% 0!eca#se the 8,AS at the same time s#pport for !oth flash, j#st after the !oot of different manifestations, please refer to Yde(elopment !oard 8,AS feat#re and #se thatY2,

S2 has !een recei(ing side of =*=D flash, the s%stem !oot from a start#p operation of =*=D flash s%stem$ EA1(':-) I:1('>-+( C*::(+1*' & Please #se o#r direct serial line to connect the Mini24404s serial port 0 and PC4s$ & 7se o#r crosso(er ca!le to the net)or" interface Mini2440 connected )ith the PC$ & 7se o#r < D po)er adapter to connect to the < D inp#t soc"et on the !oard$ & Spea"ers or headphones to pl#g access on&!oard a#dio o#tp#t port 0green2$ & ,f %o# ha(e LCD screen, follo) the direction of head data and the LCD interface Connected to Mini2440$ & Connect Mini2440 )ith 7S8 ca!le connection and the PC$

WORKING PRINCIPLE: The proposed ma"es #se em!edded !oard )hich ma"es #se of less po)er cons#mpti(e and ad(anced micro controller li"e S3C2440$ S3C2440 is a Sams#ng compan%3s microcontroller, )hich designed !ased on the str#ct#re of * M @20T famil%$ This microcontroller )or"s for a (oltage of 63$3D DC and at an operating fre-#enc% of 400 M9+, The ma/im#m fre-#enc% #p to )hich this micro controller can )or" is <33 M9+ .e cannot get S3C2440 microcontroller indi(id#all%$ .e )ill get it in the form of 1 ,'=DLN * M !oard else, )e can call it as M,=, 2440 !oard$ ,n order to )or" )ith * M @ micro controllers )e re-#ire 3 things$ The% are as follo)s$ :$ 8oot Loader 2$ Bernel 3$ oot 1ile S%stem B**1 )*-2('C The main f#nctionalit% of !oot loader is to initiali+e all the de(ices that are present on the mother!oard of M,=, 2440 and at the same time to find o#t )hether an% pro!lem or an% other fa#lt is there in the de(ices that are present on that mother!oard of M,=, 2440$ The other feat#re of the !oot loader is to find o#t )hat are the different operating s%stems that are present in the standard storage de(ices and to sho) it on to the displa% de(ice so that #ser can select !et)een the operating s%stems into )hich he )ants to enter$

Ane other feat#re of the !oot loader is lo load operating s%stem related files !%te !% !%te into the temporar% memor% li"e *M$ ,n o#r c#rrent project, )e are #sing !oot loader li"e S#per (i(i, )hich is M,=, 2440 specific$

K(':(): The core part of an operating s%stem )e can call li"e "ernel$ Aperating
s%stem )ill perform its f#nctionalities li"e 1ile management, Process management, Memor% management, =et)or" management and ,nterr#pt management )ith the help of the "ernel onl%$ Bernel holds the de(ice related dri(ers that are present on the mother!oard$ 1 ,'=DLN * M !oard s#pports for operating s%stems li"e SNM8,*=, *=D A,D, 'M8'DD'D L,=7L, .,=C'$ 9o)e(er, in all these operating s%stems 'M8'DD'D L,=7L )ill pro(ide high sec#rit% to dri(ers and files$ Therefore, in o#r c#rrent project )e are ma"ing #se of "ernel of 'M8'DD'D L,=7L )ith )hich de(ice related dri(ers that are present on the mother!oard of 1 ,'=DLN * M !oard )ill a#tomaticall% come )hen )e load 'M8'DD'D L,=7L related "ernel$ R**1 F$)( S3/1(.C 1ile s%stem )ill tell ho) files arrangement there inside the internal standard storage de(ices$ ,n em!edded Lin#/, "ernel treats e(er%thing as a file e(en the inp#t and o#tp#t de(ices$ ,n em!edded Lin#/, oot is the parent director% it contains other s#! directories li"e de(, li!, home, !in ,s!in ,media ,mnt ,temp ,proc , etc, opt and etc$ *ccording to o#r application, )e )ill interface some e/ternal de(ices also$ *ll the de(ices means internal de(ices that are present on the mother!oard of M,=, 2440 )ill get their corresponding dri(ers )hen )e load 'm!edded Lin#/ related "ernel$ 9o)e(er, these de(ice dri(ers re-#ire micro controller related header files and some other header files, )hich )ill !e present in the li! director%, )hich is present in the root director%$ ,n addition, the de(ices related dri(ers )o#ld !e present in the de( director%, )hich is again present in the

root director%$ Therefore, )hene(er )e )ill load the oot 1ile S%stem then )e )ill get different directories, )hich )ill !e helpf#l to the "ernel$ So comp#lsoril%, )e need to load the oot 1ile S%stem$ M,=, 2440 specific Jtopia$ The essential programs that are re-#ired in order to )or" )ith M,=, 2440 li"e 8oot loader, 'm!edded Lin#/ related Bernel, oot 1ile S%stem )ill !e loaded into the =A flash )hich is present on the M,=, 2440 !oard itself$ The program related )ith the application )ill !e loaded into =*=D flash, )hich is also present on the M,=, 2440 !oard itself$ 8% #sing !ootstrap s)itch that is present on the M,=, 2440 )ill help the #ser to select either =A or =*=D flash$ *fter that !% #sing D=. tool )e can load 8oot loader, 'm!edded Lin#/ related "ernel and oot 1ile S%stem into =A flash !% #sing 7S8 ca!le and the application related program into =*=D flash$ Ance loading e(er%thing into M,=, 2440 !oard it starts )or"ing !ased on the application program that )e ha(e loaded into the =*=D flash$ So controlling station )aits for the remote data that is coming from the remote location$ To pro(ide the sec#rit% for home appliances )e are #sing * M@ !oard )hich is interfaced to to#ch screen LCD, sensors li"e temperat#re and P, sensor and GP S$ 1irst of all the * M@ !oard )ill stores 3 person3s image and their information into its memor%$ 3 options are present on to#ch screen LCD li"e train, capt#re and recogni+e$ ,f an% person is entered press train !#tton on LCD as )ell as press capt#re !#tton$ *fter pressing capt#re !#tton t)o options )ill appear li"e add and delete$ 8% pressing the add !#tton the )e!cam )hich is connected to * M@ !oard )ill capt#res the person images #p to :< times$ *fter :< images the train !#tton )ill a#tomaticall% goes lo)$ =e/t press recogni+e !#tton for comparing capt#red image )ith stored images$ ,f capt#red image is matched )ith stored images then the door a#tomaticall% )ill open !% #sing rela%$ ,f capt#red oot 1ile S%stem is oot

image is not matched )ith stored images then the capt#red image )ill !e sent thro#gh GP S in the form of MMS$ ,f room temperat#re is increased or an% dangero#s gas is present then the temperat#re and smo"e sensor )ill detect it and displa% it on to#ch screen LCD$

$ $

J. CONCLUSION

CONCLUSION
The project SA L*5 C*/1 GSM/GPRS B-/(2 W$'()(// H*.( S(+&'$13 S3/1(.K has !een s#ccessf#ll% designed and tested$ ,t has !een de(eloped !% integrating feat#res of all the hard)are components and soft)are #sed$ Presence of e(er% mod#le has !een reasoned o#t and placed caref#ll% th#s contri!#ting to the !est )or"ing of the #nit$ Secondl%, #sing highl% ad(anced * M@ !oard and )ith the help of gro)ing technolog% the project has !een s#ccessf#ll% implemented$