Digital Phase Locked Loops

Mike DeLong 13 May 2004

Topic The topic for this technical paper will be FP ! i"ple"entation of digital phased locked loops# Objective The ob$ecti%e of this paper is to e&plore the history' f(nctionality' (ses and FP ! i"ple"entation of digital phase locked loops# Background Phase locked loops were first written abo(t b(t not i"ple"ented in the early 1)30*s by a French engineer na"ed de +ellesci,e# -n 1)32 a gro(p of +ritish engineers started de%eloping a recei%er based (pon de +ellesci,e*s paper that wo(ld be si"pler than the s(perheterodyne recei%er that was the best a%ailable at the ti"e# Their si"ple designe incl(ded a local oscillator' a "i&er and an a(dio a"plifier# .hen the inp(t signal and the local oscillator were "i&ed at the sa"e phase and fre/(ency the original a(dio was reprod(ced fro" its "od(lated for"# The design was %ery cle%er b(t had its drawbacks# 0eception after a period of ti"e beca"e diffic(lt d(e to fre/(ency drift of the local oscillator# Their sol(tion to this proble" incorporated a phase detector co"paring the inp(t fre/(ency to the fre/(ency of the local oscillator# The phase detector wo(ld o(tp(t a differential %oltage that was fed back into the local oscillator keeping it at the correct fre/(ency# This techni/(e was the sa"e techni/(e that was de%eloped for electronic ser%o control syste"s at the ti"e# This was the first iteration in the e%ol(tion of the phase locked loop 1PLL2# enerally considered better than the s(perheterodyne recei%er' the new phase locked loop recei%er did not see widespread adoption d(e to the fact that cost of the PLL

o(tweighed it ad%antages# .ith the de%elop"ent of the integrated circ(it' the PLL beca"e a%ailable in low cost -3 packages# This wo(ld dri%e the cost down and allow the PLL to be adopted in applications o(tside of speciali,ed sit(ations where the ad%antages o(tweighed the cost# -n the 1)40*s the PLL started seeing widespread (se in hori,ontal and %ertical sweep oscillators in tele%ision sets# 4ince then it has been adopted in !M and FM de"od(lators' F45 decoders' "otor speed controls and $(st abo(t anything that in%ol%es a constant fre/(ency that needs to be tracked# Types of Phased Lock Loops +efore detailed disc(ssion of the FP ! i"ple"entation of the PLL can be e&plored' the different types of phase locked loops need to be identified# There are basically three types of phase locked loops' the PLL' DPLL and !DPLL# First is the PLL# This is basically the original design wrote abo(t in the early 630s by de +ellesci,e# -t consists of all analog co"ponents and was the standard loop for "any years# The ne&t type of loop is the DPLL or the digital phase locked loop# This new %ersion of the PLL was de%eloped in the 1)70*s and contained both analog and digital parts# 8n "ost of these type of phase locked loops' the phase detector was digital and the oscillator and loop filter on the back end was analog# The !DPLL or all digital phased locked loop ca"e along a few years after the DPLL and was an i"ple"entation of the PLL with all digital co"ponents# 4ince the FP ! is an e&cl(si%ely digital de%ice' the type of de%ice that will be researched in this paper will be the !DPLL#

Phase Locked Loop Basics !ny phase locked loop "(st ha%e three basic co"ponents' the phase detector' the loop filter and the %oltage9controlled oscillator# The diagra" below shows the basic set(p for the PLL#

The co"ponents will differ depending on the chosen type of PLL# The phase co"parator portion of the loop co"pares the signal generated inside of the phase locked loop to the recei%ed signal# -n an analog PLL the co"parator is si"ply a "(ltiplier# The o(tp(t fro" the phase co"parator will consist of a fre/(ency co"ponent at twice the intended locking fre/(ency and an offset co"ponent e/(aling the sine of the phase difference between the two signals#

The low pass filter in a PLL filters o(t the (nwanted do(ble fre/(ency co"ponent which contains no (sef(l infor"ation# The constant phase offset is then passed on to the %oltage9controlled oscillator setting it to and keeping it at the correct fre/(ency# The !DPLL works differently b(t based (pon the sa"e concept# For a digital phase locked loop' the inp(t signal is so"e type of bit strea"# The bit strea" can ha%e a %ariety of so(rces incl(ding an analog to digital con%erter or a reg(lar bit stea" with which the recei%er "(st synchroni,e# F(rther 8peration of the !DPLL will be disc(ssed in the ne&t section# All Digital Phase Locked Loop Design and Implementation -n the pre%io(s section' the operation of a classic analog phase locked loop was disc(ssed# !nd as stated before' operation has the sa"e concept b(t works differently# The three "ain parts of the phase locked loop are still present in the !DPLL b(t they are designed and constr(cted differently d(e to the fact that the signals that they deal with are different and a FP ! is digital# The inp(t to the !DPLL is a digital strea" nor"ally fro" an analog to digital con%erter or a clock# -n this section' the indi%id(al co"ponents of the !DPLL will be broken down into their r(di"entary co"ponents 1i#e# co(nters' control bits' registers2# These are the types of co"ponents that can b(t i"ple"ented on FP !*s therefore this section will be abo(t !DPLL loop design and FP ! i"ple"entation# The first stage of the !DPLL is the phase detector as it was for the PLL# -n the case of the !DPLL the phase detector consists of either an :;80 gate or an edge triggered phase detector# The :;80 type is si"ply an :;80 logic gate#

+elow is representation of this kind of gate#

This type of detector locks itself )0 degree behind the phase of the inp(t signal# Two drawbacks to this type of phase detector is that it has a phase error li"it of < or 9 )0 degrees and it is not sensiti%e to edges in the signal b(t rather the flat section# +elow is an e&a"ple of the =locked> state#

8ne big ad%antage of this type of phase detector is its si"plicity beca(se it consists of only one logic gate#

The other type of phase detector is and edge triggered de%ice# This de%ice is an edge triggered ?5 de%ice# -ts locked state is 1@0 degrees behind the phase of the inp(t signal as shown below#

The de%ice is constr(cted as shown below#

4ince this de%ice is sensiti%e to the edges' the clock can be eli"inated# This de%ice can be (sed in con$(nction with a co(nter to o(tp(t the phase error# This co"bination is shown below#

A0 A1

? C 5

:nable 3o(nter 3lock MF0

-n the config(ration shown abo%e' the A0 and A1 are binary %al(es# The MF0 is an integer "(ltiple 1M2 of the reference signal F0# The co(nter is reset on the rising edges of A0 and is gated when the o(tp(t of C is logic 1# The o(tp(t B of the co(nter is proportional to the phase error# The ne&t stage of the loop is the loop filter# The loop filter that always works with the :;80 and the edge triggered phase detectors is the 5 co(nter# The 5 co(nter is shown below#

5 3lock APDDB

AP 3o(nter Down 3o(nter

3arry +arrow

This loop filter contains two separate co(nters both of which are co(nting (pward# The APDDB bit deter"ines which co(nter is r(nning at any "o"ent# The 5 clock is MEF0 where M is a large integer 1@' 1F' 322 of the reference signal F0# The carry and borrow o(tp(ts are the "ost significant bits of the co(nters and are only high when the contents of a partic(lar co(nter are greater than 5D2# These %al(es are (sed to control the D38 1digitally controlled oscillator2# The co(nters are reset when the contents reach a %al(e of 5 G 1# The final part of the loop is the D38 1digitally controlled oscillator2# -n a digital syste"' the oscillator is a "odified co(nter# This part of the loop is shown on the ne&t page#

The D:30 and -B30 inp(ts are the carry and borrow o(tp(ts fro" the 5 co(nter respecti%ely# This part of the loop operates in con$(nction with a di%ide by B co(nter that works to slow down this accelerated clock# The 2BFc inp(t is the center fre/(ency of the loop 1Fc2 "(ltiplied by 2B where B is the %ariable in the di%ide by B co(nter# The two co"ponents working together are shown below#

The D:30 inp(t to the "odified co(nter ca(ses the take one half9cycle o(t# 3on%ersely' the -B30 inp(t ca(ses one half9cycle to be taken o(t of the o(tp(t# The ad$(sted wa%efor" is shown on the ne&t page#

This ad$(st"ent is constantly ass(ring that the cycles stay phased locked# !ll of the co"ponents disc(ssed abo%e are looped together for"ing the phase locked loop# The loop constantly ad$(sts the prod(ced wa%e (ntil it is in phase lock with the inp(t wa%e# +elow is the entire loop wired together#

The phase detector co"ponent can be either disc(ssed "ethods b(t the rest of the co"ponents are as they are shown#

ses of All Digital Phased Locked Loops The "ain (ses for this type of digital phase locked loop are clock synchroni,ation# 3locks can be "atch or signals with e"bedded clocks 1s(ch as Manchester :ncoding2 can be easily synchroni,ed to# !lso' any repeatable code 1M93ode2 co(ld be synchroni,ed with a "odified %ersion of this loop# For the loop to synchroni,e with a repeatable code' a code generator with an identical code as the (nit in the recei%er "(st be in the loop generating the internal code# The phase detector wo(ld also ha%e to be "odified to handle long strings of bits# !P"A Implementation Technically the topic of this paper' the FP ! i"ple"entation section will be relati%ely short# The sections preceding this section spoke abo(t the indi%id(al co"ponents and their workings# 4ince the co"ponents ha%e been broken down into their r(di"entary parts in the pre%io(s disc(ssion' the i"ple"entation portion beco"es relati%ely easy# :ach part of the loop will be spoken briefly abo(t how it co(ld be i"ple"ented# The two types of phase detectors disc(ssed earlier in this paper ha%e relati%ely si"ple i"ple"entations# The :&cl(si%e9;80 gate has a si"ple' single gate i"ple"entation# The other type is a ?5 flip flop# :arlier in the paper two D flip flops and a ;80 gate were (sed to b(ild this de%ice# The second part of that phase detector was a co(nter with a clock enable and a reset# This is an -P 3ore part a%ailable in the ;ilin& library or a si"ply coded part consisting of se%eral e"bedded -F9:L4-F loops# !n e&a"ple of this code is shown below#

-F 1reset H 61*2 TI:B 3o(nt JH 0K :L4: -F 1clkLen H 61*2 TI:B 3o(nt JH 3o(nt < 1K :L4: BALLK :BD -FK :BD -FM The second part of this loop is the 5 3o(nter 1loop filter2# This part consists of two reset able' clock enabled co(nters# The i"ple"entation for both of these co(nters is the sa"e as the co(nt disc(ssed abo%e e&cept that the reset is based on a "a&i"(" %al(e and both co(nters "(st be reset si"(ltaneo(sly# The ne&t part of this loop is the D38 1digitally controlled oscillator2# -n this loop' it is si"ply a fast r(nning clock that is "odified by adding and deleting half cycles# This co(ld be done with a section of code or a "odified co(nter "ade to respond to the -B30 and D:30 bits# The last part of this loop is the di%ide by B co(nter# This is a si"ple co(nter "ade to switch its o(tp(t logic le%el after B clock cycles# -t can be seen that the FP ! i"ple"entation of a de%ice like the one described in this paper co(ld be relati%ely easily b(ilt# 8nce the indi%id(al parts are analy,ed and broken down' it can be seen how to b(ild the" in a digital syste"# !urther #tudies !n interesting research topic to branch off of this paper wo(ld be an all digital phase lock loop that locks to analog signals# The loop in this research paper synchroni,es only digital type signals# !n analog signal co(ld be taken thro(gh the analog to digital con%erter and locked to in the loop before being retranslated thro(gh the digital to analog

con%erter back to analog# !ll of the analog "ath in the analog phase lock loop co(ld be translated to discrete "ath and done in an FP !# $onclusion ! digital phase locked loop can ha%e "any (ses# -n spread spectr("' the code or clock synchroni,ation is an i"portant step in the decoding process# -f the data bits or clock bits are o(t of phase then the decoded bits co(ld be decoded incorrectly# !lso' if the decoder tries to decode the bits away fro" the center of the bits then slight %ariations co(ld ca(se the decoder to decode the wrong bit# The loop co(ld also be (sed to synchroni,e to a repeatable code# This co(ld be i"portant if the dispreading code needed synchroni,ed to the inp(t#

Bibliography Troha' Donald' # =Digital Phase9Locked Loop Design Asing 4BN4D74L42)7#>T!pplication Botes N May 200 httpMDDfoc(s#ti#co"DlitDanDsdla00NbDsdla00Nb#pdf Digital Phase Locked Loop# N May 2004 httpMDDwww#erg#abdn#ac#(kD(sersDgorryDco(rseDphy9pagesDdpll#ht"l Oan 0oon' Tony# Phase9Locked Loops# N May 2004 www#(og(elph#caDPantoonDgadgetsDpllDpll#ht"l