Amorphous silicon/amorphous silicon carbide heterojunctions applied to memory device structures

I. Sakata, M. Yamanaka, K. Nagai, T. Sekigawa and Y. Hayashi

Indexing terms: Amorphour semiconductors, Silicon, Silicon carbide, Semiconducrorjunctions. Semiconductor srorage. EPROM

the stored electrons (holes) and thus the memory is erased. Capasso et al. [2] reported similar memory devices based on AlGaAsiGaAs HJ. However, excessive leakage current made it impossible to electrically erase the memories and a visible light pulse was instead used to erase the memory.
Sample preparation: Undoped a-Si:H and a-SiC:H films were deposited on n- or p-type (100) c-Si substrates with a resistivity of

It has been proposed and experimentally confirmed that bandengineered hydrogenated amorphous silicon (a-Si:H)/ hydrogenated amorphous silicon carbide (a-SiC:H) heterojunctions on c-Si can he applied to electrically programmable and erasable memory devices. A test diode with the structure c-Silgraded a-SiC:H/a-Si:H/uniform a-SICWAI exhibits a large hysteresis in the C-V characteristic with a retention time of 0.8s at room temperature.
Introduction and device principle of operation: Although the application of the heterojunction (HI) composed of hydrogenated amorphous silicon (a-Si:H) and hydrogenated amorphous silicon carbide (a-SiC:H) has been limited to optoelectronic devices [I], this structure also has the following advantages [I] when applied to electronic devices:

0.5 - 1.58cm by an RF glow discharge method [I] at substrate temperature of 200C . Source gases were silane (SiH,) diluted with hydrogen (H,) for a-Si:H, and mixture of methane (CH,), SiH, and H2 for a-SiC:H. Aluminum (Al) dots with an area of 7.5 x IO-'crn2 were deposited as metal gates. AI was also evaporated onto the back surface of c-Si substrate to form an Ohmic contact. The thicknesses of the graded a-SiC:H layer, the a-Si:H layer, and the uniform a-SiC:H layer were 500, 100, and 600 A, respectively. The values of the optical bandgap E, [3] of the a-Si:H layer and the uniform a-SiC:H were 1.7 and 2.4eV, respectively. The value of E, was linearly vaned between 1.7 and 2.4eV in the graded a-SiC:H layer by changing the flow rate of CH,.

(i) bandgap engineering is possible by varying the carbon content of a-SiC:H (ii) an abrupt interface can be fabricated (iii) both electrons and holes can conduct through the material when it is close to intrinsic (iv) leakage currents are low because of the high resistivity.
positive bias

-3

-2

-1

0 voltage, V

Fig. 2 Capacitance-voltage characteristics of sample diode fabricated on n-type substratc with structure shown in Fig. I

f = 100kHz, dark, 0.4V/s

Arrows in figure denote directions 01.bias sweep

zero bias

negative bias

a-Sic H

a-SIC ti

Fig. 1 Schemaric band diagrams o f proposed a-SiC:H/a-Si:H heterojunction structure

e and h denote electrons and holes, respectively

In this Letter we propose and experimentally confirm that the HJ structure shown in Fig. 1 can be applied to floating-gate memory devices. Device operation can be described as follows. With the application of positive (negative) bids to the metal gate, electrons (holes) are efficiently injected from the crystalline Si (c-Si) substrate into the thin a-Si:H layer through the compositionally graded a-SiCH layer. When the bias voltage is restored to zero, injected electrons (holes) can be stored in the a-Si:H layer because of the discontinuity of the conduction (valence) band edges at the a-SiC:H/a-Si:H interfaces. By applying a negative (positive) gate bias, holes (electrons) are injected from the substrate into the aSi:H layer through the graded a-SiC:H layer and recombine with

Results and discussion: Fig. 2 shows the capacitance voltage (C-V) characteristics of the sample diode with the n-type c-Si substrate measured at IOOkHz, at 297K, and in the dark region. The sweep rate of the ramp bias applied to the gate was 0.4V/s. The variation of the measuring frequency between I and lO0kHz had little effect on the C-V properties. The capacitance at 3V (470pF) is in fairly good agreement with the calculated capacitance of stacked insulator layers when we assume that the dielectric constants E of a-Si:H and a-SiC:H are 12 and 8, respectively, and the value of E changes linearly with position in the graded a-SiC:H. Thus we can say that the C-V property in this figure is MIS (metal-insulator-semiconductor) -like. A fairly large hysteresis (memory window) is observed; the application of a positive (negative) gate bias voltage results in the positive (negative) shift of the C-V curve. This suggests that both electrons and holes are injected from c-Si substrates into the stacked amorphous layers and stored in some part of the layers. The density of slow states calculated from the hysteresis in Fig. 2 was 4.7 x 10"cm'. The width of the hysteresis increased with the sweep rate of bias voltage which was varied between 0.1 and 1V/s. When either uniform a-SiC:H or graded aSiC:H was used as an insulating layer, a large hysteresis was not observed; the presence of the undoped a-Si:H layer sandwiched between the a-SiC:H layers is essential for obtaining a large memory window. We speculate that traps in the a-Si:H and/or at the interface between a-Si:H and a-SiC:H are acting as memory sites. Essentially the same C-V properties were observed also for the diodes with p-type c-Si substrates. The band alignments at the a-SiC:Wa-Si:H interface have not yet been determined in the present samples. However, we speculate that a band offset exists at both band edges in the present samples, as schematically shown in Fig. 1, because both electrons and boles are stored in the a-Si:H layer. The switching characteristics of the sample diodes were studied by varying the width and/or the sign of injection pulses with a magnitude of 3V. When the majority carriers are injected from the c-Si substrates, the switching time, i.e. the time necessary to reach

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the steady-state capacitance, was shorter than the detection limit ( l o p ) of the capacitance meter used in the experiments. On the other hand, the switching time was longer than 1 s in the case of minority carrier injection. The ratio of these switching times (-lo6) coincides with the rectifying ratio of diode currents at 3V in the c-Si/graded a-SiC:H/AI structure. This is evidence that majority and minority carriers from the c-Si substrate indeed conduct through the graded a-SiC:H layer and are injected into the a-Si:H layer. These switching characteristics were observed irrespective of the conduction type of the substrates. The width of the memory window decreases with time when the diode is left under zero bias conditions after turning off the injection pulse. The window becomes half of the initial value after 0.8s and we define here this time as the retention time of the present sample diode. This result suggests that the present structure can be used as a component of dynamic random access memories (DRAMS) [4] at room temperature.
Conclusion: We have proposed that hand-engineered a-Si:WaSiC:H heterojunctions on c-Si can be applied to electrically pro-

unbounded space. Various methods have been proposed to permit infinite plane wave propagation in the TLM mesh without distortion [2-41. In all of these applications however, results have been presented only for the case of the incident plane wave propagating along a co-ordinate axis in a Cartesian TLM mesh. In this Letter, a technique similar to the methods used in [2-41 is implemented in the three-dimensional symmetrical condensed node TLM mesh. The method is then applied to scattering from a test object for various off axis angles of incidence.
mesh boundary

,--_-f-______--__-____.
I

connecting boundary

I
I

I I
I

grammable and erasable memory devices because both electrons and holes can conduct through undoped a-SiC:H and can be stored in a-Si:H. We have fabricated test diodes with the structure of c-Si/graded a-SiC:H/a-Si:H/uniform a-SiC:H/AI and observed a large hysteresis in the C-V characteristic with a retention time of 0.8s at room temperature. It has been confirmed that the graded a-SiC:H and the a-Si:H act as the carrier injection layer and the memory trap site, respectively.
Acknowledgment: The authors thank E. Suzuki for stimulating discussions. This work has been carried out under the contract (No. E-TT0107) from the Agency of Industrial Science and Technology of Japan.
0 IEE 1994 Electronics Letters Online No: 19940478

I I I I

scattered field reaion

Fig. 1 Separation of TLM mesh into total and scattered/ield regions

node( i,j ,k )

7 March 1994
l v ! 9

I. Sakata, M. Yamanaka, K. Nagai, T. Sekigawa and Y. Hayashi (Device Synthesis Section, Electrotechnical Laboratory, Umezono 1-1-4, Tsukuba, Ibaraki 305, Japan)

I
lo~12j

node ( l , J , k * l ) (total field region)

References
KANICKI, I.: 'Amorphous and microcrystalline semiconductor devices: Optoelectronic devices' (Artech House, Boston, 1991) 2 CAPASSO, F., BELTRAM, F , MALIK, R.J., and WALKER, J.F.: 'New floating-gate AlGaAsiGaAs memory devices with graded-gap electron injector and long retention times', IEEE Electron. Device Lett., 1988,9, pp. 377-379 3 MOTT. N.F. and DAVIS, E.A.: 'Electronic processes in non-crystalline materials' (Clarendon Press, Oxford, 1979) 2nd Edn., p. 291 4 SAH. c.T.: 'Fundamentals of solid state electronics' (World Scientific, Singapore, 1991) p. 612

Fig. 2 Connection of TLM nodes at boundary between total and scatteredfield regions

Plane wave source: To implement the plane wave source condi-

General electromagnetic scattering analysis by TLM method

F.J. German
Indexing terms: Elecrromagnetic wave scattering, Transmission line matrix method

tions, the TLM mesh is divided into a total field region and a scattered field region as shown in Fig. 1. The fields in the total field region consist of the sum of the incident plane wave fields and the fields scattered from the object under consideration which is completely contained in this region. In the scattered field region, only outward propagating scattered energy is present. The sonrce conditions for the plane wave excitation are enforced on the boundary separating these regions. As described in [3] for the two-dimensional case, the procedure consists of adding the known plane wave field contribution to pulses passing from the scattered field region to the total field region, and subtracting the plane wave contribution from the pulses travelling from the total field region to the scattered field region. The fields associated with an arbitrarily polarised plane wave are described analytically and can be translated into TLM voltage pulses for use in the TLM connection algorithm. Consider the SCNs shown in Fig. 2. The node in the back lies in the scattered field region and the node in the front is in the total field region. The voltage pulses shown in the Figure must be modified as they pass from one region to the other in order to incorporate the plane wave source. Specifically, the plane wave component must be subtracted from "V8'(i,j,k)and .V{(i,j,k) and must be added to "V2'(i,j,k + 1) and .V[(i,j,k + 1) as these pulses become incident on the adjacent node. Algorithmically, this connection procedure can be expressed as

The symmetrical condensed node TLM method is applied to the problem of electromagnetic scattering from objects illuminated by a plane wave at off axis angles of incidence. A mesh division algorithm is described for implementing the plane wave source. Good agreement with measured data is demonstrated.
Introduction: The symmetrical condensed node (SCN) transmission line matrix (TLM) method is well established for the solution of complex electromagnetic field problems [I]. The technique has been used by several authors to solve the problem of electromagnetic scattering from objects illuminated by a plane wave in

,+1VZ?i,j,k+

l)=nV;(i>j>k) + ~ [ n + l / z E : ~ U ( i , j , k + & )
+Ilon+l/2H,Pw(i,j,k

+ ill
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