Srinivasa Chaitanya Gadigatla

1255 E University drive, Apt 304,Tempe, AZ- 85281 E-Mail: sgadigat@asu.edu Phone No: 602-327-1577
OBJECTIVE
Full-time career in the field of digital/analog circuit design, layout, modeling, verification and testing
EDUCATION
• Master of Science in Electrical Engineering Dec 2009
Arizona State University, Tempe, AZ GPA: 3.74/4.0
• Bachelor of Engineering in Electronics and Communications Engineering Apr 2007
Andhra University, Visakhapatnam, AP, India GPA: 4.0/4.0
RELEVANT COURSE WORK
Switched- Capacitor Analog design Nyquist rate Analog to Digital converters
Oversampled sigma delta data converters VLSI High speed I/O circuits
Modeling and Design techniques for sub 90nm CMOS Advanced Analog Integrated circuits
VLSI design Switched logic circuits with VHDL coding
Computer Architecture and Organization Microprocessors programming and Interfacing
Digital Signal Processing with MATLAB Fundamentals of Solid-state devices
TECHNICAL SKILLS
• Simulation and Modeling tools: Cadence Design Suite, Hspice, Xilinx ISE, Lattice isp LEVER, Modelsim,
J-DSP simulator, MATLAB, LabView
• Programming : Verilog, Verilog-A, VHDL, 8085 Assembly language ,C, C++, PHP, Perl, SQL, Visual basic
• Operating Systems: Windows (XP and Vista), Mac OS , MS-DOS, UNIX, Linux
WORK EXPERIENCE
• Graduate Research Assistant, Arizona State University Jan 2008 – Present
Implemented computationally intensive algorithms in an efficient manner to work in real time using MATLAB
Effectively debugged and implemented new features in a GUI using Visual Basic
Upgraded and maintained a text file database by running Perl scripts through UNIX shell
• Summer Intern, Vital Systems Inc, Phoenix, AZ, USA Jun 2008 – Aug
2008
Wrote Verilog RTL codes for counters and selection logic to realize a custom application on a Lattice FPGA
Did timing analysis and generated bit stream files using Lattice ispLEVER software
• Embedded applications Intern, Vector Institute, Hyderabad, India Jan 2007-Aug
2007
Wrote RTL codes and test benches in VHDL and simulated their functionalities using Xilinx ISE simulator
Analyzed and verified the operation of system blocks using logic analyzers and oscilloscopes
PROJECTS
• Design and layout of a 32 bit entry, 32 bit wide register file (SRAM) [Cadence Suite, TSMC 0.24um CMOS]
Objective is to optimize the circuit for the lowest possible energy delay product
Sized and designed latches, address decoders, SRAM cells and read/write circuitry
Drew a LVS and DRC clean layout and extracted parasitic capacitances from layouts
• Design of a VLSI Phase Locked Loop [Cadence Suite, TSMC 0.18um
CMOS]
Goal is to design a PLL for a data recovery rate of 1.6 GHz with a reference frequency of 100 MHz
Designed and simulated internal blocks of PLL like VCO, Phase detector, frequency divider and LPF
Estimated jitter, phase tracking error, power dissipation and layout area of the circuit
• Design of a Single ended NMOS input folded cascode amplifier [Cadence Suite, TSMC 0.35um CMOS ]
Sized the transistors for DC power=1.1mW, o/p swing =2Vand UGF = 25MHz at a supply voltage of 2.7V
Designed biasing circuits and did a LVS and DRC clean 2D common centroid layout
 • Design of a Single ended Telescopic cascode Differential Amplifier [Cadence Suite, TSMC 0.35um
CMOS] Designed the amplifier for Vdd = 3.0-3.5V, DC gain= 50dB, UGF = 70MHz and input range =1.5-2V
Simulated test benches to measure CMRR, PSRR+/- and slew rate
• Design of Discrete time (DT) and Continuous time (CT) Low pass ΣΔ modulators [MATLAB, Cadence suite]
Designed a DT modulator using Sigma delta tool box and the system was implemented in Simulink
Designed a CT modulator using ideal elements to meet the specifications on SNR, i/p signal level and OSR
• Design of 80MHz, 10-bit fully differential RSD-based pipelined ADC [Cadence suite,
Verilog-A, MATLAB]
Used 7 stage RSD and a 3bit flash ADC architecture for an input signal of 1Vp-p and Vdd=1.8V
Implemented individual blocks of the ADC in Verilog –A to the lowest possible gate level
• Design of a Beta Multiplier current mirror [Cadence Suite, TSMC 0.35um CMOS]
Designed a current reference circuit to deliver 10uA with supply varying from 2V to 3V
• Design of a 50 ohm driver amplifier [Cadence Suite, TSMC 0.35um
CMOS]
Designed a high gain amplifier with a class AB amplifier as a buffer to drive 50ohm load
Sized the transistors for the specifications on DC power, o/p voltage, i/p common mode range, DC gain and UGF
• Design of a Matlab model for a 1.5 bit per stage RSD Pipeline Analog to Digital
Converter [MATLAB]
Implemented a user configurable model for 1.5 bit per stage RSD pipelined ADC
Analyzed the impact of finite op-amp gain, capacitor mismatch on the performance
of ADC
Tested the ADC and plotted DNL and INL error plots
• Analysis of the performance of SRAM cells built using Independent gate FinFETs [Hspice,
Cosmoscope]
Wrote Hspice net lists for four different FinFET SRAM cells to analyze their read/write margins and delays
Studied the impact of process variations on read margin and leakage through Monte Carlo simulations
• Analysis of voltage scaling on the performance of a 20FO4 inverter chain [Cadence suite, PTM
0.18um]
Analyzed the options to reduce power consumption without hurting performance by varying supply voltage and
substrate bias.
• Design of a 6 transistor SRAM cell for minimum DRV at 45nm [Cadence suite, PTM 45nm CMOS]
Sized a SRAM cell is to minimize DRV in order to reduce standby power consumption.
Analyzed the impact of process variations on DRV using Perl scripts
• VHDL coding and simulation of circuits like Full adder, multiplexer, shift register, counter, flip-flop
Wrote RTL codes in VHDL and simulated them using Xilinx ISE simulator
Wrote test benches and verified the functionalities of the above circuits
• Design of a standard cell library of MOS current mode logic (MCML) Inverter, NAND, NOR, XOR gates
[Cadence suite, PTM 0.18um CMOS]
• Design and Layout of a standard cell library of NAND, NOR, Multiplexer and D-
Flip-Flop circuits [Cadence suite, TSMC 0.25um CMOS]
• Implementation of a Resolution Enhancement scheme in Fourier domain Optical coherence Tomography
[MATLAB] Undergraduate final project. Grade received: A+
• Implementation of Frequency domain Adaptive noise cancellation scheme using FFT in MATLAB
PUBLICATIONS
• G.S.Chaitanya Chowdary. (2006) “Nano Memory Storage system – The Millipede”. It explains and examines
operation and implementation of a memory system whose data writing and retrieval capabilities are based on
 scanning probe mechanism. Presented at International Conference on Systemics, Cybernetics and Informatics,
Hyderabad, INDIA, January 2006
MEMBERSHIPS
• Chairman for the Indian Society for Technical Education chapter of our college from 2005-2007
• Webmaster of ASU-IEEE students’ chapter

• References will be furnished upon request