Kogge Stone Adder Logic Verification

D. W. Parent

This is a very efficient 1 bit full adder.

Carry Look Ahead

generate propagate carry sum

Derive the schematic.

It is easier to manage the design if you partition items into blocks

The Generate Propagate Block (4 bits seemed easier to do.)

The look ahead carry generate block

Very y similar to 4 bit CLA but note there is a P and G t term.

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The sums are broken up into 4 bits each. This will help with LVS later.

WN/WP for a 16 bit CLA Adder in Static

Did not take into account Fan out or wiring capacitance.

WN/WP for a 16 bit CLA Adder in dynamic

Higher order adders are too complex to draw at the circuit level

i:k
4 input

i:k 3 input

k-1:j

i:k

Note: Two ij i:j output vectors Black Cell Gi:j, Pi:j

i:j i j Gray Cell Gi:j

i:j Buffer

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Higher order diagrams can be made as well

i:k k-1:l l-1:m m-1:j

i:j
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The Manchester Carry Chain can be greatly simplifies in multiple output domino logic

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3:0

2:0

1:0

0:0

MCC PG Group P and d G for f Each E h line li inside i id

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

G=C

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

Final Sum XOR inside

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Example: Find the Delay of the 16bit MCC adder. Assume the MCC domino vs Static

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

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This example shows how the logic was verified ifi d of f a Kogge K St Stone Adder Add
The Major Steps were:
Convert grey and black cells to schematics Convert tree tree diagrams into a schematic Create a trusted adder Compare trusted adder to new adder

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Black Cell
When doing a completely new logic just use the th di digital it l parts t i in th the NCSU kit!

Schematic

Symbol

Make sure to edit the labels so that they can be seen in a large Schematic Schematic.
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Grey Cell
Once could use AOI or NAND NAND to implement these cells.

Schematic

Symbol

A Grey cell is a Black cell without the group propagate

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Tree Diagram of KS adder from D id H David Harris i

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8 bit KS adder schematic with carry in and carry out

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Does this adder work properly?

Boolean logic analysis would be great to try and show the equivalence of a ripple, or carry look ahead adder to a KS Not my strong suit.

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Create and verify a 1 bit full adder

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Create C eate a 8b 8bit tt trusted usted adde adder

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Create a 9 bit bit-wise bit wise XOR

This will be used to compare the carry out and sum signals of both adders.

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KS ADDER

Create a test bench that will feed the same test vectors into both adders and compare their outputs.
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Run KS adder against Trusted adder dd

Search for 1. If signals g are different then XOR will g give one.

Can not really see if there is a 1 value at this time scale.

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Export Data Into Text

NC verilog tracks the changes only. WE can see that no signal was a 1 and since we did all test vectors the adders are logically equivalent.
This is all the data.

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Summary
This technique was used to finally verify a KS adder structure. There is a reason the adder was labeled adder3 This was not an efficient method of verification
Program g adder! Use Boolean logic! It still worked.
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