Designing with DDS

A high speed solution for portable and handheld applications

Jeff Keip - Analog Devices & David Askins Avnet Electronics

Agenda
Basic

DDS review

DDS engine DDS features

ultra low power DDS Comparing stand alone DDS vs. FPGA embedded DDS engine
AD9913

Ease of implementation Performance Cost

Programmable

Modulus explained

Quick Review of DDS

Direct Digital Synthesis is:

A DIGITAL technique for generating sine waves from a fixedfrequency clock source

By using DDS:

The sine wave FREQUENCY is digitally tunable to sub-Hertz resolution The sine wave PHASE is digitally adjustable There are NO ERRORS from drift due to temperature or aging of components The synthesizer is AGILE; frequency and phase changes are made quickly with near-zero settling time Frequency, phase and amplitude ramps are easy to implement
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Basic DDS System p-bit DDS with N-bit DAC

p-bit Phase Register FTW p-bit Phase Accumulator
p
N + 2~4

(t )

sin() Phase Amplitude N Conversion

N-bit DAC

fOut FTW = round 2 f Clk

M (t ) = 2 2p INT (tfClk)

Clock

31 29
4 3 2 1 0 63

4 2 0

1 f Clk

p-bit phase resolution (p=6)

N-bit amplitude resolution (N=5) 4

Basic DDS System p-bit DDS with N-bit DAC

p-bit Phase Register FTW p-bit Phase Accumulator
p
N + 2~4

(t )

sin() Phase Amplitude N Conversion

N-bit DAC

fOut FTW = round 2 f Clk

M (t ) = 2 2p INT (tfClk)
1

Clock
f Out

31 29
4 3 2 1 0 63

vector data raw DDS-DAC output

4 2 0

1 f Clk

p-bit phase resolution (p=6)

N-bit amplitude resolution (N=5) 5

Basic DDS System p-bit DDS with N-bit DAC

p-bit Phase Register FTW p-bit Phase Accumulator
p
N + 2~4

(t )

sin() Phase Amplitude N Conversion

N-bit DAC

fOut FTW = round 2 f Clk

M (t ) = 2 2p INT (tfClk)
1

Clock
f Out

31 29
4 3 2 1 0 63

filtered output

4 2 0

6~8 Order
OR

1 f Clk

p-bit phase resolution (p=6)

N-bit amplitude resolution (N=5) 6

To Mixer, Mod/Demod, etc.

Useful DDS Features

Frequency Tuning Resolution Finer tuning capability than even fractional N PLLs Phase Offset Word Phase tuning implemented digitally to .022 resolution Auxiliary (Sweep) accumulator Enables Frequency/phase/amplitude ramping and Programmable Modulus Amplitude Scaling Factor Digital magnitude control on output Profiles/Shift Keying Extremely low settling times with no ringing RAM One way of implementing non-linear sweeps and shift keying
Matched Latency Frequency, phase, and amplitude changes all affect the output simultaneously

Clear Phase Accumulator Can establish known phase on F/P/A changes

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Phase Tuning Resolution

POW

(Phase Word -- K bits)

degrees

Register value sets resolution POW x 360 phase equation: out = 2K POW x 2 = 2K
POW

radians

p-bit Phase Accumulator p (t )

sin(x) cos(x)

Auxiliary Accumulator
Ease

of implementation for frequency sweeping makes DDS good option in radar system
M is now a variable rather than a constant q-bit Delta Register D D q M p-bit Aux. Accumulator M p p-bit Phase Accumulator (t ) sin(x) cos(x)

/K

Sample Clock

Auxiliary Accumulator: Frequency Sweep

Ease

of implementation for frequency sweeping makes DDS good option in radar system
Upconversion Circuitry if needed
Reference Oscillator
frequency sweep

VCO
DDS

PLL

2x mult

PA

X
Microcontroller

Radar System Block Diagram

DSP
ADC

ANTENNA

Receive Mixer

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Matched Latency
Unmatched Matched

Output reflects Phase change

Output reflects Amplitude change

Output reflects Frequency change

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Output reflects A, , and F changes simultaneously

Application Example Clear phase accumulator

8 kHz

AD9913
GPS RCVR I/O Update SYSCLK Ref ADCMP607

AD9549
SYSCLK Ref

10 MHz

Application: GPS Synch

12.8 MHz Clear 12.8 MHz

Phase accumulator function enables system to reset the phase of the DDS to 0 easily May be made automatic when changing profile

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Useful DDS Features

REFCLK

multiplier & PLL (AgileRF)

Allows for output frequencies higher than the reference Digital and precise

Multi-chip Synchronization

Zero Crossing

Bit

Eases system synchronization efforts Allows for square wave output

Comparator

Angle

to Amplitude Bypass

Digital ramping output instead of sinusoid

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AD9913
Primary Design considerations

Low Power <50 mW at full speed Low Price Price-equivalent to comparable DAC Very small 5x5 32 pin LFCSP

250 MSPS low power DDS core

10 Bit DAC

Digital Sine Wave

Ref Clock Input Circuitry

Timing and Control

Lower power Easier to design Cost effective

No flexibility in DAC selection Not quite as fast
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User interface

The Greening of DDS for IF generation

200

Power Consumption - mW

150

Existing DDS portfolio

100 AD9913 50
Existing PLL portfolio

The AD9913 cuts a significant swath in the power/frequency gap that exists between existing DDS and PLLs

25

50

100

200

Bandwidth - MHz
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AD9913 application examples

High
Apps served by FPGA Embedded

Wireless Scanners

Cost Sensitivity

Radar Detection

Radio Controllers

Wireless Monitors Portable Instruments

Soldier of the Future

Low
Low

Older Generation DDS Devices

UAV

AD9913
High

Power Sensitivity
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Where should I get my DDS function?

mC

FPGA
DDS Engine

From my FPGA?
DAC

FPGA mC
AD9913

Or on my DAC?

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Key factors when implementing a DDS in a FPGA

Ease

of implementation resources used, i.e. memory cells or logic blocks used.

Amount of

Performance Cost

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Ease of Implementation
Generating a DDS

engine in an FPGA is straight forward and

simple
Utilize Core Gen tool to

develop the engine

GUI interface makes it easy Input the desired DDS requirements and parameters FOUT , modulation scheme FSK, ASK, SFDR level, etc Build or compile the core and load it into the FPGA

The Core Gen

tool will build the DDS engine accordingly

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Amount of resources used

Resources in an

FPGA are memory cells 4x the silicon

FPGA logic implementation typically requires 3x to

content for the same IC implementation

Phase to

amplitude conversion in a FPGA is done with a lookup

table

The table is sized according to desired SFDR level This can make the table very deep requiring a very large amount of resources The AD9913 utilizes a real time algorithm for the phase to amplitude conversion

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Performance of the FPGA DDS

The DDS

engine in a FPGA can be very similar to that of a stand alone DDS such as the AD9913
Spurs can be set at a desired level Noise floor can be set to a desired level Similar modulation schemes can be chosen etc.

All this

comes at the price of increased resources or memory cells and increased cost.

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Performance of the FPGA DDS continued

Now

lets look at some major design considerations

The FPGA DDS

is the digital DDS engine only, an external DAC is required in order to generate the desired analog output critical when implementing a DDS design for a couple of

This is

reason

The interface between the DDS engine and the DAC

The interface can be a source of noise generation and reduced performance if not done properly

The choice of DAC

Choice of the DAC can greatly affect the overall system performance SFDR and noise floor can degrade due to a low performance DAC
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Performance of the FPGA DDS continued

With the AD9913

the DAC function is integrated onboard the device

The DAC is matched to the DDS core to maximize system performance

Design requirements are simplified for the engineer

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Cost of Implementation
The cost

if implementing a FPGA DDS is higher due to

The increased amount of resources required to implement the same IC function, i.e. 3x to 4x silicon requirement Lookup table depth Requires an external DAC

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Auxiliary Accumulator: Programmable Modulus

RAM Profile Registers FTW Phase Offset

SIN(X) COS(X)

x sin(x)

Auxiliary Accumulator

Prog. Modulus Logic

Profile Registers RAM POW

State of the art DDS Core block diagram

RAM

When

Programmable modulus mode is active, The divisor in the DDS frequency equation becomes a user-defined variable

New DDS frequency equation: Fout =

FTW x FSAM Y

Y is any value between 2(FTW) and 2 Z, where Z is the # of bits in the linear sweep accumulator, or select values between 2Z and 2X+Z where X is the # of bits in the phase accumulator

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Tuning Resolution effect of Programmable Modulus

Standard Tuning word options

Example using 3 bit accumulators

0.25

0.50

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Tuning Resolution effect of Programmable Modulus

from 3 usable options
Standard Tuning word options

Example using 3 bit accumulators

0.25

0.50

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Tuning Resolution effect of Programmable Modulus

Standard Tuning word options Programmable Modulus

To 70(+) usable options!

Example using 3 bit accumulators

0.25

0.50

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Conclusion
The

introduction of the AD9913 means

DDS is now significantly more usable in portable/handheld applications Designers relying on FPGA based DDS engines have a better alternative The frequency tuning benefit of DDS has taken a quantum leap forward thanks to Programmable Modulus

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