A Direct Digital Frequency Synthesis System for Low Power Communications

Alistair McEwan, Sunay Shah and Steve Collins

Department of Engineering Science University of Oxford Parks Road Oxford UK OX1 3PJ a istair!mce"an#eng!ox!ac!$k

A stract
%&is "ork descri'es a Direct Digita (re)$ency Synt&esis *DD(S+ arc&itect$re 'ased on non inear interpo ation for signa generation in mo'i e comm$nications systems s$c& as , $etoot&! DD(S is capa' e of "e contro ed- rapid c&anges in fre)$encyover a re ative y arge fre)$ency range- &o"ever a conventiona DD(S system re)$ires a po"er &$ngry RO.! %o avoid t&is pro' em a RO./ ess arc&itect$re "it& a o" po"er non inear interpo ation D01 is proposed!! %&is system is ro'$st to parameter variations and cons$mes on y 2m3 at 144.56!

corrupting the DDFS output. his effect is measured as SFD" which is the difference in power between the synthesised signal and the ne/t most powerful &unwanted( frequency in the output spectrum. he SFD" requirement of a 0luetooth system is -12 d0c )3,. he 0luetooth specification also requires a channel bandwidth of '$4. which is frequency hopped over 56 channels every 7*18s, with frequency resolution of 'ppm. Dynamic performance of DDFS systems rapidly degrades with frequency due to transient glitches in the DA%. hese glitches can be minimised by using a current switched cell &Figure *.( and thermometer decoding to reduce dynamic errors by ensuring that the minimum number of cells switch simultaneously. Additionally the use of latches for all switching signals ensures that all cells switch synchronously and the use of differential switches allows reduction of the voltage required to switch the current cell. 4owever timing s!ew cannot be completely removed and state of the art low power "F %$#S DA%s are limited to appro/imately -52 d0c SFD" )1, 7,. he interpolation method is introduced in section * with $atlab pro9ections of system performance. Section + presents the architecture of a prototype system and section 3 demonstrates that the system is robust to process variations. "esults and power consumption are shown in Section 1.

!" #ntroduction
A conventional DDFS system consists of an L-bit accumulator which occasionally overflows, providing a periodic sequence of numbers which represents phase of the output waveform. his phase is used to address a loo!up table of amplitude values stored in a "#$ and passed through a corresponding DA% to create a synthesised, analogue signal &Figure '.(. he "#$ consumes most of the power of the system and several alternative architectures for "#$ reduction have therefore been investigated )', *, +,.

$" %onlinear DAC inter&olation method

he "#$ may be replaced by using a nonlinear DA% to perform both phase to amplitude conversion as well as digital to analogue conversion. A nonlinear weighted array of current cells is used to store the phase to amplitude information within the DA%. :sing a trigonometric appro/imation, ;iang and Lee )*, designed a "#$-less DDFS system consisting of '6* current cells. his system has an SFD" of better than -72 d0c at low synthesised frequencies &less than '2 $4.(, which degrades to worse than -11d0c at higher frequencies &up to '22 $4.(. o reduce the number of

Figure '. DDFS system architecture.

-uantisation caused by "#$ si.e reduction and non-idealities associated with the DA% cause the generation of spectral power at unwanted frequencies,

current cells a technique is proposed which employs each current cell more efficiently.

transistors, 3s" and =s" , while !eeping 7'ias @ ; ratio constant! $"$ Efficiency #ne of the critical decisions that must be made when designing a system is the value of ratio 7'ias @ ; and the ma/imum differential input voltage that should be used. <n particular the characteristics shown in Figure +, indicate that by using a small voltage swing and a large 7'ias @ ; it might be possible to limit the circuit to the relatively linear part of itAs transfer characteristic.

Figure *. A current cell.

$"! %onlinear #nter&olation <n the thermometer decoded nonlinear DA% the output current from each current cell should represent a change in amplitude for each change in the corresponding phase, thus for a cosinusoidal wave=

Figure += <ncreasing linearity of the current cell

>hen using the linear part of the transfer characteristic, only a small fraction of the bias current in a cell is used to form the output current. A system using linear interpolation will therefore use more current to create the same output power than an alternative system that e/ploits the whole, non-linear transfer characteristic of the differential switch. 4owever a sinusoidal function is appro/imately linear over a large section of its argument and linear interpolation may give a better SFD" &Figure +(. $"' Matla Emulation

7 o$t &ma/( = cos&i ( cos&i ' (

&'(

0y using the switch voltage, 8in, to control the amount of output current, each cell can be used as an interpolation device. <f the two transistors in the differential switch are in saturation then the output current of the cell is

7 o$t =

* *

7 'ias

8 * 3

&*( Bumber of current cells C '7 +* 73 '*C Bonlinear SFD" -+5.3 d0c -3C.2 d0c -1+.6 d0c -16.2 d0c -7'.1 d0c linear SFD" -35.2 d0c -16.7 d0c -5*.2 d0c -C3.' d0c -67.* d0c

>here 98 is the differential switch voltage, *8in : 8ref+7'ias, the constant bias current and ;, the transconductance parameter of the two, well matched switch transistors &$' and $*(. >hen 98< ? * 7'ias @ ; then 7o$t ? 2 and the condition 8 > * 7 'ias @ determines the minimum input voltage swing to fully switch the current to the output. Smaller swings will steer part of the current to the output &Figure +(. Furthermore, it has been found that it is important to ensure that the slope 7'ias @ ; of the nonlinear transfer function remains constant across the current cells. herefore each cell is required to have a different bias current and ; parameter, and hence an approach which uses standard cells for each current source cannot be used. he ; of the switches in each current cell is therefore varied by changing the geometry of the switch

able '= $atlab results of using linear compared to nonlinear interpolation.

he performance was investigated in $atlab. and is surprisingly good for a small number of current sources & able '(. %ompared to LeeDs system, which requires '6* cells to produce a signal that complies with the 0luetooth requirements of -12 d0c SFD" )*,, only '7 cells are required here. $atlab was also used to investigate the trade-off between current consumption for a given output power and SFD" in a system of '7

current sources. here is a rapid improvement in SFD" as the efficiency is reduced from '22E to 62E. his '2E increase in power results in an improvement of 7 d0 in SFD". his initial rapid improvement in performance is followed by a slower improvement. 4owever a system with +2E efficiency has an SFD" of better than F15 d0c.

'" %onlinear #nter&olation Architecture

A DDFS system using a '7 current cell nonlinear interpolation DA% and thermometer decoding has been designed in 2.+1Gm, +.+H %$#S technology. A schematic of the system is shown in Figure 3. '7 current cells have been chosen as this is the minimum required to meet the most stringent SFD" requirement of the popular 0luetooth specification of -15d0c and to easily compare this design with the state of the art )*,. his corresponds to the +2E efficiency that represents nearlylinear interpolation. <n this prototype, the system is designed to deliver 51uA to the output, therefore the nonlinear DA% in this prototype system consumes 51uA / +.+H@2.+ ? C*1u>. A *2-bit accumulator is used to ensure frequency resolution of better than 'ppm, in line with the 0luetooth specification. he first '' $S0 bits are used to represent the phase to ensure that the system is not limited by phase resolution. <n order to reduce the number of current cells half wave symmetry is e/ploited by using the $S0 to ta!e the 's complement of the other phase bits using I#" gates. he first 3 bits at the output of the I#" gates are used to drive the nonlinear interpolation DA%. #n its own the nonlinear DA% would be limited by phase errors arising from using only 1 bits to a SFD" of -+2 d0c. o ensure that the overall system is limited by the phase to amplitude conversion rather than phase quanti.ation, 7 more phase bits are used to create an analogue voltage that forms the input to the interpolating nonlinear DA%. he use of the additional 7 phase bits raises the phase quanti.ation limitation on SFD" to a possible -77 d0c.

decoding logic to be modified to identify only the *J>1+t& cell. #nly this cell should receive 8p&ase at any one time. he *J>1+t& cell can be determined by the I#" of two ad9acent rows and two ad9acent columns. >hen this cell is provided with the analogue phase voltage the output will increase by the partial amount that this cell is turned on causing interpolation between the phase values encoded in this cell and the previous cell.

(" #m&act of Mismatch

<n each current cell of the thermometer decoded array the accuracy of three functional parameters, the bias current, &amplitude 7'ias(, the phase voltage, &offset 98(, and the gain &transconductance, ;(, determine the distortion in the output and thereby the SFD" and overall yield. o quantify the effect of mismatch due to process variations, a series of $atlab simulations were performed where a random number generator with normal distribution was used to set the percentage error of the parameter under test. For each percentage error the performance of '22 simulations was recorded to determine the statistical behaviour and therefore the yield of systems with SFD" better than F15 d0c.

Figure 1. Jffect of mismatch on yield of systems with SFD" better than F15 d0c.
he yield results, shown in Figure 1, suggest that there will be a high yield of systems with SFD" better than F15 d0c if the current parameter can be controlled within 'E and the phase and beta parameters within +E. For a typical 2.+1Gm process with voltage supply of +.+H this corresponds to transistors with an area of appro/imately '2 Gm* for the current source according to KelgromDs Law )5,. he analogue phase voltage for interpolation that is generated by the small linear phase DA% must be also be controlled to within 3E &Figure 1(. An identical phase DA% with the $S0 tied high and the other 1 bits tied low is used to create the phase reference 8ref . his ensures that 8p&ase and 8ref are robust to global or chip to chip variation.

Figure 3= he prototype system

A simple interface for the interpolation DA% is to provide each cell with the same analogue voltage representation of the phase 8p&ase. his is created by a small linear phase DA% which converts the additional 7 phase bits into an analogue phase voltage. he interpolation DA% requires the local thermometer

)" System *esults

$i/ed signal simulation was employed with the accumulator represented by a behavioural Herilog model and the other digital gates by their full analogue model. >hen the accumulator is loaded with a phase word of ', the system generates a synthesised frequency of (c k@*23C. >ith a cloc! frequency of '22 $4., the SFD" was -1C d0c. he dominant spur was the * nd harmonic, suggesting that the SFD" is limited by amplitude quantisation as opposed to transients that appear as a high frequency spur. fcl! 2.1 $4. '2 $4. '22 $4. 122 $4. ' L4. circuit SFD" -1C d0c -1C.3 d0c -1C.2 d0c -15.2* d0c -13.+1 d0c

+" Future ,orhe effect of mismatch requires the use of transistors larger than minimum si.e for the current sources. he design of future current sources could be made easier by using smaller trimmable current sources based on floating-gate technology )C,. Additionally, the values stored in a programmable nonlinear DA% can be trimmed to reduce the effect of variations and thus improve yield. 0y setting the phase word of the accumulator to *'2, each device in the nonlinear DA% will be turned on successively. his would allow the use of only one programming circuit to trim the amplitude values stored in each current cell in a method similar to that used to measure mismatch in )6,.

." Conclusion
An efficient DDFS technique based on analogue interpolation has been presented. he system is a good candidate for popular low power communication specifications such as 0luetooth. he power consumption of the system is 1m> at '22$4., however over half of the power is consumed by the latches.

able *= Frequency Kerformance

As e/pected the SFD" decreases at higher frequencies when glitches become the dominant source of errors in the output. he SFD" requirement for 0luetooth is -12 d0c )3,. he results in able * suggest that this system is better than required for cloc! frequencies of up to ' L4.. his is significantly higher than the bandwidth required by 0luetooth. he true impact of glitches on performance can only be !nown after measurement of the prototype chip that is currently being fabricated. hese results should be available for presentation at the conference.
Pow er (100MHz )

/" *eferences
)', A. 0ellaouar, $. #Dbrecht, A. Fahim, and $. Jlmasry, MLow-Kower Direct Digital Frequency Synthesis for >ireless %ommunications,N 7EEE J! So id/ State 1irc$its, vol. +1, no. +, $ar. *222, pp. +C1F+62 )*, ;. ;iang and J. Lee, MA "#$-less Direct Digital Frequency Synthesi.er :sing Segmented Bonlinear Digital-to-Analog %onverter,N in 7EEE 1$stom 7ntegrated 1irc$its 1onference, *22', pp. '71F'7C. )+, H. F. Oroupa, Direct Digita (re)$ency Synt&esi6ers, <JJJ Kress, '66C. )3, ;., %. 4aartsen, and S., $attisson., M0luetooth - A Bew Low-Kower "adio <nterface Kroviding Short-"ange %onnectivity,N Proceedings of t&e 7EEE, vol. CC, no. '2, #ct *222, pp. '71'F'77'. )1, A. Han den 0osch and $. A. F. 0orreman, MA '2-bit '-LSample@ s Byquist %urrent Steering %$#S D@A converter,N 7EEE J! So id/State 1irc$its, vol. +7, no. +, $ar. *22', pp. +'1F+*3. )7, ;. 0astos, A. $. $arques, $. S. ;. Steyaert, and >. Sanasen, MA '*-0it <ntrinsic Accuracy 4igh-Speed %$#S DA%,N 7EEE Jo$rna of So id State 1irc$its , vol. ++, no. '*. '66C, pp. '616F'676. )5, $.;. Kelgrom, A.%.;., MDuinmai9er and A.K.L. >ebers. $atching Kroperties of $#S ransistors,N 7EEE J! So id State 1irc$its, vol. *3, no 1, #ct. '6C6, pp. '3++-'332.

Accumulator NL DAC Logic Latches Phase-DAC

Figure 7= Kower %onsumption

he latches used to synchronise the switching signals consume over half of power in the system, 1'E, the accumulator +2E, the nonlinear DA% '5E, the logic *E and the Khase DA% only 2.1E &Figure 7(. A standard cell latch was used in the prototype to ensure that latch delays did not affect the performance. %learly there would be a considerable saving in power consumption by using a custom designed latch for low power consumption, perhaps through the use of reduced supply voltage levels )1,.

)C, S. Shah and S. %ollins., MA emperature <ndependent rimmable %urrent Source,N in 7EEE 7nternationa Symposi$m on 1irc$its and Systems, $ay *22*. )6, J. Felt, A. Barayan and A. L. SangiovanniHincentelli, M$easurements and $odeling of $#S ransistor %urrent $ismatch in Analog <%sN, in Proc! 7EEE 7110D, pp. *5*F*55, Bovember '663.