Advanced Current Mirrors and Opamps

David Johns and Ken Martin University of Toronto (johns@eecg.toronto.edu) (martin@eecg.toronto.edu)

University of Toronto

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D.A. Johns, K. Martin, 1997

Wide-Swing Current Mirrors

I bias V bias I in V out I out = I in

WL -----------------2 (n + 1)

WL ----------2 n
Q4

Q5

Q1

WL ----------2 n WL

WL

Q3

Q2

Used to increase signal swing in cascode mirror Bias drains of Q2 and Q3 close to triode region I bias set to nominal or max value of I in

University of Toronto

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D.A. Johns, K. Martin, 1997

Wide-Swing Current Mirrors

Q3 and Q4 act like a single transistor V eff = V eff 2 = V eff 3 = 2 ID2 ------------------------------ n C ox ( W L )
2 (1)

Q 5 has same drain current but ( n + 1 ) times smaller V eff5 = ( n + 1 ) V eff Similarily V eff1 = V eff4 = nV eff V G5 = V G4 = V G1 = ( n + 1 ) V eff + V tn V DS2 = V DS3 = V G5 V GS1 = V G5 ( nV eff + V tn ) = V eff Puts Q2 and Q3 right at edge of triode
University of Toronto
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D.A. Johns, K. Martin, 1997

(2)

(3) (4) (5)

Wide-Swing Current Mirrors

Min allowable output voltage V out > V eff1 + V eff2 = ( n + 1 ) V eff If n = 1 V out > 2V eff With typical value of Veff of 0.2 V, wide-swing mirror can operate down to 0.4 V Analyzed with I bias = I in . If I in varies, setting I bias to max I in will ensure transistors remain in active region Setting I bias to nominal I in will result in low output impedance during slewing (can often be tolerated)
(7) (6)

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D.A. Johns, K. Martin, 1997

Design Hints
Usually designer would take ( W L ) 5 smaller to bias Q2 and Q3 slightly larger than minimum To save power, bias Q5 with lower currents while keeping same current densities (and Veff) Choose lengths of Q2 and Q3 close to minimum allowable gate length (since Vds are quite small) maximizes freq response Choose Q1 and Q4 to have longer gate lengths since Q1 often has larger voltages ( perhaps twice minimum allowable gate length) Reduces short-channel effects

University of Toronto

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D.A. Johns, K. Martin, 1997

Enhanced Output-Impedance Current Mirror

Iout R out Vbias V out A Q1

Iin

Q3

Q2

Use feedback to keep Vds across Q2 stable R out g m1 r ds1 r ds1 ( 1 + A ) Limited by parasitic conductance between drain and substate of Q1
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D.A. Johns, K. Martin, 1997

(8)

Simplified Enhanced Output-Impedance Mirror

Iin IB2 IB1 Iout

Q4 Q6 Q5 Q3

Q1

Q2

Rather than build extra opamps, use above Feedback amplifier realized by common-source amplifier of Q3 and current source I B 1

University of Toronto

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D.A. Johns, K. Martin, 1997

Simplified Enhanced Output-Impedance Mirror

Assuming output impedance of I B 1 is equal to r ds3 , loop gain will be ( g m3 r ds3 ) 2 , resulting in g m1 g m3 r ds1 r ds2 r ds3 r out ---------------------------------------------2 Circuit consisting of Q4, Q5, Q6, I in , and I B 2 operates like a diode-connected transistor results in accurate matching of I out to I in Note that shown circuit is NOT wide-swing requires output to be 2 V eff + V tn above lower supply
(9)

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D.A. Johns, K. Martin, 1997

Wide-Swing with Enhanced Output Impedance

Add wide-swing to improve output voltage swing
4 I bias

I out
4 I bias

I in

I in 7 I bias
70 Q5 10 Q7 10 Q8 10 Q4 10 Q3

I bias

I bias

70 Q1

80

80 Q2

Q6

Q3 and Q7 biased at 4 times current density 2Veff Requires roughly twice power dissipation Might need local compensation capacitors
University of Toronto
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D.A. Johns, K. Martin, 1997

Folded-Cascode Opamp
Q11 Q3 Q4

Ibias1

Q12

V B1 Q13 Q1 Q2 CL Ibias2 V B2 Q8 Q7 Q9 Q10 Q5 Q6

Vin

Vout

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D.A. Johns, K. Martin, 1997

Folded-Cascode Opamp
Compensation achieved using load capacitor As load increases, opamp slower but more stable Useful for driving capacitive loads only Large output impedance (not useful for driving resistive loads) Single-gain stage but dc gain can still be quite large (say 1,000 to 3,000) Shown design makes use of wide-swing mirrors Simplified bias circuit shown Inclusion of Q12 and Q13 for improved slew-rate

University of Toronto

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D.A. Johns, K. Martin, 1997

Folded-Cascode Opamp
AV V out ( s ) = ----------------- = g m1 Z L ( s ) V in ( s ) g m 1 r out A V = --------------------------1 + sr out C L r out is output impedance of opamp (roughly g m r ds 2 ) For mid-band freq, capacitor dominates g m1 A V -------sC L g m1 t = -------CL
University of Toronto (12) 2 (10)

(11)

(13)

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D.A. Johns, K. Martin, 1997

Folded-Cascode Opamp
Maximizing gm of input maximizes freq response (if not limited by second-poles Choose current of input stage larger than output stage (also maximizes dc gain) Might go as high as 4:1 ratio Large input gm results in better thermal noise Second poles due to nodes at sources of Q5 and Q6 Minimize areas of drains and sources at these nodes with good layout techniques For high-freq, increase current in output stage

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D.A. Johns, K. Martin, 1997

Folded-Cascode Slew-Rate
If Q2 turned off due to large input voltage I D4 SR = ------CL
(14)

But if I bias2 > I D 3 , drain of Q1 pulled near negative power supply Would require a long time to recover from slew-rate Include Q12 (and Q13) to clamp node closer to positive power supply Q12 (and Q13) also dynamically increase bias currents during slew-rate limiting (added benefit) They pull more current through Q11 thereby increasing bias current in Q3 and Q4

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D.A. Johns, K. Martin, 1997

Folded-Cascode Example
Design Goals +-2.5V power supply and 2mW opamp with 4:1 ratio of current in input stage to output stage Set bias current in Q11 to be 1/30 of Q3 (or Q4) Channel lengths of 1.6um and max width of 300um with Veff=0.25 (except input transistors) Load cap = 10pF Circuit Design I total = 2 ( I D 1 + I D 6 ) = 2 ( 4 I B + I B ) = 10 I B IB = ID5 = ID6 I total ( 2 mW ) 5 V = --------- = ------------------------------ = 40 A 10 10
(15) (16) (17)

I D 3 = I D 4 = 5 I D 5 = 200 A
University of Toronto

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D.A. Johns, K. Martin, 1997

I D 1 = I D 2 = 4 I D 5 = 160 A To find transistor sizing: 2 I Di W ---- = -----------------------2 L i i C ox V effi rounding to nearest factor of 10 (and limiting to 300um width) results in Q1 300/1.6 Q6 60/1.6 Q11 10/1.6 Q2 300/1.6 Q7 20/1.6 Q12 10/1.6 Q3 300/1.6 Q8 20/1.6 Q13 10/1.6 Q4 300/1.6 Q9 20/1.6
Q5 60/1.6 Q10 20/1.6

(18)

(19)

Widths of Q 12 and Q 13 were somewhat arbitrarily chosen to equal the width of Q 11 Transconductance of input transistors
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D.A. Johns, K. Martin, 1997

gm1 =

2 I D 1 n C ox ( W L ) 1 = 2.4 mA/V

(20)

Unity-gain frequency gm1 8 t = -------- = 2.4 10 rad/s f t = 38 MHz CL Slew rate without clamp transistors ID4 SR = ------- = 20 V/ s CL Slew rate with clamp transistors I D 12 + I D 3 = I bias 2 = 320 A I D 3 = 30 I D 11 I D 11 = 6.6 A + I D 12
University of Toronto (23) (24) (25) (22) (21)

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D.A. Johns, K. Martin, 1997

 Solving above results in I D 11 = 10.53 A which implies I D 3 = I D 4 = 30 I D 11 = 0.32 mA leading to slew-rate ID4 SR = ------- = 32 V/ s CL
(28) (26)

(27)

More importantly, time to recover from slew-rate limiting is decreased.

University of Toronto

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D.A. Johns, K. Martin, 1997

Current-Mirror Opamp

1:K KID1 1:1 Vout Q1 Vin Ib Q2 KID2 1:K CL

University of Toronto

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D.A. Johns, K. Martin, 1997

Current-Mirror with Wide-Swing Cascodes

Q6 Q8

Q5

VB 2
Q4 Q9

Q7

VB2
Q10

Q3

VB1
Q1 Q2 Q11 Q12

Vout CL

Vin Ib

Q13

Q14

ID14 = KI1 = KIb /2

University of Toronto

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D.A. Johns, K. Martin, 1997

Current-Mirror Opamp
V out ( s ) Kg m 1 r out Kg m 1 - = Kg m 1 Z L ( s ) = --------------------------- -----------A V = ---------------V in ( s ) 1 + sr out C L sC L K factor is the current gain from mirrors Kg m 1 K 2 I D 1 n C ox ( W L ) 1 t = ------------ = -----------------------------------------------------CL CL If output capacitance set max speed, higher K results in higher speed If second-poles set max speed, higher K results in lower speed (increases capacitances of nodes) A reasonable choice for a general-purpose opamp is K = 2 (for max speed, K = 1 )
(30) (29)

University of Toronto

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D.A. Johns, K. Martin, 1997

Current-Mirror Opamp Slew-Rate

KI b SR = -------CL For given power, SR maximized by large K Example: K = 4 results in 4/5 of total bias current used in charging C L Usually has better SR than folded-cascode Usually has better bandwidth than folded-cascode Folded-cascode has better thermal noise
(31)

University of Toronto

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D.A. Johns, K. Martin, 1997

Current-Mirror Opamp Example

Design goals Same as in folded-cascode. Use K=2 Circuit Design With 2mW power limit and 5V supply, I total = 400 A I total = ( 3 + K ) I D 1 I D 1-7 = I D 9 = I D 11 = I D 13 = 80 A I D 8 = I D 10 = I D 12 = I D 14 = 160 A I b = 160 A and setting V eff around 0.25V, we find transistor sizes... Resulting in:
University of Toronto
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D.A. Johns, K. Martin, 1997

(32) (33) (34) (35)

Q1 Q2 Q3 Q4 Q5 Q6

300/1.6 300/1.6 60/1.6 60/1.6 60/1.6 60/1.6 gm1 =

Q7 Q8 Q9 Q10 Q11 Q12

60/1.6 120/1.6 60/1.6 120/1.6 30/1.6 60/1.6

Q13 Q14

30/1.6 60/1.6

2 I D 1 n C ox ( W L ) 1 = 1.7 mA/V

(36) (37) (38)

Kg m 1 8 t = ------------ = 3.4 10 rad/s f t = 54 MHz CL SR = ( KI b ) C L = 32 V/ s which is better than 20 V s for the folded-cascode opamp without clamp transistors

University of Toronto

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D.A. Johns, K. Martin, 1997

Linear Settling Time

Time constant for linear settling time equals inverse of closed-loop 3dB freq, 3dB where 3dB = t where is feedback factor and t is unity-gain freq of amplifier (not including feedback factor) For 2-stage opamp, t is relatively independent of load capacitance This is NOT the case where load capacitor is compensation capacitor (folded-cascode and currentmirror opamps) Need to find equivalent load capacitance
(39)

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D.A. Johns, K. Martin, 1997

Linear Settling Time

C2 C1 V in Cp

CC

C load

C2 1 [ s ( C1 + Cp ) ] - = ------------------------------ = ----------------------------------------------------------------1 [ s ( C 1 + C p ) ] + 1 ( sC 2 ) C1 + Cp + C2 C2 ( C1 + Cp ) C L = C C + C load + ------------------------------C1 + Cp + C2

(40)

(41)

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D.A. Johns, K. Martin, 1997

Linear Settling Time Example

Given C 1 = C 2 = C C = C load = 5 pF and C p = 0.46 pF , find settling time for 0.1 percent accuracy (i.e. 7 ) for the current-mirror opamp Solution: Equivalent load capacitance 5 ( 5 + 0.46 ) C L = 5 + 5 + ---------------------------- = 12.61 pF 5 + 5 + 0.46 which results in a unity gain freq of Kg m 1 2 1.7 mA/V 8 t = ------------ = -------------------------------- = 2.70 10 rad/s CL 12.61 pF
(43) (42)

University of Toronto

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D.A. Johns, K. Martin, 1997

Linear Settling Time Example

Feedback factor given by 5 - = 0.48 = ---------------------------5 + 0.46 + 5 causing a first-order time constant 1 = -------- = 7.8 ns t
(45) (44)

For 0.1 percent accuracy, we need a linear settling time of 7 or 54 ns.

This does not account for any slew-rate limiting time.

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D.A. Johns, K. Martin, 1997

Fully Differential Opamps

Advantages Use of fully-differential signals helps to reject commonmode noise and even-order linearities rejection only partial due to non-linearities but much better than single-ended designs Fast since no extra current mirror needed Disadvantages Requires common-mode feedback (CMFB) circuitry sets average output voltage level, should be fast adds some capacitance to output stage might limit output signal swing Negative going single-ended slew-rate slower since set by bias current not dynamic

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D.A. Johns, K. Martin, 1997

Fully Differential Folded-Cascode Opamp

Q3 Q11 VB1 Q4

Q12 Q5

VB2 Q6 Vout CMFB circuit Q10 Q9 Vcntrl

Q1 Vin

Q2

Ibias Q8 Q7

VB3

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D.A. Johns, K. Martin, 1997

Fully-Diff Current-Mirror Opamp

1:K 1:K Vout CMFB circuit Q6 Q5 Vcntrl

Q1 Vin

Q2

Ibias Q4 Q3

VB3

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D.A. Johns, K. Martin, 1997

Other Fully-Diff Opamps

K:1 Vout+ 1:1 K:1 Vin+ Vin 1:1 1:K 1:K Vout

Using 2 single-ended opamps

M2

I2 I1
Vb1

I1
Q10 Vout

Vsp Q6 Vin+ Q1 Q2 Vsn

Q9 Vout+ Q3 Q4 Vin Q7 Vb2

Q8

Q5

Rail-to-rail input common-mode range University of Toronto

I1

M1

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D.A. Johns, K. Martin, 1997

Common-Mode Feedback Circuits

IB Q1 V out+ Vcntrl IB

I B/2 I I B/2 + I
Q3

IB Q4 V out

Q2

I B/2 I
IB

Q5

I B/2 + I

Q6

Balanced signal on Vout does not affect Vcntrl Does not depend on small-signal analysis
University of Toronto
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D.A. Johns, K. Martin, 1997

Common-Mode Feedback Circuits

V out+ Q1 20 k 1.5 pF V ref Vcntrl VA V A = V CM ( V eff1 + V t1 ) V ref = ( V eff1 + V t1 ) 20 k 1.5 pF Q2 V out

Limited differential swing Should ensure CMFB loop is stable

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D.A. Johns, K. Martin, 1997

Common-Mode Feedback Circuits

1 1
CS

2 2

V out+

V out

2
CS 2

1 1
V bias

CC CC

Vcntrl

Useful for switched-capacitor circuits Caps Cs set nominal dc bias at bottom of Cc Large output signal swing allowed

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D.A. Johns, K. Martin, 1997