Ee101 DGTL 4

EE101: Digital circuits (Part 4)
M. B. Patil
mbpatil@ee.iitb.ac.in Department of Electrical Engineering Indian Institute of Technology Bombay
M. B. Patil, IIT Bombay
Sequential circuits
Sequential circuits
* The digital circuits we have seen so far (gates, multiplexer, demultiplexer, encoders, decoders) are combinatorial in nature, i.e., the output(s) depends only on the present values of the inputs and not on their past values.
Sequential circuits
* The digital circuits we have seen so far (gates, multiplexer, demultiplexer, encoders, decoders) are combinatorial in nature, i.e., the output(s) depends only on the present values of the inputs and not on their past values. * In sequential circuits, the state of the circuit is crucial in determining the output values. For a given input combination, a sequential circuit may produce dierent output values, depending on its previous state.
Sequential circuits
* The digital circuits we have seen so far (gates, multiplexer, demultiplexer, encoders, decoders) are combinatorial in nature, i.e., the output(s) depends only on the present values of the inputs and not on their past values. * In sequential circuits, the state of the circuit is crucial in determining the output values. For a given input combination, a sequential circuit may produce dierent output values, depending on its previous state. * In other words, a sequential circuit has a memory (of its past state) whereas a combinatorial circuit has no memory.
Sequential circuits
* The digital circuits we have seen so far (gates, multiplexer, demultiplexer, encoders, decoders) are combinatorial in nature, i.e., the output(s) depends only on the present values of the inputs and not on their past values. * In sequential circuits, the state of the circuit is crucial in determining the output values. For a given input combination, a sequential circuit may produce dierent output values, depending on its previous state. * In other words, a sequential circuit has a memory (of its past state) whereas a combinatorial circuit has no memory. * Sequential circuits (together with combinatorial circuits) make it possible to build several useful applications, such as counters, registers, arithmetic/logic unit (ALU), all the way to microprocessors.
NAND latch (RS latch)
X1
X1
X2
X2
* A, B : inputs, X1 , X2 : outputs
X1
X1
X2
X2
* A, B : inputs, X1 , X2 : outputs * Consider A = 1, B = 0.
X1
X1
X2
X2
* A, B : inputs, X1 , X2 : outputs * Consider A = 1, B = 0. B = 0 X2 = 1 X1 = A X2 = 1 1 = 0.
X1
X1
X2
X2
* A, B : inputs, X1 , X2 : outputs * Consider A = 1, B = 0. B = 0 X2 = 1 X1 = A X2 = 1 1 = 0. Overall, we have X1 = 0, X2 = 1.
X1
X1 0
X2 1
X2
* A, B : inputs, X1 , X2 : outputs * Consider A = 1, B = 0. B = 0 X2 = 1 X1 = A X2 = 1 1 = 0. Overall, we have X1 = 0, X2 = 1.
X1
X1 0
X2 1
X2
* A, B : inputs, X1 , X2 : outputs * Consider A = 1, B = 0. B = 0 X2 = 1 X1 = A X2 = 1 1 = 0. Overall, we have X1 = 0, X2 = 1. * Consider A = 0, B = 1. Show that X1 = 1, X2 = 0.
X1
X1 0 1
X2 1 0
1 0
0 1
X2
* A, B : inputs, X1 , X2 : outputs * Consider A = 1, B = 0. B = 0 X2 = 1 X1 = A X2 = 1 1 = 0. Overall, we have X1 = 0, X2 = 1. * Consider A = 0, B = 1. Show that X1 = 1, X2 = 0.
X1
X1 0 1
X2 1 0
1 0
0 1
X2
* A, B : inputs, X1 , X2 : outputs * Consider A = 1, B = 0. B = 0 X2 = 1 X1 = A X2 = 1 1 = 0. Overall, we have X1 = 0, X2 = 1. * Consider A = 0, B = 1. Show that X1 = 1, X2 = 0. * Consider A = B = 1.
X1
X1 0 1
X2 1 0
1 0
0 1
X2
* A, B : inputs, X1 , X2 : outputs * Consider A = 1, B = 0. B = 0 X2 = 1 X1 = A X2 = 1 1 = 0. Overall, we have X1 = 0, X2 = 1. * Consider A = 0, B = 1. Show that X1 = 1, X2 = 0. * Consider A = B = 1. X1 = A X2 = X2 , X2 = B X1 = X1 X1 = X2
X1
X1 0 1
X2 1 0
1 0
0 1
X2
* A, B : inputs, X1 , X2 : outputs * Consider A = 1, B = 0. B = 0 X2 = 1 X1 = A X2 = 1 1 = 0. Overall, we have X1 = 0, X2 = 1. * Consider A = 0, B = 1. Show that X1 = 1, X2 = 0. * Consider A = B = 1. X1 = A X2 = X2 , X2 = B X1 = X1 X1 = X2 If X1 = 1, X2 = 0 previously, the circuit continues to hold that state. Similarly, if X1 = 0, X2 = 1 previously, the circuit continues to hold that state.
X1
X1 0 1
X2 1 0
1 0
0 1 1
X2
previous
* A, B : inputs, X1 , X2 : outputs * Consider A = 1, B = 0. B = 0 X2 = 1 X1 = A X2 = 1 1 = 0. Overall, we have X1 = 0, X2 = 1. * Consider A = 0, B = 1. Show that X1 = 1, X2 = 0. * Consider A = B = 1. X1 = A X2 = X2 , X2 = B X1 = X1 X1 = X2 If X1 = 1, X2 = 0 previously, the circuit continues to hold that state. Similarly, if X1 = 0, X2 = 1 previously, the circuit continues to hold that state.
X1
X1 0 1
X2 1 0
1 0
0 1 1
X2
previous
* A, B : inputs, X1 , X2 : outputs * Consider A = 1, B = 0. B = 0 X2 = 1 X1 = A X2 = 1 1 = 0. Overall, we have X1 = 0, X2 = 1. * Consider A = 0, B = 1. Show that X1 = 1, X2 = 0. * Consider A = B = 1. X1 = A X2 = X2 , X2 = B X1 = X1 X1 = X2 If X1 = 1, X2 = 0 previously, the circuit continues to hold that state. Similarly, if X1 = 0, X2 = 1 previously, the circuit continues to hold that state. The circuit has latched in the previous state.
X1
X1 0 1
X2 1 0
1 0
0 1 1
X2
previous
* A, B : inputs, X1 , X2 : outputs * Consider A = 1, B = 0. B = 0 X2 = 1 X1 = A X2 = 1 1 = 0. Overall, we have X1 = 0, X2 = 1. * Consider A = 0, B = 1. Show that X1 = 1, X2 = 0. * Consider A = B = 1. X1 = A X2 = X2 , X2 = B X1 = X1 X1 = X2 If X1 = 1, X2 = 0 previously, the circuit continues to hold that state. Similarly, if X1 = 0, X2 = 1 previously, the circuit continues to hold that state. The circuit has latched in the previous state. * For A = B = 0, X1 and X2 are both 1. This combination of A and B is not allowed for reasons that will become clear later.
X1
X1 0 1
X2 1 0
1 0
0 1 1 0
X2
1 0
previous
* A, B : inputs, X1 , X2 : outputs * Consider A = 1, B = 0. B = 0 X2 = 1 X1 = A X2 = 1 1 = 0. Overall, we have X1 = 0, X2 = 1. * Consider A = 0, B = 1. Show that X1 = 1, X2 = 0. * Consider A = B = 1. X1 = A X2 = X2 , X2 = B X1 = X1 X1 = X2 If X1 = 1, X2 = 0 previously, the circuit continues to hold that state. Similarly, if X1 = 0, X2 = 1 previously, the circuit continues to hold that state. The circuit has latched in the previous state. * For A = B = 0, X1 and X2 are both 1. This combination of A and B is not allowed for reasons that will become clear later.
X1
X1 0 1
X2 1 0
1 0
0 1 1 0
X2
1 0
previous invalid
X1
X1 0 1
X2 1 0
1 0
0 1 1 0
X2
1 0
previous invalid
* The combination A = 1, B = 0 serves to reset X1 to 0 (irrespective of the previous state of the latch).
X1
X1 0 1
X2 1 0
1 0
0 1 1 0
X2
1 0
previous invalid
* The combination A = 1, B = 0 serves to reset X1 to 0 (irrespective of the previous state of the latch). * The combination A = 0, B = 1 serves to set X1 to 1 (irrespective of the previous state of the latch).
X1
X1 0 1
X2 1 0
1 0
0 1 1 0
X2
1 0
previous invalid
* The combination A = 1, B = 0 serves to reset X1 to 0 (irrespective of the previous state of the latch). * The combination A = 0, B = 1 serves to set X1 to 1 (irrespective of the previous state of the latch). * In other words, A = 1, B = 0 latch gets reset to 0. A = 0, B = 1 latch gets set to 1.
X1
X1 0 1
X2 1 0
1 0
0 1 1 0
X2
1 0
previous invalid
* The combination A = 1, B = 0 serves to reset X1 to 0 (irrespective of the previous state of the latch). * The combination A = 0, B = 1 serves to set X1 to 1 (irrespective of the previous state of the latch). * In other words, A = 1, B = 0 latch gets reset to 0. A = 0, B = 1 latch gets set to 1. * The A input is therefore called the RESET (R) input, and B is called the SET (S) input of the latch.
X1
X1 0 1
X2 1 0
1 0
0 1 1 0
X2
1 0
previous invalid
* The combination A = 1, B = 0 serves to reset X1 to 0 (irrespective of the previous state of the latch). * The combination A = 0, B = 1 serves to set X1 to 1 (irrespective of the previous state of the latch). * In other words, A = 1, B = 0 latch gets reset to 0. A = 0, B = 1 latch gets set to 1. * The A input is therefore called the RESET (R) input, and B is called the SET (S) input of the latch. * X1 is denoted by Q , and X2 (which is X1 in all cases except for A = B = 0) is denoted by Q .
X1
X1 0 1
X2 1 0
Q 0 1
Q 1 0
Q 1 0 Q 1 0 0 1 1 0
1 0
0 1 1 0
X2
1 0
previous invalid S
previous invalid
* The combination A = 1, B = 0 serves to reset X1 to 0 (irrespective of the previous state of the latch). * The combination A = 0, B = 1 serves to set X1 to 1 (irrespective of the previous state of the latch). * In other words, A = 1, B = 0 latch gets reset to 0. A = 0, B = 1 latch gets set to 1. * The A input is therefore called the RESET (R) input, and B is called the SET (S) input of the latch. * X1 is denoted by Q , and X2 (which is X1 in all cases except for A = B = 0) is denoted by Q .
R R R S
Q 0 1
Q 1 0 Q
S
Q 1 0 Q 1 0 0 1 1 0
t t t
previous invalid
Q
t
t1
t2
t3
R R R S
Q 0 1
Q 1 0 Q
S
Q 1 0 Q 1 0 0 1 1 0
t t t
previous invalid
Q
t
t1
t2
t3
* Up to t = t1 , R = 0, S = 1 Q = 1.
R R R S
Q 0 1
Q 1 0 Q
S
Q 1 0 Q 1 0 0 1 1 0
t t t
previous invalid
Q
t
t1
t2
t3
* Up to t = t1 , R = 0, S = 1 Q = 1. * At t = t1 , R goes high R = S = 1, and the latch holds its previous state no change at the output.
R R R S
Q 0 1
Q 1 0 Q
S
Q 1 0 Q 1 0 0 1 1 0
t t t
previous invalid
Q
t
t1
t2
t3
* Up to t = t1 , R = 0, S = 1 Q = 1. * At t = t1 , R goes high R = S = 1, and the latch holds its previous state no change at the output. * At t = t2 , S goes low R = 1, S = 0 Q = 0.
R R R S
Q 0 1
Q 1 0 Q
S
Q 1 0 Q 1 0 0 1 1 0
t t t
previous invalid
Q
t
t1
t2
t3
* Up to t = t1 , R = 0, S = 1 Q = 1. * At t = t1 , R goes high R = S = 1, and the latch holds its previous state no change at the output. * At t = t2 , S goes low R = 1, S = 0 Q = 0. * At t = t3 , S goes high R = S = 1, and the latch holds its previous state no change at the output.
R R R S
Q 0 1
Q 1 0 Q
S
Q 1 0 Q 1 0 0 1 1 0
t t t
previous
Q
t
t1
t2
t3
R R R S
Q 0 1
Q 1 0 Q
S
Q 1 0 Q 1 0 0 1 1 0
t t t
previous
Q
t
t1
t2
t3
* Why not allow R = S = 0?
R R R S
Q 0 1
Q 1 0 Q
S
Q 1 0 Q 1 0 0 1 1 0
t t t
previous
Q
t
t1
t2
t3
* Why not allow R = S = 0? - It makes Q = Q = 1, i.e., Q and Q are not inverse of each other any more.
R R R S
Q 0 1
Q 1 0 Q
S
Q 1 0 Q 1 0 0 1 1 0
t t t
previous
Q
t
t1
t2
t3
* Why not allow R = S = 0? - It makes Q = Q = 1, i.e., Q and Q are not inverse of each other any more. - More importantly, when R and S both become 1 simultaneously (starting from R = S = 0), the nal outputs Q and Q cannot be uniquely determined. We could have Q = 0, Q = 1 or Q = 1, Q = 0, depending on the delays associated with the two NAND gates.
R R R S
Q 0 1
Q 1 0 Q
S
Q 1 0 Q 1 0 0 1 1 0
t t t
previous
Q
t
t1
t2
t3
t4
R R R S
Q 0 1
Q 1 0 Q
S
Q 1 0 Q 1 0 0 1 1 0
t t t
previous
Q
t
t1
t2
t3
t4
R R R S
Q 0 1
Q 1 0 Q
S
Q 1 0 Q 1 0 0 1 1 0
t t t
previous
Q
t
t1
t2
t3
t4
t5
R R R S
Q 0 1
Q 1 0 Q Q t1 t2 t3 t4
S
Q 1 0 Q 1 0 0 1 1 0
t t
previous
?
t
?
t
t5
R R R S
Q 0 1
Q 1 0 Q Q t1 t2 t3 t4
S
Q 1 0 Q 1 0 0 1 1 0
t t
previous
?
t
?
t
t5
* Why not allow R = S = 0? - It makes Q = Q = 1, i.e., Q and Q are not inverse of each other any more. - More importantly, when R and S both become 1 simultaneously (starting from R = S = 0), the nal outputs Q and Q cannot be uniquely determined. We could have Q = 0, Q = 1 or Q = 1, Q = 0, depending on the delays associated with the two NAND gates. * We surely dont want any question marks in digital electronics!
NOR latch (RS latch)
Q 0 1
Q 1 0
Q 1 0 Q 0 1 0 1 0 1
previous invalid
Q 0 1
Q 1 0
Q 1 0 Q 0 1 0 1 0 1
previous invalid
* The NOR latch is similar to the NAND latch: When R = 1, S = 0, the latch gets reset to Q = 0. When R = 0, S = 1, the latch gets set to Q = 1.
Q 0 1
Q 1 0
Q 1 0 Q 0 1 0 1 0 1
previous invalid
* The NOR latch is similar to the NAND latch: When R = 1, S = 0, the latch gets reset to Q = 0. When R = 0, S = 1, the latch gets set to Q = 1. * For R = S = 0, the latch retains its previous state (i.e., the previous values of Q and Q ).
Q 0 1
Q 1 0
Q 1 0 Q 0 1 0 1 0 1
previous invalid
* The NOR latch is similar to the NAND latch: When R = 1, S = 0, the latch gets reset to Q = 0. When R = 0, S = 1, the latch gets set to Q = 1. * For R = S = 0, the latch retains its previous state (i.e., the previous values of Q and Q ). * R = S = 1 is not allowed for reasons similar to those discussed in the context of the NAND latch.
Comparison of NAND and NOR latches
Q 0 1
Q 1 0
Q 1 0 Q 1 0 0 1 1 0
previous invalid
Q 0 1
Q 1 0
Q 1 0 Q 0 1 0 1 0 1
previous invalid
Chatter (bouncing) due to a mechanical switch
B A
Vs
Vo
B A
Vs
Vo
* When the switch is thrown from A to B, Vo is expected to go from 0 V to Vs (say, 5 V ).
Vo
A
Vs
Vo
Vs
t expected
* When the switch is thrown from A to B, Vo is expected to go from 0 V to Vs (say, 5 V ).
Vo
A
Vs
Vo
Vs
t expected
* When the switch is thrown from A to B, Vo is expected to go from 0 V to Vs (say, 5 V ). * However, mechanical switches suer from chatter or bouncing, i.e., the transition from A to B is not a single, clean one. As a result, Vo oscillates between 0 V and 5 V before settling to its nal value (5 V ).
Vo
A
Vo Vs
t expected actual
Vs
Vo
Vs
t
* When the switch is thrown from A to B, Vo is expected to go from 0 V to Vs (say, 5 V ). * However, mechanical switches suer from chatter or bouncing, i.e., the transition from A to B is not a single, clean one. As a result, Vo oscillates between 0 V and 5 V before settling to its nal value (5 V ).
Vo
A
Vo Vs
t expected actual
Vs
Vo
Vs
t
* When the switch is thrown from A to B, Vo is expected to go from 0 V to Vs (say, 5 V ). * However, mechanical switches suer from chatter or bouncing, i.e., the transition from A to B is not a single, clean one. As a result, Vo oscillates between 0 V and 5 V before settling to its nal value (5 V ). * In some applications, this chatter can cause malfunction need a way to remove the chatter.
5V S R R B A S S
Q 0 1
Q 1 0
R
1 0 1 0
0 1 1 0
previous invalid
Q
t
5V
5V S R R B A S S
Q 0 1
Q 1 0
R
1 0 1 0
0 1 1 0
previous invalid
Q
t
5V
* Because of the chatter, the S and R inputs may have multiple transitions when the switch is thrown from A to B.
5V S R R B A S S
Q 0 1
Q 1 0
R
1 0 1 0
0 1 1 0
previous invalid
Q
t
5V
* Because of the chatter, the S and R inputs may have multiple transitions when the switch is thrown from A to B. * However, for S = R = 1, the previous value of Q is retained, causing a single transition in Q , as desired.
The clock
* Complex digital circuits are generally designed for synchronous operation, i.e., transitions in the various signals are synchronised with the clock.
The clock
* Complex digital circuits are generally designed for synchronous operation, i.e., transitions in the various signals are synchronised with the clock. * Synchronous circuits are easier to design and troubleshoot because the voltages at the nodes (both output nodes and internal nodes) can change only at specic times.
The clock
* Complex digital circuits are generally designed for synchronous operation, i.e., transitions in the various signals are synchronised with the clock. * Synchronous circuits are easier to design and troubleshoot because the voltages at the nodes (both output nodes and internal nodes) can change only at specic times. * A clock is a periodic signal, with a positive-going transition and a negative-going transition.
positivegoing transition 1 negativegoing transition
0 T
The clock
* Complex digital circuits are generally designed for synchronous operation, i.e., transitions in the various signals are synchronised with the clock. * Synchronous circuits are easier to design and troubleshoot because the voltages at the nodes (both output nodes and internal nodes) can change only at specic times. * A clock is a periodic signal, with a positive-going transition and a negative-going transition.
positivegoing transition 1 negativegoing transition
0 T
* The clock frequency determines the overall speed of the circuit. For example, a processor that operates with a 1 GHz clock is 10 times faster than one that operates with a 100 MHz clock.
Clocked RS latch
CLK
Q
A A B
Q 0 1
Q 1 0
Q
CLK
0 1 1
X 1 0 0 1
X 0 1 0 1
previous
1 0 1
0 1 1 0
0 1
1 0
B
previous invalid
Q
R B Clocked RS latch
1 1
previous invalid
Q 0
NAND RS latch
Clocked RS latch
CLK
Q
A A B
Q 0 1
Q 1 0
Q
CLK
0 1 1
X 1 0 0 1
X 0 1 0 1
previous
1 0 1
0 1 1 0
0 1
1 0
B
previous invalid
Q
1 1
previous invalid
Q 0
NAND RS latch
* When clock is inactive (0), A = B = 1, and the latch holds the previous state.
Clocked RS latch
CLK
Q
A A B
Q 0 1
Q 1 0
Q
CLK
0 1 1
X 1 0 0 1
X 0 1 0 1
previous
1 0 1
0 1 1 0
0 1
1 0
B
previous invalid
Q
1 1
previous invalid
Q 0
NAND RS latch
* When clock is inactive (0), A = B = 1, and the latch holds the previous state. * When clock is active (1), A = S , B = R . Using the truth table for the NAND RS latch (right), we can construct the truth table for the clocked RS latch.
Clocked RS latch
CLK
Q
A A B
Q 0 1
Q 1 0
Q
CLK
0 1 1
X 1 0 0 1
X 0 1 0 1
previous
1 0 1
0 1 1 0
0 1
1 0
B
previous invalid
Q
1 1
previous invalid
Q 0
NAND RS latch
* When clock is inactive (0), A = B = 1, and the latch holds the previous state. * When clock is active (1), A = S , B = R . Using the truth table for the NAND RS latch (right), we can construct the truth table for the clocked RS latch. * Note that the above table is sensitive to the level of the clock (i.e., whether CLK is 0 or 1).
Clocked RS latch
CLK
Q
CLK
0 1 1
X 1 0 0 1
X 0 1 0 1
previous
0 1
1 0
Q
R B
1 1
previous invalid
CLK R
S Q 0 0.2 0.4 time (msec) 0.6 0.8
(SEQUEL file: ee101_rs_1.sqproj)
Edge-triggered ip-ops
* The clocked RS latch seen previously is level-sensitive, i.e., if the clock is active (CLK = 1), the ip-op output is allowed to change, depending on the R and S inputs.
* The clocked RS latch seen previously is level-sensitive, i.e., if the clock is active (CLK = 1), the ip-op output is allowed to change, depending on the R and S inputs. * In an edge-sensitive ip-op, the output can change only at the active clock edge (i.e., CLK transition from 0 to 1 or from 1 to 0).
* The clocked RS latch seen previously is level-sensitive, i.e., if the clock is active (CLK = 1), the ip-op output is allowed to change, depending on the R and S inputs. * In an edge-sensitive ip-op, the output can change only at the active clock edge (i.e., CLK transition from 0 to 1 or from 1 to 0). * Edge-sensitive ip-ops are denoted by the following symbols:
R CLK S
R CLK
positive edgetriggered flipflop
negative edgetriggered flipflop
JK ip-op
Q 0 1
Q 1 0
1 0 1 0
0 1 1 0
CLK
previous invalid K
Q
S RS latch
Truth table for RS latch
JK ip-op
Q 0 1
Q 1 0
1 0 1 0
0 1 1 0
CLK
previous invalid K
Q
S RS latch
* When CLK = 0, we have R = S = 1, and the RS latch holds the previous Q . In other words, nothing happens as long as CLK = 0.
JK ip-op
CLK R S
Q (Qn+1 ) previous (Qn )
Q 0 1
Q 1 0
0 Q
1 0 1 0
0 1 1 0
CLK
previous invalid K
Q
S RS latch Truth table for JK flipflop
* When CLK = 0, we have R = S = 1, and the RS latch holds the previous Q . In other words, nothing happens as long as CLK = 0.
JK ip-op
CLK R S
Q 0 1
Q 1 0
0 Q
1 0 1 0
0 1 1 0
CLK
previous invalid K
Q
* When CLK = 0, we have R = S = 1, and the RS latch holds the previous Q . In other words, nothing happens as long as CLK = 0. * When CLK = 1:
JK ip-op
CLK R S
Q 0 1
Q 1 0
0 Q
1 0 1 0
0 1 1 0
CLK
previous invalid K
Q
* When CLK = 0, we have R = S = 1, and the RS latch holds the previous Q . In other words, nothing happens as long as CLK = 0. * When CLK = 1: - J = K = 0 R = S = 1, RS latch holds previous Q , i.e., Qn+1 = Qn , where n denotes the nth clock pulse (This notation will become clear shortly).
JK ip-op
CLK R S
Q (Qn+1 ) previous (Qn ) previous (Qn )
Q 0 1
Q 1 0
0 Q 1
X 0
X 0
1 0 1 0
0 1 1 0
CLK
previous invalid K
Q
* When CLK = 0, we have R = S = 1, and the RS latch holds the previous Q . In other words, nothing happens as long as CLK = 0. * When CLK = 1: - J = K = 0 R = S = 1, RS latch holds previous Q , i.e., Qn+1 = Qn , where n denotes the nth clock pulse (This notation will become clear shortly).
JK ip-op
CLK R S
Q 0 1
Q 1 0
0 Q 1
X 0
X 0
1 0 1 0
0 1 1 0
CLK
previous invalid K
Q
* When CLK = 0, we have R = S = 1, and the RS latch holds the previous Q . In other words, nothing happens as long as CLK = 0. * When CLK = 1: - J = K = 0 R = S = 1, RS latch holds previous Q , i.e., Qn+1 = Qn , where n denotes the nth clock pulse (This notation will become clear shortly). - J = 0, K = 1 R = 1, S = Qn .
JK ip-op
CLK R S
Q 0 1
Q 1 0
0 Q 1
X 0
X 0
1 0 1 0
0 1 1 0
CLK
previous invalid K
Q
* When CLK = 0, we have R = S = 1, and the RS latch holds the previous Q . In other words, nothing happens as long as CLK = 0. * When CLK = 1: - J = K = 0 R = S = 1, RS latch holds previous Q , i.e., Qn+1 = Qn , where n denotes the nth clock pulse (This notation will become clear shortly). - J = 0, K = 1 R = 1, S = Qn . Case (i): Qn = 0 S = 1 (i.e., R = S = 1) Qn+1 = Qn = 0.
JK ip-op
CLK R S
Q 0 1
Q 1 0
0 Q 1
X 0
X 0
1 0 1 0
0 1 1 0
CLK
previous invalid K
Q
* When CLK = 0, we have R = S = 1, and the RS latch holds the previous Q . In other words, nothing happens as long as CLK = 0. * When CLK = 1: - J = K = 0 R = S = 1, RS latch holds previous Q , i.e., Qn+1 = Qn , where n denotes the nth clock pulse (This notation will become clear shortly). - J = 0, K = 1 R = 1, S = Qn . Case (i): Qn = 0 S = 1 (i.e., R = S = 1) Qn+1 = Qn = 0. Case (ii): Qn = 1 S = 0 (i.e., R = 1, S = 0) Qn+1 = 0.
JK ip-op
CLK R S
Q 0 1
Q 1 0
0 Q 1
X 0
X 0
1 0 1 0
0 1 1 0
CLK
previous invalid K
Q
* When CLK = 0, we have R = S = 1, and the RS latch holds the previous Q . In other words, nothing happens as long as CLK = 0. * When CLK = 1: - J = K = 0 R = S = 1, RS latch holds previous Q , i.e., Qn+1 = Qn , where n denotes the nth clock pulse (This notation will become clear shortly). - J = 0, K = 1 R = 1, S = Qn . Case (i): Qn = 0 S = 1 (i.e., R = S = 1) Qn+1 = Qn = 0. Case (ii): Qn = 1 S = 0 (i.e., R = 1, S = 0) Qn+1 = 0. In either case, Qn+1 = 0 For J = 0, K = 1, Qn+1 = 0.
JK ip-op
CLK R S
Q (Qn+1 ) previous (Qn ) previous (Qn ) 0
Q 0 1
Q 1 0
0 Q 1
X 0 0
X 0 1
1 0 1 0
0 1 1 0
CLK
1 Q
S RS latch
previous invalid K
Truth table for JK flipflop
* When CLK = 0, we have R = S = 1, and the RS latch holds the previous Q . In other words, nothing happens as long as CLK = 0. * When CLK = 1: - J = K = 0 R = S = 1, RS latch holds previous Q , i.e., Qn+1 = Qn , where n denotes the nth clock pulse (This notation will become clear shortly). - J = 0, K = 1 R = 1, S = Qn . Case (i): Qn = 0 S = 1 (i.e., R = S = 1) Qn+1 = Qn = 0. Case (ii): Qn = 1 S = 0 (i.e., R = 1, S = 0) Qn+1 = 0. In either case, Qn+1 = 0 For J = 0, K = 1, Qn+1 = 0.
JK ip-op
CLK R S
Q 0 1
Q 1 0
0 Q 1 1 Q
X 0 0
X 0 1
1 0 1 0
0 1 1 0
CLK
previous invalid K S
RS latch Truth table for JK flipflop
JK ip-op
CLK R S
Q 0 1
Q 1 0
0 Q 1 1 Q
X 0 0
X 0 1
1 0 1 0
0 1 1 0
CLK
* When CLK = 1: - Consider J = 1, K = 0 S = 1, R = Qn = Qn .
JK ip-op
CLK R S
Q 0 1
Q 1 0
0 Q 1 1 Q
X 0 0
X 0 1
1 0 1 0
0 1 1 0
CLK
* When CLK = 1: - Consider J = 1, K = 0 S = 1, R = Qn = Qn . Case (i): Qn = 0 R = 0 (i.e., R = 0, S = 1) Qn+1 = 1.
JK ip-op
CLK R S
Q 0 1
Q 1 0
0 Q 1 1 Q
X 0 0
X 0 1
1 0 1 0
0 1 1 0
CLK
* When CLK = 1: - Consider J = 1, K = 0 S = 1, R = Qn = Qn . Case (i): Qn = 0 R = 0 (i.e., R = 0, S = 1) Qn+1 = 1. Case (ii): Qn = 1 R = 1 (i.e., R = 1, S = 1) Qn+1 = Qn = 1.
JK ip-op
CLK R S
Q 0 1
Q 1 0
0 Q 1 1 Q
X 0 0
X 0 1
1 0 1 0
0 1 1 0
CLK
* When CLK = 1: - Consider J = 1, K = 0 S = 1, R = Qn = Qn . Case (i): Qn = 0 R = 0 (i.e., R = 0, S = 1) Qn+1 = 1. Case (ii): Qn = 1 R = 1 (i.e., R = 1, S = 1) Qn+1 = Qn = 1. For J = 1, K = 0, Qn+1 = 1.
JK ip-op
CLK R S
Q (Qn+1 ) previous (Qn ) previous (Qn ) 0 1
Q 0 1
Q 1 0
0 Q 1 1 Q 1
X 0 0 1
X 0 1 0
1 0 1 0
0 1 1 0
CLK
* When CLK = 1: - Consider J = 1, K = 0 S = 1, R = Qn = Qn . Case (i): Qn = 0 R = 0 (i.e., R = 0, S = 1) Qn+1 = 1. Case (ii): Qn = 1 R = 1 (i.e., R = 1, S = 1) Qn+1 = Qn = 1. For J = 1, K = 0, Qn+1 = 1.
JK ip-op
CLK R S
Q 0 1
Q 1 0
0 Q 1 1 Q 1
X 0 0 1
X 0 1 0
1 0 1 0
0 1 1 0
CLK
* When CLK = 1: - Consider J = 1, K = 0 S = 1, R = Qn = Qn . Case (i): Qn = 0 R = 0 (i.e., R = 0, S = 1) Qn+1 = 1. Case (ii): Qn = 1 R = 1 (i.e., R = 1, S = 1) Qn+1 = Qn = 1. For J = 1, K = 0, Qn+1 = 1. - Consider J = 1, K = 1 R = Qn , S = Qn .
JK ip-op
CLK R S
Q 0 1
Q 1 0
0 Q 1 1 Q 1
X 0 0 1
X 0 1 0
1 0 1 0
0 1 1 0
CLK
* When CLK = 1: - Consider J = 1, K = 0 S = 1, R = Qn = Qn . Case (i): Qn = 0 R = 0 (i.e., R = 0, S = 1) Qn+1 = 1. Case (ii): Qn = 1 R = 1 (i.e., R = 1, S = 1) Qn+1 = Qn = 1. For J = 1, K = 0, Qn+1 = 1. - Consider J = 1, K = 1 R = Qn , S = Qn . Case (i): Qn = 0 R = 0, S = 1 Qn+1 = 1.
JK ip-op
CLK R S
Q 0 1
Q 1 0
0 Q 1 1 Q 1
X 0 0 1
X 0 1 0
1 0 1 0
0 1 1 0
CLK
* When CLK = 1: - Consider J = 1, K = 0 S = 1, R = Qn = Qn . Case (i): Qn = 0 R = 0 (i.e., R = 0, S = 1) Qn+1 = 1. Case (ii): Qn = 1 R = 1 (i.e., R = 1, S = 1) Qn+1 = Qn = 1. For J = 1, K = 0, Qn+1 = 1. - Consider J = 1, K = 1 R = Qn , S = Qn . Case (i): Qn = 0 R = 0, S = 1 Qn+1 = 1. Case (ii): Qn = 1 R = 1, S = 0 Qn+1 = 0.
JK ip-op
CLK R S
Q 0 1
Q 1 0
0 Q 1 1 Q 1
X 0 0 1
X 0 1 0
1 0 1 0
0 1 1 0
CLK
* When CLK = 1: - Consider J = 1, K = 0 S = 1, R = Qn = Qn . Case (i): Qn = 0 R = 0 (i.e., R = 0, S = 1) Qn+1 = 1. Case (ii): Qn = 1 R = 1 (i.e., R = 1, S = 1) Qn+1 = Qn = 1. For J = 1, K = 0, Qn+1 = 1. - Consider J = 1, K = 1 R = Qn , S = Qn . Case (i): Qn = 0 R = 0, S = 1 Qn+1 = 1. Case (ii): Qn = 1 R = 1, S = 0 Qn+1 = 0. For J = 1, K = 1, Qn+1 = Qn .
JK ip-op
CLK R S
Q (Qn+1 ) previous (Qn ) previous (Qn ) 0 1 toggles (Qn )
Q 0 1
Q 1 0
0 Q 1 1 Q 1 1
X 0 0 1 1
X 0 1 0 1
1 0 1 0
0 1 1 0
CLK
RS latch
* When CLK = 1: - Consider J = 1, K = 0 S = 1, R = Qn = Qn . Case (i): Qn = 0 R = 0 (i.e., R = 0, S = 1) Qn+1 = 1. Case (ii): Qn = 1 R = 1 (i.e., R = 1, S = 1) Qn+1 = Qn = 1. For J = 1, K = 0, Qn+1 = 1. - Consider J = 1, K = 1 R = Qn , S = Qn . Case (i): Qn = 0 R = 0, S = 1 Qn+1 = 1. Case (ii): Qn = 1 R = 1, S = 0 Qn+1 = 0. For J = 1, K = 1, Qn+1 = Qn .
JK ip-op
CLK J R
0 Q 1 1 Q 1 1
X 0 0 1 1
X 0 1 0 1
CLK
RS latch
Consider J = K = 1 and CLK = 1.
JK ip-op
CLK J R
0 Q 1 1 Q 1 1
X 0 0 1 1
X 0 1 0 1
CLK
RS latch
Consider J = K = 1 and CLK = 1. As long as CLK = 1, Q will keep toggling! (The frequency will depend on the delay values of the various gates).
JK ip-op
CLK J R
0 Q 1 1 Q 1 1
X 0 0 1 1
X 0 1 0 1
CLK
RS latch
Consider J = K = 1 and CLK = 1. As long as CLK = 1, Q will keep toggling! (The frequency will depend on the delay values of the various gates). When CLK changes from 1 to 0, the toggling will stop. However, the nal value of Q is not known; it could be 0 or 1.
JK ip-op
CLK J R
0 Q 1 1 Q 1 1
X 0 0 1 1
X 0 1 0 1
CLK
RS latch
Consider J = K = 1 and CLK = 1. As long as CLK = 1, Q will keep toggling! (The frequency will depend on the delay values of the various gates). When CLK changes from 1 to 0, the toggling will stop. However, the nal value of Q is not known; it could be 0 or 1. Use the Master-slave conguration.
JK ip-op (Master-Slave)
Master
Slave
R1
Q1
R2
Q S1
RS latch 1
S2
RS latch 2
CLK
CLK
Master
Slave
R1
Q1
R2
Q S1
RS latch 1
S2
RS latch 2
CLK
CLK
* When CLK goes high, only the rst latch is aected; the second latch retains its previous value (because CLK = 0 R2 = S2 = 1).
Master
Slave
R1
Q1
R2
Q S1
RS latch 1
S2
RS latch 2
CLK
CLK
* When CLK goes high, only the rst latch is aected; the second latch retains its previous value (because CLK = 0 R2 = S2 = 1). * When CLK goes low, the output of the rst latch (Q1 ) is retained (since R1 = S1 = 1), and Q1 can now aect Q .
Master
Slave
R1
Q1
R2
Q S1
RS latch 1
S2
RS latch 2
CLK
CLK
* When CLK goes high, only the rst latch is aected; the second latch retains its previous value (because CLK = 0 R2 = S2 = 1). * When CLK goes low, the output of the rst latch (Q1 ) is retained (since R1 = S1 = 1), and Q1 can now aect Q . * In other words, the eect of any changes in J and K appears at the output Q only when CLK makes a transition from 1 to 0. This is therefore a negative edge-triggered ip-op.
Master
Slave
CLK
Qn+1 Qn 0 1 Qn
R1
Q1
R2
0 0 1
0 1 0 1
Q S1
RS latch 1
S2
1
RS latch 2
CLK
CLK
* When CLK goes high, only the rst latch is aected; the second latch retains its previous value (because CLK = 0 R2 = S2 = 1). * When CLK goes low, the output of the rst latch (Q1 ) is retained (since R1 = S1 = 1), and Q1 can now aect Q . * In other words, the eect of any changes in J and K appears at the output Q only when CLK makes a transition from 1 to 0. This is therefore a negative edge-triggered ip-op.
Master
Slave
CLK
Qn+1 Qn 0 1 Qn
R1
Q1
R2
0 0 1
0 1 0 1
Q S1
RS latch 1
S2
1
RS latch 2
CLK
CLK
* When CLK goes high, only the rst latch is aected; the second latch retains its previous value (because CLK = 0 R2 = S2 = 1). * When CLK goes low, the output of the rst latch (Q1 ) is retained (since R1 = S1 = 1), and Q1 can now aect Q . * In other words, the eect of any changes in J and K appears at the output Q only when CLK makes a transition from 1 to 0. This is therefore a negative edge-triggered ip-op. * Note that, unlike the RS NAND latch which does not allow one of the combinations of R and S (viz., R = S = 0), the JK ip-op allows all four combinations.
JK ip-op
CLK J CLK K
Qn+1 Qn 0 1 Qn
J CLK K
CLK
Qn+1 Qn 0 1 Qn
0 0
0 1 0 1
0 0
0 1 0 1
1 1
1 1
positive edgetriggered JK flipflop
negative edgetriggered JK flipflop
JK ip-op
CLK J CLK K
Qn+1 Qn 0 1 Qn
J CLK K
CLK
Qn+1 Qn 0 1 Qn
0 0
0 1 0 1
0 0
0 1 0 1
1 1
1 1
* Both negative (e.g., 74101) and positive (e.g., 7470) edge-triggered JK ip-ops are available as ICs.
JK ip-op
J Master K
Q1
Slave
Q CLK Q
Q1 CLK CLK
t1A t1B
t2A t2B
Consider a negative edge-triggered JK ip-op.
JK ip-op
J Master K
Q1
Slave
Q CLK Q
Q1 CLK CLK
t1A t1B
t2A t2B
Consider a negative edge-triggered JK ip-op. * As seen earlier, when CLK is high (i.e., t1A < t < t1B , etc.), the input J and K determine the Master latch output Q1 . During this time, no change is visible at the ip-op output Q .
JK ip-op
J Master K
Q1
Slave
Q CLK Q
Q1 CLK CLK
t1A t1B
t2A t2B
Consider a negative edge-triggered JK ip-op. * As seen earlier, when CLK is high (i.e., t1A < t < t1B , etc.), the input J and K determine the Master latch output Q1 . During this time, no change is visible at the ip-op output Q . * When the clock goes low, the Slave ip-op becomes active, making it possible for Q to change.
JK ip-op
J Master K
Q1
Slave
Q CLK Q
Q1 CLK CLK
t1A t1B
t2A t2B
Consider a negative edge-triggered JK ip-op. * As seen earlier, when CLK is high (i.e., t1A < t < t1B , etc.), the input J and K determine the Master latch output Q1 . During this time, no change is visible at the ip-op output Q . * When the clock goes low, the Slave ip-op becomes active, making it possible for Q to change. * In short, although the ip-op output Q can only change after the active edge, (t1B , t2B , etc.), the new Q value is determined by J and K values just before the active edge.
JK ip-op
J Master K
Q1
Slave
Q CLK Q
Q1 CLK CLK
t1A t1B
t2A t2B
Consider a negative edge-triggered JK ip-op. * As seen earlier, when CLK is high (i.e., t1A < t < t1B , etc.), the input J and K determine the Master latch output Q1 . During this time, no change is visible at the ip-op output Q . * When the clock goes low, the Slave ip-op becomes active, making it possible for Q to change. * In short, although the ip-op output Q can only change after the active edge, (t1B , t2B , etc.), the new Q value is determined by J and K values just before the active edge. This is a very important point!
JK ip-op
CLK J CLK K
Qn+1 Qn 0 1 Qn
0 0
0 1 0 1
1 1
CLK J K Q 0 0.1 0.2 0.3 0.4 time (msec) 0.5 0.6
JK ip-op
CLK J CLK K
Qn+1 Qn 0 1 Qn
J CLK K
CLK
Qn+1 Qn 0 1 Qn
0 0
0 1 0 1
0 0
0 1 0 1
1 1
1 1
CLK J K Q 0 0.1 0.2 0.3 0.4 time (msec) 0.5 0.6
CLK J K Q 0 0.1 0.2 0.3 0.4 time (msec) 0.5 0.6
JK ip-op
J1 = K1 = 1. Assume Q1 = Q2 = 0 initially.
1
CLK
J1
Q1
J2
Q2
Q1
t
K1
CLK
K2
Q2
t
t1
t2
t3
t4
t5
JK ip-op
1
CLK
J1
Q1
J2
Q2
Q1
t
K1
CLK
K2
Q2
t
t1
t2
t3
t4
t5
* Since J1 = K1 = 1, Q1 toggles after every active clock edge.
JK ip-op
1
CLK
J1
Q1
J2
Q2
Q1
t
K1
CLK
K2
Q2
t
t1
t2
t3
t4
t5
* Since J1 = K1 = 1, Q1 toggles after every active clock edge.
JK ip-op
1
CLK
J1
Q1
J2
Q2
Q1
t
K1
CLK
K2
Q2
t
t1
t2
t3
t4
t5
* Since J1 = K1 = 1, Q1 toggles after every active clock edge. * J2 = Q1 , K2 = Q1 . We need to look at J2 and K2 values just before the active edge, to determine the next value of Q2 .
JK ip-op
1
CLK
J1
Q1
J2
Q2
Q1
t
K1
CLK
K2
Q2
t
t1
t2
t3
t4
t5
* Since J1 = K1 = 1, Q1 toggles after every active clock edge. * J2 = Q1 , K2 = Q1 . We need to look at J2 and K2 values just before the active edge, to determine the next value of Q2 . * It is convenient to construct a table listing J2 and K2 to gure out the next Q2 value.
JK ip-op
1
CLK
t t
+ J2 (t = t k ) K2 (t = tk ) Q2 (t = tk )
J1
Q1
J2
Q2
t1 t2
1 0 1 0 1
0 1 0 1 0
1 0 1 0 1
Q1
t
t3 t4
K1
CLK
K2
Q2
t
t5
t1
t2
t3
t4
t5
JK ip-op
1
CLK
t t
+ J2 (t = t k ) K2 (t = tk ) Q2 (t = tk )
J1
Q1
J2
Q2
t1 t2
1 0 1 0 1
0 1 0 1 0
1 0 1 0 1
Q1
t
t3 t4
K1
CLK
K2
Q2
t
t5
t1
t2
t3
t4
t5
JK ip-op
1
CLK
t t
+ J2 (t = t k ) K2 (t = tk ) Q2 (t = tk )
J1
Q1
J2
Q2
t1 t2
1 0 1 0 1
0 1 0 1 0
1 0 1 0 1
Q1
t
t3 t4
K1
CLK
K2
Q2
t
t5
t1
t2
t3
t4
t5
* Since J1 = K1 = 1, Q1 toggles after every active clock edge. * J2 = Q1 , K2 = Q1 . We need to look at J2 and K2 values just before the active edge, to determine the next value of Q2 . * It is convenient to construct a table listing J2 and K2 to gure out the next Q2 value. * Note that the circuit is not doing much, apart from taxing our minds! But hold on, some useful circuits will appear soon.

Ee101 DGTL 4

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EE101: Digital circuits (Part 4)

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

NAND latch (RS latch)

NAND latch (RS latch)

* A, B : inputs, X1 , X2 : outputs * Consider A = 1, B = 0.

NAND latch (RS latch)

* A, B : inputs, X1 , X2 : outputs * Consider A = 1, B = 0. B = 0 X2 = 1 X1 = A X2 = 1 1 = 0.

NAND latch (RS latch)

* A, B : inputs, X1 , X2 : outputs * Consider A = 1, B = 0. B = 0 X2 = 1 X1 = A X2 = 1 1 = 0. Overall, we have X1 = 0, X2 = 1.

NAND latch (RS latch)

* A, B : inputs, X1 , X2 : outputs * Consider A = 1, B = 0. B = 0 X2 = 1 X1 = A X2 = 1 1 = 0. Overall, we have X1 = 0, X2 = 1.

NAND latch (RS latch)

* A, B : inputs, X1 , X2 : outputs * Consider A = 1, B = 0. B = 0 X2 = 1 X1 = A X2 = 1 1 = 0. Overall, we have X1 = 0, X2 = 1. * Consider A = 0, B = 1. Show that X1 = 1, X2 = 0.

NAND latch (RS latch)

* A, B : inputs, X1 , X2 : outputs * Consider A = 1, B = 0. B = 0 X2 = 1 X1 = A X2 = 1 1 = 0. Overall, we have X1 = 0, X2 = 1. * Consider A = 0, B = 1. Show that X1 = 1, X2 = 0.

NAND latch (RS latch)

* A, B : inputs, X1 , X2 : outputs * Consider A = 1, B = 0. B = 0 X2 = 1 X1 = A X2 = 1 1 = 0. Overall, we have X1 = 0, X2 = 1. * Consider A = 0, B = 1. Show that X1 = 1, X2 = 0. * Consider A = B = 1.

NAND latch (RS latch)

* A, B : inputs, X1 , X2 : outputs * Consider A = 1, B = 0. B = 0 X2 = 1 X1 = A X2 = 1 1 = 0. Overall, we have X1 = 0, X2 = 1. * Consider A = 0, B = 1. Show that X1 = 1, X2 = 0. * Consider A = B = 1. X1 = A X2 = X2 , X2 = B X1 = X1 X1 = X2

NAND latch (RS latch)

NAND latch (RS latch)

NAND latch (RS latch)

NAND latch (RS latch)

NAND latch (RS latch)

M. B. Patil, IIT Bombay

NAND latch (RS latch)

NAND latch (RS latch)

NAND latch (RS latch)

NAND latch (RS latch)

NAND latch (RS latch)

NAND latch (RS latch)

NAND latch (RS latch)

M. B. Patil, IIT Bombay

NAND latch (RS latch)

M. B. Patil, IIT Bombay

NAND latch (RS latch)

M. B. Patil, IIT Bombay

NAND latch (RS latch)

M. B. Patil, IIT Bombay

NAND latch (RS latch)

M. B. Patil, IIT Bombay

NAND latch (RS latch)

M. B. Patil, IIT Bombay

NAND latch (RS latch)

NAND latch (RS latch)

* Why not allow R = S = 0?

NAND latch (RS latch)

NAND latch (RS latch)

NAND latch (RS latch)

NAND latch (RS latch)

NAND latch (RS latch)

NAND latch (RS latch)

NAND latch (RS latch)

M. B. Patil, IIT Bombay

NOR latch (RS latch)

M. B. Patil, IIT Bombay

NOR latch (RS latch)