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Sunday, October 31, 2010

Sequence detector using state machine in VHDL


Some readers were asking for more examples related with state machine and some where asking for codes related with sequence detector.This article will be helpful for state machine designers and for people who try to implement sequence detector circuit in VHDL. I have created a state machine for non-overlapping detection of a pattern "1011" in a sequence of bits. The state machine diagram is given below for your reference.

The VHDL code for the same is given below. I have added comments for your easy understanding.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; --Sequence detector for detecting the sequence "1011". --Non overlapping type. entity seq_det is port( clk : in std_logic; --clock signal reset : in std_logic; --reset signal seq : in std_logic; --serial bit sequence det_vld : out std_logic --A '1' indicates the pattern "1011" is detected in the sequence. ); end seq_det; architecture Behavioral of seq_det is type state_type is (A,B,C,D); --Defines the type for states in the state machine signal state : state_type := A; --Declare the signal with the corresponding state type. begin process(clk) begin if( reset = '1' ) then det_vld <= '0';

--resets state and output signal when reset is asserted.

state <= A; elsif ( rising_edge(clk) ) then --calculates the next state based on current state and input bit. case state is when A => --when the current state is A. det_vld <= '0'; if ( seq = '0' ) then state <= A; else state <= B; end if; when B => --when the current state is B. if ( seq = '0' ) then state <= C; else state <= B; end if; when C => --when the current state is C. if ( seq = '0' ) then state <= A; else state <= D; end if; when D => --when the current state is D. if ( seq = '0' ) then state <= C; else state <= A; det_vld <= '1'; --Output is asserted when the pattern "1011" is found in the sequence. end if; when others => NULL; end case; end if; end process; end Behavioral;
If you check the code you can see that in each state we go to the next state depending on the current value of inputs.So this is a mealy typestate machine. The testbench code used for testing the design is given below.It sends a sequence of bits "1101110101" to the module. The code doesnt exploit all the possible input sequences. If you want another sequence to be checked then edit the testbench code. If it is not working as expected, let me know.

LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY blog_cg IS END blog_cg; ARCHITECTURE behavior OF blog_cg IS signal clk,reset,seq,det_vld : std_logic := '0'; constant clk_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: entity work.seq_det PORT MAP ( clk => clk, reset => reset, seq => seq, det_vld => det_vld ); -- Clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1';

wait for clk_period/2; end process; -- Stimulus process : Apply the bits in the sequence one by one. stim_proc: process begin seq <= '1'; --1 wait for clk_period; seq <= '1'; --11 wait for clk_period; seq <= '0'; --110 wait for clk_period; seq <= '1'; --1101 wait for clk_period; seq <= '1'; --11011 wait for clk_period; seq <= '1'; --110111 wait for clk_period; seq <= '0'; --1101110 wait for clk_period; seq <= '1'; --11011101 wait for clk_period; seq <= '0'; --110111010 wait for clk_period; seq <= '1'; --1101110101 wait for clk_period; wait; end process; END;
The simulated waveform is shown below:

Note:- The code was simulated using Xilinx 12.1 version. The results may vary slightly depending on your sim