Homework 3 ECE 4530 Due Oct 1.

The goal of this homework is to go through the design of a simple amplifier, similar to what would be needed to drive a high-bandwidth signal off chip onto a transmission line. You will verify your results in Lab 3. Your specifications are to design and amplifier which provides a voltage gain (Vout/Vs) of 10 (20dB), with a 3-dB bandwidth of 250MHz while driving an output load of 50 Ohms in parallel with 1pF (this is a good model of a data bus on a board) the 50 Ohm load can be tied to either ground or Vdd (Vdd = 2.5V). Your source impedance is 300 Ohms. That is: you have this situation:

300 Vout 50 Vs Vsupp either (gnd or Vdd) 1pF

Starting with the 6 topologies on the next page, which you simulated in Lab 2a, your goal is to design an amplifier that meets or exceeds the above gain and bandwidth specs, while consuming minimum total bias current. Your available design parameters are: input bias voltage Vin = Vs, RL1 and RL2, W, and L of each transistor, and Vsupp (which can either be Vdd or gnd). You may assume the following properties for your transistors (though you may not need them all): VTH = 600mV ncox = 400A/V2 Lmin = 0.25 m -1 = 0.5V for L = Lmin, (assume =0.5V-1*Lmin/L) gmb/gm = 0.1 2 cox = 4fF/m col = 0.6fF/ m cj = 1fF/ m assume that: Cgs = 2/3W*L*cox+W*col Cgd = W*col And Cdb=Csb=W*cj

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VDD RL1 Vout

VDD 2) RL1 Vout Vbias Vin 3) Vin

VDD

Vin

Vout RL1

4)

VDD RL1 RL2 Vout

5) Vbias

VDD RL1 Vout

6)

VDD RL1

Vin VIN

Vin

Vout RL2

We will attack this problem in a series of steps, intended to reduce the number of free parameters while building intuition about these circuits. You should feel free to use Cadence and the results of lab 2a to check yourself at each stage, as well as to inform your intuition. Follow the steps described below: Although there is not really a single right answer to an open-ended design problem like this, many of these steps ask for answers that can be right or wrong. One of the keys to good design is eliminating bad ideas as quickly as possible, so as you work through the problem, you should identify topologies that are inferior, and eliminate them. Among other things, this will save you having to analyze them at later steps (less work = good). BONUS: come up with your own topology (no more than 4 transistors) proceed through the same steps and show that it outperforms the given amplifiers when optimized. Although each student needs to do their own work, I VERY STRONGLY RECOMEND DOING THIS IN A GROUP!!! Step 1: Identify each topology (or combination of topologies) above (ie (1) is a common source amplifier, etc). List them in your answer. Based upon what you know of these types of amplifier, and your specifications, eliminate at least one topology from contention: explain why in one or two sentences.

Step 2: for the remaining topologies, compute DC gain in each case. To do this, write out the simplest low frequency small signal model possible: that is, include gm for each device, and include ro only if necessary (hint: compute the minimum value for gm*ro) to define the impedance of a given node. Also include the explicit resistors, including 50 ohm load and 300 ohm source: can you proceed to ignore any of the gms based on topology? If so, do so. Try to eliminate at least one more topology based on the results (hint compute the maximum possible gain in each case: you may need to put ro back in to compute this). For each topology, state which components you can probably safely ignore Step 3: for the remaining topologies, work out the required relationships between gm and RL to get the desired gain. For the multi-stage amplifiers you will need to make a (slightly arbitrary) decision about how to distribute gain between the two stages: you need to choose the gain of the first stage, Av1, and second stage, Av2, so that Av1*Av2 = 5. Ultimately this gain distribution is something you may want to optimize, but the next few steps are much easier if you make a reasonable first guess. You may then want to loop back to this step after step 6 and revise your choice. Here are a few reasonable rules of thumb when making arbitrary decisions like this in high-bandwidth systems: 1) keep gm of a transistor equal to or greater than one over the resistance it drives (gm 1/RL), otherwise gain will be significantly less than one and the amplifier isnt an amplifier. 2) For common source stages, where reasonably accurate gain matters, keep gain per stage well below gmro (since ro is poorly controlled). 3) Put your higher-gain stage early (good for noise, often good for power consumption) 4) For simplicity, make the gains nice integers, or at least low-order ratios of integers (ie, 4, 2 1, , etc). Step 4: Estimate power consumption in order to achieve the gms from step 3, what must each ID be, and so, what must the total current consumption be? In most cases you will find that this depends on your choice of RL as well as VOD for each transistor. If we make the assumption that VOD = 200mV for each transistor and send RL, are there obvious winners/losers? Dont eliminate the losers just yet, but this gives you a sense of where this is going. Step 5: for the remaining topologies, work out the restrictions on bias points (ie ID and Vod) of each transistor to ensure that all transistors remain in saturation (assume squarelaw). These will take the form of inequalities relating Vod, RL, and ID. Also, where needed, compute the dependence of Vod2 on RL1 and ID1. At this point you should make an intelligent decision about the value of Vsupp for each topology to make biasing as easy as possible.

Step 6: Find the total current as a function of the overdrive voltages of the transistors and RL. Do this for each remaining topology, while meeting the restrictions from steps 3, 4 and 5. Find the minimum current in each case (by varying RL, VOD), while keeping VOD greater or equal to 100mV, so that the square-law is valid. The current you calculate wont necessarily be sufficient when trying to meet bandwidth requirements too, but it provides a good guess at the relative efficiency of different designs. Are there any obvious losers? If so, dump them (but keep at least 2). Comment on how this compares to your observations in part 4. Step 7: For the remaining designs, translate the equations from step 3 into descriptions involving W/L: In particular, solve for W/L in terms of Vod and RL. Simplify your life by defining k = ncox Step 8: Now we look at bandwidth: for each of the nodes of each of the remaining topologies (there will be 2 or 3 nodes), find the effective capacitance and resistance. Be sure to account for Miller effect: you already know the gain of each stage, since you picked it! Compute R and C as a function of RL, W and L and in terms of known constants such as cox, col, etc. Compute the pole frequency at each node. Rather than trying to solve for the 3db bandwidth of a multi-pole system, write the equation for attenuation of the signal at = 2500MHz in terms of these pole values: to meet the bandwidth specification, you will need simply to make this attenuation less than 3dB. Helpful note: 20*log(|1/(1+j/p)|) = -10*log(1+(/p)2) Step 9: If you have not already, narrow your choices down to two topologies. Copy the design equations (or inequalities) from above for those topologies: Specifically, write out the equations for W/L and Itot as a function of Vin and RL. Also copy the equations for each pole as a function of W, L, RL and Vin, as well as the equation for attenuation as a function of these poles. Before copying them down, simplify matters by identifying parameters that seem to provide optimal results at extreme values (ie do things get better as RL , and/or as L0?) set them to extreme values (RL implies removing RL entirely, L0 is impossible, so set L = Lmin). Note: what does better mean? Here it means higher frequency poles, lower power consumption. State whatever simplifications you are making. Simplify your equations and write them out, but dont try to solve them by hand: there is a lot of nasty, nasty algebra even in these simple cases. However, for each case, think about the following questions and write one or two sentences to describe, qualitatively, how: a) If you apply the equations for W/L to maintain gain, how does increasing Vin affect the power consumption of the circuit? b) How does it affect the pole locations? c) Similarly, how does RL affect current and pole locations? d) If you were to slightly increase W for each device, how would that affect gain, bandwidth and current consumption?

Step 10: optimize: You can try to solve this closed form if you really want too, but the math is very unpleasant. Instead, plug your equations into a numerical math solver (ie excel, MATLAB, Mathcad, etc), and fiddle with your free variables (Vin and RL) to get minimum current while preserving bandwidth and gain. Once you find the optimum, extract and report all of the critical design parameters you find: Vin, Vbias, W, L, RL. Also, report which pole dominates your bandwidth (ie which is lowest frequency) Input? Output? A middle pole? Finally, which topology is lowest power? Eliminate the other one. Heres how you do it in Excel: I made fields (columns) for Vin and RL, which I could change. Then I created columns where I computed W and L for each device, as well as columns where I computed Vds and Vod for each device to ensure that they were in saturation. From W and L I computed the pole at each node, each in its own column, and so created a column where I computed attenuation at 250MHz. By sweeping my free variables, based on my understanding from above, I looked for the values that gave me minimum current while still providing less than 3dB attenuation at 250MHz. Step 11: Write a few sentences about how parameters you neglected (ie ro, gmb) could affect your circuit: especially gain, bandwidth and power consumption. Also discuss how you can adjust your design to correct these errors. Similarly, the parameters given at the start of the problem are almost certainly in correct, describe how errors in each parameter might affect the performance of your circuit, and how you might correct for these errors. Finally, discuss how short-channel effects would degrade your design. Step 12: Overdesign. Every time you make things more realistic, they will get worse: lower gain, higher power, lower bandwidth, etc. So simulation with real components is worse than hand calculations, and real circuits are worse than simulation. Thus, it is always a good idea to over-design a bit. In this case, we will overdesign in terms of bandwidth. For your final design, using the same approach as in step 10, re-optimize so that attenuation at 250MHz is only 1dB. This will provide a better starting point, in terms of component values, for optimization in cadence (Lab 2b).