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Description a) Write a Verilog Code to simulate SR- Flip/Flop and JK- Master- Slave Flip/Flop and Synthesize the design for 1ns timing constraints. b) Design a CMOS Differential Amplifier with proper aspect ratio to amplify 5mv of 1KHz and 10mv of 1KHz inputs and perform Transient & DC Analysis. a) Write a Verilog Code to simulate 4- Bit Serial Adder and Synthesize the design for 1ns timing constraints. b) Design a CMOS Inverter with proper aspect ratio and perform Transient & DC Analysis for a input signal of pulse period 30ns and pulse width 20ns. a) Write a Verilog Code to simulate 4- Bit Successive Approximation register[SAR] and Synthesize the design for 1ns timing constraints. b) Design a CMOS Common- Drain Amplifier with proper aspect ratio to amplify 5mv of 1KHz and perform Transient & DC Analysis. a) Write a Verilog Code to simulate 4- Bit Synchronous UP Counter and Synthesize the design for 1ns timing constraints. b) Design a CMOS Common- Source Amplifier with proper aspect ratio to amplify 100mv of 2KHz and perform Transient & DC Analysis. a) Write a Verilog Code to simulate 4- Bit Synchronous UP Counter and Synthesize the design for 1ns timing constraints. b) Design a CMOS Common- Source Amplifier with proper aspect ratio to amplify 500mv of 2KHz and perform Transient & DC Analysis. a) Write a Verilog Code to simulate 4- Bit Asynchronous UP Counter and Synthesize the design for 1ns timing constraints. b) Design a CMOS Common- Drain Amplifier with proper aspect ratio to amplify 5mv of 1KHz and perform Transient & DC Analysis. a) Write a Verilog Code to Simulate 4- Bit Serial-In & Serial Out Shift register and Synthesize the design for 1ns timing constraints. b) Design a CMOS Common- Source Amplifier with proper aspect ratio to amplify 500mv of 2KHz and perform Transient & DC Analysis. a) Write a Verilog Code to simulate 5- Bit Parallel Adder to add 32 and 30. b) Design a CMOS Op- Amp with proper aspect ratio to amplify 10mv of 2KHz and 5mv of 2KHz inputs and perform Transient & DC Analysis. a) Write a Verilog Code to simulate Ex-OR Gate using minimum number of NAND Gates Using Switch Level Description. b) Design a CMOS Op- Amp with proper aspect ratio to amplify 5mv of 5KHz and 3mv of 5KHz inputs and perform Transient & DC Analysis. a) Write a Verilog Code to simulate 4- Bit Asynchronous Down Counter and Synthesize the design for 1ns timing constraints. b) Design a CMOS Common- Drain Amplifier with proper aspect ratio to amplify 100mv of 10KHz and perform Transient & DC Analysis. a) Write a Verilog Code to simulate 3- input AND & OR Gates using Switch Level Description. b) Design a CMOS Differential Amplifier with proper aspect ratio to amplify 5mv of 1KHz and 2mv of 1KHz inputs and perform Transient & DC Analysis.