PicoBlaze Emulated 8051 Microcontroller (PB8051-MX/TF)

September 10, 2003 Product Specification

AllianceCORE Facts
Core Specifics See Table 1 Provided with Core

Roman-Jones, Inc.
Roman-Jones, Inc. 11679 La Core Ave Empire, MI 49630 Ph: 231.326.5194 Fax: 231.326.5195 rj@roman-jones.com www.roman-jones.com

Features
8031 software compatible microcontroller (includes serial port & timers) Low cost - $495, support is available on an hourly basis, if needed Small size - 368 slices in Spartan-3 Custom 8051 configurations available Support in all Xilinx FPGAs Spartan II and above Available under terms of the SignOnce IP License

User Guide Design Guide Design File Formats NGC/NGO netlist Constraints File PB8051.ucf Verification Test Bench and 8051 Test Code Instantiation Templates VHDL, Verilog Reference designs and Design Examples with External application notes Bus Interface and Test Software Additional Items Custom Versions of 8051 Core Simulation Tool Used ModelSim and Aldec Active HDL Support
Documentation Support provided by Roman-Jones, Inc.

Applications
Small FPGA area embedded microcontroller Unaltered use of Legacy 8051 object code

Table 1: Example Implementation Data Supported Family Example Device Fmax (MHz) 72 69 72 131 142 73 113 CLB Slices1 336 290 336 285 329 297 330 IOBs2 GCLK BRAM MULT 96 96 96 96 96 96 96 1 1 1 1 1 1 1 3 6 6 3 3 3 3 0 N/A N/A 0 0 0 0 DCM 0 0 0 0 0 0 0 MGT N/A N/A N/A 0 0 N/A N/A PPC N/A N/A N/A 0 0 N/A N/A Design Tools ISE 5.2.02i ISE 5.2.02i ISE 5.2.02i ISE 5.2.02i ISE 5.2.02i ISE 5.2.02i ISE 5.2.02i

Spartan-3 XC3S200-4 Spartan-IIE3 XC2S50E-7 Spartan-IIE4 XC2S50E-7 Virtex-II Pro3 XC2VP2-7 Virtex-II Pro4 XC2VP2-7 Virtex-II3 XC2V80-6 Virtex-II XC2V80-6
Notes:

1. Actual slice count may vary depending on the percentage of unrelated logic. See the Mapping Report file for details. 2. Assuming all core I/Os and clocks are routed off-chip 3. Implemented in PB8051-x-tbuf version of the core. 4. Implemented without TBUFs for maximum performance.

September 10, 2003

PicoBlaze Emulated 8051 Microcontroller (PB8051-MX/TF)

1K 1Kx x16 16 Block BlockROM ROM Emulation Emulation Program Code Program Code
Interrupt

256 256 x x 16 16 Instruction Instruction Decode ROM Decode ROM

PicoBlaze PicoBlaze
Data

8051 Emulation Peripherals

RST_8051 WR RD PSEN INSTR_FETCH EXT_BUS_START EXT_BUS_HOLD P1_IN[7:0] P1_OUT[7:0] P3_IN[7:0] P3_OUT[7:0} EXT_DATA_IN[7:0]

256 256 x x8 8 Block BlockRAM RAM

Address Decode, Data, Signals SERIAL0_PRE12 SERIAL2_PRE32

Serial Serial Port Port

Address Decode, Data, Signals

Address

Address Decode

TIMER_PRE

Timer Timer Internal Address/Data Bus

EXT_DATA_OUT[7:0] EXT_ADDRESS[15:0]

CLK RST

ROM_ADDRESS[15:0] ROM_DATA[7:0]
xip237

Figure 1: PicoBlaze Emulated 8051-MX/TF Microcontroller

General Description
The PB8051 is an 8031 implementation of the popular 8051 microcontroller family. The PB8051 includes the serial port and two timers found in the 8031. In addition, it is software compatible with the 8031, able to execute object code generated by 8051 design tools. Program code may be executed from an FPGA internal Block RAM(ROM) or external (to FPGA) EPROM. The core is not clock cycle execution compatible with the native microcontroller.

Functional Description
8051 compatibility is emulated using the Xilinx PicoBlaze softcore microcontroller. This architecture optimizes for small core size, only 25% the size of competing 8051 cores. The performance speed is similar to that of the 8051 when operated at 4X the clock rate. In other words, a PB8051 operated at 48 MHz will perform similar to a Legacy 8051 running at 12 MHz. The core is comprised of the functional blocks shown in Figure 1. The primary block of the core is a PicoBlaze softcore processor and its emulation program stored in a 1K x 16 Block ROM. The PicoBlaze allows for a 256 byte addressable peripheral bus that provides access to the serial port, timers, emulation peripherals, and Block RAM. Access to this bus remains internal to the PB8051.

significant portion of this block is the needed PicoBlaze peripheral address decode function for 8031 SFRs and other emulation peripherals. All undecoded addresses show up as RAM access. Two versions of the PB8051 are provided, a TBUF(TF) and MUXCY(MX). The TBUF version uses an internal tri-state data bus while the MUXCY performs address decoding and data muxing using the embedded carry chain. The TBUF version employs fewer slices, while the MUXCY version allows faster clock speed and is especially compatible with Spartan-3.

Instruction Emulation
Execution of 8031 program code is not clock cycle compatible with the native 8031, since each instruction is emulated in PicoBlaze software. Some instruction emulation is more efficient than others. Instruction execution times, in clock cycles, are provided.

Memory & Peripheral Interface

To accommodate slower off FPGA memory and peripherals, the INSTR_FETCH and EXT_BUS_START output signals indicate the start of 8031 bus cycles. These signals can interface to a bus controller to extend access time via the input signal EXT_BUS_HOLD. A reference design is provided.

Two PB8051 Implementation Choices

The emulation peripheral block provides special emulation acceleration hardware and 8031 port emulation. A

September 10, 2003

Roman-Jones, Inc.

Timer & Serial Clocking

Separate clock enable signals are provided for 8031 timer prescale and serial mode 0 and mode 2 prescale. These provide user flexibility in providing counting and baud rates. These clock prescale enables are periodic, one clock wide, and synchronous to the system CLK input.

Pinout
The core I/O signals have not been fixed to specific device pins to provide flexibility for interfacing with user logic. Any signals may be used internal or external to the FPGA. The signals are shown in Figure 1 and described in Table 2.

8051 Reset
While the RST input resets the entire core, it is not necessary and may be tied to GND. RST_8051 is an emulated reset that performs the same function as the 8031 reset input.

Table 2: Core Signal Pinout Name CLK RST RST_8051 TIMER_PRE SERIAL0_PRE12 SERIAL2_PRE32 WR RD PSEN EXT_BUS_HOLD
Input

Direction
Input Input Input Input Input Input Output Output Output

Core Modifications
The design of the PB8051 is organized as a 8051 core with timers and serial port. While the PB8051 is not user configurable, Roman-Jones, Inc. is available to custom build a 8051 derivative to meet specific user needs.

Verification Methods
A reference design including a VHDL/Verilog Testbench and 8051 hex with assembler source code is provided. The testbench simulates virtual execution of 8051 code from an intel hex file (8051 software tool output). The testbench includes an 8031 external bus Block RAM, and off FPGA use of 8031 ports. This flexibility allows users to quickly integrate their FPGA RTL with the PB8051 core and use their own 8051 code.

Recommended Design Experience

The PB8051 core is designed for ease of use. Designer should be experienced in instantiating cores. Although it may present an aggressive challenge as a first Xilinx design experience, it should prove simple for someone with Xilinx tool experience. Users should be familiar with 8051 microcontrollers, skilled with assembler and/or C language, and related software development tools.

INSTR_FETCH
Output

EXT_BUS_START
Output

Product Support
The PB8051 core is affordably priced and includes the two versions of the core, reference design, simulation test bench, and documentation. Support is provided on an hourly basis at additional cost via telephone, email, or on site.

P1_IN[7:0] P1_OUT[7:0] P3_IN[5:0] P3_OUT[5:0] EXT_DATA_IN [7:0] EXT_DATA_OUT [7:0] EXT_ADDRESS [15:0] ROM_DATA[7:0] ROM_ADDRESS [15:0]

Input Output Input Output Input Output Output Input Output

Description Clock input Core reset 8051 reset emulation Clock enable for timers, see text Clock enable for serial mode 0, see text Clock enable for serial mode 2, see text External write enable, High for one clock External read enable, High for one clock Instruction read enable, High for one clock Hold line for access to slow memory or peripherals Indicates start of instruction fetch cycle, High for one clock Indicates start of external bus cycle, High for one clock Port 1 data in Port 1 data out Port 3 data in Port 3 data out External bus data in (port 0) External bus data out (port 0) External bus address out (ports 0 and 2) Code space data in (port 0) Code space address out (ports 0 and 2)

September 10, 2003

PicoBlaze Emulated 8051 Microcontroller (PB8051-MX/TF)

Ordering Information
This AllianceCORE product is available from Xilinx AllianceCORE member Roman-Jones, Inc. under the terms of the SignOnce IP License. To learn about the SignOnce IP License program, contact Roman-Jones, Inc., visit www.xilinx.com/ipcenter/signonce.htm or write to commonlicense@xilinx.com. Please contact Roman-Jones, Inc. for pricing and additional information about this AllianceCORE product.

Xilinx Programmable Logic

For information on Xilinx programmable logic or development system software, contact your local Xilinx sales office, or: Xilinx, Inc. 2100 Logic Drive San Jose, CA 95124 Phone: 408-559-7778 Fax: 408-559-7114 URL: www.xilinx.com For general Xilinx literature, contact: Phone: E-mail: +1 800-231-3386 (inside the US) +1 408-879-5017 (outside the US) literature@xilinx.com

Related Information
Roman-Jones, Inc. specializes in consulting and contract engineering for your Xilinx and microprocessor needs. For more information about Roman-Jones, Inc: Roman-Jones, Inc. 11679 La Core Ave Empire, MI 49630 Phone: 231.326.5194 Fax: 231.326.5195 URL: www.roman-jones.com E-mail: rj@roman-jones.com

For AllianceCORE specific information, contact: URL: www.xilinx.com/products/logicore/alliance/ tblpart.htm

September 10, 2003