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4, APRIL 2013

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Differential Power Processing for DC Systems

Pradeep S. Shenoy, Member, IEEE, and Philip T. Krein, Fellow, IEEE
AbstractThis paper introduces an approach to dc power delivery that reduces power loss by minimizing redundant energy conversion. Existing power distribution techniques tend to increase the number of cascaded conversion stages, which limits overall efciency. Differential power processing enables independent load regulation, while processing only a small portion of the total load power. Bulk power conversion occurs once. Load voltage domains are connected in series, and differential converters act as controllable current sources to regulate intermediate nodes. This enables independent, low supply voltages, which can reduce system energy consumption, especially in digital circuits and solid-state lighting. Since differential voltage regulators process a fraction of the load power, decreased size, cost, and conversion losses are attainable. Under balanced load conditions, secondary differential converters do not process any power. This paper analyzes several differential power delivery architectures that can be applied to homogenous and heterogeneous loads at various levels: chip, board, blade, etc. A variety of operating conditions for a test system with four series voltage domains are examined in simulation and veried with experimental hardware. Results in a reference application show a 78% decrease in input power and 67 percentage points increase in overall conversion efciency as compared to a conventional cascaded approach. Index TermsDC distribution, differential power processing, power delivery architectures, voltage regulation.

in load power consumption may be obtained by dynamically varying supply voltage or by introducing multiple voltage domains [3], [4]. The advanced power delivery designs that support this often place fast, on-chip VRs in the power path [5], but this approach may not be effective for system-level energy reduction. Power delivery efciency decreases since chip-level converters tend to be less efcient than discrete designs and add another power conversion stage [6]. A nonlinear breakthrough in power delivery has been called for [7]. Differential power processing for series-connected load-voltage domains, as described in this paper, has the potential to be such a breakthrough. As digital circuits continue to scale down in size for faster devices and a smaller area, supply voltage scales down as well. According to the International Technology Roadmap for Semiconductors (ITRS), supply voltage will fall below 600 mV by 2024 [8]. Researchers are exploring subthreshold voltages, suggesting energy reductions down to 350 mV or less [9]. Lower supply voltage levels have been successfully used to reduce device power consumption over several generations of microprocessors. A simple model for active power consumption in microprocessors and other CMOS (complementary metal oxide semiconductor) circuits is
2 fb P = CVdd

(1)

I. INTRODUCTION

LECTRICAL systems with low-voltage dc loads typically have several cascaded power conversion stages. In computer data centers, multiple conversion stages are necessary after ac rectication to step down the bus voltage (which could exceed 600-V dc [1]) to a level acceptable to end-user components. Each conversion stage must process the total load power plus any power lost in subsequent stages. The nal stage in microprocessor power delivery is the point-of-load (PoL) voltage regulator (VR), which must supply high current (100 A or more at full load) at a low-voltage level (such as 1 V) [2]. A move to many-core microprocessors (i.e., tens, hundreds, or thousands of cores) motivates rethinking power delivery. Some reduction

Manuscript received April 10, 2012; revised June 23, 2012; accepted August 3, 2012. Date of current version October 26, 2012. This work was supported in part by the Grainger Center for Electric Machinery and Electromechanics at the University of Illinois at Urbana-Champaign and in part by the Advanced Research Projects Agency-Energy (ARPA-E), U.S. Department of Energy under Award Number DE-AR0000217. Recommended for publication by Associate Editor S. Y. (Ron) Hui. P. S. Shenoy is with Kilby Labs, Texas Instruments, Dallas, TX 75243 USA (e-mail: pshenoy@ieee.org). P. T. Krein is with the Department of Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign, Urbana, IL 61801 USA (e-mail: krein@illinois.edu). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TPEL.2012.2214402

as these circuits alternately charge and discharge a portion of their internal capacitance. Here is the activity factor, C is the total equivalent capacitance, Vdd is the supply voltage, and fb is the base clock frequency [10]. Lowering the supply voltage is attractive since active load power consumption is proportional to the square of the supply voltage. It is also a motivating factor behind computational parallelism and multiple voltage domains that enable functional blocks to operate at independent voltage levels to reduce overall energy consumption. However, the basic model in (1) does not account for leakage, gate drive overhead, or the losses upstream in power converters. Ultimately, low supply voltages negatively impact the efciency and performance of conventional VRs [11]. In fact, the most efcient operating point for a digital circuit [9] is not the most efcient operating point for the overall system [12]. An alternative approach to power distribution is to form a series connection of load-voltage domains as in Fig. 1. The load elements can represent various levels of abstraction: functional blocks such as microprocessor cores or memory sections, discrete integrated circuits, circuit boards, server blades, etc. When voltage domains are connected in series as opposed to in parallel, the overall supply voltage increases, and the load current required from the power supply decreases for a given load power. This reduces conduction losses in power conversion. If the total load voltage is high enough, some of the cascaded dcdc conversion stages can be removed, resulting in substantially higher system efciency. Less thermal management overhead is needed

0885-8993/$31.00 2012 IEEE

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Fig. 1. Series connected voltage domains enabled by differential power processing.

operation benets of multistory power delivery have also been highlighted previously [16], [17]. The contribution that this research makes is to introduce and analyze power architectures for efcient and effective regulation of series-connected voltage domains. Section II briey reviews conventional power delivery approaches to provide a context for this study. Several differential power-processing architectures are presented and compared in Section III. In Section IV, load management strategies to reduce load current mismatch are discussed. A comparative analysis of power consumption in series and parallel voltage domains is presented in Section V. Simulation and experimental results for a test system with four series connected voltage domains are shown in Section VI. Digital circuit loads provide the primary context but other applications of differential power processing are discussed in Section VII, and conclusions are presented in Section VIII. II. APPROACHES TO POWER DELIVERY The architecture of dc power supplies has changed as the needs of the load elements have changed. Early power supplies could be contained in one unit, but as load power demands increased and diversied, other approaches became necessary. A driving force has been the evolution of telecommunications and computing platforms. Until about year 2000, microprocessors consumed progressively more power. Then, Intel took its righthand turn toward multimodule processors, and the full-load power consumption of microprocessors has remained about the same ever since [19]. Heat dissipation from a given package area was a major limitation that motivated the move to multicore designs. Heat removal is only one challenge associated with the socalled power wall [20]. As the supply voltage is lowered, power delivery becomes more challenging and costly. Highcurrent, low-voltage supply requirements place a heavy burden on dcdc converters in the system [2]. To understand the state of the art, it is worthwhile to examine previous power delivery architectures and the motivations behind them. There are tradeoffs with these various power delivery architectures, and some may be more advantageous in certain situations [21]. Hybrid versions are also employed [22]. A. Centralized Power Architecture (CPA) Initially, the CPA was prevalent. Power supplies contained in many silver boxes would convert from the ac grid to one or more dc voltages, as shown in Fig. 2(a). Common voltage levels were 15 V, 12 V, and 5 V. A yback or forward converter with multiple output windings was often used to create multiple, isolated voltage levels. Many analog circuits would runoff two opposite-polarity voltage rails and digital circuits would use the 5-V logic rail. This worked reasonably well when load currents were relatively low and only a few voltage levels were needed. B. Distributed Power Architecture (DPA) The centralized power architecture gave way to the DPA shown in Fig. 2(b). The rst stage in the DPA generally

because there is less power loss. Faster effective slew rates and improved transient performance can be achieved in PoL converters since currents are lower. Fewer power pins would be needed on a microprocessor because the supply current has decreased. This approach gives the loads and power delivery circuits freedom to operate at their individual points of highest efciency. The paradigm for power distribution is turned around: instead of adding cascaded conversion stages to provide low voltages, voltage domains are added together to meet a higher input voltage level. Balance is an important attribute of the system in Fig. 1. In multicore processor congurations and massively parallel computing, it is well established that the best operating strategy is to divide effort evenly among units [13]. For power distribution, this can be used to advantage: in such a system, the loads in Fig. 1 should operate at matched power levels. Even so, short-term mismatches, or even distinct operating voltages associated with function blocks like memory, computation, and communications may not support ideal matching. Differential power processing facilitates scalable, series voltage domains. The system in Fig. 1 is relatively straightforward for balanced, homogenous load modules. An important benet of the approach introduced in this paper is that it allows heterogeneous loads to operate at independent supply voltage levels. Voltage regulation is necessary to maintain the desired local load voltage in the presence of load current mismatches. A current mismatch occurs when the steady-state current demand is not identical for each series load domain. Differential power converters regulate the intermediate voltage nodes by providing only the difference between the load current of adjacent domains, not the full load current. The regulation challenge is minimized by balancing the computational load among the load elements, but, in general, local voltage regulation circuits are needed. While the basic concept of series connection has been discussed in the context of digital circuits [14][18], small systems with just two or three modules, often using stacked linear regulators, have been proposed so far. With linear regulators, signicant system-level power loss occurs when a current mismatch exists. The power supply noise reduction and low-voltage

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dynamic variation within bounds also increases as Vdd drops. Some have suggested moving to a two stage VR to overcome the dynamic regulation challenges [29]. Many have also explored integrating voltage regulators on chip [5], [6]. The clear trend is to add an energy conversion stage. Although some gains can be made, from a basic power delivery perspective, this is a move in the wrong direction. More cascaded stages tend to reduce overall conversion efciency. Gains made by reducing load energy consumption are diminished by added losses in energy conversion. What is needed is a power delivery approach that enables both the power processing circuits and the load elements to operate in their most efcient regions. III. DIFFERENTIAL POWER PROCESSING (DPP) DPP recongures power delivery. Instead of forcing power delivery to conform to low-voltage load needs through multiple cascaded conversion stages, load voltage domains are connected in series and sum to a relatively high-dc voltage. In a system with series-connected voltage domains, independent supply voltage levels are obtained without the use of cascaded converters. Independent voltage domains allow load elements to minimize the energy consumed [3], [4]. The challenge with series-connected voltage domains is regulating the local voltage for each load domain when the load currents are not equal (e.g., the computational activity of each load is not the same). If action is not taken to regulate voltages in a series load, each load voltage depends on its effective impedance, just like a resistive voltage divider. This is not acceptable in digital circuits if the desired supply voltage band is narrow (e.g., 50 mV). Although bulk voltage regulation can be accomplished through load balancing by managing computational activity, local base clock frequency, or other factors, these load management techniques may be insufcient, and differential power converters would be required for high-performance voltage regulation. Fundamentally, a controllable current source can regulate the local voltage at the node between adjacent series loads. The current source provides the difference between adjacent load currents, as seen in Fig. 3(a). The steady-state current provided by the ith local voltage regulator is IVR ,i = Iload ,i Iload ,i +1 (2)

Fig. 2. The three main power delivery architectures: (a) CPA, (b) DPA, and (c) IBA.

consisted of a converter, which performed rectication from the ac grid to a medium voltage bulk dc bus (e.g., 48 V nominally) and might also support active power-factor correction. The second stage was separate, isolated dcdc converters that provided the necessary dc supply levels. This approach had several advantages including modularity, high reliability, scalability, and easier output regulation. In many applications such as data centers [23] and telecommunications [24], power could also be distributed with a high-voltage bus for delivery to the isolated dcdc converters. The challenge to this architecture occurs when numerous low-voltage levels are powered by isolated converters that require a fair amount of printed circuit board space [25]. C. Intermediate Bus Architecture (IBA) The DPA has been replaced in many systems by the IBA, shown in Fig. 2(c). A benet of this approach is that only one isolated dcdc converter is needed. Smaller, non-isolated PoL converters can tightly regulate the various load voltages [26]. PoL converters are relatively simple, and often take the form of multiphase buck converters. Another motivating factor is high power demands at progressively lower voltages as digital circuit feature sizes get smaller [27]. A question, as in [28], is What is the best voltage level for the intermediate bus? In todays systems, 12 V is standard, and sometimes 5 V is used. PoL VRs often consist of several buck dcdc switching converters interleaved and operated in parallel to meet output impedance and performance requirements. This multiphase approach reduces component stress, decreases output ripple, increases transient response, and improves thermal management but at the cost of additional components and control complexity. As supply voltages decrease for a given power, the effective load 2 , complicating power impedance decreases by a factor of 1/Vdd delivery. The bus capacitance required to keep supply voltage

where Iload , i is the current of the ith load. If the steady-state currents of two adjacent loads match, no current needs to be provided by the differential VR. If there is a mismatch, the differential VR provides only the difference in current. This is a tremendous potential benet because under reasonably matched operating conditions, the differential VRs process only a fraction of the total load power. Bulk power comes from a single-power supply at the relatively high total series voltage. Differential converters can also act to bypass current as needed to maintain a well regulated local voltage, as shown in Fig. 3(b). Many converter topologies can function as differential VRs, motivated in part by circuits developed for battery balancing in series strings [30], [31]. The converters can be on-chip or off-chip, isolated or nonisolated, inductive, or capacitive. For simplicity and exibility, this research begins with a buckboost

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Fig. 3. Differential power converters act as controllable current sources to regulate intermediate voltage nodes.

switching conguration similar to [30]. The main focus is on the overall regulation architecture rather than the local converter topology or implementation. It is useful to notice that if there are n load elements, only n1 differential VRs are needed to provide complete voltage control, as depicted in Fig. 3(a). The top voltage domain is regulated by the main power supply (i.e., it is the nth control actuator). If n differential VRs are employed, as shown in Fig. 3(b), the control system has an extra degree of freedom. This can be used, for example, to minimize the current that is processed. The following subsections examine several local series power delivery architectures. A. Bus-to-Load Architecture The input of differential voltage regulators is connected to the dc bus in the bus-to-load architecture. This approach is similar to a conventional multiphase buck converter except each phase output is connected to a different node in the load stack, as shown in Fig. 4(a). The output inductors serve as controllable current sources used to regulate the various node voltages. The duty ratios of the switches control the average voltage at each switching nodes, which, in turn, controls the load voltage. This architecture can also be implemented using isolated converters (e.g., yback or forward converters) as shown in Fig. 4(b). The main dcdc converter is rated for the entire load power since all the energy supplied to the load must pass through it. A potential benet is that current demand is reduced since the output voltage has increased. By applying Kirchhoffs Current Law (KCL) to the top node of the system shown in Fig. 4(a), the instantaneous current provided by the main supply is im ain = iload ,n + iC n = iload ,n + Cn dvC n dt (3)
Fig. 4. The bus-to-load architecture with differential voltage regulators using (a) synchronous buck converters and (b) yback converters.

The differential VRs for the intermediate nodes are rated for the expected maximum current mismatch. It should also be noted that generally these differential VRs should be bidirectional. This is apparent when considering (2) since the VR current can be positive or negative depending on load conditions. However, this does not substantially complicate the converter; a synchronous buck converter operates in both directions provided both switches are active devices. The instantaneous current of each differential VR is dvC i + 1 dvC i Ci +1 . (4) dt dt The steady-state currents are the same as in (2) for this architecture since the average capacitor voltage is constant. The advantage is that the current provided by one regulator does not inuence the current of any other VRs. The energy is transferred directly between the main dc bus and the load. iV R ,i = iload ,i iload ,i +1 + Ci B. Load-to-Load Architecture The voltage nodes to which the differential VR switches are connected can be changed to create other feasible architectures. If the nodes closest to the load are chosen, a local, bidirectional buck converter, similar to that used for charge balancing in battery packs [30], can accomplish the desired voltage regulation.

where Iload , 1 is the instantaneous current of the rst load domain, iC n is the capacitor current, vC n is the capacitor voltage, and Cn is the capacitance. In periodic steady state, the average capacitor voltage is constant (i.e., dv C n /dt = 0), and the average current from the main supply is equal to the current of the rst load element.

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Fig. 5. The load-to-load architecture with differential voltage regulators using a synchronous buck topology.

This architecture is shown in Fig. 5. The output inductors act as controllable current sources, and the load voltages are regulated by controlling the duty ratios of the switches. As before, the main supply is rated for full load power, but the local voltage regulators are rated only for the differential. One important difference in this architecture is evident when applying KCL to the intermediate nodes in the local converter architecture. The steady-state equation is not the same as (2) but is IVR ,i = IL ,i = Iload ,i Iload ,i +1 + Di 1 IVR ,i 1 + (1 Di +1 )IVR ,i +1 (5)

Fig. 6.

The hybrid architecture with differential voltage regulators.

where Di is the duty ratio of the ith local VR. This can be written in matrix form for n load elements as 1 (1 D2 ) 0 0 . .. . . 1 (1 D3 ) . D1 .. .. 0 . . D2 0 . . . . . . . . 1 (1 Dn 1 ) . 1 0 0 Dn 2 I Iload , 1 Iload , 2 L ,1 IL , 2 Iload , 2 Iload , 3 . . . . . (6) = . . IL ,n 2 Iload ,n 2 Iload ,n 1 IL ,n 1 Iload ,n 1 Iload ,n Equations (5) and (6) show coupling: the current in one VR depends not only on the difference in the load current but also on current in the neighboring VRs. This has the effect of cascading the power delivery in some circumstances. The power needed for regulation is transferred from one voltage level to the next through multiple converters, even though it is a small amount. In practice, there will be many voltage domains re-

quiring current to be supplied or removed. This can result in current demands canceling each other out. The net effect may be small and depends on load conditions. The advantages of this approach are considerably lower voltage requirements for local switches, typical duty ratios near 50%, and the ability to integrate the converters on-chip and close to the local loads. C. Hybrid Architecture A promising architecture for power delivery is a hybrid of the two previously examined. Load-to-load converters can be used for regulating subsections of loads locally with simple, low-power converters, and bus-to-load converters could regulate large sections of the series load, as illustrated in Fig. 6. The load-to-load converters could be integrated on-chip and controlled using basic algorithms. The higher level, bus-to-load converters could be more sophisticated and operate over a wider load range. Another important benet of the hybrid architecture is that bus-to-load converters enable heterogeneous loads by decoupling sections of series-stacked voltage domains. This limits the effects of load current mismatch to smaller sections of the system. For example, apply KCL to the node immediately above the node with the bus-to-load converter output (e.g., output of iVR , 3 in Fig. 6). The steady-state current of the local VR is IVR ,i = Iload ,i +1 Iload ,i + (1 Di 1 )IVR ,i 1 . (7)

This VRs current is not inuenced by the current provided by the following regulator, as shown in (7), because, unlike in (6), the term Di +1 IVR ,i +1 is absent from the equation. Thus, if IVR ,i +1 is delivering current to regulate its load, it does not

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Fig. 7. Comparison of a 64-core, 30-W processor with cores connected (a) in parallel, and (b) in series. The effective impedance of series cores is about 4000 times larger than parallel cores. Fig. 8. Various methods of load balancing and voltage regulation using software, rmware, and hardware.

force IVR ,i to conduct current unnecessarily. An equation similar to (7) can be obtained for the node following the bus-to-load converter node through KCL and is IVR ,i = Iload ,i +1 Iload ,i + Di +1 IVR ,i +1 . (8)

A. Homogeneous Load Domains Homogeneous loads are comparably easy to manage. If the desired voltage level of each series load domain is the same and the effective impedance of each load domain is well matched, little effort needs to be taken to regulate the voltage. Homogeneous loads have regulation needs equivalent to charge balancing in batteries [30], [31]. As such, known circuits and control techniques for equalization could be used in these systems. Semipassive regulation schemes using switched capacitor converters may be sufcient for the homogeneous load case. B. Heterogeneous Load Domains Heterogeneous loads require more exibility and control on the part of the power delivery system. When load voltages or current levels of each load domain are unmatched, equalization strategies used in battery balancing may be ineffective. Voltage regulators must be able to efciently and effectively provide the required current at varying voltage levels. DPP enables heterogeneous load elements to efciency operate under independent conditions. The heterogeneous elements can be managed so as to decrease overall system power loss. C. Hierarchy of Voltage Regulation Several techniques can be used to actively regulate series voltage domains. Broadly speaking, the goal is to manage the effective impedance of each load in software and utilize hardware mechanisms only for small differences. This proactive approach reduces loss in the power delivery circuits. A hierarchical list of techniques (shown pictorially in Fig. 8) is as follows: 1) compiler system/scheduler; 2) run-time system/scheduler; 3) distributed hardware schedule implementer; 4) clock rates; 5) communications (local and external); 6) task swapping; 7) external power exchange (local power electronics); 8) tolerance allowance;

This shows that upstream mismatches will not impact VRs downstream when the bus-to-load converter is present. The hybrid architecture also supports the ability to shutdown or bypass load sections with relative ease. This functionality can save energy or enhance system reliability if there is a fault in a subsection of the load. In general, however, load balancing is preferable to load shedding. If load balancing is present, the power loss of the power delivery circuits can be very low. Little to no power will be processed by the local regulators, and the main power supply voltage will be relatively high. Each digital load can operate at the voltage that provides the lowest energy consumption per computation. IV. LOAD MANAGEMENT Computing systems can intelligently manage their load prole. This ability can be used to ease voltage regulation requirements through load balancing. Voltage domains should be regulated to avoid computational errors in digital circuits and limit stress on the transistors. The digital circuits in each voltage domain may not draw the same current at the desired operating voltage. Series circuits, however, must conduct the same current through each element. The voltage at each domain may deviate from the desired level. A key challenge in series voltage domains is regulating the intermediate node voltages. The tradeoff is clear when a potential design is considered. For example, a 64-core processor designed to work at 30 W and 0.3 V requires 0.3 V and 100 A when connected in parallel as shown in Fig. 7(a). In series, it requires 19.2 V and only 1.6 A as shown in Fig. 7(b). This is an increase in the effective load impedance from 3 m to 12.3 (about 4000 times larger). The latter power supply will be much more efcient, with better transient response and lower node-by-node voltage ripple. However, the higher operating voltage introduces 63 intermediate voltage nodes that need regulation.

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9) global supply; 10) protection; The rst lines of defense in voltage regulation occur at the software level. If the desired voltage of each voltage domain is equal, the operating system should manage software threads at compile time or run time to evenly balance the computational load of each element. The operating system can also dispatch activity unevenly if unequal voltage levels are desired. On computer servers, virtual machines could be managed so that the computational activity on each motherboard or server blade is approximately equal. Another regulation layer is at the rmware level. A task manager can distribute operations among computational elements without intervention from the operating system. Task swapping and task rotation are possible techniques. Clock rates can be adjusted to throttle the activity within each voltage domain and control the effective load impedance. It is important to keep in mind that, even though Fig. 8 abstractly displays one circuit at each voltage level, a voltage domain could support several elements in parallel. The activity of all the elements must be managed to control the effective load impedance. If the preceding methods are unable to maintain voltages at the specied targets, hardware-based regulation approaches can be used. This includes using local dcdc converters to actively regulate the voltage [32] as discussed in Section III. The unique advantage of DPP is that power delivery circuits process only a fraction of the load power when providing the difference in current between load domains. The voltage overshoot or undershoot caused by load transients will also be less severe since load transient magnitude will be substantially reduced (e.g., by a factor of 1/n, where n is the number of voltage domains). In extreme situations, Zener diodes can protect local domains from overvoltage conditions. D. Communication Overhead While series-connected voltage domains have considerable promise, level shifting for interdomain communications complicates implementation. Level conversion is standard in modern digital circuits, and microprocessors which employ multiple voltage domains already exist. Other viable communication techniques include capacitively driven wires [33], optical interconnects [34], and even wireless transmission [35]. It remains to be seen whether or not communication overhead would increase. These issues motivate computer architectures that reduce communications or limit it so that latency and power overhead have minimal impacta typical architectural issue in parallel computing. Similarly, the series conguration may lend itself to applications in which there is little interdependence in the data, and computations can be made in parallel without signicant interaction. The goal may be to develop an initial mapping that balances workloads across computational units with limited communication. V. ENERGY CONSUMPTION ANALYSIS A comparative analysis of a candidate system is undertaken to quantify the benets of the DPP approach. As digital circuits are

a motivating factor, system efciency for a multicore microprocessor with separate voltage domains for each core is examined. While the emerging approach is to have an additional cascaded VR to supply an independent voltage for each core, DPP can meet the same objectives with less energy consumption. A. Independent Loads With Cascaded VRs An additional conversion stage is needed if independent voltage levels are desired in a conventional power delivery architecture. Each PoL converter must be rated for the full-load power of its respective load element and must process all the power delivered to the load. This added conversion stage decreases overall power conversion efciency. It is also difcult to design and implement an integrated conversion circuit that is efcient over a wide load range. While peak efciency numbers are often quoted for dcdc converters, the important gure of merit is converter energy efciency based on an extended interval of typical operation. This is dened as = Eout /Ein , where Eout is the total energy output for the entire duration of a suitable test and Ein is the total input energy. In typical computing applications, the system operates at light or medium load levels much of the time. This means overall efciency is load-prole dependent, and is a weighted average of power conversion efciency. Another gure of merit is the total system input energy Ein . In the end, energy is paid for whether it is shown on a utility bill for a data center or as battery life in a portable application. For comparison, let us consider the dc portion of a typical computer server. There will likely be an isolated dcdc converter and a voltage regulator upstream from the microprocessor load. The input energy is Ein = Eload 1 2 (9)

where Eload is the energy consumed in the microprocessor, 1 is the efciency of the isolated dcdc converter, and 2 is the boardlevel VR efciency. If independent voltage domains are desired to reduce load-energy consumption, a cascaded conversion stage is necessary and the input energy becomes Ein = Eload 1 2 3 (10)

where Eload is the reduced energy consumed by the load and 3 is the efciency of the added conversion stage. For this approach to be worthwhile, the input energy should be lower than the previous case (i.e., (10) is less than (9)). Thus, the following is sought Eload < 3 Eload . (11)

The reduction in energy consumption must compensate for the energy lost in the extra conversion stage. This assumes the efciency of the other energy conversion stages (i.e., 1 and 2 ) remains the same. Even if the energy consumed by the load is reduced sufciently, the overall gains in terms of input energy reduction are diminished by the added conversion loss. Another perspective can be taken by rearranging (11) to conclude that the required efciency of the additional conversion stage needs

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to be sufciently high. The efciency should be 3 > Eload Eload (12)

to ensure input energy savings for the system. B. Independent Loads With Differential VRs An advantage of series-connected voltage domains is that the each domain voltage is intrinsically independent. Although differential VRs generally are still needed for regulation, they process only a fraction of the total load power. Cascaded conversion stages can be eliminated if the overall voltage of the series domains is sufciently high. Consider the same system as above using differential VRs instead of cascaded converters to provide independent voltage domains for multiprocessor cores. The input energy to the system is Ein = Eload + EDVRloss 1 2 (13)

Fig. 9. The minimum efciency of differential VRs that result is less system energy consumed compared to conventional cascaded VR approaches.

where EDVRloss is the energy loss due to differential power processing, 1 is the efciency of the isolated dcdc converter, and 2 is the efciency of the second conversion stage. The fraction of the load energy processed by differential VRs can be represented as an energy-processing factor , where = EDVR /ELoad . Thus, the energy lost in differential VRs is EDVRloss Eload (1 4 ) = 4 (14)

If, for example, the efciency of differential VRs and cascaded VRs is the same (i.e., 3 = 4 ), the expression simplies to < 1. (19)

where 4 is the efciency of the differential VRs. Equation (13) can then be explicitly written as Ein = 4 + (1 4 ) . 1 2 4 (15) If the voltage of the series load stack is high enough to remove the second conversion stage, 2 is effectively equal to 1. Eload Eload (1 4 ) + = Eload 1 2 1 2 4

This result signies that the differential system will be more efcient as long as the differential VRs process less than the total load energy. If the second conversion stage is avoided through a higher load stage voltage, there is benet even if > 1. Equation (18) can be rewritten to solve for the desired differential VR efciency which is 4 > 3 . 3 3 + 1 (20)

C. Comparison The goal now is to determine under what conditions the differential power processing system results in lower energy consumption than the conventional system with cascaded VRs. Using (10) and (15), if the differential VR system consumes less energy, the following must be true: Eload 4 + (1 4 ) 1 2 4 < Eload . 1 2 3 (16)

Assuming the energy consumed in the load and the upstream conversion efciency is the same in both systems, this expression can be simplied to 4 + (1 4 ) 1 < . 4 3 (17)

Hence, the fraction of load energy that can be processed by differential converters and result in less total energy consumption is < 1 3 3 4 1 4 . (18)

The desired minimum efciency of the differential VRs for varying values of and 3 is shown in Fig. 9. This gure indicates that as the fraction of power processed decreases, the efciency that differential VRs need in order to outperform the cascaded approach also decreases. For example, if a differential VR processes 10% of the load power on average and has 66% efciency or greater, it will result in a system with higher overall efciency than one using a cascaded converter with 95% efciency. The efciency of differential VRs can be very low and still reduce system energy consumption. The system efciency for cascaded and differential systems is compared in Fig. 10. The gure assumes the load energy consumption is the same in both systems, that 1 = 2 = 0.95, and that 3 = 4 = 0.9. The cascaded system processes all the load power, and its efciency is the product cas = 1 2 3 = 0.812. The differential system is shown with and without the second conversion stage and has almost ten percentage points higher system efciency when is low. When approaches 1 (i.e., 100% of load power processed), the system efciency is the same as the cascaded system. This demonstrates that even with modest matching levels, the differential system will have higher system efciency than the cascaded system.

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Fig. 11. Effect of load steps in a conventional, parallel digital circuit load system on (a) processor voltage regulation, and (b) inductor current in voltage regulator and processor core current.

Fig. 10. System efciency for a cascaded system and for a differential system with and without the second conversion stage over varying fractions of power processed by differential VRs.

VI. RESULTS A. Simulation Results To highlight the salient aspects of series-congured voltage regulation, the setup shown in Fig. 5 using load-to-load differential VRs with four digital circuit loads was compared with a conventional parallel load system supplied by one main VR. The simulated response of each system to equal load steps is shown in Figs. 11 and 12. The digital loads were modeled as a set of variable resistors. The resistance is selected to be 1/(Cfb ) depending on the load condition being modeled. The main power supply had a buck topology and a 12-V input. All local VRs had a 500-kHz switching frequency, 1-H inductance, and 500-F output capacitance. A simple PI controller is used for regulation. The voltage of each core is the same in the parallel system. In Fig. 11(a), the load voltage in the parallel system is found to deviate by 7 mV in response to 1.25-A load transients. The current in the main supplys inductor and the processor cores, shown in Fig. 11(b), demonstrates that the main VR must process the entire load current, here 8385 A. The power consumed in the load is 85 W at full load. Independently regulated voltages are observed in the series system. As seen in Fig. 12(a), the local core voltages reach steady state in approximately 100 s with maximum voltage deviation of 20 mV. Since individual processor voltages can be lowered, several processor currents decrease, as shown in Fig. 12(b). The total power consumed by the load in this case is about 70 W. The VR currents included in Fig. 12(c) demonstrate active regulation of core voltages with reduced power processing. The main power supply only provides about 20 A and the differential VRs provide less than 5A each. This results in substantially reduced power loss in the power delivery circuits. Assuming the same conduction path resistance for both cases, the conduction losses (i.e., i2 R) are reduced by over 90%. Similarly, the switching losses in the voltage regulators decrease. In practice, the switching converters used in the two systems would be designed and implemented differently, resulting in reduced cost and additional energy savings for the series system.

Fig. 12. Load-transient response of four stacked cores showing (a) core voltage, (b) core current, and (c) VR inductor current.

Fig. 13. Diagram of experimental prototype with four series voltage domains. Differential VRs are shown with a bus-to-load architecture. Thick lm resistors and microcontrollers act as loads on each domain. Digital isolator chips enable communication across domains.

B. Experimental Results A hardware prototype was developed to experimentally verify the potential of differential power processing. The prototype, illustrated in Fig. 13, consists of four voltage domains connected in series. Three MSP430 microcontrollers are powered from each voltage domain for a total of 12 microcontrollers. Each domain also includes thick-lm resistors and highbrightness LEDs to increase the load current and to test load transient response. TPS54550 chips along with other necessary

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TABLE I COMPARISON OF CASCADED AND DIFFERENTIAL ARCHITECTURE CONVERSION EFFICIENCY

components were selected for voltage regulation of the three intermediate nodes. A central converter regulated the overall voltage. Microcontrollers communicated across voltage domains using the SPI protocol through ISO7241C digital isolators. Several load conditions were examined to compare the efciency of differential power delivery with the traditional cascaded approach. The measured results are tabulated in Table I. The cascaded architecture was formed by reconguring the hardware prototype, and the same voltage regulation circuits were used. Voltage domains 1 through 4 were regulated at 2.25 V, 2.75 V, 2.5 V, and 2.5 V, respectively. For load cases 1 and 2, the load was varied on the second domain V2 , and for cases 3 and 4 the rst domain load was adjusted. As seen in Table I, the differential architecture can regulate the same loads with about 1-W less input power. This represents a 78% decrease in input power and an increase in overall conversion efciency by about 67 percentage points. This improvement is due to both the central converter efciency increasing from around 91% to 93% and the VRs effective efciency increasing from about 92% to 97%. Power loss in energy conversion circuits decreases by 4050%. The prototype system was tested with load steps on the lowest voltage domain using a buckboost bus-to-load architecture. Fig. 14(a) shows the current into each regulated node. The main power supply current Iin increases as the load increases. The average current of the differential VRs that regulate two higher intermediate voltage nodes (i.e., IL 2 and IL 3 ) does not change. Only the differential VR for the lowest voltage domain responds to the load increase by increasing its current IL 1 . This is in line with the analysis of the bus-to-load architecture. Fig. 14(b) shows the differential voltage of the second domain V2 , the voltage with respect to ground of domains one (V1 ) and two (V21 ), and the differential VR current for domain one (IL 1 ). The voltage of domain one (V1 ) dips during a load increase and overshoots during a load decrease as expected. Although the voltage of the second domain with respect to ground also dips during the transient, its differential voltage increases during the load step up. The system was also tested with a load transient on the second voltage domain. Fig. 15 shows the response of bus-to-load differential VRs. The current supplied by the second differential VR (IL 2 ) increases to meet the increased load demand on that domain. The differential VR for domain one removes this current (i.e., (IL 1 ) is negative) in order to regulate domain one (V1 ). The input current (Iin ) increases since the overall load has increased. These results validate the analysis presented previously.

Fig. 14. Response to a load step on domain one of four series voltage domains. In (a), the main supply current and differential VR currents are shown. In (b), the differential voltage of domain two, the voltage with respect to ground of domain one and two, and the current in the differential VR are shown.

Fig. 15. Response to a load step on domain two of four series voltage domains. The gate-to-source voltage V g s of the load switch indicates the timing of the transient. The main supply input current and differential VR currents are also shown.

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VII. OTHER APPLICATIONS Thus far the discussion surrounding DPP has focused on digital loads. Other homogeneous and heterogeneous elements acting as loads, sources, and energy storage devices can benet from this approach as well. Some systems with intrinsically heterogeneous characteristics such as solar photovolatics (PV) and solid-state lighting are well suited to DPP. To demonstrate the generality, these two applications are examined further. A. Solid-State Lighting LEDs are increasingly being used in lighting applications. LED characteristics can vary substantially, and a binning process is commonly employed by manufacturers. Furthermore, some applications like RGB (red, green, and blue) lighting require dissimilar LEDs whose voltage and current characteristics do not match. Linear current regulators used to overcome this drawback add cost and decrease efciency. The DPP concept can be applied to enable sections of a series string of LEDs to operate at independent voltage and current levels with less power-processing overhead than conventional solutions. B. Solar Photovoltaics Maximum power point (MPP) current mismatch is a wellknown challenge in series solar photovoltaic (PV) systems. Module-integrated converters are sometimes employed to overcome MPP mismatch. The trouble is that the energy loss from the added conversion stage can outweigh the increase in energy generated by the PV system. DPP has been successfully applied to series PV panels in [36][38]. Some earlier studies take a similar approach [39], [40]. A high level of MPP granularity is achieved, and only a small fraction of total power is processed by differential converters. Another benet is increased system reliability. VIII. CONCLUSION System-level design of digital circuits must change to address power concerns. Currently available options will not be sufcient to overcome the power wall. Series-connected load voltage domains can reduce power consumption in the load and energy loss in the power delivery system. This paper introduces and analyzes differential power processing architectures to facilitate series-connected circuits and is in stark contrast to conventional methods that add energy conversion stages to meet power delivery objectives. A major benet of differential power processing is that local voltage regulators process only a fraction of the load power when a load current mismatch exists. This improves performance, signicantly reduces power loss, lowers costs, and reduces component size. Converter components with lower ratings can be used, allowing integrated converters with simple controls. In digital applications, this approach is enabled by computational load management and regulation of the intermediate-node voltages. A variety of regulation mechanisms ranging from software to power electronics is feasible. A series connection facilitates substantial voltage reduction. Independent supply voltage

levels for heterogeneous loads can be varied dynamically to operate each load at its most efcient operating point. This technique is especially suited for multicore processors that run most efciently at very low voltage (e.g., 0.3 V). In turn, the number of pins dedicated to power is reduced. Analysis has shown that differential power processing will result in a more efcient system than conventional approaches. Three different differential power delivery architectures were presented and compared. Simulation and experimental results for a test system with four series voltage domains demonstrate its validity. A 78% reduction in input power and an increase in overall conversion efciency by 67 percentage points compared to the conventional cascaded approach were measured for several load conditions. This represents a 40%50% decrease in power loss in energy conversion circuits. Differential power processing can be successfully applied to integrated circuits, solid-state lighting, solar photovolatics, and other low-voltage dc power delivery applications. ACKNOWLEDGMENT The authors would like to thank T. Neyens and I. Federov for assisting in prototype hardware builds. The authors would also like to thank N.R. Shanbhag, R. Campbell, R. Abdallah, S. Zhang, and H. Kharbanda for insights related to CMOS circuits and software management. The information, data, or work presented herein was funded in part by an agency of the United States Government. Neither the United States Government nor any agency thereof, nor any of their employees, makes any warranty, express or implied, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any information, apparatus, product, or process disclosed, or represents that its use would not infringe privately owned rights. Reference herein to any specic commercial product, process, or service by trade name, trademark, manufacturer, or otherwise does not necessarily constitute or imply its endorsement, recommendation, or favoring by the United States Government or any agency thereof. The views and opinions of authors expressed herein do not necessarily state or reect those of the United States Government or any agency thereof. REFERENCES
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Pradeep S. Shenoy (S06M12) received the B.S. degree in electrical engineering from the Illinois Institute of Technology, Chicago, in 2007, and the M.S. and Ph.D. degrees in electrical engineering from the University of Illinois, Urbana-Champaign, in 2010 and 2012, respectively. In 2008, he participated in the National Science Foundations East Asia and Pacic Summer Institutes program during his research at Tsinghua University, Beijing, China. He interned with Caterpillars Electric Power Division in 2005 and with Texas Instruments Systems and Applications Lab in 2011. He is currently with Kilby Labs, Texas Instruments, Dallas. Dr. Shenoy received the Camras Scholarship in 20032007 and a Foreign Language and Area Studies Fellowship in 20092010. He received the Illinois International Graduate Achievement Award in 2010 and was a nalist for the Lemelson-MIT Illinois Student Prize for innovation in 2012. He was the Vice Chair of the IEEE Power Electronics Society/Power and Energy Society Joint Student Chapter at the University of Illinois in 20092010 and the Co-Director of the 2011 IEEE Power and Energy Conference at Illinois. He serves as the Student Liaison for the IEEE Power Electronics Society.

Philip T. Krein (S76M82SM93F00) received the B.S. degree in electrical engineering and the A.B. degree in economics and business from Lafayette College, Easton, PA, and the M.S. and Ph.D. degrees in electrical engineering from the University of Illinois, Urbana. He was an engineer with Tektronix in Beaverton, Oregon, then returned to the University of Illinois at Urbana-Champaign. At present, he holds the Grainger Endowed Directors Chair in Electric Machinery and Electromechanics as Professor and Director of the Grainger Center for Electric Machinery and Electromechanics. His research interests address all aspects of power electronics, machines, drives, and electrical energy, with emphasis on nonlinear control and distributed systems. He published an Undergraduate Textbook Elements of Power Electronics (Oxford University Press, 1998). In 2001, he helped initiate the International Future Energy Challenge, a major student competition involving fuel cell power conversion and energy efciency. He is the Academic Advisor for the Department of Electronic and Information Engineering, Hong Kong Polytechnic University, Hong Kong. He is the Chairman of the Board of SolarBridge Technologies, Austin, TX, a developer of long-life integrated solar energy systems. He holds 20 U.S. patents with additional patents pending. Dr. Krein is a Registered Professional Engineer in Illinois and in Oregon. He was a Senior Fulbright Scholar at the University of Surrey, Guildford, U.K., in 19971998, and was recognized as a University Scholar in 1999, the highest research award at the University of Illinois. In 2003, he received the IEEE William E. Newell Award in Power Electronics. He was the President of the IEEE Power Electronics Society, and was a Member of the IEEE Board of Directors. In 20052007, he was a Distinguished Lecturer for the IEEE Power Electronics Society. In 2008, he received the Distinguished Service Award from the IEEE Power Electronics Society.