Electronic Circuits Lab Manual 1

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Document Name: Electronic Circuits -1 Lab Manual
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SYLLABUS 147352 ELECTRONIC CIRCUITS LAB I
(Common to ECE & Bio Medical Engineering) Expt No.1 Fixed Bias amplifier circuit using BJT 1. Waveforms at input and output without bias. 2. Determination of bias resistance to locate Q-point at center of load line. 3. Measurement of gain. 4. Plot the frequency response & Determination of Gain Bandwidth Product Expt No.2 Design and construct BJT Common Emitter Amplifier using voltage divider bias (self-bias) with and without bypassed emitter resistor. 1. Measurement of gain. 2. Plot the frequency response & Determination of Gain Bandwidth Product. Expt No.3 Design and construct BJT Common Collector Amplifier using voltage Divider bias (self-bias). 1. Measurement of gain. 2. Plot the frequency response & Determination of Gain Bandwidth Product. Expt No.4 Darlington Amplifier using BJT. 1. Measurement of gain and input resistance. 2. Comparison with calculated values. 3. Plot the frequency response & Determination of Gain Bandwidth Product Expt No.5 Source follower with Bootstrapped gate resistance 1. Measurement of gain, input resistance and output resistance with and without Bootstrapping. 2. Comparison with calculated values. Expt No.6 Differential amplifier using BJT 1. Measurement of CMRR. 2. Expt No.7 Class A Power Amplifier 1. Observation of output waveform. 2. Measurement of maximum power output. 3. Determination of efficiency. 4. Comparison with calculated values. Expt No.8 Class B Complementary symmetry power amplifier 1. Observation of the output waveform with crossover Distortion. 2. Modification of the circuit to avoid crossover distortion. 3. Measurement of maximum power output.
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4. Determination of efficiency. 5. Comparison with calculated values. Expt No.9 Power Supply circuit - Half wave rectifier with simple capacitor filter. 1. Measurement of DC voltage under load and ripple factor, Comparison with calculated values. 3. Plot the Load regulation characteristics using Zener diode. Expt No.10 Power Supply circuit - Full wave rectifier with simple capacitor filter 1. Measurement of DC voltage under load and ripple factor, Comparison with calculated values. 2. Measurement of load regulation characteristics. Comparison with calculated values.
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1. &'ED (&)* )M+L& &E, C&,C-&% 1.1. )&M:
To construct a fixed bias amplifier circuit and to plot the frequency response characteristics. 1..)++),)%-* ,E/-&,ED:
S.No. 1. 2. 3. 4. 5. 6. 7.
Name Transistor Resistor Regulated power supply Signal Generator CRO Bread Board Capacitor
Range BC107 10 k,100 k,680 (0-30)V (0-3)MHz 30 MHz 47F
Quantity 1 1,1,1 1 1 1 1 2
C&,C-&% D&)0,)M
M1DEL 0,)+2
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f1 %)(.1.1:
&0.3..
f2
f (Hz)
,E/-ENC4 ,E*+1N*E 1
&'ED (&)* )M+L& &E,
Keep the input voltage constant (Vin) =
Frequency (in Hz)
Output Voltage (in volts)
Gain = 20 log (Vo / Vin) (in dB)
1.5. 1,M-L):
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a) ,. # 6,17,.8 9 voltage at which lass !" lass # or lass operation ta$es place
b) hfe = %&c ' %&b

1.:. %2E1,4:
&n order to operate the transistor in the desired region" we have to apply an external dc voltage of correct polarity and magnitude to the two (unctions of the transistor. This is called biasing of the transistor.
)hen we bias a transistor" we establish certain current and voltage conditions for the transistor. These conditions are called operating conditions or dc operating point or quiescent point. This point must be stable for proper operation of transistor. !n important and common type of biasing is called *ixed #iasing. The circuit is very simple and uses only few components. #ut the circuit does not chec$ the collector current which increases with the rise in temperature.
1.;. +,1CED-,E +. onnections are made as per the circuit diagram. ,. The waveforms at the input and output are observed for lass !" lass # and lass operations by varying the input voltages. -. The biasing resistances needed to locate the ./point are determined. 0. 1et the input voltage as +V and by varying the frequency" note the output voltage. 2. alculate gain=,3 log (Vo ' Vin) 4. ! graph is plotted between frequency and gain.
1.<. C)LC-L)%&1N*:
a8
%o determine the $alue o" bias resistance
Page 6
,. # 6,17 ,.8
b8
h"e 9= &C#=&(
1.>. ,E*-L%: Thus" the *ixed bias amplifier was constructed and the frequency response curve is plotted. The 5ain #andwidth 6roduct is found to be =
Page
.. (?% )M+L& &E, -*&N0 V1L%)0E D&V&DE, (&)*
..1. )&M: To constant a voltage divider bias amplifier and measure input resistance and gain and also to plot the dc collector current as a function of collector resistance.
.... )++),)%-* ,E/-&,ED:
S.No. 1. 2. 3. 4. 5. 6. 7.
Name Transistor Resistor Capacitor Function Generator CRO Regulated power supply Bread Board
Range BC 107 56k ,12k ,2.2k ,470 0.1F, 47F (0-3)MHz 30MHz (0-30)V
Quantity 1 1,1,1,1 2, 1 1 1 1 1
&0.;.1
Page !
M1DEL 0,)+2
f1
&0...
f2
f (Hz)
%)( ..1:
@eep the input $oltaAe constantB Vin 9
Frequency (in Hz)
Gain= 20 log(Vo/Vin) (in dB)
..5. 1,M-L):
a) 7in = 8 9 7e b) 5ain = 8 9 7e'7in

..:. %2E1,4:
Page "
This type of biasing is otherwise called :mitter #iasing. The necessary biasing is provided using resistors; 7+" 7, and 7e. The resistors 7+ and 7, act as a potential divider and give a fixed voltage to the base. &f the collector current increases due to change in temperature or change in 8" the emitter current &e also increases and the voltage drop across 7e increases" reducing the voltage difference between the base and the emitter. <ue to reduction in Vbe" base current &b and hence collector current &c also reduces. This reduction in Vbe" base current &b and hence collector current &c also reduces. This reduction in the collector current compensates for the original change in &c. The stability factor 1= (+=8) 9 ((+' (+=8)). To have better stability" we must $eep 7b'7e as small as possible. >ence the value of 7+ 7, must be small. &f the ratio 7b'7e is $ept fixed" 1 increases with 8.
;. +,1CED-,E:
+. onnections are given as per the circuit diagram. ,. ?easure the input resistance as 7in=Vin'&in (with output open) and gain by plotting the frequency response. -. ompare the theoretical values with the practical values. 0. 6lot the dc collector current as a function of the collector resistance (ie) plot of Vcc and &c for various values of 7e.
..<. ,E*-L%:
Thus the voltage divider bias amplifier was constructed and input resistance and gain were determined. The 5ain #andwidth 6roduct is found to be =
Page 10
5. C1MM1N C1LLEC%1, )M+L& &E,
5.1 )&M: To construct a common collector amplifier circuit and to plot the frequency response characteristics.
5... )++),)%-* ,E/-&,ED:
S.No. 1. 2. 3. 4. 5. 6. 7.
Range BC 107 15k ,10k ,680 ,6k 0.1F, 47F (0-3)MHz 30MHz (0-30)V
Quantity 1 1,1,1,1 2, 1 1 1 1 1
C&,C-&% D&)0,)M
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M1DEL 0,)+2
f1
&0...
f2
f (Hz)
%)( 5.1:
Frequency (in Hz)
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5.5 %2E1,4: The d.c biasing in common collector is provided by 7+" 7, and 7: .The load resistance is capacitor coupled to the emitter terminal of the transistor. )hen a signal is applied to the base of the transistor "V# is increased and decreased as the signal goes positive and negative" respectively. onsidering V#: is constant the variation in the V# appears at the emitter and emitter voltage V: will vary same as base voltage V# . 1ince the emitter is output terminal" it can be noted that the output voltage from a common collector circuit is the same as its input voltage. >ence the common collector circuit is also $nown as an emitter follower.
5.; +,1CED-,E:
+. onnect the circuit as per the circuit diagram. ,. 1et Vi =23 mV" using the signal generator. -. Keeping the input voltage constant" vary the frequency from 3 >@ to +? >@ in regular steps and note down the corresponding output voltage. 0. 6lot the graphA 5ain (d#) Vs *requency (>@).
,EV&EC /-E*%&1N*:
+. )hy the common collector amplifier is also called an emitter followerB
,. )hat is the need for coupling capacitorsB
-. )hat will be the input Coutput impedance of common collector amplifierB
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0.)rite some applications of common collector amplifier.
2.)hat is the current amplification factor of common collector amplifierB
5.<. ,E*-L%: Thus" the ommon collector amplifier was constructed and the frequency response curve is plotted. The 5ain #andwidth 6roduct is found to be =
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:. D),L&N0%1N )M+L& &E, -*&N0 (?%
:.1 )&M: To construct a <arlington current amplifier circuit and to plot the frequency response characteristics.
:... )++),)%-* ,E/-&,ED:
S.No. 1. 2. 3. 4. 5. 6. 7.
Range BC 107 15k ,10k ,680 ,6k 0.1F, 47F (0-3)MHz 30MHz (0-30)V
Quantity 1 1,1,1,1 2, 1 1 1 1 1
C&,C-&% D&)0,)M
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M1DEL 0,)+2
f1
&0...
f2
f (Hz)
%)( :.1:
Frequency (in Hz)
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%2E1,4:
&n <arlington connection of transistors" emitter of the first transistor is directly connected to the base of the second transistor .#ecause of direct coupling dc output current of the first stage is (+=hfe )&b+.&f <arlington connection for n transitor is considered" then due to direct coupling the dc output current foe last stage is (+=hfe ) n times &b+ .<ue to very large amplification factor even two stage <arlington connection has large output current and output stage may have to be a power stage. !s the power amplifiers are not used in the amplifier circuits it is not possible to use more than two transistors in the <arlington connection. &n <arlington transistor connection" the lea$age current of the first transistor is amplified by the second transistor and overall lea$age current may be high" )hich is not desired.
:.: +,1CED-,E:
+. onnect the circuit as per the circuit diagram. ,. 1et Vi =23 mv" using the signal generator. -. Keeping the input voltage constant" vary the frequency from 3 >@ to +? >@ in regular steps and note down the corresponding output voltage. 0. 6lot the graphA 5ain (d#) vs *requency(>@). 2. alculate the bandwidth from the graph. :.;. ,E*-L%: Thus" the <arlington current amplifier was constructed and the frequency response curve is plotted. . The 5ain #andwidth 6roduct is found to be =
,EV&EC /-E*%&1N*:
+. )hat is meant by <arlington pairB
,. >ow many transistors are used to construct a <arlington amplifier circuitB
Page 1
-. )hat is the advantage of <arlington amplifier circuitB
0.)rite some applications of <arlington amplifier .
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;. *1-,CE 1LL1CE, C&%2 (11%*%,)++ED 0)%E ,E*&*%)NCE ;.1. )&M: To construct a source follower with bootstrapped gate resistance amplifier and plot its frequency response characteristics.
;... )++),)%-* ,E/-&,ED:
1.Do. +. ,. -. 0. 2. 4. E. Transistor 7esistor
Dame # +3E
7ange
.uantity , +"+"+ + + + +
+$F"++ $F"+? $F (3/-3)V (3/-)?>@ -3 ?>@
7egulated power supply 1ignal 5enerator 7G #read #oard apacitor
3.3+H*
&0.15.1
Page 1"
M1DEL 0,)+2
f1 &0.15..
f2
f (Hz)
%)(.;.1.
Keep the input voltage constant (Vin) =
Frequency (in Hz)
Gain = 20 log (Vo / Vin) (in dB)
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;.5. %2E1,4:
Source follower is similar to the emitter follower( the output source voltage follow the gate input voltage),the circuit has a voltage gain of less than unity, no phase reversal, high input impedance, low output impedance. Here the Bootstrapping is used to increase the input resistance by connecting a resistance in between gate and source terminals. The resister RA is required to develop the necessary bias for the gate. 5.4. PROCEDURE:
+. onnections are made as per the circuit diagram. ,. The waveforms at the input and output are observed for cascode operations by varying the input frequency. -. The biasing resistances needed to locate the ./point are determined. 0. 1et the input voltage as +V and by varying the frequency" note the output voltage. 2. alculate gain=,3 log (Vo ' Vin.) 4. ! graph is plotted between frequency and gain. ,E*-L%:
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Thus" the 1ource follower with #ootstrapped gate resistance was constructed and the gain was determined.
,EV&EC /-E*%&1N*:
+. )hat is meant by source followerB
,. )hat is meant by #ootstrappingB
-. >ow the above circuit is used to provide a good impedance matchingB
0. )hat is the advantage of bootstrapping methodB
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<.D& E,EN%&)L )M+L& &E, -*&N0 (?% <.1)im: To construct a differential amplifier using #IT and to determine the dc collector current of individual transistors and also to calculate the ?77.
<... )++),)%-* ,E/-&,ED:
S.No. 1. 2. 3. 4. 5. 6.
Name Transistor Resistor Regulated power supply Function Generator CRO Bread Board
Range BC107 4.7k, 10k (0-30)V (0-3) MHz 30 MHz
Quantity 2 2,1 1 2 1 1
C&,C-&% D&)0,)M
1(*E,V)%&1N V&N 9V1 9)C 9 V1 # V&N
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1,M-L):
ommon mode 5ain
(!c) = VG ' V&D
<ifferential mode 5ain (!d) = V3 ' V&D )here V&D = V+ J V, ommon ?ode 7e(ection 7atio ( ?77) = !d'!c )here" !d is the differential mode gain !c is the common mode gain. %2E1,4: The differential amplifier is a basic stage of an integrated operational amplifier. &t is used to amplify the difference between , signals. &t has excellent stability" high versatility and immunity to noise. &n a practical differential amplifier" the output depends not only upon the difference of the , signals but also depends upon the common mode signal. Transistor .+ and ., have matched characteristics. The values of 7 + and 7 , are equal. 7e+ and 7e, are also equal and this differential amplifier is called emitter coupled differential amplifier. The output is ta$en between the two output terminals.
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1(*E,V)%&1N
V&N 9 V1 V. VD 9 )d 9 VD# V&N *or the differential mode operation the input is ta$en from two different sources and the common mode operation the applied signals are ta$en from the same source ommon ?ode 7e(ection 7atio ( ?77) is an important parameter of the differential amplifier. ?77 is defined as the ratio of the differential mode gain" !d to the common mode gain" !c.
?77 = !d ' !c &n ideal cases" the value of ?77 is very high.
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<.;. +,1CED-,E:
+. onnections are given as per the circuit diagram. ,. To determine the common mode gain" we set input signal with voltage Vin=,V and determine Vo at the collector terminals. alculate common mode gain" !c=Vo'Vin. -. To determine the differential mode gain" we set input signals with voltages V+ and V,. ompute Vin=V+/V, and find Vo at the collector terminals. alculate differential mode gain" !d=Vo'Vin. 0. alculate the ?77=!d'!c. 2. ?easure the dc collector current for the individual transistors.
<.<. ,E*-L%:
Thus" the <ifferential amplifier was constructed and dc collector current for the individual transistors is determined. The ?77 is calculated as
,EV&EC /-E*%&1N*
+. )hat is a differential amplifierB ,. )hat is common mode and differential mode inputs in a differential amplifierB -. <efine ?77. 0. )hat is common mode signalB
2. )rite some applications of <ifferential amplifier.
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>. CL)** - ) +1CE, )M+L& &E, >.1. )&M:
To construct a lass ! power amplifier and observe the waveform and to compute maximum output power and efficiency. >... )++),)%-* ,E/-&,ED:
S.No. 1. 2. 3. 4. 5. 6. 7.
Name Transistor Resistor Capacitor Signal Generator CRO Regulated power supply Bread Board
Range CL100, BC558 47k ,33 ,220, 47 F (0-3)MHz 30MHz (0-30)V
Quantity 1,1 2,1 2 1 1 1 1
C&,C-&% D&)0,)M
Page 2
%)( ..1:
Frequency (in Hz)
>.5. 1,M-L)
MaEimum power trans"er 9+oBmaE9Vo.#,L E""eciencyBF 9 +oBmaE#+c
>.:. %2E1,4: The power amplifier is said to be lass ! amplifier if the . point and the input signal are selected such that the output signal is obtained for a full input signal cycle. *or all values of input signal" the transistor remains in the active region and never enters into cut/ off or saturation region. )hen an a.c signal is applied" the collector voltage varies sinusoidally hence the
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collector current also varies sinusoidally.The collector current flows for -433 (full cycle) of the input signal. i e the angle of the collector current flow is -433 .
>.; +,1CED-,E: +. onnect the circuit as per the circuit diagram. ,. 1et Vi =23 mv" using the signal generator. -. Keeping the input voltage constant" vary the frequency from +3 >@ to +? >@ in regular steps and note down the corresponding output voltage. 0. 6lot the graphA 5ain (d#) vs *requency(>@). >.<.,E*-L%: Thus the lass ! power amplifier was constructed. The following parameters were calculated; a) ?aximum output power= b) :fficiency=
,EV&EC /-E*%&1N*:
+. )hat is meant by 6ower !mplifierB
,. )hat is the maximum efficiency in class J ! amplifier.
-. )hat are the disadvantages of lass J! amplifierB
0. )rite some applications of 6ower amplifier.
2. )hat is the position of ./point in lass J! amplifierB
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G. CL)** ( C1M+LEMEN%),4 *4MME%,4 +1CE, )M+L& &E, G.1. )&M: To construct a lass # complementary symmetry power amplifier and observe the waveforms with and without cross/over distortion and to compute maximum output power and efficiency.
G... )++),)%-* ,E/-&,ED:
S.No. 1. 2. 3. 4. 5. 6. 7. 8.
Name Transistor Resistor Capacitor Diode Signal Generator CRO Regulated power supply Bread Board
Range CL100, BC558 4.7k ,15k 100F IN4007 (0-3)MHz 30MHz (0-30)V
Quantity 1,1 2,1 2 2 1 1 1 1
C&,C-&% D&)0,)M
Page 30
G.5. 1,M-L):
&nput power" 6in=,Vcc&m'L Gutput power" 6out=Vm&m', 6ower 5ain or efficiency" M=N'0(Vm'Vcc) +33
G.:. %2E1,4: ! power amplifier is said to be lass # amplifier if the ./point and the input signal are selected such that the output signal is obtained only for one half cycle for a full input cycle. The ./point is selected on the O/axis. >ence" the transistor remains in the active region only for the positive half of the input signal. There are two types of lass # power amplifiers; 6ush 6ull amplifier and complementary symmetry amplifier. &n the complementary symmetry amplifier" one n/p/n and another p/n/p transistor is used. The matched pair of transistor are used in the common collector configuration. &n the positive half cycle of the input signal" the n/p/n transistor is driven into active region and starts conducting and in negative half cycle" the p/n/p transistor is driven into conduction. >owever there is a period between the crossing of the half cycles of the input signals" for which none of the transistor is active and output" is @ero C&,C-&% D&)0,)M
&0.<..
Page 31
1(*E,V)%&1N 1-%+-% *&0N)L )M+L&%-DE %&ME +E,&1D : :
C)LC-L)%&1N
+1CE,B +&N
9 .VCC &m#H
1-%+-% +1CE,B +1-% 9 Vm&m#. E &C&ENC4B F
9 6 H#:86 Vm# VCC8 E 1DD
M1DEL 0,)+2
&0.<.5
Page 32
G.;. +,1CED-,E: +. onnections are given as per the circuit diagram without diodes. ,. Gbserve the waveforms and note the amplitude and time period of the input signal and distorted waveforms. -. onnections are made with diodes. 0. Gbserve the waveforms and note the amplitude and time period of the input signal and output signal. 2. <raw the waveforms for the readings. 4. alculate the maximum output power and efficiency. >ence the nature of the output signal gets distorted and no longer remains the same as the input. This distortion is called cross/over distortion. <ue to this distortion" each transistor conducts for less than half cycle rather than the complete half cycle. To overcome this distortion" we add , diodes to provide a fixed bias and eliminate cross/over distortion. G.<.,E*-L%: Thus the lass # complementary symmetry power amplifier was constructed to observe cross/ over distortion and the circuit was modified to avoid the distortion. The following parameters were calculated; a)?aximum output power= b):fficiency=
Page 33
3. 2)L C)VE ,EC%& &E,
3.1. )&M:
To construct half wave rectifier with and without filter and to draw their input and output waveforms.
3... )++),)%-* ,E/-&,ED: 1.Do. +. ,. -. 0. 2. 4. Dame Transformer <iode 7esistor apacitor 7G #read #oard 7ange ,-3 V ' 4/3/(/4) &D033E + $F +33H* -3 ?>@ .uantity + + + + + +
C&,C-&% D&)0,)M: C&%21-% &L%E,:
&0.15.1
Page 34
C&%2 &L%E,:
&0.15..
3.5. 1,M-L) -*ED:
,ipple actor 9 Chere &m is the pea! current
3.:. %2E1,4:
2al" wa$e recti"ier:
! rectifier is a circuit" which uses one or more diodes to convert !. voltage into <. voltage. &n this rectifier during the positive half cycle of the !. input voltage" the diode is forward biased and conducts for all voltages greater than the offset voltage of the semiconductor material used. The voltage
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produced across the load resistor has same shape as that of the positive input half cycle of !. input voltage. <uring the negative half cycle" the diode is reverse biased and it does not conduct. 1o there is no current flow or voltage drop across load resistor. The net result is that only the positive half cycle of the input voltage appears at the output.
3.;. +,1CED-,E:
+. onnect the circuit as per the circuit diagram. ,. !pply a.c input using transformer. -. ?easure the amplitude and time period for the input and output waveforms. 0. alculate ripple factor.
M1DEL 0,)+2:
&0.15.;
Page 36
%)(.3.1:
2)L C)VE ,EC%& &E,:
)ithout filter &nput signal !mplitude(V) Time period
)ith filter Gutput signal !mplitude(V) Time period
3.<. ,E*-L%: Thus the half wave rectifier was constructed and its input and output waveforms are drawn. The ripple factor of capacitive filter is calculated as
7ipple factor=
Page 3
1D. -LL C)VE ,EC%& &E, 1D.1. )&M: To construct a full wave rectifier and to measure dc voltage under load and to calculate the ripple factor. 1D... )++),)%-* ,E/-&,ED:
S.No. 1. 2. 3. 4. 5. 6.
Name Transformer Diode Resistor Capacitor CRO Bread Board
Range 230 V / 6-0-(-6) IN4007 1 k 100F 30 MHz
Quantity 1 2 1 1 1 1
-LLC)VE ,EC%& &E, C&%21-% &L%E,
&0.G.1
Page 3!
-LLC)VE ,EC%& &E, C&%2 &L%E,
&0.G..
1D.5. 1,M-L) ,ipple actor 9 I J6&m#I.8 # 6.K&m #H8L Chere &m is the pea! current
.
-1
1D.:. %2E1,4: The full wave rectifier conducts for both the positive and negative half cycles of the input ac supply. &n order to rectify both the half cycles of the ac input" two diodes are used in this circuit. The diodes feed a common load 7P with the help of a centre tapped transformer. The ac voltage is applied through a suitable power transformer with proper turnQs ratio. The rectifierQs dc output is obtained across the load. The dc load current for the full wave rectifier is twice that of the half wave rectifier. The lowest ripple factor is twice that of the full wave rectifier. The efficiency of full wave rectification is twice that of half wave rectification. The ripple factor also for the full wave rectifier is less compared to the half wave rectifier.
Page 3"
+,1CED-,E: +. onnections are given as per the circuit diagram wiyhout filter. ,. Dote the amplitude and time period of the input signal at the secondary winding of the transformer and rectified output. -. 7epeat the same steps with the filter and measure Vdc. 0. alculate the ripple factor. 2. <raw the graph for voltage versus time. M1DEL 0,)+2
,E*-L%: Thus" the full wave rectifier was constructed and the ripple factor was calculated as 7ipple factor =
Page 40
1D.; ,EV&EC /-E*%&1N*:
+. )hat is meant by rectifierB
,. )rite the operation of two diodes during the application of ! input signal
-. )hich type of transformer used for the rectifier inputB
0. <efine ripple factor.
2. )rite the efficiency of this rectifier.
Page 41
11. C)*C)DE )M+L& &E, C&,C-&% 11.1. )&M: To construct a cascade amplifier circuit and to plot the frequency response characteristics. 11... )++),)%-* ,E/-&,ED: 1.Do. +. ,. -. 0. 2. 4. E. Transistor 7esistor 7egulated power supply 1ignal 5enerator 7G #read #oard apacitor 3.3+H* Dame # +3E +3$F"R $F"233 F"+33F (3/-3)V (3/-)?>@ -3 ?>@ 7ange .uantity + +"+"+"+ + + + + 2
11.5. %2E1,4:
A cascade amplifier has many of the same benefits as a cascode. A cascade is basically a differential amplifier with one input grounded and the side with the real input has no load. It can also be seen as a common collector (emitter follower) followed by a common base. By cascading a CE stage followed by an emitter-follower (CC) stage, a good voltage amplifier results. The CE input resistance is high and CC output resistance is low. The CC contributes no increase in voltage gain but provides a near voltage-source (low resistance) output so that the gain is nearly independent of load resistance. The high input resistance of the CE stage makes the input voltage nearly independent of input-source resistance. Multiple CE stages can be cascaded and CC stages inserted between them to reduce attenuation due to inter-stage loading.
Page 42
&0.11.1
M1DEL 0,)+2
f1
&0.11..
f2
f (Hz)
11.:. +,1CED-,E:
Page 43
+. onnections are made as per the circuit diagram. ,. The waveforms at the input and output are observed for cascade operations by varying the input frequency. -. The biasing resistances needed to locate the ./point are determined. 0. 1et the input voltage as +V and by varying the frequency" note the output voltage. 2. alculate gain=,3 log (Vo ' Vin.) 4. ! graph is plotted between frequency and gain. %)(.11.1. ,E/-ENC4 ,E*+1N*E 1 C)*C1DE )M+L& &E, Keep the input voltage constant (Vin) =
Frequency (in Hz) Output Voltage (in volts) Gain = 20 log (Vo / Vin) (in dB)
11.;. ,E*-L%:
Thus" the ascade amplifier was constructed and the gain was determined.
,EV&EC /-E*%&1N* +. )hat is meant by ascadingB
Page 44
,. )hat is the overall gain of the two stage cascaded amplifierB
-. )hat methods are used for cascadingB
0. )hat is the disadvantage of direct coupled cascade amplifierB 2. )rite some application of cascaded amplifier.
Page 45
1.. C)*C1DE )M+L& &E, C&,C-&% 1..1. )&M:
To construct a cascode amplifier circuit and to plot the frequency response characteristics.
1.... )++),)%-* ,E/-&,ED:
1.Do. +. Transistor
Dame # +3E
7ange
.uantity , +"+"+"+" +"+"+" + + + + +
,,$F"4 $F"E33 F"0E3F ,. 7esistor +4 $F"4., $F"-.- $F +.+ $F -. 0. 2. 4. E. 7egulated power supply 1ignal 5enerator 7G #read #oard apacitor 3.3+H* (3/-3)V (3/-)?>@ -3 ?>@
1..5. %2E1,4:
A cascode amplifier consists of a common emitter amplifier stage in series with a common base amplifier stage. It it one approach to solve the low impedance problem of a common base circuit. Transistor Q1 and its associated components operate as a common emitter amplifier, while the circuit of Q2 functions as a common base output stage. The cascade amplifier gives the high input impedance of a common emitter amplifier, as well as the good voltage gain and frequency performance of a common base circuit.
Page 46
&0.1..1 M1DEL 0,)+2
f1
&0.1...
f2
f (Hz)
12.4. PROCEDURE:
+. onnections are made as per the circuit diagram. ,. The waveforms at the input and output are observed for cascode operations by varying the input frequency. -. The biasing resistances needed to locate the ./point are determined. 0. 1et the input voltage as +V and by varying the frequency" note the output voltage.
Page 4
2. alculate gain=,3 log (Vo ' Vin.) 4. ! graph is plotted between frequency and gain.
%)(.1..1.
,E/-ENC4 ,E*+1N*E 1 C)*C1DE )M+L& &E, Keep the input voltage constant (Vin) =
Frequency (in Hz) Output Voltage (in volts) Gain = 20 log (Vo / Vin) (in dB)
1..;. ,E*-L%:
Thus" the ascade amplifier was constructed and the gain was determined.
,EV&EC /-E*%&1N*: +. )hat is meant by ascodingB ,. )hat is the overall gain of the two stage cascaded amplifierB -. )hat methods are used for cascadingB 0. )hat is the disadvantage of direct coupled cascade amplifierB 2. ompare cascade amplifier with cascade amplifier.
Page 4!

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Document Name: Electronic Circuits -1 Lab Manual

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Range BC107 10 k,100 k,680 (0-30)V (0-3)MHz 30 MHz 47F

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&'ED (&)* )M+L& &E,

Keep the input voltage constant (Vin) =

Frequency (in Hz)

Output Voltage (in volts)

Gain = 20 log (Vo / Vin) (in dB)

Copyright 2011-2015 VidyarthiPlus.in

b) hfe = %&c ' %&b

%o determine the $alue o" bias resistance

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Copyright 2011-2015 VidyarthiPlus.in

.. (?% )M+L& &E, -*&N0 V1L%)0E D&V&DE, (&)*

.... )++),)%-* ,E/-&,ED:

Copyright 2011-2015 VidyarthiPlus.in

@eep the input $oltaAe constantB Vin 9

Frequency (in Hz)

Output Voltage (in volts)

Gain= 20 log(Vo/Vin) (in dB)

a) 7in = 8 9 7e b) 5ain = 8 9 7e'7in

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Copyright 2011-2015 VidyarthiPlus.in

5... )++),)%-* ,E/-&,ED:

Copyright 2011-2015 VidyarthiPlus.in

@eep the input $oltaAe constantB Vin 9

Frequency (in Hz)

Output Voltage (in volts)

Gain= 20 log(Vo/Vin) (in dB)

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+. )hy the common collector amplifier is also called an emitter followerB

,. )hat is the need for coupling capacitorsB

-. )hat will be the input Coutput impedance of common collector amplifierB

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2.)hat is the current amplification factor of common collector amplifierB

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:... )++),)%-* ,E/-&,ED:

Copyright 2011-2015 VidyarthiPlus.in

@eep the input $oltaAe constantB Vin 9

Frequency (in Hz)

Output Voltage (in volts)

Gain= 20 log(Vo/Vin) (in dB)

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+. )hat is meant by <arlington pairB

,. >ow many transistors are used to construct a <arlington amplifier circuitB

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0.)rite some applications of <arlington amplifier .

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;... )++),)%-* ,E/-&,ED:

1.Do. +. ,. -. 0. 2. 4. E. Transistor 7esistor

+$F"++ $F"+? $F (3/-3)V (3/-)?>@ -3 ?>@

7egulated power supply 1ignal 5enerator 7G #read #oard apacitor

Copyright 2011-2015 VidyarthiPlus.in

Keep the input voltage constant (Vin) =

Frequency (in Hz)

Output Voltage (in volts)

Gain = 20 log (Vo / Vin) (in dB)

Copyright 2011-2015 VidyarthiPlus.in

.. (?% )M+L& &E, -&N0 V1L%)0E D&V&DE, (&)

1D.; ,EV&EC /-E%&1N:

,EV&EC /-E%&1N +. )hat is meant by ascadingB