AMIS-30622 I2C Micro-Stepping Motor Driver

INTRODUCTION

The AMIS30622 is a singlechip microstepping motor driver with a position controller and control/diagnostic interface. It is ready to build intelligent peripheral systems where up to 32 drivers can be connected to one I2C master. This significantly reduces system complexity. The chip receives positioning instructions through the bus and subsequently drives the stator coils so the twophase stepper motor moves to the desired position. The onchip position controller is configurable (OTP or RAM) for different motor types, positioning ranges and parameters for speed, acceleration and deceleration. Micro stepping allows silent motor operation and increased positioning resolution. The advanced motion qualification mode enables verification of the complete mechanical system in function of the selected motion parameters. The AMIS30622 can easily be connected to an I2C bus where the I2C master can fetch specific status information like actual position, error flags, etc. from each individual slave node. The chip is implemented in I2T100 technology, enabling both high voltage analog circuitry and digital functionality on the same chip.
PRODUCT FEATURES Motor Driver

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SOIC20 3 or 7 SUFFIX CASE 751AQ

MicroStepping Technology Peak Current Up to 800 mA Fixed Frequency PWM CurrentControl Automatic Selection of Fast and Slow Decay Mode No external Flyback Diodes Required 14 V/24 V Compliant

NQFP32 8 SUFFIX CASE 560AA

ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.

Controller with RAM and OTP Memory

Position Controller Configurable Speeds and Acceleration Input to Connect Optional Motion Switch
I2C Interface

BiDirectional 2Wire Bus for Inter IC Control Field Programmable Node Addresses Full Diagnostics and Status Information
Protection

Overcurrent Protection Undervoltage Management Opencircuit Detection High Temperature Warning and Management Low Temperature Flag

EMI Compatibility

High Voltage Outputs with Slope Control This is a PbFree Device

Semiconductor Components Industries, LLC, 2013

July, 2013 Rev. 5

Publication Order Number: AMIS30622/D

AMIS30622
APPLICATIONS The AMIS30622 is ideally suited for small positioning applications. Target markets include: automotive (headlamp alignment, HVAC, idle control, cruise control), industrial equipment (lighting, fluid control, labeling, process control, XYZ tables, robots) and building automation (HVAC,
Table 1. ORDERING INFORMATION
Part No. AMIS30622C6223G AMIS30622C6223RG AMIS30622C6227G AMIS30622C6227RG AMIS30622C6228G AMIS30622C6228RG Peak Current 800 mA 800 mA 800 mA 800 mA 800 mA 800 mA Industrial High Voltage Version Automotive High Voltage Version End Market/Version Package* SOIC20 (PbFree) SOIC20 (PbFree) SOIC20 (PbFree) SOIC20 (PbFree) NQFP32 (7 x 7 mm) (PbFree) NQFP32 (7 x 7 mm) (PbFree) Shipping 38 Rail 1500 Tape & Reel 38 Rail 1500 Tape & Reel 40 Rail 2500 Tape & Reel

surveillance, satellite dish, renewable energy systems). Suitable applications typically have multiple axes or require mechatronic solutions with the driver chip mounted directly on the motor.

*For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.

QUICK REFERENCE DATA

Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter VBB, VHW, VSWI TJ Tst Vesd (Note 3) Supply voltage, hardwired address and SWI pins Junction temperature range (Note 2) Storage temperature Human Body Model (HBM) Electrostatic discharge voltage on pins Machine Model (MM) Electrostatic discharge voltage on pins Min 0.3 50 55 2 200 Max +40 (Note 1) +175 +160 +2 +200 Unit V C C kV V

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. For limited time: VBB < 0.5 s, SWI and HW pins <1.0 s. 2. The circuit functionality is not guaranteed. 3. HBM according to AECQ100: EIAJESD22A114B (100 pF via 1.5 kW) and MM according to AECQ100: EIAJESD22A115A.

Table 3. OPERATING RANGES

Parameter VBB TJ Supply voltage Operating temperature range Min +6.5 40 Max +29 +165 Unit V C

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Table of Contents

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Product Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Quick Reference Data . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Package Thermal Resistance . . . . . . . . . . . . . . . . . . . . . 5 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SDA SCK SWI

Positioning Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Structural Description . . . . . . . . . . . . . . . . . . . . . . . . . 14 Functions Description . . . . . . . . . . . . . . . . . . . . . . . . . 15 Position Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Main Control and Register . . . . . . . . . . . . . . . . . . . . . . 22 OTP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Priority Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Motordriver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 I2C Bus Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 I2C Application Commands . . . . . . . . . . . . . . . . . . . . . 40 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

AMIS30622 I2C bus Interface Position Controller Controller TST1 TST2 Decoder Main Control Registers OTP ROM Sinewave Table DACs 4MHz Vref Temp sense Oscillator PWM regulator Y Charge Pump
Isense Isense

HW

PWM regulator X

MOTXP MOTXN

Stall detection

MOTYP MOTYN

Voltage Regulator

VBB

VDD

CPN

CPP

VCP

GND

Figure 1. Block Diagram

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GND 32 XP XP VBB VBB VBB SWI NC SDA 9 SCK VDD GND TST1 TST2 GND HW NC 1 2 3 4 5 6 7 8 AMIS30622 (Top View) 31 30 29 28 27 26 24 23 22 21 20 19 18 10 11 12 13 14 15 17 16 GND GND GND XN YP YP XN

SDA SCK VDD GND TST1 TST2 GND HW CPN CPP

1 2 3 4 5 6 7 8 9 10 SOIC20 AMIS30622

20 19 18 17 16 15 14 13 12 11

SWI VBB MOTXP GND MOTXN MOTYP GND MOTYN VBB VCP

25 YN YN VBB VBB VBB VCP CPP CPN

Figure 2. SOIC20 and NQFP32 Pinout

Table 4. PIN DESCRIPTION

Pin Name SDA SCK VDD GND TST1 TST2 HW CPN CPP VCP VBB MOTYN MOTYP MOTXN MOTXP SWI NC I2C serial data line Pin Description SOIC20 1 2 3 4, 7, 14, 17 5 6 8 9 10 11 12, 19 13 15 16 18 20 NQFP32 8 9 10 11, 14, 25, 26, 31, 32 12 13 15 17 18 19 3, 4, 5, 20, 21, 22 23, 24 27, 28 29, 30 1, 2 6 7, 16

I2C serial clock line Internal supply (needs external decoupling capacitor) Ground, heat sink Test pin (to be tied to ground in normal operation) Test pin (to be left open in normal operation: internally pulled up) Hard wired address bit Negative connection of pumpcapacitor (charge pump) Positive connection of pumpcapacitor (charge pump) Chargepump filtercapacitor Battery voltage supply Negative end of phase Y coil Positive end of phase Y coil Negative end of phase X coil Positive end of phase X coil Switch input Not connected (to be tied to ground)

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PACKAGE THERMAL RESISTANCE The AMIS30622 is available in SOIC20 or optimized NQFP32 packages. For cooling optimizations, the NQFP has an exposed thermal pad which has to be soldered to the PCB ground plane. The ground plane needs thermal vias to conduct the head to the bottom layer. Figures 3 and 4 give examples for good power distribution solutions. For precise thermal cooling calculations the major thermal resistances of the devices are given. The thermal media to which the power of the devices has to be given are: Static environmental air (via the case) PCB board copper area (via the device pins and exposed pad) The thermal resistances are presented in Table 5: DC Parameters.
Rth JunctiontoLeads and Exposed Pad Rthjp Rth JunctiontoLeads Rthjp 19 0,95

The major thermal resistances of the device are the Rth from the junction to the ambient (Rthja) and the overall Rth from the junction to the leads (Rthjp). The NQFP device is designed to provide superior thermal performance. Using an exposed die pad on the bottom surface of the package is mainly contributing to this performance. In order to take full advantage of the exposed pad, it is most important that the PCB has features to conduct heat away from the package. A thermal grounded pad with thermal vias can achieve this. In the table below, one can find the values for the Rthja and Rthjp, simulated according to the JESD51 norm:

Package SOIC20 NQFP32

Rth JunctiontoAmbient Rthja (1S0P) 62 60

Rth JunctiontoAmbient Rthja (2S2P) 39 30

The Rthja for 2S2P is simulated conform to JESD51 as follows: A 4layer printed circuit board with inner power planes and outer (top and bottom) signal layers is used Board thickness is 1.46 mm (FR4 PCB material) The 2 signal layers: 70 mm thick copper with an area of 5500 mm2 copper and 20% conductivity

The 2 power internal planes: 36 mm thick copper with

an area of 5500 mm2 copper and 90% conductivity The Rthja for 1S0P is simulated conform to JESD51 as follows: A 1layer printed circuit board with only 1 layer Board thickness is 1.46 mm (FR4 PCB material) The layer has a thickness of 70 mm copper with an area of 5500 mm2 copper and 20% conductivity

Figure 3. Example of SOIC20 PCB Ground Plane Layout (preferred layout at top and bottom)

SOIC20

Figure 4. Example of NQFP32 PCB Ground Plane Layout (preferred layout at top and bottom)

NQFP32

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DC PARAMETERS The DC parameters are guaranteed overtemperature and VBB in the operating range, unless otherwise specified. Convention: currents flowing into the circuit are defined as positive.
Table 5. DC PARAMETERS
Symbol Pin(s) Parameter Test Conditions Min Typ Max Unit MOTORDRIVER IMSmax,Peak IMSmax,RMS IMSabs IMSrel RDS(on) Max current through motor coil in normal operation Max rms current through coil in normal operation Absolute error on coil current (Note 4) VBB = 14 V VBB = 14 V VBB = 14 V VBB = 14 V VBB = 12 V, Tj = 50C VBB = 8 V, Tj = 50C VBB = 12 V, Tj = 150C VBB = 8 V, Tj = 150C IMSL I2C VIL VIH VnL SDA SCK Pulldown current HiZ mode, VBB = 7.8 V 0.5 0.7 * VDD 0.1 * VDD SERIAL INTERFACE Input level low (Note 10) Input level high (Note 11) Noise margin at the LOW level for each connected device (including hysteresis) Noise margin at the HIGH level for each connected device (including hysteresis) 0.3 * VDD VDD + 0.5 V V V 10 7 0 0.50 0.55 0.70 0.85 2 800 570 10 7 1 1 1 1 mA mA % % W W W W mA

MOTXP MOTXN Matching of X & Y MOTYP coil currents MOTYN On resistance for each motor pin at IMSmax (Note 5)

VnH

0.2 * VDD

THERMAL WARNING & SHUTDOWN Ttw Ttsd Tlow Thermal warning (Notes 6 and 7) Thermal shutdown (Note 8) Low temperature warning (Note 8) 138 145 Ttw + 10 Ttw 155 152 C C C

SUPPLY AND VOLTAGE REGULATOR VbbOTP UV1 UV2 Ibat Supply voltage for OTP zapping (Note 9) VBB Stop voltage high threshold Stop voltage low threshold Total current consumption Unloaded outputs VBB = 29 V 9.0 7.7 7.0 8.3 7.5 3.50 10.0 8.9 8.0 10.0 V V V mA

4. Tested in production for 800 mA, 400 mA, 200 mA and 100 mA current settings for both X and Y coil. 5. Not measured in production. Guaranteed by design. 6. Parameter guaranteed by trimming relevant OTPs in production test at 143C (5C) and VBB = 14 V. 7. No more than 100 cumulated hours in life time above Tw. 8. Thermal shutdown and low temperature warning are derived from thermal warning. Guaranteed by design. 9. A buffer capacitor of minimum 100 mF is needed between VBB and GND. Short connections to the power supply are recommended. 10. If input voltages < 0.3 V, than a resistor between 22 W to 100 W needs to be put in series. 11. If the I2Cbus is operated in Fast Mode VIHmin = 0.7 * VDD.

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Table 5. DC PARAMETERS
Symbol Pin(s) Parameter Test Conditions Min Typ Max Unit SUPPLY AND VOLTAGE REGULATOR VDD VddReset IddLim Regulated internal supply (Note 12) VDD Digital supply reset level @ power down (Note 13) Current limitation Pin shorted to ground VBB = 14 V 10 Switch to GND or VBB 6 Short to GND or Vbat VBB = 29 V VBB = 14 V VBB = 14 V VBB = 14 V 7 V VBB 14 V 14 V VBB 30 V External buffer capacitor CPP CPN External pump capacitor VBB + 10 220 220 0.075 * Vdd 2 * VBB 2.5 VBB + 15 470 470 20 30 2 29 45 8 V < VBB < 29 V 4.75 5 5.50 4.5 45 V V mA

SWITCH INPUT AND HARDWIRE ADDRESS INPUT Rt_OFF Rt_ON Vbb_sw Ilim_sw TEST PINS Vihigh Vilow Vihyst CHARGE PUMP Vcp VCP Cbuffer Cpump Output voltage V V nF nF TSTx Input level high Input level low Hysteresis 0.7 * Vdd 0.3 * Vdd V V V Switch OPEN resistance (Note 14) Switch ON resistance SWI HW (Note 14) VBB range for guaranteed operation of SWI and HW Current limitation kW kW V mA

PACKAGE THERMAL RESISTANCE VALUES Rthja Rthjp Rthja Rthjp SO SO NQ NQ Thermal resistance junction to ambient (2S2P) Thermal resistance junction to leads Thermal resistance junction to ambient (2S2P) Thermal resistance junction to leads and exposed pad Simulated conform JEDEC JESD51 39 19 30 0.95 K/W K/W K/W K/W

12. Pin VDD must not be used for any external supply 13. The RAM content will not be altered above this voltage. 14. External resistance value seen from pin SWI or HW, including 1 kW series resistor. For the switch OPEN, the maximum allowed leakage current is represented by a minimum resistance seen from the pin.

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AC PARAMETERS The AC parameters are guaranteed for temperature and VBB in the operating range unless otherwise specified.
Table 6. AC PARAMETERS
Symbol POWERUP Tpu fosc fSCL tHD,START tLOW tHIGH tSU,START tHD,DATA tSU,DATA tR tF tSU,STOP tBUF SDA SCK Powerup time Guaranteed by design 10 ms Pin(s) Parameter Test Conditions Min Typ Max Unit

INTERNAL OSCILLATOR Frequency of internal oscillator VBB = 14 V 3.6 4.0 4.4 MHz

I2C TRANSCEIVER (STANDARD MODE) SCL clock frequency Hold time (repeated) START condition. After this period the first clock pulse is generated. LOW period of the SCK clock HIGH period of the SCK clock Setup time for a repeated START condition Data hold time for I2C bus devices Data setup time Rise time of SDA and SCK signals Fall time of SDA and SCK signals Setup time for STOP condition Bus free time between STOP and START condition 4.0 4.7 4.0 4.7 4.0 4.7 0 (Note 16) 250 1.0 0.3 3.45 (Note 17) 100 kHz ms ms ms ms ms ns ms ms ms ms

I2C TRANSCEIVER (FAST MODE) fSCL tHD,START tLOW tHIGH tSU,START tHD,DATA tSU,DATA tR tF tSU,STOP tBUF SDA SCK SCL clock frequency Hold time (repeated) START condition. After this period the first clock pulse is generated. LOW period of the SCK clock HIGH period of the SCK clock Setup time for a repeated START condition Data hold time for Data setup time Rise time of SDA and SCK signals Fall time of SDA and SCK signals Setup time for STOP condition Bus free time between STOP and START condition I2C bus devices 0.6 1.3 0.6 0.6 0 (Note 16) 100 (Note 18) 20 + 0.1 CB 20 + 0.1 CB 0.6 1.3 300 300 0.9 (Note 17) 360 kHz ms ms ms ms ms ns ns ns ms ms

15. The maximum number of connected I2C devices is dependent on the number of available addresses and the maximum bus capacitance to still guarantee the rise and fall times of the bus signals. 16. An I2C device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. 17. The maximum tHD,DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. 18. A Fastmode I2Cbus device can be used in a standardmode I2C bus system, but the requirement tSU,DATA w 250 ns must than be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU,DATA = 1000 + 250 = 1250 ns (according to the standardmode I2Cbus specification) before the SCL line is released.

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Table 6. AC PARAMETERS
Symbol Pin(s) Parameter Test Conditions Min Typ Max Unit SWITCH INPUT AND HARDWIRE ADDRESS INPUT Tsw Tsw_on SWI HW Scan pulse period (Note 19) Scan pulse duration (Note 19) VBB = 14 V VBB = 14 V 1024 64 ms ms

MOTORDRIVER Fpwm Tbrise Tbfall Tstab CHARGE PUMP fCP CPN CPP Charge pump frequency (Note 19) VBB = 14 V 250 kHz MOTxx PWM frequency (Note 19) Turnon transient time Turnoff transient time Run current stabilization time (Note 19) Between 10% and 90% 18 20 140 130 1/Vmin 22 kHz ns ns ms

19. Derived from the internal oscillator 20. See SetMotorParam

START VIHmin VILmax tF SCK tHD,START tR tHD,DATA tSU,DATA tSU,START tSP tSU,STOP tBUF REPEATED START STOP START

SDA

tLOW

tHIGH

Figure 5. I2C Timing Diagrams

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Typical Application
VBAT C8 100 nF C7 100 mF CPN VDD 9 3 220 nF C5 C6 220 nF VBB 12 C3 100 nF VBB 19 20 1k SWI MOTXP C2 2,7 nF Connect to VBAT or GND C4 100 nF

CPP VCP 10 11

SDA I2C Bus 1k C1 2,7 nF TST2 SCK HW

1 2 8 AMIS30622

18

16 MOTXN MOTYP MOTYN M

Connect to VBAT or GND

15 13 5 4 7 14 17

6 TST1 GND

Figure 6. Typical Application Diagram for SO Device

NOTES: All resistors are 5%, 1/4 W C1, C2 minimum value is 2.7 nF, maximum value is 10 nF Depending on the application, the ESR value and working voltage of C7 must be carefully chosen C3 and C4 must be close to pins VBB and GND C5 and C6 must be as close as possible to pins CPN, CPP, VCP, and VBB to reduce EMC radiation C9 must be a ceramic capacitor to assure low ESR

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AMIS30622
POSITIONING PARAMETERS
Stepping Modes Maximum Velocity

One of four possible stepping modes can be programmed: Halfstepping 1/4 microstepping 1/8 microstepping 1/16 microstepping

For each stepping mode, the maximum velocity Vmax can be programmed to 16 possible values given in the table below. The accuracy of Vmax is derived from the internal oscillator. Under special circumstances it is possible to change the Vmax parameter while a motion is ongoing. All 16 entries for the Vmax parameter are divided into four groups. When changing Vmax during a motion the application must take care that the new Vmax parameter stays within the same group.

Table 7. MAXIMUM VELOCITY SELECTION TABLE

Vmax Index Vmax (full step/s) 99 136 167 197 213 228 243 273 303 334 364 395 456 546 729 973 D C B Halfstepping Group A (halfstep/s) 197 273 334 395 425 456 486 546 607 668 729 790 912 1091 1457 1945 Stepping Mode 1/4th Microstepping (microstep/s) 395 546 668 790 851 912 973 1091 1213 1335 1457 1579 1823 2182 2914 3891 1/8th Microstepping (microstep/s) 790 1091 1335 1579 1701 1823 1945 2182 2426 2670 2914 3159 3647 4364 5829 7782 1/16th Microstepping (microstep/s) 1579 2182 2670 3159 3403 3647 3891 4364 4852 5341 5829 6317 7294 8728 11658 15564

Hex 0 1 2 3 4 5 6 7 8 9 A B C D E F

Dec 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

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Minimum Velocity

Once the maximum velocity is chosen, 16 possible values can be programmed for the minimum velocity Vmin. The table below provides the obtainable values in fullstep/s. The accuracy of Vmin is derived from the internal oscillator.
Table 8. OBTAINABLE VALUES IN FULLSTEP/s FOR THE MINIMUM VELOCITY
Vmax (Fullstep/s) Vmin Index Hex 0 1 2 3 4 5 6 7 8 9 A B C D E F Vmax Dec Factor 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 1/32 2/32 3/32 4/32 5/32 6/32 7/32 8/32 9/32 10/32 11/32 12/32 13/32 14/32 15/32 A 99 99 3 6 9 12 15 18 21 24 28 31 34 37 40 43 46 136 136 4 8 12 16 21 25 30 33 38 42 47 51 55 59 64 167 167 5 10 15 20 26 31 36 41 47 51 57 62 68 72 78 197 197 6 11 18 24 31 36 43 49 55 61 68 73 80 86 93 B 213 213 6 12 19 26 32 39 46 52 59 66 72 79 86 93 99 228 228 7 13 21 28 35 42 50 56 64 71 78 85 93 99 107 243 243 7 14 22 30 37 45 52 60 68 75 83 91 98 106 113 273 273 8 15 25 32 42 50 59 67 76 84 93 101 111 118 128 303 303 8 17 27 36 46 55 65 74 84 93 103 113 122 132 141 334 334 10 19 31 40 51 61 72 82 93 103 114 124 135 145 156 C 364 364 10 21 32 44 55 67 78 90 101 113 124 135 147 158 170 395 395 11 23 36 48 61 72 86 97 111 122 135 147 160 172 185 456 456 13 27 42 55 71 84 99 113 128 141 156 170 185 198 214 546 546 15 31 50 65 84 99 118 134 153 168 187 202 221 237 256 D 729 729 19 42 65 88 111 134 156 179 202 225 248 271 294 317 340 973 973 27 57 88 118 149 179 210 240 271 301 332 362 393 423 454

NOTES: The Vmax factor is an approximation. In case of motion without acceleration (AccShape = 1) the length of the steps = 1/Vmin. In case of accelerated motion (AccShape = 0) the length of the first step is shorter than 1/Vmin depending of Vmin, Vmax and Acc.

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Acceleration and Deceleration

Sixteen possible values can be programmed for Acc (acceleration and deceleration between Vmin and Vmax). The table below provides the obtainable values in fullstep/s2. One observes restrictions for some
Vmax (FS/s) " O Acc Index Hex 0 1 2 3 4 5 6 7 8 9 A B C D E F Dec 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 29570 14785 49 99 136 167 197 213 228

combinations of acceleration index and maximum speed (gray cells). The accuracy of Acc is derived from the internal oscillator.
243 273 303 334 364 395 456 546 729 973

Table 9. ACCELERATION AND DECELERATION SELECTION TABLE

Acceleration (Fullstep/s2) 106 218 1004 3609 6228 8848 11409 13970 16531 19092 21886 24447 27008 29570 34925 40047 473 735

The formula to compute the number of equivalent fullsteps during acceleration phase is:
Nstep + Vmax 2 2 * Acc Vmin 2

Positioning

The position programmed in command SetPosition is given as a number of (micro)steps. According to the chosen stepping mode, the position words must be aligned as described in the table below. When using command GotoSecurePosition, data is automatically aligned.

Table 10. POSITION WORD ALIGNMENT

Stepping Mode 1/16th 1/8th 1/4th Halfstepping SecurePosition S S S S S Position Word: Pos[15:0] B14 B13 B12 B11 B10 B13 B12 B11 B12 B11 B10 B11 B10 B9 B8 B9 B7 B10 B9 B8 B6 B9 B8 B7 B5 B9 B8 B7 B6 B4 B8 B7 B6 B5 B3 B7 B6 B5 B4 B2 B6 B5 B4 B3 B1 B5 B4 B3 B2 LSB B4 B3 B2 B1 0 B3 B2 B1 LSB 0 B2 B1 LSB 0 0 B1 LSB 0 0 0 LSB 0 0 0 0 Shift No shift 1bit left 2 2bit left 4 3bit left 8 No shift

NOTES: LSB: Least Significant Bit S: Sign bit

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Position Ranges

A position is coded by using the binary twos complement format. According to the positioning commands used and to the chosen stepping mode, the position range will be as shown in the following table.
Table 11. POSITION RANGE
Command Stepping Mode Halfstepping SetPosition 1/4th 1/8th microstepping microstepping microstepping Position Range 4096 to +4095 8192 to +8191 16384 to +16383 32768 to +32767 Full Range Excursion 8192 halfsteps 16384 microsteps 32768 microsteps 65536 microsteps Number of Bits 13 14 15 16

1/16th

When using the command SetPosition, although coded on 16 bits, the position word will have to be shifted to the left by a certain number of bits, according to the stepping mode.
Table 12. SECURE POSITION
Stepping Mode Halfstepping 1/4th microstepping

Secure Position

A secure position can be programmed. It is coded in 11bits, thus having a lower resolution than normal positions, as shown in the following table. See also command GotoSecurePosition.

Secure Position Resolution 4 halfsteps 8 microsteps (1/4th) 16 microsteps (1/8th) 32 microsteps (1/16th)

1/8th microstepping 1/16th microstepping

Important
NOTES: The secure position is disabled in case the programmed value is the reserved code 10000000000 (0x400 or most negative position). The resolution of the secure position is limited to 9 bit at startup. The OTP register is copied in RAM as illustrated below. The RAM bits SecPos1 and SecPos0 are set to 0. SecPos10 SecPos9 SecPos8 SecPos2 SecPos1 SecPos0 RAM

SecPos10

SecPos9

SecPos8

SecPos2

OTP

Shaft

A shaft bit, which can be programmed in OTP or with command SetMotorParam, defines whether a positive motion is a clockwise (CW) or counterclockwise rotation (CCW) (an outer or an inner motion for linear actuators):

Shaft = 0 MOTXP is used as positive pin of the X

coil, while MOTXN is the negative one. Shaft = 1 opposite situation

STRUCTURAL DESCRIPTION See also the Block Diagram in Figure 1.

Stepper Motordriver

The control block for the Hbridges, including the

The Motordriver receives the control signals from the control logic. The main features are: Two Hbridges, designed to drive a stepper motor with two separated coils. Each coil (X and Y) is driven by one Hbridge, and the driver controls the currents flowing through the coils. The rotational position of the rotor, in unloaded condition, is defined by the ratio of current flowing in X and Y. The torque of the stepper motor when unloaded is controlled by the magnitude of the currents in X and Y.

PWM control, the synchronous rectification and the internal current sensing circuitry. The charge pump to allow driving of the Hbridges high side transistors. Two prescale 4bit DACs to set the maximum magnitude of the current through X and Y. Two DACs to set the correct current ratio through X and Y. Battery voltage monitoring is also performed by this block, which provides the required information to the control logic part. The same applies for detection and

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reporting of an electrical problem that could occur on the coils or the charge pump.
Control Logic (Position Controller and Main Control) Miscellaneous

An internal oscillator, needed for the control logic

The AMIS30622 also contains the following:

The control logic block stores the information provided by the I2C interface (in a RAM or an OTP memory) and digitally controls the positioning of the stepper motor in terms of speed and acceleration, by feeding the right signals to the motordriver state machine. It will take into account the successive positioning commands to properly initiate or stop the stepper motor in order to reach the set point in a minimum time. It also receives feedback from the motordriver part in order to manage possible problems and decide on internal actions and reporting to the I2C interface.

handler as well as the control logic and the PWM control of the motordriver. An internal trimmed voltage source for precise referencing. A protection block featuring a thermal shutdown and a poweronreset circuit. A 5 V regulator (from the battery supply) to supply the internal logic circuitry.

FUNCTIONS DESCRIPTION This chapter describes the following functional blocks in more detail: Position controller Main control and register, OTP memory + ROM Motordriver Position Controller
Positioning and Motion Control

Zero Speed Hold Current

Pmin

A positioning command will produce a motion as illustrated in Figure 7. A motion starts with an acceleration phase from minimum velocity (Vmin) to maximum velocity (Vmax) and ends with a symmetrical deceleration. This is defined by the control logic according to the position required by the application and the parameters programmed by the application during the configuration phase. The current in the coils is also programmable.
Velocity Deceleration range

Acceleration range

Vmax

Vmin Pstart P=0 Pstop

Figure 7. Positioning and Motion Control

Pmax

Zero Speed Hold Current

Position

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Table 13. POSITION RELATED PARAMETERS
Parameter Pmax Pmin Zero Speed Hold Current Maximum Current Acceleration and Deceleration Vmin Vmax See Positioning See Ihold See Irun See Acceleration and Deceleration See Minimum Velocity See Maximum Velocity Reference

Different positioning examples are shown in the table below.

Table 14. POSITIONING EXAMPLES
Short motion. Velocity

time New positioning command in same direction, shorter or longer, while a motion is running at maximum velocity. Velocity

time New positioning command in same direction while in deceleration phase (Note 21) Note: there is no wait time between the deceleration phase and the new acceleration phase. New positioning command in reverse direction while motion is running at maximum velocity. Velocity

time

Velocity

time

New positioning command in reverse direction while in deceleration phase.

Velocity

time

New velocity programming while motion is running.

Velocity

time 21. Reaching the end position is always guaranteed, however velocity rounding errors might occur after consecutive accelerations during a deceleration phase. The velocity rounding error will be removed at Vmin (e.g. at end of acceleration or when AccShape=1).

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Dual Positioning

A SetDualPosition command allows the user to perform a positioning using two different velocities. The first motion is done with the specified Vmin and Vmax velocities in the SetDualPosition command, with the acceleration (deceleration) parameter already in RAM, to a position Pos1[15:0] also specified in SetDualPosition. Then a second motion to a physical position Pos2[15:0] is done at the specified Vmin velocity in the

SetDualPosition command (no acceleration). Once the second motion is achieved, the ActPos register is reset to zero, whereas TagPos register is not changed. When the Secure position is enabled, after the dual positioning, the secure positioning is executed. The figure below gives a detailed overview of the dual positioning function. After the dual positioning is executed an internal flag is set to indicate the AMIS30622 is referenced.
A new motion will start here Depends on AccShape

Vmax Profile: Vmin first movement 27 ms 0 00 During one Vmin time the ActPos is 100 Position: xx 0 second movement 00 5 steps 100 101 104 105 105 0 Secure positioning (if enabled) 00

27 ms 0

Motion status:

60

Pos: xx Assume: First Position = 100 Second Position = 105 Secure Position = 60

ActPos: 100 ActPos: 100

ActPos:0

ActPos: 60

ResetPos

Figure 8. Dual Positioning

Remark: This operation cannot be interrupted or influenced by any further command unless the occurrence of the conditions driving to a motor shutdown or by a HardStop command. Sending a SetDualPosition command while a motion is already ongoing is not recommended.
22. The priority encoder is describing the management of states and commands. 23. A DualPosition sequence starts by setting TagPos buffer register to SecPos value, provided secure position is enabled otherwise TagPos is reset to zero. If a SetPosition(Short) command is issued during a DualPosition sequence, it will be kept in the position buffer memory and executed afterwards. This applies also for the command GotoSecurePosition . 24. Commands such as GetFullStatus1 or GetFullStatus2 will be executed while a Dual Positioning is running. 25. The Pos1, Pos2, Vmax and Vmin values programmed in a SetDualPosition command apply only for this sequence. All other motion parameters are used from the RAM registers (programmed for instance by a former SetMotorParam command). After the DualPosition motion is completed, the former Vmin and Vmax become active again. 26. Commands ResetPosition, SetDualPosition, and SoftStop will be ignored while a DualPosition sequence is ongoing, and will not be executed afterwards. 27. Recommendation: a SetMotorParam command should not be sent during a SetDualPosition sequence: all the motion parameters defined in the command, except Vmin and Vmax, become active immediately.

Position Periodicity

Depending on the stepping mode the position can range from 4096 to +4095 in halfstep to 32768 to +32767 in 1/16th microstepping mode. One can project all these positions lying on a circle. When executing the command SetPosition, the position controller will set the movement direction in such a way that the traveled distance is minimal.

The figure below illustrates that the moving direction going from ActPos = +30000 to TagPos = 30000 is clockwise. If a counter clockwise motion is required in this example, several consecutive SetPosition commands can be used.

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+10000 +20000 ActPos = +30000 0 Motion direction TagPos = 30000 10000 20000

Hardwired Address HW

Figure 9. Motion Direction is Function of Difference between ActPos and TagPos

In the drawing below, a simplified schematic diagram is shown of the HW comparator circuit. The HW pin is sensed via 2 switches. The DriveHS and DriveLS control lines are alternatively closing the top and bottom switch connecting HW pin with a current to resistor converter. Closing STOP (DriveHS = 1) will sense a current to GND. In that case the top I R converter output is low, via the closed passing switch SPASS_T this signal is fed to the R comparator which output HW_Cmp is high. Closing bottom switch SBOT (DriveLS = 1) will sense a current to VBAT. The corresponding I R converter output is low and via SPASS_B fed to the comparator. The output HW_Cmp will be high.

SPASS_T I/R

State STOP HW SBOT DriveHS LOGIC DriveLS High Low Float

1k

2 1 = R2GND 2 = R2VBAT 3 = OPEN

3 I/R SPASS_B

RComp Debouncer COMP Rth 32 ms

HW_Cmp

Figure 10. Simplified Schematic Diagram of the HW Comparator

3 cases can be distinguished (see also Figure 10 above): HW is connected to ground: R2GND or drawing 1 HW is connected to VBAT: R2VBAT or drawing 2 HW is floating: OPEN or drawing 3

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Table 15. STATE DIAGRAM OF THE HW COMPARATOR
Previous State Float Float Float Float Low Low Low Low High High High High DriveLS 1 1 0 0 1 1 0 0 1 1 0 0 DriveHS 0 0 1 1 0 0 1 1 0 0 1 1 HW_Cmp 0 1 0 1 0 1 0 1 0 1 0 1 New State Float High Float Low Low High Float Low Float High High Low Condition R2GND or OPEN R2VBAT R2VBAT or OPEN R2GND R2GND or OPEN R2VBAT R2VBAT or OPEN R2GND R2GND or OPEN R2VBAT R2VBAT or OPEN R2GND Drawing 1 or 3 2 2 or 3 1 1 or 3 2 2 or 3 1 1 or 3 2 2 or 3 1

The logic is controlling the correct sequence in closing the switches and in interpreting the 32 ms debounced HW_Cmp output accordingly. The output of this small statemachine is corresponding to: High or address = 1 Low or address = 0 Floating

As illustrated in the table above (Table 15), the state is depending on the previous state, the condition of the 2 switch controls (DriveLS and DriveHS) and the output of HW_Cmp. Figure 11 shows an example of a practical case where a connection to VBAT is interrupted.

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Condition R2 VBAT DriveLS Tsw = 1024 ms OPEN R2 VBAT R2 GND t

t DriveHS Tsw_on = 64 ms

t RComp Rth

t HW_Cmp

t State Float Float High High Low

Figure 11. Timing Diagram Showing the Change in States for HW Comparator R2VBAT

A resistor is connected between VBAT and HW. Every 1024 ms SBOT is closed and a current is sensed. The output of the I R converter is low and the HW_Cmp output is high. Assuming the previous state was floating, the internal logic will interpret this as a change of state and the new state will be high (see also Table 15). The next time SBOT is closed the same conditions are observed. The previous state was high so based on Table 15 the new state remains unchanged. This high state will be interpreted as HW address = 1.
OPEN

a motion to secure position after a debounce time of 64 ms, which prevents false triggering in case of micro interruptions of the power supply.
R2GND

If a resistor is connected between HW and the GND, a current is sensed every 1024 ms when STOP is closed. The output of the top I R converter is low and as a result the HW_Cmp output switches to high. Again based on the stated diagram in Table 15 one can see that the state will change to Low. This low state will be interpreted as HW address = 0.
External Switch SWI

In case the HW connection is lost (broken wire, bad contact in connector) the next time SBOT is closed, this will be sensed. There will be no current, the output of the corresponding I R converter is high and the HW_Cmp will be low. The previous state was high. Based in Table 15 one can see that the state changes to float. This will trigger

As illustrated in Figure 12 the SWI comparator is almost identical to HW. The major difference is in the limited number of states. Only open or closed is recognized leading to respectively ESW = 0 and ESW = 1.

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SPASS_T I/R

State STOP 1k SWI SBOT LOGIC DriveLS Open DriveHS Closed

2 1 = R2GND 2 = R2VBAT 3 = OPEN

3 I/R SPASS_B

RComp COMP 32 ms Debouncer SWI_Cmp

Rth

Figure 12. Simplified Schematic Diagram of the SWI Comparator

As illustrated in the drawing above, a change in state is always synchronized with DriveHS or DriveLS. The same synchronization is valid for updating the internal position register. This means that after every current pulse (or closing of STOP or SBOT) the state of the position switch together with the corresponding position is memorized.
Table 16. GetFullStatus1 I2C COMMAND

The FullStatus1 command reads back the <ActPos> register and the status of ESW. In this way the master node may get synchronous information about the state of the switch together with the position of the motor. See Table 16 below.

GetFullStatus1 Response Frame Structure Byte 0 1 2 3 4 5 6 7 8 Content Address Address Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 1 1 AccShape VddReset Bit 7 1 1 Bit 6 1 1 Irun[3:0] Vmax[3:0] StepMode[1:0] StepLoss Motion[2:0] 1 1 1 1 ElDef Shaft UV2 ESW 1 1 TSD OVC1 1 1 TW OVC2 1 1 1 1 1 Bit 5 OTP3 1 Bit 4 OTP2 OTP3 Bit 3 OTP1 OTP2 Bit 2 OTP0 OTP1 Bit 1 HW OTP0 Bit 0 1 HW

Ihold[3:0] Vmin[3:0] Acc[3:0] Tinfo[1:0] CPFail 1 1

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DriveHS Tsw = 1024 ms 512 ms

Tsw_on = 64 ms DriveLS

t RComp Rth

t SWI_Cmp 60 ms

t ESW 0 1 1 1 t ActPos + 1 ActPos + 2 ActPos + 3 ActPos ActPos

Figure 13. Simplified Timing Diagram Showing the Change in States for SWI Comparator

Main Control and Register, OTP memory + ROM

Powerup Phase

Powerup phase of the AMIS30622 will not exceed 10 ms. After this phase, the AMIS30622 is in standby mode, ready to receive I2C messages and execute the associated commands. After powerup, the registers and flags are in the reset state, while some of them are being loaded with the OTP memory content (see Table 19: RAM Registers).
Reset

level), the Hbridges will be in highimpedance mode, and the registers and flags will be in a predetermined position. This is documented in Table 19: RAM Registers and Table 20: Flags Table.
Softstop

After powerup, or after a reset occurrence (e.g. a microcut on pin VBB has made VDD to go below VddReset

A softstop is an immediate interruption of a motion, but with a deceleration phase. At the end of this action, the register <TagPos> is loaded with the value contained in register <ActPos>, see Table 19: Ram Registers). The circuit is then ready to execute a new positioning command, provided thermal and electrical conditions allow for it.

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Thermal Shutdown Mode

When thermal shutdown occurs, the circuit performs a <SoftStop> command and goes to motor shutdown mode (see Figure 14: State Diagram Temperature Management).
Temperature Management

diagram and illustration of Figure 14: State Diagram Temperature Management below. The only condition to reset flags <TW> and <TSD> (respectively thermal warning and thermal shutdown) is to be at a temperature lower than Ttw and to get the occurrence of a GetFullStatus1 I2C frame.

The AMIS30622 monitors temperature by means of two thresholds and one shutdown level, as illustrated in the state
Normal Temp. <Tinfo> = 00 <TW> = 0 <TSD> = 0 T > Ttw Thermal warning <Tinfo> = 10 <TW> = 1 <TSD> = 0 T > Ttsd Thermal shutdown <Tinfo > = 11 <TW> = 1 <TSD> = 1 SoftStop if motion ongoing Motor shutdown (motion disabled)

T < Ttw & T > Ttw I2C Frame: GetFullStatus1

T < Ttw

Post thermal warning <Tinfo> = 00 <TW> = 1 <TSD> = 0 T < Ttw T > Tlow Low Temp. <Tinfo> = 01 <TW> = 0 <TSD> = 0 Post thermal shutdown 2 <Tinfo> = 00 <TW> = 1 <TSD> = 1 Motor shutdown (motion disabled)

T > Ttsd

T < Ttsd

T < Tlow

Post thermal shutdown 1 <Tinfo > = 10 <TW> = 1 <TSD> = 1 Motor shutdown (motion disabled)

T > Ttw

Figure 14. State Diagram Temperature Management

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T shutdown level T

T warning level

t T <tw> bit
T < Ttw and getfullstatus1

T <tsd> bit

T > Ttsd, motor stops and shutdown

T < Ttw and getfullstatus1

Figure 15. Illustration of Thermal Management Situation Battery Voltage Management

The AMIS30622 monitors the battery voltage by means of one threshold and one shutdown level. The only condition

to reset flags <UV2> and <StepLoss> is to recover by a battery voltage higher than UV1 and to receive a GetFullStatus1 command.

<UV2> = 0 <Steploss> = 0

NORMAL VOLTAGE

VBB > UV1 VBB > UV1 & LIN Frame & LIN Frame <GetFullStatus> or <GetFullStatus> or <GetStatus <GetStatus> VBB < UV2 VBB < UV2 No Motion & Motion Ongoing STOP MODE 1 STOP MODE 2

<UV2> = 1 <Steploss> = 0 Motor Shutdown

<UV2> = 1 <Steploss> = 1 HardStop Motor Shutdown

Figure 16. State Diagram Battery Voltage Management

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In Stop mode 1 the motor is put in shutdown state. The <UV2> flag is set. In case VBB > UV1, AMIS30622 accepts updates of the target position by means of the reception of SetPosition or GotoSecurePosition commands, only AFTER the <UV2> flag is cleared by receiving a GetFullStatus1 or GetFullStatus2 command. In Stop mode 2 the motor is stopped immediately and put in shutdown state. The <UV2> and <Steploss> flags are set. In case VBB > UV1, AMIS30622 accepts updates of the target position by means of the reception of SetPosition or GotoSecurePosition commands, only AFTER the <UV2> and <Steploss> flags are cleared by receiving a GetFullStatus1 or GetFullStatus2 command. OTP Register
OTP Memory Structure Important Notes:

In the case of Stop mode 2, care needs to be taken

because the accumulated steploss can cause a significant deviation between physical and stored actual position. The SetDualPosition command will only be executed after clearing the <UV2> and <Steploss> flags. RAM reset occurs when VDD < VDDReset (digital POR level).

The table below shows how the parameters to be stored in the OTP memory are located.
Table 17. OTP MEMORY STRUCTURE
Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 Irun3 Vmax3 SecPos10 SecPos7 Irun2 Vmax2 SecPos9 SecPos6 Irun1 Vmax1 SecPos8 SecPos5 Irun0 Vmax0 Shaft SecPos4 Bit 7 OSC3 0 Bit 6 OSC2 TSD2 Bit 5 OSC1 TSD1 Bit 4 OSC0 TSD0 Bit 3 IREF3 BG3 PA3 Ihold3 Vmin3 Acc3 SecPos3 StepMode1 Bit 2 IREF2 BG2 PA2 Ihold2 Vmin2 Acc2 SecPos2 StepMode0 Bit 1 IREF1 BG1 PA1 Ihold1 Vmin1 Acc1 SecPos1 LOCKBT Bit 0 IREF0 BG0 PA0 Ihold0 Vmin0 Acc0 SecPos0 LOCKBG

Parameters stored at address 0x00 and 0x01 and bit <LOCKBT> are already programmed in the OTP memory at circuit delivery. They correspond to the calibration of the circuit and are just documented here as an indication. Each OTP bit is at 0 when not zapped. Zapping a bit will set it to 1. Thus only bits having to be at 1 must be zapped. Zapping of a bit already at 1 is disabled. Each OTP byte will be programmed separately (see command SetOTPparam). Once OTP programming is completed, bit <LOCKBG> can be zapped to disable future zapping, otherwise any OTP bit at 0 could still be zapped by using a SetOTPparam command.
Table 18. OTP OVERWRITE PROTECTION
Lock Bit LOCKBT (factory zapped before delivery) LOCKBG Protected Bytes 0x00 to 0x01 0x00 to 0x07

programming is SetMotorParam. This allows for a functional verification before using a SetOTPparam command to program and zap separately one OTP memory byte. A GetOTPparam command issued after each SetOTPparam command allows verifying the correct byte zapping. Note: Zapped bits will become active only after a power cycle. After programming the I2C bits the power cycle has to be performed first to guarantee further communication with the device.
Application Parameters Stored in OTP Memory

The command used to load the application parameters via the I2C bus in the RAM prior to an OTP Memory

Except for the physical address <PA[3:0]> these parameters, although programmed in a nonvolatile memory can still be overridden in RAM by a I2C writing operation. PA[3:0] In combination with hired wired (HW) address, it forms the physical address AD[6:0] of the steppermotor. Up to 32 stepper motors can theoretically be connected to the same I2C bus.

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Irun[3:0] Current amplitude value to be fed to each coil of the steppermotor. The table below provides the 16 possible values for <IRUN>.
Index 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Irun 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Run Current (mA) 59 71 84 100 119 141 168 200 238 283 336 400 476 566 673 800

Ihold[3:0] Hold current for each coil of the steppermotor. The table below provides the 16 possible values for <IHOLD>.
Index 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Ihold 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Hold Current (mA) 59 71 84 100 119 141 168 200 238 283 336 400 476 566 673 800

Note: When the motor is stopped, the current is reduced from <IRUN> to <IHOLD>. StepMode Setting of step modes.
StepMode 0 0 1 1 0 1 0 1 Step Mode 1/2 stepping 1/4 stepping 1/8 stepping 1/16 stepping

Shaft This bit distinguishes between a clockwise or counterclockwise rotation. The shaft bit is not working in RunVelocity mode. SecPos[10:0] Secure Position of the steppermotor. This is the position to which the motor is driven in case of a HW pin connection is lost. If <SecPos[10:0]> = 100 000000 00, secure positioning is disabled; the steppermotor will be kept in the position occupied at the moment these events occur.

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Note: The Secure Position is coded on 11 bits only, providing actually the most significant bits of the position, the non coded least significant bits being set to 0. Vmax[3:0] Maximum velocity
Index 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Vmax 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Vmax(full step/s) 99 136 167 197 213 228 243 273 303 334 364 395 456 546 729 973 D C B Group A

Acc[3:0] Acceleration and deceleration between Vmax and Vmin.

Index 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Acc 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Acceleration (Fullstep/s2) 49 218 1004 3609 6228 8848 11409 13970 16531 19092 21886 24447 27008 29570 34925 40047 (*) (*) . . . . . . . (*) (*) (*) (*) (*) (*) (*)

(*) restriction on speed

Vmin[3:0] Minimum velocity.

Index 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Vmin 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Vmax Factor 1 1/32 2/32 3/32 4/32 5/32 6/32 7/32 8/32 9/32 10/32 11/32 12/32 13/32 14/32 15/32

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Table 19. RAM REGISTERS
Register Actual position Mnemonic ActPos Length (bit) 16 Related Commands Comment 16bit signed Reset State

GetFullStatus2 GotoSecurePos ResetPosition GetFullStatus2 GotoSecurePos ResetPosition SetPosition GetFullStatus1 SetMotorParam ResetToDefault GetFullStatus1 SetMotorParam ResetToDefault GetFullStatus1 SetMotorParam ResetToDefault GetFullStatus1 SetMotorParam ResetToDefault GetFullStatus1 SetMotorParam ResetToDefault GetFullStatus1 SetMotorParam ResetToDefault GetFullStatus1 SetMotorParam ResetToDefault GetFullStatus2 SetMotorParam ResetToDefault GetFullStatus1 SetStallParam ResetToDefault

Last programmed Position

Pos/TagPos

16/11

16bit signed or 11bit signed for half stepping (see Positioning) 0 normal acceleration from Vmin to Vmax 1 motion at Vmin without acceleration Operating current See lookup table Irun Standstill current See lookup table Ihold See Section Minimum Velocity See lookup table Vmin See Section Maximum Velocity See lookup table Vmax Direction of movement From OTP memory 0

Acceleration shape

AccShape

Coil peak current

Irun

Coil hold current

Ihold

Minimum Velocity

Vmin

Maximum Velocity

Vmax

Shaft

Shaft

Acceleration/ deceleration Secure Position

Acc

See Section Acceleration See lookup table Acc Target position when HW connection fails; 11 MSBs of 16bit position (LSBs fixed to 0) See Section Stepping Modes See lookup table StepMode

SecPos

11

Stepping mode

StepMode

28. A ResetToDefault command will act as a reset of the RAM content, except for ActPos and TagPos, which are registers that are not modified. Therefore, the application should not send a ResetToDefault during a motion, to avoid any unwanted change of parameter.

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Table 20. FLAGS TABLE
Flag Charge pump failure Mnemonic CPFail Length (bit) 1 Related Commands Comment 0 = charge pump OK 1 = charge pump failure Resets only after GetFullStatus1 <OVC1> or <OVC2> or openload on coil X or openload on coil XY or <CPFail> Resets only after GetFullStatus1 0 = open 1 = close <CPFail> or <UV2> or <ElDef> or <VDDreset> x00 = Stop 001 = inner (CCW) motion acceleration 010 = inner (CCW) motion deceleration 011 = inner (CCW) motion max. speed 101 = outer (CW) motion acceleration 110 = outer (CW) motion deceleration 111 = outer (CW) motion max. speed 1 = over current; reset only after GetFullStatus1 1 = over current; reset only after GetFullStatus1 0 if <SecPos> = 100 0000 0000 1 otherwise 1 = step loss due to under voltage, over current, open circuit or stall; Resets only after GetFullStatus1 Reset State 0

GetFullStatus1

Electrical defect

ElDef

GetFullStatus1

External switch status Electrical flag Motion status

ESW HS Motion

1 1 3

GetFullStatus1
Internal use

0 0

GetFullStatus1

000

Over current in coil X Over current in coil Y Secure position enabled Step loss

OVC1 OVC2 SecEn StepLoss

1 1 1 1

GetFullStatus1 GetFullStatus1
Internal use

0 0 n.a. 1

GetFullStatus1

Motor stop Temperature info

Stop Tinfo

1 2

Internal use

0 00 = normal temperature range 01 = low temperature warning 10 = high temperature warning 11 = motor shutdown 1 = shutdown (Tj > Ttsd) Resets only after GetFullStatus 1 and if <Tinfo> = 00 1 = over temperature (Tj > Ttw) Resets only after GetFullStatus 1 and if <Tinfo> = 00 0 = VBB > UV2 1 = VBB UV2 Resets only after GetFullStatus1 Set at 1 after powerup of the circuit. If this was due to a supply microcut, it warns that the RAM contents may have been lost; can be reset to 0 with a Get(Full)Status1 command 00

GetFullStatus1

Thermal shutdown

TSD

GetFullStatus1

Thermal warning

TW

GetFullStatus1

Battery stop voltage

UV2

GetFullStatus1

Digital supply reset

VddReset

GetActualPos GetStatus GetFullStatus1

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Priority Encoder

The table below describes the simplified state management performed by the main control block.
Table 21. PRIORITY ENCODER
State " Command O GetOTPparam Standby Stopped Motor Stopped, Ihold in Coils OTP refresh; I2C slave response I2C slave response GotoPos Motor Motion Ongoing OTP refresh; I2C slave response I2C slave response DualPosition No Influence on RAM and TagPos OTP refresh; I2C slave response I2C slave response SoftStop Motor Decelerating OTP refresh; I2C slave response I2C slave response HardStop Motor Forced to Stop OTP refresh; I2C slave response I2C slave response ShutDown Motor Stopped, Hbridges in HiZ OTP refresh; I2C slave response I2C slave response; if (<TSD> or <ElFlag> = 0 then Stopped I2C slave response OTP refresh; OTP to RAM; AccShape reset RAM update RAM update RAM update HardUnder ShutUnder

GetFullStatus1 [attempt to clear all flags] (Note 29) GetFullStatus2 ResetToDefault [ ActPos and TagPos are not altered ] SetMotorParam [Master takes care about proper update] ResetPosition RAM update

I2C slave response OTP refresh; OTP to RAM; AccShape reset RAM update

I2C slave response OTP refresh; OTP to RAM; AccShape reset RAM update

I2C slave response OTP refresh; OTP to RAM; AccShape reset (Note 31) RAM update

I2C slave response OTP refresh; OTP to RAM; AccShape reset RAM update

I2C slave response OTP refresh; OTP to RAM; AccShape reset RAM update

<TagPos> and <ActPos> reset <TagPos> updated; GotoPos If <SecEn> = 1 then <TagPos> = <SecPos>; GotoPos DualPosition SoftStop HardStop HardUnder Shutdown Shutdown HardUnder HardStop; <StepLoss> = 1 SoftStop HardStop HardStop HardStop; <StepLoss> = 1 SoftStop HardStop HardUnder HardStop; <StepLoss> = 1 <TagPos> updated <TagPos> updated

<TagPos> and <ActPos> reset

<TagPos> and <ActPos> reset

SetPosition

GotoSecPosition

If <SecEn> = 1 If <SecEn> = 1 then <TagPos> = then <TagPos> = <SecPos> <SecPos>

DualPosition SoftStop HardStop VBB < UV2 <ElDef> = 1 <HS> = 1 Thermal shutdown [<TSD> = 1] Motion finished

Shutdown Shutdown

n.a.

Stopped

Stopped

Stopped; <TagPos> = <ActPos>

Stopped; <TagPos> = <ActPos>

n.a.

With the Following Color Code:

Command Ignored NOTE: Transition to Another State Master is responsible for proper update (see Note 34)

See table notes on the following page.

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29. <ElFlag> = <CPFail> or <UV2> or <ElDef> or <VDDreset> 30. After poweronreset, the <Standby> state is entered. 31. A DualPosition sequence runs with a separate set of RAM registers. The parameters that are not specified in a DualPosition command are loaded with the values stored in RAM at the moment the DualPosition sequence starts. <AccShape> is forced to 1 during second motion. <AccShape> at 0 will be taken into account after the DualPosition sequence. A GetFullStatus1 command will return the default parameters for <Vmax> and <Vmin> stored in RAM. 32. Shutdown state can be left only when <TSD> and <HS> flags are reset. 33. Flags can be reset only after the master could read them via a GetFullStatus1 command, and provided the physical conditions allow for it (normal temperature, correct battery voltage and no electrical or charge pump defect). 34. A SetMotorParam command sent while a motion is ongoing (state <GotoPos>) should not attempt to modify <Acc> and <Vmin> values. This can be done during a DualPosition sequence since this motion uses its own parameters, the new parameters will be taken into account at the next SetPosition command. 35. <SecEn> = 1 when register <SecPos> is loaded with a value different from the most negative value (i.e. different from 0x400 = 100 0000 0000). 36. <Stop> flag allows distinguishing whether state <Stopped> was entered after HardStop/SoftStop or not. <Stop> is set to 1 when leaving state <HardStop> or <SoftStop> and is reset during first clock edge occurring in state <Stopped>. 37. While in state <Stopped>, if <ActPos> <TagPos> there is a transition to state <GotoPos>. This transition has the lowest priority, meaning that <Stop>, <TSD>, etceteras are first evaluated for possible transitions. 38. If <StepLoss> is active, then SetPosition and GotoSecurePosition commands are not ignored. <StepLoss> can only be cleared by a GetFullStatus1 command.

POR

Referencing

Thermal Shutdown HardStop HardStop

Softstop

Dual Positioning Motion finished

HardStop Motion Finished GotoSecPos HardStop

Thermal ShutDown SoftStop

HardStop Thermal Shutdown Shutdown GetFullStatus1 Stopped

SetPosition Motion Finished

GotoPos

Motion Finished Priorities 1 2 3 4 Vbb < UV2 or CPFAIL HardStop Vbb < UV2 or CPFAIL

Figure 17. Simplified State Diagram

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Motordriver
Current Waveforms in the Coils

Figure 18 below illustrates the current fed to the motor coils by the motordriver in halfstep mode.
Ix Iy Coil X

t Coil Y

Figure 18. Current Waveforms in Motor Coils X and Y in Halfstep Mode

Whereas Figure 19 below shows the current fed to the coils in 1/16th micro stepping (1 electrical period).
Coil X Iy

Ix

t Coil Y

Figure 19. Current Waveforms in Motor Coils X and Y in 1/16th MicroStep Mode PWM Regulation

In order to force a given current (determined by <Irun> or <Ihold> and the current position of the rotor) through the motor coil while ensuring high energy transfer efficiency, a regulation based on PWM principle is used. The

regulation loop performs a comparison of the sensed output current to an internal reference, and features a digital regulation generating the PWM signal that drives the output switches. The zoom over one microstep in the Figure 19 above shows how the PWM circuit performs this regulation.

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Motor Starting Phase Motor Stopping Phase

At motion start, the currents in the coils are directly switched from <Ihold> to <Irun> with a new sine/cosine ratio corresponding to the first half (or micro) step of the motion.

At the end of the deceleration phase, the currents are maintained in the coils at their actual DC level (hence keeping the sine/cosine ratio between coils) during the stabilization time tstab (see AC Table). The currents are then set to the hold values, respectively Ihold x sin(TagPos) and Ihold x cos(TagPos), as illustrated below. A new positioning order can then be executed.

Iy

Ix

Figure 20. Motor Stopping Phase Charge Pump Monitoring

t stab

Motor Shutdown Mode

If the charge pump voltage is not sufficient for driving the high side transistors (due to failure), an internal HardStop command is issued. This is acknowledged to the master by raising flag <CPFail> (available with command GetFullStatus1). In case this failure occurs while a motion is ongoing, the flag <StepLoss> is also raised.
Electrical Defect on Coils, Detection and Confirmation

The principle relies on the detection of a voltage drop on at least one transistor of the Hbridge. Then the decision is taken to open the transistors of the defective bridge. This allows the detection the following short circuits: External coil short circuit Short between one terminal of the coil and Vbat or GND One cannot detect an internal short in the motor. Open circuits are detected by 100% PWM duty cycle value during one electrical period with duration, determined by Vmin.
Table 22. ELECTRICAL DEFECT DETECTION
Pins Yi or Xi Yi or Xi Yi or Xi Y1 and Y2 X1 and X2 Xi and Yi Fault Mode Shortcircuit to GND Shortcircuit to Vbat Open Short circuited Short circuited Short circuited

A motor shutdown occurs when: The chip temperature rises above the thermal shutdown threshold Ttsd (see Thermal Shutdown Mode). The battery voltage goes below UV2 for longer than 15 seconds (see Battery Voltage Management). The charge pump voltage goes below the charge pump comparator level for more than 15 seconds. Flag <ElDef> = 1, meaning an electrical problem is detected on one or both coils, e.g. a short circuit. A motor shutdown leads to the following: Hbridges in high impedance mode. The <TagPos> register is loaded with the <ActPos>, except in autarkic states. The conditions to get out of a motor shutdown mode are: Reception of a GetFullStatus1 command AND The four above causes are no longer detected This leads to Hbridges going in Ihold mode. Hence, the circuit is ready to execute any positioning command.

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This can be illustrated in the following sequence given as an application example. The master can check whether there is a problem or not and decide which application strategy to adopt.
Table 23. Example of Possible Sequence used to Detect and Determine Cause of Motor Shutdown
Tj Tsd or VBB UV2 or <ElDef> = 1 or <CPFail> = 1 The circuit is driven in motor shutdown mode The application is not aware of this

SetPosition frame The position setpoint is updated by the I2C Master Motor shutdown mode no motion The application is still unaware

GetFullStatus1 frame The application is aware of a problem

GetFullStatus1 frame ... Possible confirmation of the problem

Reset <TW> or <TSD> or <UV2> or <StepLoss> or <ElDef> or <CPFail> by the application Possible new detection of over temperature or low voltage or electrical problem Circuit sets <TW> or <TSD> or <UV2> or <StepLoss> or <ElDef> or <CPFail> again at 1

Important: While in shutdown mode, since there is no hold current in the coils, the mechanical load can cause a step loss, which indeed cannot be flagged by the AMIS30622. Note: The Priority Encoder is describing the management of states and commands.

Warning: The application should limit the number of consecutive GetFullStatus1 commands to try to get the AMIS30622 out of shutdown mode when this proves to be unsuccessful, e.g. there is a permanent defect. The reliability of the circuit could be altered since GetFullStatus1 attempts to disable the protection of the Hbridges.

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I2C BUS DESCRIPTION General Description AMIS30622 uses a simple bidirectional 2wire bus for efficient interic control. This bus is called the Inter IC or I2Cbus. Features include: Only two bus lines are required; a serial data line (SDA) and a serial clock line (SCK). Each device connected to the bus is software addressable by a unique address and simple master/slave relationships exists at all times; master can operate as mastertransmitter or as master receiver. Serial, 8bit oriented, bidirectional data transfers can be made up to 400 kb/s. Onchip filtering rejects spikes on the bus data line to preserve data integrity.
Table 24. DEFINITION OF I2CBUS TERMINOLOGY
Term Transmitter Receiver Master Slave Synchronization The device which sends data on the bus The device which receives data from the bus The device which initiates a transfer, generates clock signals and terminates a transfer The devices addressed by a master Procedure to synchronizer the clock signals of two or more devices Description

No need to design bus interfaces because I2Cbus ICs can be added to or removed from a system without
affecting any other circuits on the bus. Concept The I2Cbus consists of two wires, serial data (SDA) and serial clock (SCK), carrying information between the devices connected on the bus. Each device connected to the bus is recognized by a unique address and operates as either a transmitter or receiver, depending on the function of the device. AMIS30622 can both receive and transmit data. In addition to transmitters and receivers, devices can also be considered as masters or slaves when performing data transfers. AMIS30622 is a slave device. See Table 25. interface is already integrated onchip.

Micro controller

Motordriver_2 AMIS30622

Motordriver_4 AMIS30622

SDA SCL

Motordriver_1 AMIS30622

Motordriver_3 AMIS30622

Figure 21. Example of an I2Cbus Configuration Using One Microcontroller and Four Slaves

Figure 21 highlights the masterslave and receivertransmitter relationships to be found on the I2Cbus. It should be noted that these relationships are not permanent but only depend on the direction of data transfer at that time. The transfer of data would proceed as follows: 1. Suppose the microcontroller wants to send information to motordriver_1: Microcontroller (master) addresses motordriver_1 (slave) Microcontroller (mastertransmitter) sends data to motordriver_1 (slavereceiver) Microcontroller terminates the transfer

2. If the microcontroller wants to receive information from motordriver_2: Microcontroller (master) addresses motordriver_2 (slave) Microcontroller (masterreceiver) receives data from motordriver_2 (slavetransmitter) Microcontroller terminates the transfer Even in this case the master generates the timing and terminates the transfer. Generation of the signals on the I2Cbus is always the responsibility of the master device. It generates its own clock signal when transferring data on the bus. Bus clock signals from a master can only be altered when they are stretched by a slow slave device holdingdown the clock line.

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General Characteristics
+5 V Rp Serial Data Line Serial Clock Line SCK 2
Clock IN Clock OUT Data IN Data OUT

Rp

SDA 1
Clock IN Clock OUT

SCL
Data IN Data OUT

SDA

AMIS30624, NCV70624

MASTER

Figure 22. Connection of a Device to the I2Cbus

Both SDA and SCK are bidirectional lines connected to a positive supply voltage via a pullup resistor (see Figure 22). When the bus is free both lines are HIGH. The output stages of the devices connected to the bus must have an open drain to perform the wiredAND function. Data on the I2Cbus can be transferred up to 400 kb/s in fast mode. The number of interfaces connected to the bus is dependent on the maximum bus capacitance limit (See CB in Table 6) and the available number of addresses. Bit Transfer The levels for logic 0 (LOW) and 1 (HIGH) are not fixed in the I2C standard but dependent on the used VDD level. Using AMIS30622, the levels are specified in Table 5. One clock pulse is generated for each data bit transferred.
Data Validity

The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW (See Figure 23).
SDA

Within the procedure of the I2Cbus, unique situations arise, which are defined as START (S) and STOP (P) conditions (See Figure 24). A HIGH to LOW transition on the SDA line while SCK is HIGH is one such unique case. This situation indicates a START condition. LOW to HIGH transition on the SDA line while SCK is HIGH defines a STOP condition. START and STOP conditions are always generated by the master. The bus is considered to be busy after the START condition. The bus is considered to be free again a certain time after the STOP condition. The bus free situation is specified as tBUF in Table 6. The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. In this respect, the START (S) and repeated START (Sr) conditions are functionally identical (See Figure 25). The symbol S will be used to represent START and repeated START, unless otherwise noted.
START SDA STOP

START and STOP Conditions

SCK

SCK

Data line stable > Data valid

Change of data allowed

START condition

Figure 23. Bit Transfer on the I2Cbus

STOP condition

Figure 24. START and STOP Conditions

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Transferring Data
Byte Format

Every byte put on the SDA line must be 8bits long. The number of bytes that can be transmitted per transfer to AMIS30622 is restricted to eight. Each byte has to be followed by an acknowledge bit. Data is transferred with the
START SDA

most significant bit (MSB) first (See Figure 25). If a slave cant receive or transmit another complete byte of data, it can hold the clock line SCK LOW to force the master into a wait state. Data transfer then continues when the slave is ready for another byte of data and releases clock line SCK.

STOP

MSB Acknowledgement signal from slave SCK

Clock line held low by slave

1 START condition

38

9 ACK STOP condition

Aknowledge related clock puse from master

Figure 25. Data Transfer on the I2Cbus Acknowledge

Data transfer with acknowledge is obligatory. The acknowledgerelated clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse (see Figure 26). Of course, setup and hold times must also taken into account (see Table 6). When AMIS30622 doesnt acknowledge the slave address, the data line will be left HIGH. The master can than generate either a STOP condition to abort the transfer, or a repeated START condition to start a new transfer.
START SDA by master transmitter MSB SDA by slave receiver

If AMIS30622 as slavereceiver does acknowledge the slave address but later in the transfer cannot receive any more data bytes, this is indicated by generating a notacknowledge on the first byte to follow. The master generates than a STOP or a repeated START condition. If a masterreceiver is involved in the transfer, it must signal the end of data to the slavetransmitter by not generating an acknowledge on the last byte that was clocked out of the slave. AMIS30622 as slavetransmitter shall release the data line to allow the master to generate STOP or repeated START condition.

Master releases the Data line

Not acknowledged

SCK from master 1 START condition 2

Acknowledged 8 9

Slave pulls data line low if Acknowledged

Aknowledge related clock puse from master

Figure 26. Acknowledge on the I2Cbus

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Clock Generation

The master generates the clock on the SCK line to transfer messages on the I2Cbus. Data is only valid during the HIGH period of the clock. Data Formats with 7bit Addresses Data transfers follow the format shown in Figure 27. After the START condition (S), a slave address is sent. This
START SDA

address is 7bit long followed by an eighth bit which is a data direction bit (R/W) a zero indicates a transmission (WRITE), a one indicates a request for data (READ). A data transfer is always terminated by a STOP condition (P) generated by the master.

STOP

SCK 17 START condition 8 9 17 8 9 17 8 9

ADDRESS

R/W

ACK

DATA

ACK

DATA

ACK

STOP condition

Figure 27. A Complete Data Transfer

However, if a master still wishes to communicate on the bus, it can generate a repeated START (Sr) and address another slave without first generating a STOP condition. Various combinations of read/write formats are then possible within such a transfer.
Data Transfer Formats
Writing Data to AMIS30622

When writing to AMIS30622, the mastertransmitter transmits to slavereceiver and the transfer direction is not changed. A complete transmission consists of: Start condition The slave address (7bit)
S Slave Address
R/W

Read/Write bit (0 = write) Acknowledge bit Any further data bytes are followed by an acknowledge bit. The acknowledge bit is used to signal a correct reception of the data to the transmitter. In this case the AMIS30622 pulls the SDA line to 0. The AMIS30622 reads the incoming data at SDA on every rising edge of the SCK signal Stop condition to finish the transmission

Data

Data

0 = WRITE Master to AMIS 30624 AMIS 30624 to Master

N bytes + Acknowledge S = Start condition P = Stop condition A = Acknowledge (SDA = LOW) A = No Acknowledge (SDA = HIGH)

Figure 28. Master Writing Data to AMIS30622

Some commands for the AMIS30622 are supporting eight bytes of data, other commands are transmitting two bytes of data. See Table 25.
Reading Data to AMIS30622

When reading data from AMIS30622 two transmissions are needed:

1. The first transmission consists of two bytes of data: The first byte contains the slave address and the write bit. The second byte contains the address of an internal register in the AMIS30622. This internal register address is stored in the circuit RAM.

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S Slave Address
R/W

Internal Address

0 = WRITE

Figure 29. Master Reading Data from AMIS30622: First Transmission is Addressing

2. The second transmission consists of the slave address and the read bit. Then the master can read the data bits on the SDA line on every rising edge of signal SCK. After each byte of data the master has to acknowledge correct data reception by
S Slave Address
R/W

pulling SDA LOW. The last byte is not acknowledged by the master and therefore the slave knows the end of transmission.

Data

Data

0 = WRITE Master to AMIS 30624 AMIS 30624 to Master

N bytes + Acknowledge S = Start condition P = Stop condition A = Acknowledge (SDA = LOW) A = No Acknowledge (SDA = HIGH)

Figure 30. Master Reading Data from AMIS30622: Second Transmission is Reading Data

Notes:
1. Each byte is followed by an acknowledgment bit as indicated by the A or A in the sequence. 2. I2Cbus compatible devices must reset their bus logic on receipt of a START condition such that they all anticipate the sending of a slave address, even if these START conditions are not positioned according to the proper format. 3. A START condition immediately followed by a STOP condition (void message) is an illegal format.

7bit Addressing The addressing procedure for the I2Cbus is such that the first byte after the START condition usually determines which slave will be selected by the master. The exception is the general call address which can call all devices. When this address is used all devices should respond with an acknowledge. The second byte of the general call address then defines the action to be taken.
Definition of Bits in the First Byte

The first seven bits of the first byte make up the slave address. The eighth bit is the least significant bit (LSB). It determines the direction of the message. If the LSB is a zero it means that the master will write information to a selected slave. A one in this position means that the master will read information from the slave. When an address is sent, each device in a system compares the first seven bits after the START condition with its address. If they match, the device considers itself addressed by the master as a slavereceiver or slavetransmitter, depending on the R/W bit.
MSB LSB R/W

AMIS30622 is provided with a physical address in order to discriminate this circuit from other circuits on the I2C bus. This address is coded on seven bits (two bits being internally hardwired to 1), yielding the theoretical possibility of 32 different circuits on the same bus. It is a combination of four OTP memory bits (OTP Memory Structure OPEN) and of the externally hardwired address bits (pin HW). HW must either be connected to ground or to Vbat. When HW is not connected and is left floating, correct functionality of the positioner is not guaranteed. The motor will be driven to the programmed secure position (See Hardwired Address OPEN).
MSB 1 1 LSB PA3 PA2 PA1 PA0 HW R/W

OTP memory

Hardwired Address Bit

Figure 32. First Byte after START Procedure General Call Address

SLAVE ADDRESS

Figure 31. First Byte after START Procedure

The AMIS30622 supports also a general call address 000 0000, which can address all devices. When this address is used all devices should respond with an acknowledge. The second byte of the general call address then defines the action to be taken.

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I2C APPLICATION COMMANDS Introduction Communications between the AMIS30622 and a 2wire serial bus interface master takes place via a large set of commands. Reading commands are used to: Get actual status information, e.g. error flags Get actual position of the stepper motor Verify the right programming and configuration of the AMIS30622. Commands Table
Table 25. I2C COMMANDS WITH CORRESPONDING ROM POINTER
Command Byte Command Mnemonic GetFullStatus1 GetFullStatus2 GetOTPParam GotoSecurePosition HardStop ResetPosition ResetToDefault SetDualPosition SetMotorParam SetOTP SetPosition SoftStop Function Returns complete status of the chip Returns actual, target and secure position Returns OTP parameter Drives motor to secure position Immediate full stop Sets actual position to zero Overwrites the chip RAM with OTP contents Drives the motor to two different positions with different speed Sets motor parameter Zaps the OTP memory Programs a target and secure position Motor stopping with deceleration phase Binary 1000 0001 1111 1100 1000 0010 1000 0100 1000 0101 1000 0110 1000 0111 1000 1000 1000 1001 1001 0000 1000 1011 1000 1111 Hexadecimal 0x81 0xFC 0x82 0x84 0x85 0x86 0x87 0x88 0x89 0x90 0x8B 0x8F

Writing commands are used to: Program the OTP memory Configure the positioner with motion parameters (max/min speed, acceleration, stepping mode, etc.) Provide target positions to the Stepper motor The I2Cbus master will have to use commands to manage the different application tasks the AMIS30622 can feature. The commands summary is given in Table 25.

These commands are described hereafter, with their corresponding I2C frames. Refer to Data Transfer Formats for more details. A color coding is used to distinguish
Light Gray: Master Data

between master and slave parts within the frames. An example is shown below.

White: Slave Response Figure 33. Color Code Used in the Definition of I2C Frames

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Application Commands
GetFullStatus1

This command is provided to the circuit by the master to get a complete status of the circuit and of the stepper motor. Refer to Tables 19 and 20 to see the meaning of the parameters sent back to the I2C master.
Table 26. GetFullStatus1 COMMAND FRAME

Note: A GetFullStatus1 command will attempt to reset flags <TW>, <TSD>, <UV2>, <ElDef>, <StepLoss>, <CPFail>, <OVC1>, <OVC2>, and <VddReset>.

GetFullStatus1 corresponds to the following I2C command frame:

Structure Byte 0 1 Content Address Command Bit 7 1 1 Bit 6 1 0 Bit 5 OTP3 0 Bit 4 OTP2 0 Bit 3 OTP1 0 Bit 2 OTP0 0 Bit 1 HW 0 Bit 0 0 1

Table 27. GetFullStatus1 RESPONSE FRAME

Structure Byte 0 1 2 3 4 5 6 7 8 Content Address Address Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 1 1 AccShape VddReset Bit 7 1 1 Bit 6 1 1 Irun[3:0] Vmax[3:0] StepMode[1:0] StepLoss Motion[2:0] 1 1 1 1 ElDef Shaft UV2 ESW 1 1 TSD OVC1 1 1 TW OVC2 1 1 1 1 1 Bit 5 OTP3 1 Bit 4 OTP2 OTP3 Bit 3 OTP1 OTP2 Bit 2 OTP0 OTP1 Bit 1 HW OTP0 Bit 0 1 HW

Ihold[3:0] Vmin[3:0] Acc[3:0] Tinfo[1:0] CPFail 1 1

Where: OTP(n) HW Irun[3:0] Ihold[3:0] Vmax[3:0] Vmin[3:0] AccShape StepMode[1:0] Shaft Acc[3:0] VddReset

OTP address bits PA[3:0] Hardwired address bit Operating current in the motor coil Standstill current in the motor coil Maximum velocity Minimum velocity Enables motion without acceleration Step mode definition Direction of movement Acceleration form minimum to maximum velocity Reset of digital supply

StepLoss ElDef UV2 TSD TW Tinfo[1:0] Motion[2:0] ESW OVC1 OVC2 CPFail

Step loss occurred Electrical defect Battery under voltage detected Thermal shutdown Thermal warning Temperature Info Motion status External switch status Over current in Xcoil detected Over current in Ycoil detected Charge pump failure

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GetFullStatus2

This command is provided to the circuit by the master to get the actual, target and secure position of the stepper motor. Both the actual and target position are returned in signed twos complement 16bit format. Secure position is coded in 10bit format. According to the programmed
Table 28. GetFullStatus2 COMMAND FRAME

stepping mode the LSBs of ActPos[15:0] and TagPos[15:0] may have no meaning and should be assumed to be 0. This command also gives additional information concerning stall detection. Refer to Tables 19 and 20 to see the meaning of the parameters sent back to the I2C master.

GetFullStatus2 corresponds to the following I2C command frame:

Structure Byte 0 1 Content Address Command Bit 7 1 1 Bit 6 1 1 Bit 5 OTP3 1 Bit 4 OTP2 1 Bit 3 OTP1 1 Bit 2 OTP0 1 Bit 1 HW 0 Bit 0 0 0

Table 29. GetFullStatus2 RESPONSE FRAME

Structure Byte 0 1 2 3 4 5 6 7 8 Content Address Address Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 1 1 1 1 1 1 1 1 Bit 7 1 1 Bit 6 1 1 Bit 5 OTP3 1 Bit 4 OTP2 OTP3 Bit 3 OTP1 OTP2 Bit 2 OTP0 OTP1 Bit 1 HW OTP0 Bit 0 1 HW

ActPos[15:8] ActPos[7:0] TagPos[15:8] TagPos[7:0] SecPos[7:0] 1 1 1 SecPos[10:8] 1 1

Where: OTP(n) HW ActPos[15:0]

OTP address bits PA[3:0] Hardwired address bit Actual position

TagPos[15:0] SecPos[10:0]

Target position Secure position

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This command is provided to the circuit by the I2C master to read the content of the OTP memory. More information can be found in OTP Memory Structure corresponds to the following I2C command frame:. GetOTPParam
Table 30. GetOTPParam COMMAND FRAME
Structure Byte 0 1 Content Address Command Bit 7 1 1 Bit 6 1 0 Bit 5 OTP3 0 Bit 4 OTP2 0 Bit 3 OTP1 0 Bit 2 OTP0 0 Bit 1 HW 1 Bit 0 0 0

GetOTPParam

Table 31. GetOTPParam RESPONSE FRAME

Structure Byte 0 1 2 3 4 5 6 7 8 Content Address OTP byte 0 OTP byte 1 OTP byte 2 OTP byte 3 OTP byte 4 OTP byte 5 OTP byte 6 OTP byte 7 Bit 7 1 Bit 6 1 Bit 5 OTP3 Bit 4 OTP2 Bit 3 OTP1 Bit 2 OTP0 Bit 1 HW Bit 0 1

OTP byte @0x00 OTP byte @0x01 OTP byte @0x02 OTP byte @0x03 OTP byte @0x04 OTP byte @0x05 OTP byte @0x06 OTP byte @0x07

This command is provided by the I2C master to one or all the stepper motors to move to the secure position SecPos[10:0]. See the priority encoder corresponds to GotoSecurePosition
Table 32. GotoSecurePosition COMMAND FRAME

GotoSecurePosition

the following I2C command frame: description for more details. The priority encoder table also acknowledges the cases where a GotoSecurePosition command will be ignored.

Structure Byte 0 1 Content Address Command Bit 7 1 1 Bit 6 1 0 Bit 5 OTP3 0 Bit 4 OTP2 0 Bit 3 OTP1 0 Bit 2 OTP0 1 Bit 1 HW 0 Bit 0 0 0

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HardStop

This command will be internally triggered when an electrical problem is detected in one or both coils, leading to shutdown mode. If this occurs while the motor is moving, the <StepLoss> flag is raised to allow warning of the I2C HardStop corresponds to the following I2C command frame:
Table 33. HardStop COMMAND FRAME

master at the next GetStatus1 command that steps may have been lost. Once the motor is stopped, ActPos register is copied into TagPos register to ensure keeping the stop position. The I2C master for some safety reasons can also issue a HardStop command.

Structure Byte 0 1 Content Address Command Bit 7 1 1 Bit 6 1 0 Bit 5 OTP3 0 Bit 4 OTP2 0 Bit 3 OTP1 0 Bit 2 OTP0 1 Bit 1 HW 0 Bit 0 0 1

This command is provided to the circuit by the I2C master to reset ActPos and TagPos registers to zero. This can be helpful to prepare for instance a relative positioning. ResetPosition corresponds to the following I2C command frame:
Table 34. ResetPosition COMMAND FRAME
Structure Byte 0 1 Content Address Command Bit 7 1 1 Bit 6 1 0 Bit 5 OTP3 0 Bit 4 OTP2 0 Bit 3 OTP1 0 Bit 2 OTP0 1 Bit 1 HW 1 Bit 0 0 0

ResetPosition

This command is provided to the circuit by the I2C master in order to reset the whole slave node into the initial state. ResetToDefault will, for instance, overwrite the RAM with the reset state of the registers parameters (see Table 19). This is another way for the I2C master to initialize a slave node in case of emergency, or simply to refresh the RAM content.
Table 35. ResetToDefault COMMAND FRAME

ResetToDefault

Note: ActPos and TagPos are not modified by a ResetToDefault command. Important: Care should be taken not to send a ResetToDefault command while a motion is ongoing, since this could modify the motion parameters in a way forbidden by the position controller.

ResetToDefault corresponds to the following I2C command frame:

Structure Byte 0 1 Content Address Command Bit 7 1 1 Bit 6 1 0 Bit 5 OTP3 0 Bit 4 OTP2 0 Bit 3 OTP1 0 Bit 2 OTP0 1 Bit 1 HW 1 Bit 0 0 1

This command is provided to the circuit by the I2C master in order to put the motor in continuous motion state. RunVelocity corresponds to the following I2C command frame:
Table 36. RunVelocity COMMAND FRAME
Structure Byte 0 1 Content Address Command Bit 7 1 1 Bit 6 1 0 Bit 5 OTP3 0 Bit 4 OTP2 1 Bit 3 OTP1 0 Bit 2 OTP0 1 Bit 1 HW 1 Bit 0 0 1

RunVelocity

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SetDualPosition

This command is provided to the circuit by the I2C master in order to perform a positioning of the motor using two different velocities. See Section Dual Positioning. Note: This sequence cannot be interrupted by another positioning command. Important: If for some reason ActPos equals Pos1[15:0] at the moment the SetDualPosition SetDualPosition
Table 37. SetDualPosition COMMAND FRAME

command is issued, the circuit will enter in deadlock state. Therefore, the application should check the actual position by a GetFullStatus2 corresponds to the following I2C command frame command prior to starting a dual positioning. Another solution may consist of programming a value out of the stepper motor range for Pos1[15:0]. For the same reason Pos2[15:0] should not be equal to Pos1[15:0].

Structure Byte 0 1 2 3 4 5 6 7 8 Content Address Command Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Bit 7 1 1 1 1 Bit 6 1 0 1 1 Vmax[3:0] Pos1[15:8] Pos1[7:0] Pos2[15:8] Pos2[7:0] Bit 5 OTP3 0 1 1 Bit 4 OTP2 0 1 1 Bit 3 OTP1 1 1 1 Bit 2 OTP0 0 1 1 Bit 1 HW 0 1 1 Vmin[3:0] Bit 0 0 0 1 1

Where: Vmax[3:0] Vmin[3:0]

Max. velocity for first motion Min. velocity for first motion and velocity for the second motion

Pos1[15:0] Pos2[15:0]

First position to be reached during the first motion Relative position of the second motion

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This command is provided to the circuit by the I2C master to set the values for the stepper motor parameters (listed below) in RAM. Refer to Table 19 to see the meaning of the parameters sent by the I2C master. Important: If a SetMotorParam occurs while a motion is ongoing, it will modify at once the motion parameters (see SetMotorParam
Table 38. SetMotorParam COMMAND FRAME
Structure Byte 0 1 2 3 4 5 6 7 8 Content Address Command Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 1 1 1 Bit 7 1 1 1 1 Bit 6 1 0 1 1 Irun[3:0] Vmax[3:0] SecPos[10:8] Shaft SecPos[7:0] AccShape StepMode[1:0] 1 1 Bit 5 OTP3 0 1 1 Bit 4 OTP2 0 1 1 Bit 3 OTP1 1 1 1 Bit 2 OTP0 0 1 1 Ihold[3:0] Vmin[3:0] Acc[3:0] Bit 1 HW 0 1 1 Bit 0 0 1 1 1

SetMotorParam

Position Controller corresponds to the following I2C command frame:). Therefore the application should not change parameters other than Vmax while a motion is running, otherwise correct positioning cannot be guaranteed.

This command is provided to the circuit by the I2C master to program and zap the OTP data D[7:0] in OTP address OTPA[2:0].
Table 39. SetOTPParam COMMAND FRAME

SetOTPParam

Important: This command must be sent under a specific VBB voltage value. See parameter VBBOTP in Table 5. This is a mandatory condition to ensure reliable zapping.

SetOTPParam corresponds to the following I2C command frame:

Structure Byte 0 1 2 3 4 5 Content Address Command Data 1 Data 2 Data 3 Data 4 Bit 7 1 1 1 1 1 Bit 6 1 0 1 1 1 Bit 5 OTP3 0 1 1 1 Bit 4 OTP2 1 1 1 1 D[7:0] Bit 3 OTP1 0 1 1 1 Bit 2 OTP0 0 1 1 Bit 1 HW 0 1 1 OTPA[2:0] Bit 0 0 0 1 1

Where: OTPA[2:0]: D[7:0]:

OTP address Corresponding OTP data

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SetPosition

This command is provided to the circuit by the I2C master to drive the motor to a given absolute position. See Positioning (see Priority Encoder) for more details. The SetPosition corresponds to the following I2C command frame:
Table 40. SetPosition COMMAND FRAME

priority encoder table acknowledges the cases where a SetPosition command will be ignored.

Structure Byte 0 1 2 3 4 5 Content Address Command Data 1 Data 2 Data 3 Data 4 Bit 7 1 1 1 1 Bit 6 1 0 1 1 Bit 5 OTP3 0 1 1 Bit 4 OTP2 0 1 1 Pos[15:8] Pos[7:0] Bit 3 OTP1 1 1 1 Bit 2 OTP0 0 1 1 Bit 1 HW 1 1 1 Bit 0 0 1 1 1

Where: Pos [15:0]

SoftStop

Signed 16bit position setpoint for motor. command frame:) followed by a stop, regardless of the position reached. Once the motor is stopped, TagPos register is overwritten with value in ActPos register to ensure keeping the stop position. The I2C Master for some safety reasons can also issue a SoftStop command.

This command will be internally triggered when the chip temperature rises above the thermal shutdown threshold (see Table 5 and the Temperature Management Section). It provokes an immediate deceleration to Vmin (see Minimum Velocity corresponds to the following I2C SoftStop
Table 41. SoftStop COMMAND FRAME

Structure Byte 0 1 Content Address Command Bit 7 1 1 Bit 6 1 0 Bit 5 OTP3 0 Bit 4 OTP2 0 Bit 3 OTP1 1 Bit 2 OTP0 1 Bit 1 HW 1 Bit 0 0 1

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PACKAGE DIMENSIONS
SOIC 20 W CASE 751AQ ISSUE O

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PACKAGE DIMENSIONS
NQFP32, 7x7 CASE 560AA ISSUE O

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NQFP32, 7x7 CASE 560AA ISSUE O

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