//filename :

//author :
//date
:

motion_estimation.v
Ray Luo
2007.12.25

module motion_estimation(
clk_sys,
rst_n,
frm_start,
frm_cf_d,
frm_pf_da,
frm_pf_db,
frm_cf_addr,
frm_cf_rd,
frm_pf_addra,
frm_pf_rda,
frm_pf_addrb,
frm_pf_rdb,
vect_row,
vect_col
);
input
input
input
input
input
input
output
output
output
output
output
output
output
output

clk_sys;
rst_n;
frm_start;
[7:0] frm_cf_d;
[7:0] frm_pf_da;
[7:0] frm_pf_db;
[15:0] frm_cf_addr;
frm_cf_rd;
[15:0] frm_pf_addra;
frm_pf_rda;
[15:0] frm_pf_addrb;
frm_pf_rdb;
[2:0] vect_row;
[2:0] vect_col;

wire
wire
wire
wire
[7:0]
wire
[7:0]
wire
[7:0]
reg
[15:0]
ram
reg
[15:0]
sram
reg
[15:0]
sram
reg
[2:0]
or transmit
reg
[2:0]
for transmit
reg
[15:0]
lock
reg
[8:0]
t blok
reg
reg
reg

clk_sys;
rst_n;
frm_start;
frm_cf_d;
frm_pf_da;
frm_pf_db;
frm_cf_addr;

//the clock of system

//the reset signal
//the motion estimation start

//the address of the current frame's s

frm_pf_addra;

//the addressa of the previous frame's

frm_pf_addrb;

//the addressb of the previous frame's

vect_row;

//the row of the matching best block f

vect_col;

//the column of the matching best blok

blk_row;

//the first row of the matching best b

blk_col;

//the first column of the matching bes

frm_cf_rd;
frm_pf_rda;
frm_pf_rdb;

//read signal for the current frame

//read signal for the current frame
//read signal for the current frame

reg
[8:0]
previous frame
reg
[8:0]
previous frame
reg
[8:0]
current frame
reg
[8:0]
e
reg
[2:0]
reg
reg

blk_i_starta;
a
blk_i_startb;
b
blk_i_startc;

//the first column of the block in the

blk_j_start;

//the first row of the block in the fram

blk_i_cnt8;

//the cloumn of the block

[11:0] srh_l_addr_cnta;
[11:0] srh_l_addr_cntb;

reg
window

srh_win_en;

//the first column of the block in the

//the first column of the block in the

//the addressa of the row in the block

//the addressb of thw row in the block
//enable signal for search in the search

reg
srh_win_enda;
calculate a
reg
srh_win_endb;
calculate b
reg
[11:0] srh_blkaddr_lstarta;
n the search window a
reg
[11:0] srh_blkaddr_lstartb;
n the search window b
reg
[2:0] srh_blk_lstarta;
earch window a
reg
[2:0] srh_blk_lstartb;
earch window a
reg
[2:0] srh_lstartb_ff;
n the search window b

//the end signal for search window when

reg
reg
[15:0]
previous frame
reg
[15:0]
previous frame
reg
[15:0]
rrent frame

frm_start_ff ;
blk_jaddr_starta;

//delay frm_sart signal one cycle

//the first address of the row a in the

blk_jaddr_startb;

//the first address of the row b in the

blk_jaddr_startc;

//the first address of the row in the cu

//the end signal for search window when

//the start first row address of block i
//the start first row address of block i
//the start first row of block int the s
//the start first row of block int the s
//the start first row address of block i

reg
[11:0] blk_jaddr_cnt8;
reg
[2:0] srh_lblk_cnt;
ch window
reg
pf_da_sam_en;

//count the row of one block in the sear

reg

pf_db_sam_en;

//enable signal for pf_db

pf_da0;

//register the previous frame data when

pf_da1;

//register the previous frame data when

pf_da2;

//register the previous frame data when

pf_da3;

//register the previous frame data when

pf_da4;

//register the previous frame data when

pf_da5;

//register the previous frame data when

pf_da6;

//register the previous frame data when

reg
read
reg
read
reg
read
reg
read
reg
read
reg
read
reg

[7:0]
a address
[7:0]
a address
[7:0]
a address
[7:0]
a address
[7:0]
a address
[7:0]
a address
[7:0]

//enable signal for pf_da

read
reg
read
reg
read
reg
read
reg
read
reg
read
reg
read
reg
read
reg

a address
[7:0]
b address
[7:0]
b address
[7:0]
b address
[7:0]
b address
[7:0]
b address
[7:0]
b address
[7:0]
b address
[7:0]

reg
ame
reg
ame
reg
ame
reg
ame
reg
ame
reg
ame
reg
ame
reg
reg
reg
reg
reg
reg
reg
reg
reg
reg
reg
reg
reg
reg
reg
reg
reg
reg
reg
reg
reg
reg
b
reg
b
reg
b
reg
b

pf_db0;

//register the previous frame data when

pf_db1;

//register the previous frame data when

pf_db2;

//register the previous frame data when

pf_db3;

//register the previous frame data when

pf_db4;

//register the previous frame data when

pf_db5;

//register the previous frame data when

pf_db6;

//register the previous frame data when

cf_d;

//register the current frame data

[7:0]

pf_d0;

//the pixel number come from previous fr

[7:0]

pf_d1;

//the pixel number come from previous fr

[7:0]

pf_d2;

//the pixel number come from previous fr

[7:0]

pf_d3;

//the pixel number come from previous fr

[7:0]

pf_d4;

//the pixel number come from previous fr

[7:0]

pf_d5;

//the pixel number come from previous fr

[7:0]

pf_d6;

//the pixel number come from previous fr

[8:0]
[8:0]
[8:0]
[8:0]
[8:0]
[8:0]
[8:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]
[13:0]

cf_sub_pf0;
cf_sub_pf1;
cf_sub_pf2;
cf_sub_pf3;
cf_sub_pf4;
cf_sub_pf5;
cf_sub_pf6;
abs_sub0;
abs_sub1;
abs_sub2;
abs_sub3;
abs_sub4;
abs_sub5;
abs_sub6;
acc_abs_sub0;
acc_abs_sub1;
acc_abs_sub2;
acc_abs_sub3;
acc_abs_sub4;
acc_abs_sub5;
acc_abs_sub6;
acc_abs_sub_ff0;

//the substraction of two row pixel

//the substraction of two row pixel
//the substraction of two row pixel
//the substraction of two row pixel
//the substraction of two row pixel
//the substraction of two row pixel
//the substraction of two row pixel
//absolute the subtract
//absolute the subtract
//absolute the subtract
//absolute the subtract
//absolute the subtract
//absolute the subtract
//absolute the subtract
//accumulation register for abs_sub
//accumulation register for abs_sub
//accumulation register for abs_sub
//accumulation register for abs_sub
//accumulation register for abs_sub
//accumulation register for abs_sub
//accumulation register for abs_sub
//delay accumulation register for abs_su

[13:0] acc_abs_sub_ff1;

//delay accumulation register for abs_su

[13:0] acc_abs_sub_ff2;

//delay accumulation register for abs_su

[13:0] acc_abs_sub_ff3;

//delay accumulation register for abs_su

reg
[13:0]
b
reg
[13:0]
b
reg
[13:0]
b
reg
[13:0]
reg
[13:0]
reg
reg
[3:0]
in the window
reg
[3:0]
in the window
reg
reg

acc_abs_sub_ff4;

//delay accumulation register for abs_su

acc_abs_sub_ff5;

//delay accumulation register for abs_su

acc_abs_sub_ff6;

//delay accumulation register for abs_su

comp_acc_op;
comp_acc_abs;
comp_acc_en ;
srh_ka_cnt;

//one option number for compare

//register for the minimus accumulation
//enable signal for compare accumulation
//counter for the a collumn of the block

srh_kb_cnt;

//counter for the b collumn of the block

srh_kb_cnt_en;
srh_kb_cnt_en_ff;

//enable the srh_kb_cnt

//delay srh_kb_cnt one cycle

reg
b_cnt
reg
[2:0]

srh_k_sel;

//select signal for srh_ka_cnt and srh_k

comp_cnt;

//counter for compare

reg
reg
reg
reg
reg

[15:0]
[15:0]
[7:0]
[7:0]

srh_win_laddra;
srh_win_laddrb;
srh_win_kaddra;
srh_win_kaddrb;
srh_array_end;

//search window row addressa

//search window row addressb
//search window column addressa
//search window column addressa
//one array block end signal

reg
reg

[2:0]

srh_win_end_cnt;
srh_win_end_cnt_en;

//the counter after end signal generate

//the enable signal for srh_win_end_cnt

blk_i_cnt8_en;
i;

//enable signal for blk_i_cnt8

reg
integer

//****************************control the address of current frame**************

*****************//
//******************************************************************************
*****************//
//******************************************************************************
*****************//
//******************************************************************************
*****************//
//******************************************************************************
*****************//
//register the frame start signal
always @(posedge clk_sys)
begin
if (!rst_n)
frm_start_ff <= 1'b0;
else if (frm_start)
frm_start_ff <= 1'b1;
else if ((blk_jaddr_startb==16'd98560)&(blk_i_startb==9'd344)&srh_win_endb)
frm_start_ff <= 1'b0;
end
always @(posedge clk_sys)
begin
if (!rst_n)
frm_cf_rd <= 1'b1;
else if (frm_start)
frm_cf_rd <= 1'b0;
end

always @(posedge clk_sys)

begin
if (!rst_n)
frm_pf_rda <= 1'b1;
else if (frm_start)
frm_pf_rda <= 1'b0;
end
always @(posedge clk_sys)
begin
if (!rst_n)
frm_pf_rdb <= 1'b1;
else if (frm_start)
frm_pf_rdb <= 1'b0;
end
//register the frm_start_ff
always @(posedge clk_sys)
begin
if (!rst_n)
srh_win_en <= 1'b0;
else
srh_win_en <= frm_start_ff;
end
//genrate the first column of the block a
always @(posedge clk_sys)
begin
if (!rst_n)
blk_i_starta <= 9'd0;
else if (!frm_start_ff)
blk_i_starta <= 9'd0;
else if (frm_start_ff&srh_win_enda)
begin
if (blk_i_starta==9'd344)
blk_i_starta <= 9'd0;
else
blk_i_starta <= blk_i_starta+1;
end
end
//genrate the first row of the block
always @(posedge clk_sys)
begin
if (!rst_n)
blk_j_start <= 9'd0;
else if (frm_start_ff)
begin
if ((blk_i_starta==9'd344)&srh_win_enda)
blk_j_start <= blk_j_start + 1'b1;
end
end
//generate address of the first row in the block a
always @(posedge clk_sys)
begin
if (!rst_n)

blk_jaddr_starta <= 16'd0;

else if (frm_start_ff)
begin
if ((blk_i_starta==9'd344)&srh_win_enda)
blk_jaddr_starta <= blk_jaddr_starta + 9'd352;
end
end
//generate address of the first row in the block b
always @(posedge clk_sys)
begin
if (!rst_n)
begin
blk_jaddr_startb <= 16'd0;
blk_i_startb <= 9'd0;
end
else if (!frm_start_ff)
begin
blk_jaddr_startb <= 16'd0;
blk_i_startb <= 9'd0;
end
else if ((srh_ka_cnt==4'b0111)&frm_start_ff)
begin
blk_jaddr_startb <= blk_jaddr_starta;
blk_i_startb <= blk_i_starta;
end
end
//generate address of the first row in the block b
always @(posedge clk_sys)
begin
if (!rst_n)
begin
blk_jaddr_startc <= 16'd0;
blk_i_startc <= 9'd0;
end
else if (!frm_start_ff)
begin
blk_jaddr_startc <= 16'd0;
blk_i_startc <= 9'd0;
end
else if ((srh_ka_cnt==4'b0101)&frm_start_ff)
begin
blk_jaddr_startc <= blk_jaddr_starta;
blk_i_startc <= blk_i_starta;
end
end
//generate the cloumn of the block for substract
always @(posedge clk_sys)
begin
if (!rst_n)
blk_i_cnt8 <= 3'b000;
else if (blk_i_cnt8_en)
blk_i_cnt8 <= blk_i_cnt8+1'b1;
end
//generate the row address increment of block
always @(posedge clk_sys)
begin

if (!rst_n)
blk_jaddr_cnt8 <= 12'd0;
else if ((blk_jaddr_cnt8 ==12'd2464)&(blk_i_cnt8==3'b111))
blk_jaddr_cnt8 <= 12'd0;
else if (blk_i_cnt8==3'b111)
blk_jaddr_cnt8 <= blk_jaddr_cnt8 +9'd352;
end
//generate the address of current frame
always @(posedge clk_sys)
begin
if (!rst_n)
frm_cf_addr <= 16'h00000;
else
frm_cf_addr <= blk_jaddr_startc + blk_jaddr_cnt8 + blk_i_cnt8 + blk_i_star
tc;
end
//******************************************************************************
*****************//
//******************************************************************************
*****************//
//******************************************************************************
*****************//
//******************************************************************************
*****************//

//**************************control the address of previous frame***************

*****************//
//******************************************************************************
*****************//
//******************************************************************************
*****************//
//******************************************************************************
*****************//
//******************************************************************************
*****************//
//*****************************control one block in the window******************
*****************//
//******************************************************************************
*****************//
//generate the address of columna in the search window
always @(posedge clk_sys)
begin
if (!rst_n)
srh_ka_cnt <= 4'b0000;
else if (srh_win_en)
srh_ka_cnt <= srh_ka_cnt + 1'b1;
else
srh_ka_cnt <= 4'b0000;
end
//generate the enable signal for blk_i_cnt8_en
always @(posedge clk_sys)
begin
if (!rst_n)

blk_i_cnt8_en <= 1'b0;

else if (srh_win_en&(srh_ka_cnt==4'b0101))
blk_i_cnt8_en <= 1'b1;
else if (!srh_win_en)
blk_i_cnt8_en <= 1'b0;
end
//generate the enable signal for srh_kb_cnt
always @(posedge clk_sys)
begin
if (!rst_n)
srh_kb_cnt_en <= 1'b0;
else if (srh_win_en&(srh_ka_cnt==4'b0111))
srh_kb_cnt_en <= 1'b1;
else if (!srh_win_en)
srh_kb_cnt_en <= 1'b0;
end
//delay srh_kb_cnt_en one cycle
always @(posedge clk_sys)
begin
if (!rst_n)
srh_kb_cnt_en_ff <= 1'b0;
else
srh_kb_cnt_en_ff <= srh_kb_cnt_en;
end
//generate the address of columna in the search window
always @(posedge clk_sys)
begin
if (!rst_n)
srh_kb_cnt <= 4'b0000;
else if (srh_kb_cnt_en)
srh_kb_cnt <= srh_kb_cnt + 1'b1;
else
srh_kb_cnt <= 4'b0000;
end
//generate the select signal for the row of search window block
always @(posedge clk_sys)
begin
if (!rst_n)
srh_k_sel <= 1'b0;
else if ((srh_win_en)&(srh_ka_cnt==4'b1000))
srh_k_sel <= 1'b1;
else if ((srh_win_en)&(srh_kb_cnt==4'b1000))
srh_k_sel <= 1'b0;
else if (!srh_win_en)
srh_k_sel <= 1'b0;
end
//generate the row of one block in the search window
always @(posedge clk_sys)
begin
if (!rst_n)
srh_lblk_cnt <= 3'b000;
else if ((srh_win_en)&((srh_ka_cnt==4'b1111)|(srh_kb_cnt==4'b1111)))
srh_lblk_cnt <= srh_lblk_cnt + 1'b1;
end

//generate the addressa increment of block in the search window

always @(posedge clk_sys)
begin
if (!rst_n)
srh_l_addr_cnta <= 12'd0;
else if ((srh_win_en)&(srh_ka_cnt==4'b1111))
begin
if (srh_lblk_cnt ==3'b110)
srh_l_addr_cnta <= 12'd0;
else
srh_l_addr_cnta <= srh_l_addr_cnta +12'd704;
end
end
//generate the data enable signal
always @(posedge clk_sys)
begin
if (!rst_n)
pf_da_sam_en <= 1'b0;
else if ((srh_win_en)&(srh_ka_cnt==4'b0001))
pf_da_sam_en <= 1'b1;
else if (srh_ka_cnt==4'b1111)
pf_da_sam_en <= 1'b0;
end
always @(posedge clk_sys)
begin
if (!rst_n)
pf_db_sam_en <= 1'b0;
else if ((srh_win_en)&(srh_kb_cnt==4'b0001))
pf_db_sam_en <= 1'b1;
else if (srh_kb_cnt==4'b1111)
pf_db_sam_en <= 1'b0;
end
//generate the addressb increment of block in the search window
always @(posedge clk_sys)
begin
if (!rst_n)
srh_l_addr_cntb <= 12'd352;
else if ((srh_win_en)&(srh_kb_cnt==4'b1111))
begin
if (srh_lblk_cnt ==3'b111)
srh_l_addr_cntb <= 12'd352;
else
srh_l_addr_cntb <= srh_l_addr_cntb +12'd704;
end
end
//generate search window row address
always @(blk_jaddr_starta or srh_blkaddr_lstarta or srh_l_addr_cnta)
begin
if ((blk_jaddr_starta + srh_blkaddr_lstarta + srh_l_addr_cnta) < 11'd1056)
srh_win_laddra = 16'h00000;
else if ((blk_jaddr_starta+srh_blkaddr_lstarta+srh_l_addr_cnta)>16'd98560)
srh_win_laddra = 16'd98560;
else
srh_win_laddra = blk_jaddr_starta - 11'd1056 + srh_blkaddr_lstarta + srh

_l_addr_cnta;
end
always @(blk_jaddr_startb or srh_blkaddr_lstartb or srh_l_addr_cntb)
begin
if ((blk_jaddr_startb + srh_blkaddr_lstartb + srh_l_addr_cntb) < 11'd1056)
srh_win_laddrb = 16'd0;
else if ((blk_jaddr_startb+srh_blkaddr_lstartb+srh_l_addr_cntb)>16'd98560)
srh_win_laddrb = 16'd98560;
else
srh_win_laddrb = blk_jaddr_startb - 11'd1056 + srh_blkaddr_lstartb + srh
_l_addr_cntb;
end
//generate search window row address
always @(blk_i_starta or srh_ka_cnt)
begin
if ((blk_i_starta + srh_ka_cnt ) < 2'd3)
srh_win_kaddra = 9'd0;
else if ((blk_i_starta + srh_ka_cnt ) > 9'd351)
srh_win_kaddra = 9'd351;
else
srh_win_kaddra = blk_i_starta + srh_ka_cnt -2'd3;
end
always @(blk_i_startb or srh_kb_cnt)
begin
if ((blk_i_startb + srh_kb_cnt ) < 2'd3)
srh_win_kaddrb = 9'd10;
else if ((blk_i_startb + srh_kb_cnt ) > 9'd351)
srh_win_kaddrb = 9'd351;
else
srh_win_kaddrb = blk_i_startb + srh_kb_cnt -2'd3;
end
//generate the addressa of previous frame
always @(posedge clk_sys)
begin
if (!rst_n)
frm_pf_addra <= 16'h00000;
else
frm_pf_addra <= srh_win_laddra + srh_win_kaddra;
end
always @(posedge clk_sys)
begin
if (!rst_n)
frm_pf_addrb <= 16'd352;
else
frm_pf_addrb <= srh_win_laddrb + srh_win_kaddrb;
end
//generate the first row address increment of each block in the window
always @(posedge clk_sys)
begin
if (!rst_n)
begin
srh_blkaddr_lstarta <= 12'd0;
srh_blk_lstarta <= 3'd0;

end
else if (srh_win_enda)
begin
srh_blkaddr_lstarta <= 12'd0;
srh_blk_lstarta <= 3'd0;
end
else if ((srh_win_en)&(srh_ka_cnt==4'b1111))
begin
if (srh_lblk_cnt==3'b110)
begin
srh_blkaddr_lstarta <= srh_blkaddr_lstarta +9'd352;
srh_blk_lstarta <= srh_blk_lstarta + 1'b1;
end
end
end
always @(posedge clk_sys)
begin
if (!rst_n)
begin
srh_blkaddr_lstartb <= 12'd0;
srh_blk_lstartb <= 3'd0;
end
else if ((srh_win_en)&(srh_ka_cnt==4'b0111))
begin
srh_blkaddr_lstartb <= srh_blkaddr_lstarta;
srh_blk_lstartb <= srh_blk_lstarta;
end
end
//gernerate the search window end signal
always @(srh_lblk_cnt or srh_ka_cnt or srh_win_en or srh_blkaddr_lstarta)
begin
srh_win_enda = ((srh_win_en)&(srh_lblk_cnt==3'b110)&(srh_ka_cnt==4'b1111)&(s
rh_blkaddr_lstarta==12'd2112));
end
always @(srh_lblk_cnt or srh_kb_cnt or srh_win_en or srh_blkaddr_lstartb)
begin
srh_win_endb = ((srh_win_en)&(srh_lblk_cnt==3'b111)&(srh_kb_cnt==4'b1111)&(s
rh_blkaddr_lstartb==12'd2112));
end
//generate the one array block end signal
always @(srh_win_en or srh_lblk_cnt or srh_kb_cnt)
begin
srh_array_end = ((srh_win_en)&(srh_lblk_cnt==3'b111)&(srh_kb_cnt==4'b1111));
end
//******************************************************************************
*****************//
//******************************************************************************
*****************//
//******************************************************************************
*****************//
//******************************************************************************
*****************//

//**************************subtration absolute aacumultation compare***********

*****************//
//******************************************************************************
*****************//
//******************************************************************************
*****************//
//******************************************************************************
*****************//
//******************************************************************************
*****************//
//register the data from sram
always @(posedge clk_sys)
begin
if (!rst_n)
begin
cf_d <= 8'h00;
end
else if (srh_kb_cnt_en)
cf_d <= frm_cf_d;
end
always @(posedge clk_sys)
begin
if (!rst_n)
begin
pf_da0 <= 8'h00;
pf_da1 <= 8'h00;
pf_da2 <= 8'h00;
pf_da3 <= 8'h00;
pf_da4 <= 8'h00;
pf_da5 <= 8'h00;
pf_da6 <= 8'h00;
end
else if (pf_da_sam_en)
pf_da6 <= frm_pf_da;
pf_da5 <= pf_da6;
pf_da4 <= pf_da5;
pf_da3 <= pf_da4;
pf_da2 <= pf_da3;
pf_da1 <= pf_da2;
pf_da0 <= pf_da1;
end
always @(posedge clk_sys)
begin
if (!rst_n)
begin
pf_db0 <= 8'h00;
pf_db1 <= 8'h00;
pf_db2 <= 8'h00;
pf_db3 <= 8'h00;
pf_db4 <= 8'h00;
pf_db5 <= 8'h00;
pf_db6 <= 8'h00;
end
else if ((pf_db_sam_en)&(srh_kb_cnt_en))
pf_db6 <= frm_pf_db;
pf_db5 <= pf_db6;
pf_db4 <= pf_db5;
pf_db3 <= pf_db4;

pf_db2 <= pf_db3;

pf_db1 <= pf_db2;
pf_db0 <= pf_db1;
end
//select a or b
always @(srh_k_sel or pf_da0 or pf_da1 or pf_da2 or pf_da3 or pf_da4 or pf_da5 o
r pf_da6 or pf_db0 or pf_db1 or pf_db2 or pf_db3 or pf_db4 or pf_db5 or pf_db6)
begin
pf_d0 = srh_k_sel ? pf_da0 : pf_db0;
pf_d1 = srh_k_sel ? pf_da1 : pf_db1;
pf_d2 = srh_k_sel ? pf_da2 : pf_db2;
pf_d3 = srh_k_sel ? pf_da3 : pf_db3;
pf_d4 = srh_k_sel ? pf_da4 : pf_db4;
pf_d5 = srh_k_sel ? pf_da5 : pf_db5;
pf_d6 = srh_k_sel ? pf_da6 : pf_db6;
end
//subtract
always @(cf_d or
begin
cf_sub_pf0 =
cf_sub_pf1 =
cf_sub_pf2 =
cf_sub_pf3 =
cf_sub_pf4 =
cf_sub_pf5 =
cf_sub_pf6 =
end

pf_d0 or pf_d1 or pf_d2 or pf_d3 or pf_d4 or pf_d5 or pf_d6)

cf_d
cf_d
cf_d
cf_d
cf_d
cf_d
cf_d

pf_d0;
pf_d1;
pf_d2;
pf_d3;
pf_d4;
pf_d5;
pf_d6;

//absolute
always @(cf_sub_pf0 or cf_sub_pf1 or cf_sub_pf2 or cf_sub_pf3 or cf_sub_pf4 or c
f_sub_pf5 or cf_sub_pf6)
begin
abs_sub0 =cf_sub_pf0[8] ? (~cf_sub_pf0[7:0]+1'b1) : cf_sub_pf0[7:0];
abs_sub1 =cf_sub_pf1[8] ? (~cf_sub_pf1[7:0]+1'b1) : cf_sub_pf1[7:0];
abs_sub2 =cf_sub_pf2[8] ? (~cf_sub_pf2[7:0]+1'b1) : cf_sub_pf2[7:0];
abs_sub3 =cf_sub_pf3[8] ? (~cf_sub_pf3[7:0]+1'b1) : cf_sub_pf3[7:0];
abs_sub4 =cf_sub_pf4[8] ? (~cf_sub_pf4[7:0]+1'b1) : cf_sub_pf4[7:0];
abs_sub5 =cf_sub_pf5[8] ? (~cf_sub_pf5[7:0]+1'b1) : cf_sub_pf5[7:0];
abs_sub6 =cf_sub_pf6[8] ? (~cf_sub_pf6[7:0]+1'b1) : cf_sub_pf6[7:0];
end
//accumulation
always @(posedge clk_sys)
begin
if (!rst_n)
begin
acc_abs_sub0 <= 14'h0000;
acc_abs_sub1 <= 14'h0000;
acc_abs_sub2 <= 14'h0000;
acc_abs_sub3 <= 14'h0000;
acc_abs_sub4 <= 14'h0000;
acc_abs_sub5 <= 14'h0000;
acc_abs_sub6 <= 14'h0000;
end
else if (srh_kb_cnt_en_ff)
begin

if (srh_array_end)
begin
acc_abs_sub0 <=
acc_abs_sub1 <=
acc_abs_sub2 <=
acc_abs_sub3 <=
acc_abs_sub4 <=
acc_abs_sub5 <=
acc_abs_sub6 <=
end
else
begin
acc_abs_sub0 <=
acc_abs_sub1 <=
acc_abs_sub2 <=
acc_abs_sub3 <=
acc_abs_sub4 <=
acc_abs_sub5 <=
acc_abs_sub6 <=
end

14'h0000;
14'h0000;
14'h0000;
14'h0000;
14'h0000;
14'h0000;
14'h0000;

acc_abs_sub0
acc_abs_sub1
acc_abs_sub2
acc_abs_sub3
acc_abs_sub4
acc_abs_sub5
acc_abs_sub6

end

+
+
+
+
+
+
+

end
//register the accumulation
always @(posedge clk_sys)
begin
if (!rst_n)
begin
acc_abs_sub_ff0 <= 14'h0000;
acc_abs_sub_ff1 <= 14'h0000;
acc_abs_sub_ff2 <= 14'h0000;
acc_abs_sub_ff3 <= 14'h0000;
acc_abs_sub_ff4 <= 14'h0000;
acc_abs_sub_ff5 <= 14'h0000;
acc_abs_sub_ff6 <= 14'h0000;
end
else if (srh_array_end)
begin
acc_abs_sub_ff0 <= acc_abs_sub0;
acc_abs_sub_ff1 <= acc_abs_sub1;
acc_abs_sub_ff2 <= acc_abs_sub2;
acc_abs_sub_ff3 <= acc_abs_sub3;
acc_abs_sub_ff4 <= acc_abs_sub4;
acc_abs_sub_ff5 <= acc_abs_sub5;
acc_abs_sub_ff6 <= acc_abs_sub6;
end
end
//generate the enable signal for comp_acc
always @(posedge clk_sys)
begin
if (!rst_n)
comp_acc_en <= 1'b0;
else if (srh_array_end)
comp_acc_en <= 1'b1;
else if (comp_cnt==3'b110)
comp_acc_en <= 1'b0;
end
always @(posedge clk_sys)

abs_sub0;
abs_sub1;
abs_sub2;
abs_sub3;
abs_sub4;
abs_sub5;
abs_sub6;

begin
if (!rst_n)
comp_cnt <= 3'b000;
else if (comp_acc_en)
begin
if (comp_cnt==3'b110)
comp_cnt <= 3'b000;
else
comp_cnt <= comp_cnt + 1'b1;
end
end
always @(comp_cnt or acc_abs_sub_ff0 or acc_abs_sub_ff1 or acc_abs_sub_ff2 or ac
c_abs_sub_ff3 or acc_abs_sub_ff4 or acc_abs_sub_ff5 or acc_abs_sub_ff6)
begin
case(comp_cnt)
3'b000 :
comp_acc_op = acc_abs_sub_ff0;
3'b001 :
comp_acc_op = acc_abs_sub_ff1;
3'b010 :
comp_acc_op = acc_abs_sub_ff2;
3'b011 :
comp_acc_op = acc_abs_sub_ff3;
3'b100 :
comp_acc_op = acc_abs_sub_ff4;
3'b101 :
comp_acc_op = acc_abs_sub_ff5;
3'b100 :
comp_acc_op = acc_abs_sub_ff6;
default :
comp_acc_op = acc_abs_sub_ff0;
endcase
end
always @(posedge clk_sys)
begin
if (!rst_n)
comp_acc_abs <= 14'h3fff;
else if (comp_acc_en)
begin
if (comp_acc_abs >comp_acc_op)
comp_acc_abs <= comp_acc_op;
end
else if (srh_win_end_cnt==3'b111)
comp_acc_abs <= 14'h3fff;
end
//generate the enable signal for srh_win_end_cnt
always @(posedge clk_sys)
begin
if (!rst_n)
srh_win_end_cnt_en <= 1'b0;
else if (srh_win_endb)
srh_win_end_cnt_en <= 1'b1;
else if (srh_win_end_cnt==3'b111)
srh_win_end_cnt_en <= 1'b0;
end
always @(posedge clk_sys)
begin
if (!rst_n)
srh_win_end_cnt <= 3'b000;
else if (srh_win_end_cnt_en)
srh_win_end_cnt <= srh_win_end_cnt + 1'b1;
end

//register the vector collumn

always @(posedge clk_sys)
begin
if (!rst_n)
blk_col <= 3'd0;
else if ((comp_acc_en)&(comp_acc_abs >comp_acc_op))
blk_col <= comp_cnt;
end
//register the first row address of block
always @(posedge clk_sys)
begin
if (!rst_n)
srh_lstartb_ff <= 3'd0;
else if (srh_array_end)
srh_lstartb_ff <= srh_blk_lstartb;
end
//register the vector row
always @(posedge clk_sys)
begin
if (!rst_n)
blk_row <= 3'd0;
else if ((comp_acc_en)&(comp_acc_abs >comp_acc_op))
blk_row <= srh_lstartb_ff;
end
//register the vector address
always @(posedge clk_sys)
begin
if (!rst_n)
begin
vect_row <= 3'd0;
vect_col <= 3'd0;
end
else if (srh_win_end_cnt==3'b111)
begin
vect_row <= blk_row;
vect_col <= blk_col;
end
end
endmodule