HW #2 Analog Integrated Circuits Layout

Problem 1.1
In this problem our goal is to run the DC I-V Simulation of NMOS transistor for W/L = 10/1.6m and to plot the I-V graph and also we need to calculate the channel length modulation () for the above devices. Firstly we will run the DC I-V simulation for NMOS transistor with W/L = 10/1.6m. In this we connect a NMOS of the above mentioned channel length size and then gate to source (Vgs) is connected to the gate of the NMOS whereas the drain to source voltage (Vds) is connected to the drain of the NMOS, body and source is connected to the ground terminal. In the below figure we can see the schematic diagram of the device.

Figure 1: shows the schematic of NMOS with two voltage sources

HW #2 Analog Integrated Circuits Layout

Next we would plot the I-V graph by launching the ADE-L. In this we will run a DC simulation of the above circuit. c

Figure 2: shows the analysis and ADE launcher window In the analyses we choose DC as the option and Vds is selected as the design variable. Once it is done we do a parametric analysis of the above variable and I-V plot is drawn. Which is shown in figure 3.

HW #2 Analog Integrated Circuits Layout

Figure 3: Shows I-V Characteristics of NMOS with W/L= 10/1.6m From the above figure we get to know that for different values of Vgs we get Id vs Vds plot. Channel length modulation lamda () is calculated by taking the slope of the curve in saturation region. First we consider 2 points on purple line that is the Id current at vds X1=5.4; X2=7.4; Y1=355.56A; Y2=357.20A The slope equation is Y = m*X + C Where m = =

Substituting value of m and X1 and Y1 in equation we get C = 7.136 Hence the equation becomes

HW #2 Analog Integrated Circuits Layout

Y- 0.165X= 7.136 Hence at Y=0 the line would meet the X axis at X= -(7.136/0.165) = -43.24

Problem 1.1
In this problem our goal is to run the DC I-V Simulation of NMOS transistor for W/L = 10/10m and to plot the I-V graph and also we need to calculate the channel length modulation () for the above devices. Firstly we will run the DC I-V simulation for NMOS transistor with W/L = 10/10m. In this we connect a NMOS of the above mentioned channel length size and then gate to source (Vgs) is connected to the gate of the NMOS whereas the drain to source voltage (Vds) is connected to the drain of the NMOS, body and source is connected to the ground terminal. In the below figure 4 we can see the schematic diagram of the device

Figure 4: shows the schematic of NMOS with two voltage sources

HW #2 Analog Integrated Circuits Layout

Next we would plot the I-V graph by launching the ADE-L. In this we will run a DC simulation of the above circuit

Figure 5: shows the analysis and ADE launcher window In the analyses we choose DC as the option and Vds is selected as the design variable. Once it is done we do a parametric analysis of the above variable and I-V plot is drawn. Which is shown in figure 6.

HW #2 Analog Integrated Circuits Layout

Figure 6: Shows I-V Characteristics of NMOS with W/L= 10/10m From the above figure we get to know that for different values of Vgs we get Id vs Vds plot. Channel length modulation lamda () is calculated by taking the slope of the curve in saturation region. First we consider 2 points on purple line that is the Id current at vds X1=4.9; X2=6.9; Y1=1.623mA; Y2=1.651mA The slope equation is Y = m*X + C Where m = =

Substituting value of m and X1 and Y1 in equation we get C = 7.136 Hence the equation becomes Y- 0.165X= 7.136 Hence at Y=0 the line would meet the X axis at X= -(7.136/0.165) = -43.24

HW #2 Analog Integrated Circuits Layout

Problem 3
In this problem we need to lay out a resistor using N-well of width W=10 m, length L = 50 m and we use n-active and cc for contacting. Resistor ID is drawn upon the N-well region such that upon extracting the layout the region covering the resistor ID is considered as the resistor and an equivalent resistor is shown in the extracted layout depending upon the length and width of the material used.

Figure 7: shows the resistor layout In the above figure 7 we can see that the resistor ID is marked for width = 10m and length=50m

Figure 8: Shows the extracted layout of resistor In the figure 8 we can see the value of the resistor defined.

Figure 9: Close extracted layout showing the resistor value

HW #2 Analog Integrated Circuits Layout

From the above figure 9 we can see that for W=10m and L=50m we obtained a resistance of 7.325K

Problem 4

Figure : Schematic of BJT with current and voltage source Here in this we have to perform DC analysis of BJT transistor. So for plotting we have to do schematic plot of only BJT transistor with W/L dimensions as given in the question. So the width of the above BJT transistor is taken as 2um and length is taken as 2um as given. The above is the schematic of the BJT transistor and for DC analysis we have to provide dc source at input as well as output. The input acts as vbe i.e. base to emitter voltage and at output acts as vce which is collector to emitter voltage.

HW #2 Analog Integrated Circuits Layout

For performing the DC analysis we have to plot the graph I-V characteristics where in Ic is the collector current and vce is collector to emitter voltage and the graph is plotted between Ic vs vce (plotted in red line). Here the value of vbe has been given as 1 V and at same value the above graph is plotted. It shows that after certain vce the Ic i.e. the collector current saturates and that region is called as linear region in BJT transistors

HW #2 Analog Integrated Circuits Layout

The above graph shows both Ib and Ic plotted. The Ib appears constant because the vbe is which is applied at input is constant. And the current Ic increases exponentially and then saturates. The gain of BJT is found out by Beeta = Ic/Ib Here by the above graph Ic = 1.4857 A and Ib = 54.636 mA Hence beeta = 1.4857/(54.636E-3) = 27.19 Here we have to find early voltage so it can be found out by performing parametric analysis on the schematic. Here on plot we have taken vce on x axis and on y axis we have considered current and at different vbe values we have plotted the graphs of Ic and Ib. Now to find early voltage we consider 2 points on green line that is the Ic current at vbe = 4.333. X1=5 X2=3 Y1=7.80 Y2=7.47 The slope equation is Y-mX=C Where m=(Y1-Y2)/(X1-X2) = 0.33/2 = 0.165 Substituting value of m and X1 and Y1 in equation we get C = 7.136 Hence the equation becomes Y- 0.165X= 7.136 Hence at Y=0 the line would meet the X axis at X= -(7.136/0.165) = -43.24 Hence the early voltage is vce(early) = -43.24 V