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A Cascade Multilevel Frequency Changing Converter for High-Power Applications

Diego E. Soto-Sanchez, Member, IEEE, Rubn Pea, Member, IEEE, Roberto Crdenas, Senior Member, IEEE, Jon Clare, Senior Member, IEEE, and Patrick Wheeler, Member, IEEE

AbstractA novel frequency changing conversion scheme using three cascade multilevel converters in a topology is presented. The scheme resembles a direct frequency converter using the cascade converter in its simplest form (series strings of H-bridge modules equipped with a dc link capacitor) as the building block of the overall converter. This yields a highly modular implementation approach which may be attractive for large power applications such as intertie connections and variable speed drives. Frequency conversion takes place in a cascade converter which connects the input and output ports. Two other converters are placed, respectively, in parallel to the input, to remove unwanted current components from the input, and the output to regulate output voltage. Operation of this topology is explained and a scheme to control all the converters is developed, including control of converter currents, capacitor voltages, and output voltage. Experimental results, using a low-power prototype, conrm the foundations of the topology and verify its overall performance operating as a power supply at typical output frequencies (25 Hz, 162/ 3 Hz and dc) while being fed from a 50-Hz system. Additionally, PowerSIM simulations demonstrate that the topology may be suitable for implementing high-performance, high-power ac drive systems using vector control techniques. Index TermsFrequency conversion, multilevel converter, power conversion.

I. I NTRODUCTION ECAUSE of the limitations of the current generation of power semiconductors devices (voltage and switching frequency), large power converters typically use multimodule topologies such as multipulse and the multilevel converters [1]. In this context, the cascade multilevel converter, as compared to other multimodule converters, is one of the most suitable topologies for very high-power applications [1][8], particularly for static var compensators systems such as StatComs [5][8] and active power lters (APFs) [2], where oating capacitors can implement the multiple isolated dc voltage sources needed.
Manuscript received July 23, 2011; revised October 30, 2011; accepted January 27, 2012. Date of publication April 17, 2012; date of current version February 6, 2013. This work was supported by Fondecyt Chile under Contract 1071136. The support of the Industrial Electronics and Mechatronics Millennium Nucleus is also acknowledged. D. E. Soto-Sanchez is with the Department of Electrical Engineering, University of Magallanes, Punta Arenas 6210427, Chile (e-mail: diego.soto@ umag.cl). R. Pea is with the Department of Electrical Engineering, University of Concepcin, Concepcin 4074580, Chile (e-mail: rupena@udec.cl). R. Crdenas is with the Department of Electrical Engineering, University of Chile, Santiago 8370451, Chile (e-mail: rcd@ieee.org). J. Clare and P. Wheeler are with the Department of Electrical and Electronic Engineering, University of Nottingham, Nottingham NG7 2RD, U.K. (e-mail: jon.clare@nottingham.ac.uk; pat.wheeler@nottingham.ac.uk). Digital Object Identier 10.1109/TIE.2012.2194971

On rst sight, applications which require a cascade converter to process active power (as in the case of a unied power ow controller (UPFC) [9] and a frequency changer converter [10]) may not seem as appealing as the case of a StatCom, if implemented as a back-to-back topology [1]. To maintain isolation among the multiple H-bridge modules, a back-to-back cascade-based topology needs either multiple standard isolation transformers or a complex multiwinding isolation transformer [10][13]. Recently, a non-back-to-back implementation approach, resembling direct ac/ac converter topologies, has led to a new family of cascade-based converters which has become known as the modular multilevel converter (MMC) topology [14][18]. The main feature of an MMC topology is that it uses the cascade converter, or a similar modular converter, as the building block of the main converter topology. In this approach, the cascade converter resembles a high-voltage valve in a standard converter topology, e.g., a series string of H-bridge modules arranged in a single-phase bridge, three-phase bridge or even in a full matrix converter topology. Series strings of half-bridge modules are attractive for ac-dc conversion systems [14] and [17], and a few installations of MMC-based HVDC systems have already been commissioned [19], whereas full-bridge (FB)-based converters seem more attractive for ac-ac conversion [14][16], e.g., cycloconverters. Generalization of this concept, and the realization of the enormous potential it may have in the area of large power converters, is attributed to [14]. However, there were also a few preliminary works that applied cascade converters in a modular fashion. These included a full matrix cascade-based converter [20] and a cascade-based UPFC [21] and [22]. In [21], the cascade converter is intended as the building block of a network of series and parallel elements that could emulate a UPFC. The single series-parallel arrangement proposed in [21] and [22] has a limited operation area when compared to a standard UPFC, but the double series-parallel arrangement in [23] demonstrates feasibility of a fully controllable cascade-based UPFC. In a similar context, a matrix converter applying the ying capacitor converter, and therefore not as modular as the cascade-based matrix converter, was reported in [24]. This paper proposes a novel MMC-based frequency changing converter which, as shown in Fig. 1, uses three cascade converters arranged in a topology. The topology itself follows the idea of implementing a converter as a network of series and parallel elements (in this case two parallel and one series element) and the MMC concept. An alternative interpretation of the topology would be that it corresponds to a special

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cusses the requirements of semiconductor devices and storage capacitors. II. P RINCIPLE OF O PERATION The basic operation of the proposed topology is described in this section. The analysis which follows ignores switching effects. Fig. 1 shows the basis of the proposed new topology; where for simplicity of illustration, each cascade converter uses two H-bridge modules per branch. Clearly, the number of modules can be increased, as required, to meet the voltage rating of a frequency changer in a high-power application. In Fig. 1, the main conversion element is the series converter. This enables exchange of active power from the input, at the input frequency, to the output, at the output frequency, and vice versa. The purpose of the output converter is to support the output voltage, i.e., maintain output voltage as externally demanded, independent of operation conditions. The shunt converter lters out current components which are not at the input frequency and compensates for reactive current at the fundamental input frequency. Note that each converter branch in Fig. 1 is a series string of H-bridge modules equipped only with a capacitor on the dc link. The inductors in series with the shunt and the series converters are interface reactors which, as a StatCom, are added to reduce ripple current due to the switching. For the frequency range of interest, the inductor voltage is small, in comparison with the overall converter voltage, and therefore its effect can be neglected in analysis. Thus, as in a cascade StatCom [5], [6], neglecting converter losses, each H-bridge module, and hence each cascade branch, is constrained to zero active power exchange with the rest of the system in order to avoid divergence of capacitor voltages. The rate of change in the total stored energy in the capacitors of each converter in Fig. 1 corresponds to the instantaneous power exchanged by that particular converter with the rest of the system, as given in dWsh = vs ish dt dWse = (vs vo )ise dt dWpo = vo ipo dt

Fig. 1. Simplied schematic of the proposed frequency changer converter topology. In this arrangement, each module is an H-bridge converter.

case of the FB ac-ac converter [15], where one of the arms has been shorted. Like the FB-MMC converter, advantages of the topology come mainly from its highly modular structure and the use of one of the simplest converter modules to implement it (the H-bridge converter), which may have a signicant impact on the nal cost of a large power installation (manufacture of the Power Electronics Building Block and assembly of the topology on the installation site). Compared to the FB-MMC topology, the topology requires a larger overall power rating in terms of power semiconductor devices and storage capacitors. However, it may require a smaller number of modules. An exhaustive comparison among the various potential MMC topologies for ac-ac conversion is beyond the scope of this work. This paper describes the principle of operation of the topology of Fig. 1 and develops suitable control strategies for the topology to operate as a frequency changer. As recognized in [15] and [16], control of the capacitor voltages, in particular, the balance of capacitor voltages in each converter branch is one of the main issues with these topologies. A novel method which uses a dedicated converter current component to balance capacitor voltages, and which enables a systematic design approach, is proposed. Experimental results, from a low-power prototype, and simulations of the proposed topology applied to the case of a vector-controlled induction machine, validate operation of the proposed topology and its associated control strategies. Because of the similarities with a UPFC, the cascade converter placed between the input and the output ports will be referred to as the series converter, whereas the cascade converters in parallel to the input and in parallel to the output will be referred to as the shunt and output converters, respectively. The remainder of this paper is organized as follows. Section II describes basic operation of the proposed topology, Section III develops a dynamic model of the series converter, with emphasis on capacitor voltages, and proposes a suitable control scheme for regulation of the series bridge capacitor voltages. By extension of the control strategy for the series converter, Section III also describes control strategies for the shunt and output converters. Section IV presents both experimental and simulation results; and nally, Section V briey dis-

(1)

where vs is the input voltage, assumed sinusoidal at frequency s ; vo is the output voltage, assumed sinusoidal at frequency o ; and ish , ise and ipo are, respectively, the shunt, the series, and the output converter current. Wsh , Wse , and Wpo are, respectively, the total stored energy in the capacitors of the shunt, the series, and the output converter. For the case of Fig. 1, Wconv , with conv = {sh, se, po}, is given in c 2 2 v (2) + vC Wconv = 2conv 2 C 1conv where C is the capacitance of the dc storage capacitor of the H-bridge module (assumed the same for all the H-bridge modules); and vc1conv and vc2conv are the capacitor voltage of capacitor C1conv and C2conv , respectively.

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In general, the converter currents in (1) can be set to contain two components, one at frequency s , the s-component, and another at frequency o , the o-component. These components can be further resolved into an in-phase component and a quadrature component, - and -component, respectively. Thus, converter currents can be expressed as given in
s o o ish = is sh + ish + ish + ish s o o ise = is se + ise + ise + ise s s o ipo = ipo + ipo + ipo + io po

(3)

s where is conv and iconv , with conv = {sh, se, po}, are, respectively, the component of iconv in-phase and in-quadrature to vs . o Similarly, io conv and iconv are, respectively, the component of iconv in-phase and in-quadrature to vo . In steady state,

Wconv = W conv + Wconv

(4)

where W conv and Wconv , with conv = {sh, se, po}, are, respectively, the dc component and the ripple component of Wconv . In general, Wconv may contain components at frequencies 2s , (s o ), (s + o ) and 2o . For stable operation, W conv is kept at a constant and sufciently high value, hence sufciently high total capacitor voltage (vCT conv = vC 1conv + vC 2conv ), to manipulate the converter currents. The dynamics of the capacitor voltages, in terms of W conv , can be written as dW sh = Psh dt dW se = Pse dt dW po = Ppo dt

Fig. 2. Steady-state operation of the proposed topology; simulated voltage and current waveforms in the: (a) supply, (b) load, (c) series converter, (d) shunt converter, and (e) output converter.

(5)

where Psh , Pse , and Ppo are, respectively, the active power exchanged by the shunt, the series and the output converter. Manipulation of W conv requires a net exchange of energy, hence active power, from/to the system to/from the capacitors. In steady state, dW conv /dt = Pconv = 0. Therefore, as anticipated, for stable operation, each converter branch is constrained to zero active power exchange. For the converter of Fig. 1, the following equations apply:
s Psh = Vs Ish =0 s o =0 Pse = Vs Ise Vo Ise o =0 Ppo = Vo Ipo

(6)

where Vo and Vs are, respectively, the amplitude of vs and vo . s o is the amplitude of is Iconv conv , and Iconv is the amplitude of o iconv , where conv = {sh, se, po}. Note that in (6)Psh = Ppo = 0, therefore, the balance of active power in the series converter, second equation in (6), corresponds to the balance between the input (supply) power, Ps , and the output (load) power, Po . For stable operation, the series converter is therefore required to draw a current component from the supply such as it balances the power demanded by the load. This current component corresponds to is se in (3), s ), as described in Section III, is set by and its amplitude (Ise

a dc capacitor voltage regulator system. In simple terms, this s so that, for a given Po , corresponds to the manipulation of Ise o represented by Vo Ise in (6), Pse is kept to zero. Regulation of capacitor voltages of the shunt and output converter are implemented in a similar way to that of the series converter but s o and Ipo , respectively. by manipulating Ish To illustrate operation of the proposed converter, Fig. 2 shows the voltage and current waveforms in all converter branches for a given operation condition. For simplicity, the output voltage is set to the same amplitude as the supply voltage (Vo = Vs ) while the frequency is set to half of the supply frequency (25 Hz considering the converter is supplied from a 50-Hz supply). As shown in Fig. 2, the load current is assumed to be in phase with the output voltage. The amplitude of the 50-Hz current component of the series converter, hence supply current, that balances the load power (due to the 25-Hz output voltage and current) can be calculated as given in (7), which follows from (6). In this particular case, (7) yields a supply current of the same amplitude as the load s o = Ise = Io ), where Is is the amplitude current (i.e., Is = Ise of the supply current
s = Ise

Vo o I . Vs se

(7)

The resulting series converter current, along with the series converter voltage, is shown in Fig. 2(c). Note that both series voltage and current are complex waveforms which, in this case, contain a 50-Hz component, due to the supply, and a

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25-Hz component, due to the load. Because the shunt converter bypasses the 25-Hz current component, the line current in Fig. 2(a) is sinusoidal and in phase with the supply voltage. Note that in Fig. 2(d), the shunt converter current is at 25 Hz whereas its voltage is at 50 Hz. Thus, the shunt converter in Fig. 1 does not exchange active power with the system. Similarly, the output converter bypasses the 50-Hz current component while its voltage is at 25 Hz, Fig. 2(e). III. M ODELING AND C ONTROL This section develops suitable control strategies to regulate the capacitor voltages in all three cascade converters, control the current through the series and shunt converters, and set the output voltage of the output converter. In controlling the converter topology of Fig. 1, one of the main issues is regulation of capacitor voltages. Balance of active power between the supply and load power is an implicit requirement for the controller. To derive a suitable control scheme, the dynamics of the capacitor voltages must rst be addressed. To this end, a dynamic model of the series converter is developed next. A. Model of the Series Converter In analyzing the series converter dynamics, the following assumptions are made. The voltage/current component x and y are considered to be orthogonal if the mean, or average, value of its dot product over a certain period of time, assumed much smaller than the time constants governing the dynamics of the capacitor voltages, is zero. The instantaneous current ise closely follows its demand; therefore, dynamics of converter current can be neglected. Good tracking of the current is ensured by a suitable current control loop. The series inductor voltage is negligible. Assuming that deviations in capacitor voltages, from the balanced condition, are small, i.e., vC 1se = vC 2se VC , the dynamics of the capacitor voltages can be represented by dvC 1se v1se ise = dt CVC v2se ise dvC 2se = . dt CVC

ise can be resolved into the following three components: 1) is se , a component which is in phase with the input voltage; 2) io se , a component which is at the output frequency and it corresponds, in principle, to the load current; and 3) ibal , a component which will be referred to as the balance component and it is at the input frequency, but in quadrature to vs
o ise = is se + ise + ibal .

(10)

The component is se is used to control overall capacitor voltage; whereas ibal is needed to implement balancing of the capacitor voltages. Similar to the converter current ise , each H-bridge converter voltage contains one component at the input frequency and another at the output frequency (both set so that vs and vo are equally shared among all converters in the branch). In addition, there is a component which is in phase with the balance current component ibal . This voltage corresponds to bal which is controlled according to the balance component, vse a voltage equalization system. For the cascade series converter of Fig. 1, the H-bridge converter voltages are set as given in (11).The general case of a series converter having N modules, where N is the number of H-bridge modules, is explained in Appendix 1 bal v1se = (vs vo ) + vse 2 1 bal v2se = (vs vo ) vse . 2

(11)

Using (9), (10) and (11) in (8), and then taking the mean value, the capacitor voltage dynamics can be represented by dVCT se 1 s o = (Vs Ise Vo Ise ) dt 2CVC dVCse 1 bal = Ibal Vse dt CVC (12)

(8)

In a cascade converter, regulation of the capacitor voltages is typically implemented as the regulation of the overall capacitor voltage and equalization of all capacitor voltages in the string, as given in (9) for the case of Fig. 1 vCT se = vC 1se + vC 2se vCse = vC 1se vC 2se . (9)

bal where Vse is the amplitude of voltage injected as a balance component in (11) and Ibal is the amplitude of the balance current component, set constant at a small fraction of the nominal input current, but sufciently high to ensure proper equalization of capacitor voltages. For example, as given in (13) (20% of nominal input current). Remaining voltages and currents in (12) are as in (6) (13) Ibal = 0.2 2Inom_s

where Inom_s = Pnom /Vnom_s and Vnom_s and Pnom are, respectively, the nominal input voltage (RMS amplitude), and the nominal power of the converter. B. Control of the Series Converter From (12), considering that the load current is set by external conditions, it follows that the overall capacitor voltage VCT se s can be regulated by adjusting Ise ; whereas voltage deviation bal VCse can be controlled by adjusting Vse . Adjustment of s bal Ise and Vse can be accomplished in a closed-loop fashion using proportional integral (PI) controllers. Fig. 3 summarizes

Capacitor voltages are regulated by manipulating the converter current, ise and converter voltages v1se and v2se using a similar approach to that proposed in [25] for a cascade StatCom. For the case of Fig. 1, as given in (3), ise can be set to contain four orthogonal components. Setting is se = ibal o o in (3) and noting that io = i + i yields (10). Therefore, se se se

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Fig. 3. Simplied control system block diagram for the series converter.

Fig. 4. Simplied equivalent control system block diagram for the series converter including the dynamic model of the capacitor voltages.

implementation of this strategy, including the overall capacitor voltage controller, the current controller, and the subsystem for the equalization of capacitor voltages. Assuming load power, Po behaves as an external disturbance, design of the control system for capacitor voltages is straightforward. Fig. 4 shows the block diagram of the equivalent system which represents the dynamics of the capacitor voltages in (12) and the controller of Fig. 3. Controller gains can be chosen so that resulting system (i.e., PI controller plus rstorder plant) behaves as a second-order system with a specied natural frequency, n and a damping factor = 0.707. Tracking of the reference current i se is accomplished by a dead-beat controller [26]. To minimize coupling with the capacitor voltage control loops, the voltage needed to impose the demanded current (voltage demand set by the dead-beat current controller, vlse in Fig. 3) is equally shared among all converter modules. To improve performance, load current io is measured and added as a feedforward term to the reference input of the series current controller. In Fig. 3, us and ubal are sinusoidal signals of unity amplitude which are, respectively, in phase to vs and in phase to ibal . s These signals shape the output from the PI controllers (Ise bal and Vse ) into the appropriate voltage reference and current reference waveforms.

Fig. 5.

Simplied control system block diagram for the output converter.

C. Control of the Output Converter The main purpose of the output converter is to set the output voltage as demanded by external means, e.g., a master controller. Providing that the capacitor voltages are kept at a sufciently high value, the output converter will be able to set its voltage demand independent from the output current, if kept within practical limits. Control of capacitor voltages vC 1o and vC 2o is accomplished in a similar way to that of the series converter. However, the output converter current is not forced by the output converter itself but by the series converter. Fig. 5 shows the control scheme of the output converter. To control the overall capacitor voltage of the output converter, a current component which is in phase with vo , denoted as io po , is forced through the series converter, and by this means through the output converter. Note in Fig. 3 that io po is fed forward into the reference input of the series current controller. A PI controller, driven by voltage error in the overall capacitor voltage, adjusts the magnitude of io po . Equalization of vC 1o and vC 2o is achieved in a similar way to that shown in Fig. 3. The balance current ibal , which is forced by the series converter,

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is in this case bypassed by the output converter, and it can therefore be used, as in the case of the series converter, to equalize vC 1o to vC 2o . D. Control of the Shunt Converter Control of the shunt converter is similar to that of a parallel APF which operates in the power factor correction mode [27]. The main purpose of this converter is to compensate for the input of the frequency changer so that it draws a current, not only at the fundamental input frequency, but also in phase with the input voltage. For this, all current components which are forced by the series converter, with exception of that in phase with vs , must also be forced through the shunt converter, but in the opposite direction. Thus, ibal , io po , and io are fed forward into the reference input of the shunt converter current controller. Note that in this way, ibal is kept owing inside the loop provided by the topology, thus preventing it from owing into the input or into the output. In addition to ibal , io po , and io , a current component which is in phase with vs , and whose amplitude is set by an overall capacitor voltage controller of the shunt converter, is forced through the shunt converter. Equalization of the capacitor voltages in the shunt converter is achieved in a similar way to that shown in Fig. 3. IV. S IMULATION AND E XPERIMENTAL R ESULTS To validate the proposals, topology, and associated control strategies, a low-power single-phase experimental prototype system was built and tested. In addition, PowerSIM (PSIM) simulations of a vector-controlled induction machine drive system applying the proposed converter were conducted. Experiments are intended to demonstrate system performance under load impact for different conditions of output frequency. PSIM simulations illustrate capability of the proposed frequency changer to force fast dynamic currents on an induction motor (both in amplitude and phase, hence frequency), as is typically required during a fast reversal of speed in a vector-controlled induction machine drive system. The experimental prototype uses six H-bridge modules, as shown in Fig. 1, and is controlled using a DSK 6713 DSP system equipped with a daughter card that implements an analog interface and PWM units. Switching frequency of the H-bridge modules is set to 1.0 kHz. The parameters and ratings of the experimental prototype are listed in Table I. Note that the series converter requires being rated at twice the nominal input voltage (assuming equal nominal input and output voltage). This is twice the voltage rating required by the shunt and output converter. Therefore, each module of the series converter, as compared to one of the shunt and output converter, requires twice as much dc voltage. Making a small allowance for the inductor voltage, the dc voltage of the H-bridge modules of the series, shunt, and output converter were chosen to be 50 V, 30 V, and 30 V, respectively. Parameters of all six PI-based capacitor voltage controllers (i.e., overall voltage and voltage balance controllers of the shunt, the series, and the output converters) are chosen so that simplied dynamic model of capacitor voltages plus PI controller has a response time of 200 ms. Forcing of the converter

TABLE I P ROTOTYPE R ATINGS

current, both in the series and shunt converters, is based on the use of a dead-beat controller, as shown in Fig. 3. A. Experimental Results for Load Impact Tests This section presents the system response to load impacts when the experimental prototype operates as a voltage source of a constant magnitude and frequency, i.e., as a power supply. Experiments were conducted for an output frequency of 25 Hz, 162/3 Hz and dc, which are typical in locomotive systems, for example [28], [29]. In each test, a switched R-L load is used to apply load steps from zero to full load and back again. Results shown in Figs. 68 correspond to tests undertaken at 25 Hz, 162/3 Hz and dc, respectively; showing: line voltage and current; reference output voltage and load current; shunt and series converter currents; and dc link capacitor voltage of each H-bridge module in the prototype system. These results are system voltages and currents as sampled, every 500 us, by the DSP-based control system. Therefore, Figs. 68 do not generally show switching effects such as ripple current. Experimental steady-state converter voltage and current waveforms, as captured by a digital scope, for the case of 25 Hz output are shown in Fig. 9. Fig. 6 shows the system response for the case of 25-Hz output. As can be seen from Fig. 6, following the load impact, the capacitor voltages of both series H-bridge modules vC 1se and vC 2se start dropping but, after approximately 50 ms, the voltages begin to recover from the load impact, exhibiting only a small voltage drop before stabilizing again to the reference voltage. As expected from the design specications, the recovery takes place within 200 ms. Concerning balance of capacitor voltages, Fig. 6 reveals that the strategy for the equalization of capacitor voltages has such a good performance that, even during transients, it is hard to distinguish between the two capacitor voltages in Fig. 6 (deviation between capacitor voltages is less than 1 V). In regard to capacitor voltage of the shunt and output converters shown in Fig. 6, following the load impact, with the exception of a small increase in voltage ripple, there is no noticeable disturbance in the capacitor voltages. This conrms the benet of feeding forward the measured load current into

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Fig. 6. System response to a load impact when the frequency changer operates as a power supply at 25-Hz output.

Fig. 7. System response to a load impact when the frequency changer operates as a power supply at 162/3 Hz output.

the series and shunt current control loops and also indicates that most of the impact, because of a load disturbance, is absorbed by the capacitors of the series converter. Fig. 6 also shows the supply voltage and current along with the reference output voltage and load current. As expected, consistent with a relatively slow series capacitor voltage controller, following the load impact, the line current increases slowly, to compensate for the loss of stored energy in the series capacitors, reaching a small overshoot, close to the current limit, before stabilizing to a current which is well within rated current and that balances the active power demanded by the load.

Note that soon after the load is switched on, the series and shunt converters start drawing larger currents. This is consistent with the use of the load current as a feedforward term and therefore conrms that the load current component is being rapidly forced through the series and shunt converters. Note also that the supply current is nearly sinusoidal and in phase with the line voltage, even during transients, thus conrming that the output frequency current component is effectively cancelled from the line current by the shunt converter. Fig. 7 shows similar results to that of Fig. 6 but for operation at 162/3 Hz. As it can be seen from this gure, system response,

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Fig. 8.

System response to a load impact when the frequency changer operates as a dc power supply.

in terms of capacitor voltages and line current, is very similar to that of Fig. 6. As expected, because of the different output frequency, the main differences from Fig. 6, in addition to the output voltage and load current, are in the series converter and shunt converter currents, which now contain a 162/3 Hz component. Notwithstanding the exact current waveform, the converter currents in Fig. 7 show similar dynamic performance to those in Fig. 6 (e.g., overshoot, rise and stabilization time), and they are all maintained well within normal operation values. Fig. 8 shows the system response to a load impact when the proposed topology operates as a dc power supply. Note that, in comparison to Fig. 6, the voltage magnitude in Fig. 8 has been reduced to 75% of rated output voltage; otherwise the R-L load would have demanded approximately twice as much power and hence 50-Hz current from the line than in Fig. 6. As experimentally conrmed, but not shown here, the series converter current hits the limit current, and after a short period of operation at current limit, the system trips because it is unable to control the series capacitor voltages. Nevertheless, the results in Fig. 8 show that for a dc output, the system is also able to rapidly reject the load disturbance, keeping a stable and well-regulated dc link voltage and all converter currents within normal operation conditions. One interesting feature in Fig. 8 is that it clearly shows that both the series and shunt converter currents contain, as expected, a 50-Hz and dc component. In general, the system performance when the R-L load is shed from the output, as seen in Figs. 68, is very similar to that when the load is switched on. In the main, following disconnection of the load, the capacitor voltages in the series converter show a small increase before they start recovering to the reference value within 200 ms. Capacitor voltages maintain balance, even during the transient, and the supply current, as dictated by the series capacitor voltage controller, gradually decreases to the no-load condition.

To further conrm operation of the proposed topology, Fig. 9 shows steady-state converter voltage and current waveforms of all three converters following the load impact of Fig. 6. As it can be seen from Fig. 9(a), the supply current is nearly sinusoidal and in phase with the line voltage. Output voltage shown in Fig. 9(b) is a ve-level sinusoidal PWM voltage waveform which results in a nearly sinusoidal load current. Results in Fig. 9(a), in terms of compensation for distortion and power factor in the supply, also conrm a good performance of shunt converter and its control strategy. Fig. 9(c) shows the overall series converter voltage and current. Note that the PWM voltage in Fig. 9(c) is not as regular as that of Fig. 9(b); recall that the series converter must impose a voltage with a relatively large 50-Hz and 25-Hz component. Similarly, because of the load, the series converter current is a complex waveform which, as expected, contains components at 50 Hz and 25 Hz, Fig. 9(c). Fig. 9 also shows the voltage across and the current both through the shunt converter [Fig. 9(d)] and the output converter [Fig. 9(e)]. Like the series converter current, the shunt converter current contains components at 50 Hz and 25 Hz. The 50-Hz component corresponds mainly to the quadrature balance current component (needed for balancing capacitor voltages), whereas the 25-Hz component corresponds to the load current that the shunt converter bypasses to prevent it from owing into the supply. For the case of Fig. 9(d), the quadrature balance current component is small, compared to the 50-Hz series converter current component that balances the load, thus the shunt converter current appears to be dominated by the 25-Hz component. In contrast to Fig. 9(d), the output converter current in Fig. 9(e) is clearly dominated by the 50-Hz component. This demonstrates that the 25-Hz component needed to regulate the output capacitor voltages, because of the converter losses, is actually very small. In summary, results in Fig. 9(d) and (e)

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TABLE II R ATINGS OF S IMULATED C ONVERTER

TABLE III PARAMETERS OF S IMULATED M OTOR

Fig. 9. Steady-state results for 25-Hz output: (a) line voltage and current; (b) load voltage and current; (c) series converter voltage and current; (d) shunt converter voltage and current, and (e) output converter voltage and current. Scales (1): 40 V/div, 5 A/div. Note (1): In the scope, the current is scaled so that it has smaller amplitude than its corresponding voltage.

conrm that both the shunt and output converters are behaving very effectively as bypass lters for the 25-Hz and 50-Hz component, respectively. Furthermore, the output converter is able to impose a high quality sinusoidal PWM voltage, as demanded by the control system (constant amplitude and frequency in this case), on the load. B. Simulation Results for a Drive System To further verify potential applications for the proposed converter system and to illustrate expected performance, a simulation of vector-controlled induction machine drive, employing the proposed converter conguration has been implemented in PSIM. To illustrate dynamic performance, the simulation has been run to investigate speed reversal transients. The vector control scheme uses an indirect ux-oriented control technique, with d-axis aligned to an estimated-rotor ux position [30].

The machine is fed by a three-phase version of the frequency changer in Fig. 1. This comprises three single-phase units, using two H-bridge modules per branch, in a star connection. The simulated machine is a 4.5 kW/380 V, 50-Hz, four-pole induction motor. Parameters and ratings of the motor and frequency changer are listed in Tables II and III, respectively. The d- and q -axis motor current control loops use PI controllers and cross compensation to improve decoupling [25]. Parameters were chosen for a closed-loop frequency response of 667 rad/s (rise time of 5 ms). The speed controller is based on a PI controller and its parameters were chosen for a closedloop frequency response of 33 rad/s. Current limitation was set to twice rated motor current (2 2 10 30 A). In regard to the control system of the frequency changer, d- and q-axis voltage demands from motor current controller are transformed back into the phase coordinate system and used as reference inputs to the control system of Fig. 3, one for each phase. Capacitor voltage controllers, both overall capacitor voltage and voltage balance, are designed to the same specication as the experimental prototype, i.e., 200-ms response time. Series and shunt converter current control loops are the same as those of the experimental system. Fig. 10 shows the simulated system response to a speed change from 750 RPM to +750 RPM. For the speed reversal of Fig. 10, as in a typical vector-controlled motor drive system, the motor speed steadily rises to the reference speed while the motor currents limited to the maximum transient rating to achieve as much braking and then acceleration torque as possible. Therefore, in controlling an induction motor, Fig. 10 demonstrates that the proposed frequency changer can achieve the same performance as a vector-controlled drive system that employs a standard PWM converter. As far as operation of each converter is of concern, as in the case of the load impact in Fig. 6, the series capacitor voltages show only a small disturbance during reversal of speed

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particular case, during braking, most of the stored energy in the inertia of the motor was actually dissipated by the frictional load, and only a small fraction was delivered back to the line. Results shown in Fig. 10 therefore conrm that the proposed frequency changer can be used to replace a standard back-toback-based frequency changer. The modularity of the system also lends itself to use at high powers. V. VA R ATING AND C APACITOR R EQUIREMENTS This section briey discusses the requirements of: 1) power semiconductor devices; 2) dc capacitor lter on the H-bridge module; and 3) interface inductors of the PI topology. The requirements of power semiconductor devices are typically expressed in terms of the total VA rating of the devices (i.e., voltage rating current rating of the devices) needed to implement the converter. This measure is useful when comparing to alternative converter topologies. In this case, the PI topology will be compared to the FB-MMC topology [15]. For this, it is sufcient to consider the converter voltage and current waveforms and to examine their maximum and minimum values (peak values). For the converter current, a more useful measure of the current capability of the devices, instead of the peak value or RMS value, is the average of the absolute value of the current [15]. The comparison is made for the operation condition plotted in Fig. 2. This corresponds to nominal input and output voltage, at 50 Hz and 25 Hz, respectively, and nominal output current and at unity power factor. The voltage and current of each arm of the FB-MMC are given in (14)[15], where the subscript i = {1, 2, 3, 4} denotes the i th arm of the topology
Fig. 10. Response to a speed reversal command from 750 rpm to 750 rpm.

va1 = va4 = va2 = va3

(a small increase toward the end of acceleration), whereas the shunt and output capacitor voltages show only a small increase in voltage ripple. Furthermore, capacitor voltages in all the converter branches maintain good balance. Note that the two shunt capacitor voltages and the two output capacitor voltages are all plotted together in Fig. 10. Close examination of Fig. 10 reveals there is subtle difference in voltage ripple between the shunt and output capacitor voltages. Note also that the series and shunt converter currents follow a similar prole to the motor currents and that they keep well within the transient converter ratings. As expected, the line currents are nearly sinusoidal and in phase with their respective line voltages. Following the speed reversal command, the line currents start decreasing from their pre-disturbance values, reversing phase, and hence direction of the power ow for a while, but reaching only a small amplitude. This contrasts with the line currents during acceleration, when the frequency converter draws relatively large currents, and hence power, from the line to rapidly deliver accelerating power to the motor. This difference can be explained by the type of load being driven by the motor (a frictional load in this case) which aids braking. From these results, it can be concluded that in this

1 1 (vs vo )ia1 = ia4 = (is + io ) 2 2 1 1 = (vs + vo )ia2 = ia3 = (is io ). 2 2

(14)

For the case of Fig. 1, it can be shown that a good approximation of each converter voltage and current is as given in vsh = vs ish = io

vse = (vs vo ) ise = (is + io ) vpo = vo iop = is . (15)

Calculation of the peak values of the voltages in (14) and in (15), as well as the average of the absolute value of the currents, shows that each arm of the FB-MMC, as compared to the series converter, requires to be rated at half the current and half the voltage. Therefore, the series converter alone requires the same amount, in terms of VA rating, of semiconductor devices as the FB-MMC. The shunt and output converter further increase this requirement, when considering the average of the absolute value of the shunt and output converter current, to almost twice as much. Capacitor requirements, in terms of energy storage, can be determined by calculating the maximum amplitude of the ripple

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on the stored energy over a period (T ) of the instantaneous power, as given in tf vidt (16) W = maxti ,tf
ti

rate of change of converter current under abnormal operation conditions (e.g., ac system disturbances). The current rating of the inductors is dictated by the total RMS current. In the case of the series inductor, the current rating, considering the is se and io se components, is
o (is se + ise )RM S = 2 2 IsRM S + IoRM S =

where ti and tf are the instants at which the stored energy reaches its maximum and minimum values, respectively. The capacitance of the storage capacitors is typically specied so that they limit W to a small fraction of the dc component of the stored energy. For the purpose of a comparison, the actual value of the capacitance and the voltage rating of the capacitor are not required. Given the allowed rW , W can be calculated using (17). The larger W , the larger W , and therefore, the larger capacitance that the H-bridge module will require (assuming a given dc-side voltage rating). Therefore, W can be used as a measure of capacitor requirements rW = W . W (17)

2Inom_s

(18)

where Is_nom is the amplitude of the nominal input current. Insulation voltage level, neglecting the switching nature of converter voltages (which is typically small in multilevel waveforms), is set by the sinusoidal input voltage vs . Therefore, the inductor winding does not require reinforced insulation. VI. C ONCLUSION A novel frequency changer topology using the multilevel cascade converter in its simplest form (a series string of H-bridge modules equipped with a capacitor on each dc link) has been proposed. In this topology, the cascade converter, hence the H-bridge module is used as a building block. This enables a modular implementation approach in which voltage rating, hence power rating, can be readily extended to higher values by adding as many H-bridge modules as needed to meet voltage and power ratings of the application. The proposed frequency changer can provide high quality output voltage waveforms and can draw low distortion current from the line, at close to unity power factor, thus facilitating interfacing to the load and the line. The various control strategies needed to successfully operate the proposed topology as a frequency changer have been developed and presented. This includes schemes which are suitable for: regulation of all capacitor voltages; tracking of the series and shunt converter currents; and setting of the output voltage. One of the main issues of the topology is regulation of capacitor voltages. This is accomplished in the form of regulation of overall capacitor voltage of a branch and by balancing of the individual capacitor voltages of each particular branch. Operation of the proposed topology as a power supply with a specied output voltage magnitude and frequency was successfully demonstrated in a practical prototype. Experiments with load impacts, at various values of output frequency, demonstrate that the system (proposed topology and its associated control strategies) has an excellent performance in rejecting load disturbances. In terms of mitigation to a load impact, the proposed topology exhibits only a small impact in the series capacitor voltages while keeping all the converter currents within normal operating conditions. Furthermore, it draws sinusoidal current from the line, at close to unity power factor; and it provides an adequate support to the output voltage during the impact. Preliminary results, from PSIM simulations of a vectorcontrolled induction machine, fed by the proposed frequency changer, demonstrate such a drive can achieve similar performance to a vector-controlled drive equipped with a standard PWM converter. Therefore, the proposed converter may be suitable for high-performance induction machine drives in a range of high-power applications.

Calculation of (16) using the voltages and currents in (14) and (15) shows that the series converter alone has the same capacitor requirements as the FB-MMC. Additional storage capacitors in the shunt and series converter increase this requirement to ve times as much. This signicant increase is largely explained by the reduction in the frequency of the power oscillation of the shunt and output converter (half the frequency of the power oscillations in the series converter). In general, selection of the capacitors is largely dictated by the low frequency oscillation component of the instantaneous power. The lower the frequency, the larger the capacitors required to maintain the ripple on the stored energy low. Low frequency power oscillations occur when o is small or when o is close to s Unless a low frequency modulation of the input current is allowed, to supply the low-power oscillation from the input, operation at low output frequency or close to the input frequency should be avoided. This may not apply to the case of a variable speed motor drive if its nominal frequency is smaller than the input frequency. In this case, the power demand, hence the amplitude of the power oscillations, reduces with reducing operation frequency, and therefore, power oscillations could be supplied from the capacitors, without incurring into a signicant ripple capacitor voltage. Compensation for the power oscillations among the three phases of three-phase converter, for example by injecting zero sequence voltage and current components, is currently being investigated. The interface inductors in Fig. 1 are primarily intended to limit the ripple current due to the switching. In a standard converter which interfaces to the grid, operating at a switching frequency of a few kHz, the impedance of the inductor (at the fundamental frequency), as compared to the base impedance of the converter (Zbases_s = Vnom_s /Inom_s ), is typically in the order of 5%15%. In a multilevel converter having a number of H-bridge modules, each switching a few hundred Hz, because of the higher quality of the output voltage, the inductance of the inductor can be reduced. However, it may still be practical to use an inductor in the order of 10% to help reducing the

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A PPENDIX This Appendix describes implementation of the voltage balance scheme for a series converter having N H-bridge converter modules. In this case, (N-1) capacitor voltage deviations, with respect to the average capacitor voltage, are dened as given in (19). Each voltage deviation, vCise , is fed into a dedicated PI controller. The output of each PI controller corresponds to bal , which is the amplitude of the voltage balance component, vise injected into the corresponding H-bridge converter module, as given in (20). Note that the voltage balance component of the Nth H-bridge module is calculated so that all voltage balance components sum to zero. This decouples regulation of the total capacitor voltage from the balancing of the N capacitor voltages vCise = vCise vise =
bal vise =

1 N

vCise
i=1

(19)

1 bal (vs vo ) + vise i = 1, 2, . . . , N N V u i = 1, 2, . . . (N 1) ibal bal

N 1 i=1

Vibal ubal

i = N.

(20)

The control system of Fig. 3 requires two PI controllers for controlling the two capacitor voltages of the series converter, one to regulate the total capacitor voltage and the other to balance the two capacitor voltages. An N H-bridge module series converter, in addition to the PI controller which regulates the total capacitor voltage, requires (N-1) PI voltage balancing controllers, each one setting the corresponding voltage balance component. A similar method, as that given in (19) and (20), applies to a shunt and output converters having N H-bridge modules. R EFERENCES
[1] D. Soto and T. C. Green, A comparison of high-power converter topologies for the implementation of FACTS controllers, IEEE Trans. Ind. Electron., vol. 49, no. 5, pp. 10721080, Oct. 2002. [2] J. Rodriguez, J.-S. Lai, and F. Z. Peng, Multilevel inverters: A survey of topologies, controls and applications, IEEE Trans. Ind. Electron., vol. 49, no. 5, pp. 724738, Aug. 2002. [3] S. Kouro, M. Malinowski, M. K. Gopakumar, K. J. Pou, L. G. Franquelo, B. Wu, J. Rodriguez, M. A. Prez, and J. I. Leon, Recent advances and industrial applications of multilevel converters, IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 25532580, Aug. 2010. [4] S. Vazquez, J. I. Leon, J. M. Carrasco, L. G. Franquelo, E. Galvan, M. Reyes, J. A. Sanchez, and E. Dominguez, Analysis of the power balance in the cells of a multilevel cascaded H-bridge converter, IEEE Trans. Ind. Electron., vol. 57, no. 7, pp. 22872296, Jul. 2010. [5] F. Z. Peng, J.-S. Lai, J. McKeever, and J. VanCoevering, A multilevel voltage-source inverter with separate dc sources for static VAr generation, IEEE Trans. Ind. Appl., vol. 32, no. 5, pp. 11301138, Sep./Oct. 1996. [6] J. D. Ainsworth, M. Davies, P. J. Fitz, K. E. Owen, and D. R. Trainer, Static VAr compensator (STATCOM) based on single-phase chain circuit converters, Proc. Inst. Elect. Eng.Gener. Transm. Distrib., vol. 145, no. 4, pp. 381386, Jul. 1998. [7] W. Song and A. Q. Huang, Fault-tolerant design and control strategy for cascaded H-bridge multilevel converter-based STATCOM, IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 27002708, Aug. 2010. [8] A. Yazdani, H. Sepahvand, M. L. Crow, and M. Ferdowsi, Fault detection and mitigation in multilevel converter STATCOMs, IEEE Trans. Ind. Electron., vol. 58, no. 4, pp. 13071315, Apr. 2011. [9] B. A. Renz, A. Keri, A. S. Mehraban, C. Schauder, E. Stacey, L. Kovalsky, L. Gyugyi, and A. Edris, AEP unied power ow controller performance, IEEE Trans. Power Del., vol. 14, no. 4, pp. 13741381, Oct. 1999.

[10] P. K. Steimer, H. E. Gruning, J. Werninger, and D. Schroder, State of the art verication of the hard driven GTO inverter development for a 100 MVA intertie, IEEE Trans. Power Electron., vol. 13, no. 6, pp. 1182 1190, Nov. 1998. [11] J. Rodrguez, L. Morn, J. Pontt, J. L. Hernndez, L. Silva, C. Silva, and P. Lezana, High-voltage multilevel converter with regeneration capability, IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 839846, Aug. 2002. [12] A. Rufer, N. Schibli, C. Chabert, and C. Zimmermann, Congurable front-end converters for multi current locomotives operated on 16 2/3 Hz ac and 3 kV dc systems, IEEE Trans. Power Electron., vol. 18, no. 5, pp. 11861193, Sep. 2003. [13] B. Han, B. Bae, S. Baek, and G. Jang, New conguration of UPQC for medium-voltage application, IEEE Trans. Power Del., vol. 21, no. 3, pp. 14381444, Jul. 2006. [14] A. Lesnicar and R. Marquardt, A new modular voltage source inverter topology, in Proc. EPE, Toulouse, France , 2003. [15] M. Glinka and R. Marquardt, A new ac/ac multilevel converter family, IEEE Trans. Ind. Electron., vol. 52, no. 3, pp. 662669, Jun. 2005. [16] M. Hagiwara and H. Akagi, Control and experiment of modular multilevel converters, IEEE Trans. Power Electron., vol. 24, no. 7, pp. 1737 1746, Jul. 2009. [17] S. Allebrod, R. Hamerski, and R. Marquardt, New transformerless, scalable, modular multilevel converters for HVDC transmission, in Proc. PESC, Rhodes, Greece, 2008, pp. 174179. [18] S. Rohner, S. Bernet, M. Hiller, and R. Sommer, Modulation, losses, and semiconductor requirements of modular multilevel converters, IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 26332642, Aug. 2010. [19] T. Westerweller, K. Friedrich, and U. Armonies, Trans Bay Cableworlds rst HVDC system using multilevel voltage-source converter, presented at the CIGRE, Paris, France, 2010. [20] R. W. Erickson and O. A. Al-Naseem, A new family of matrix converters, in Proc. IECON , 2001, pp. 15151520. [21] D. W. Sandells and T. C. Green, The chain cell PFC (power ow controller), in Proc. PESC, 2000, vol. 2, pp. 955960. [22] J. Wang and F. Z. Peng, A novel conguration of a unied power ow controller, in Proc. APEC, 2003, pp. 919924. [23] D. Soto, R. Pena, F. Gutierrez, and T. C. Green, A new power ow controller based on a bridge converter topology, in Proc. PESC, Aachen, Germany , 2004, pp. 25402545. [24] Y. Shi, X. Yang, and Q. He, Research on a novel capacitor clamped multilevel matrix converter, IEEE Trans. Power Electron., vol. 20, no. 5, pp. 10551065, Sep. 2005. [25] D. Soto, R. Pena, and P. Wheeler, Decoupled control of capacitor voltages in a cascade PWM StatCom, in Proc. PESC, Rhodes, Greece, 2008, pp. 13841389. [26] F. Blaabjerg, R. Teodorescu, M. Liserre, and A. V. Timbus, Overview of control and grid synchronization for distributed power generation systems, IEEE Trans. Ind. Electron., vol. 53, no. 5, pp. 13981409, Oct. 2006. [27] A. Chandra, B. Singh, B. N. Singh, and K. Al-Haddad, An improved control algorithm of shunt active lter for voltage regulation, harmonic elimination, power-factor correction, and balancing of nonlinear loads, IEEE Trans. Power Electron., vol. 15, no. 3, pp. 495507, May 2000, 2000. [28] R. B. Fisher, Introduction of static frequency converters on SEPTAs 25 Hz commuter rail system, in Proc. ASME/IEEE Joint Railroad Conf., Apr. 1719, 1990, pp. 149155. [29] A. Steimel, Electric railway traction in Europe, IEEE Ind. Appl. Mag., vol. 2, no. 6, pp. 617, Nov./Dec. 1996. [30] C. Patel, R. Ramchand, K. Sivakumar, A. Das, and K. Gopakumar, A rotor ux estimation during zero and active vector periods using current error space vector from a hysteresis controller for a sensorless vector control of IM drive, IEEE Trans. Ind. Electron., vol. 58, no. 6, pp. 2334 2344, Jun. 2011.

Diego E. Soto-Sanchez (M95) received the B.Sc. Electr. Eng. degree from the University of Magallanes, Punta Arenas, Chile, in 1990, and the Ph.D. degree from Imperial College, London, U.K., in 1999. Since 1990, he has been a Lecturer in power electronics and drives in the Department of Electrical Engineering, University of Magallanes. His research interests include high-power converters for FACTS and HVDC systems.

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Rubn Pea (S95M97) was born in Coronel, Chile. He received the Electrical Engineering degree from the University of Concepcion, Concepcion, Chile, in 1984, and the M.Sc. and Ph.D. degrees from the University of Nottingham, Nottingham, U.K., in 1992 and 1996, respectively. From 1985 to 2008, he was a Lecturer in the University of Magallanes, Punta Arenas, Chile. He is currently with the Department of Electrical Engineering, University of Concepcin. His main interests are in control of power electronics converters, ac drives, and renewable energy systems. Dr. Pea is a member of the Institute of Electrical and Electronic Engineers.

Jon Clare (M90SM04) was born in Bristol, England. He received the B.Sc. and Ph.D. degrees in electrical engineering from The University of Bristol, Bristol, U.K. From 1984 to 1990, he worked as a Research Assistant and Lecturer at The University of Bristol involved in teaching and research in power electronic systems. Since 1990, he has been with the Power Electronics, Machines, and Control Group at the University of Nottingham, Nottingham, U.K. and is currently Professor in Power Electronics. His research interests are in power electronic converters and modulation strategies, variable speed drive systems, and electromagnetic compatibility. Dr. Clare is a member of the Institution of Engineering Technology.

Roberto Crdenas (S95M97SM07) was born in Punta Arenas, Chile. He received the B.S. degree from the University of Magallanes, Punta Arenas, in 1988, and the M.Sc. and Ph.D degrees from the University of Nottingham, Nottingham, U.K., in 1992 and 1996, respectively. From 1989 to 1991 and 1996 to 2008, he was a Lecturer in the University of Magallanes. From 1991 to 1996, he was with the Power Electronics Machines and Control Group, University of Nottingham. He is currently an Associate Professor in Power Electronics and Drives with the Department of Electrical Engineering, University of Chile, Santiago, Chile. His main interests include control of electrical machines, variable speed drives, and renewable energy systems. Dr. Crdenas received the Best Paper Award from the IEEE T RANSACTIONS ON I NDUSTRIAL E LECTRONICS in 2004, and the Ramon Salas Edward Award for research excellence from the Chilean Institute of Engineers in 2009.

Patrick Wheeler (M00) received the B.Eng. degree in electrical engineering, in 1990, and the Ph.D. degree for work on matrix converters at the University of Bristol, Bristol, U.K., in 1994. In 1993, he moved to the University of Nottingham, Nottingham, U.K., and worked as a Research Assistant in the Department of Electrical and Electronic Engineering. In 1996, he was appointed Lecturer (subsequently Senior Lecturer in 2002 and Professor in Power Electronic Systems in 2007) with the Power Electronics, Machines, and Control Group at the University of Nottingham. His research interests are in variable speed ac motor drives, particularly different circuit topologies, power converters for power systems, and semiconductor switch use. Dr. Wheeler is a member of the Institution of Engineering Technology.