CD4049UB, CD4050B

Data sheet acquired from Harris Semiconductor SCHS046I

August 1998 - Revised May 2004

CMOS Hex Buffer/Converters

The CD4049UB and CD4050B devices are inverting and non-inverting hex buffers, respectively, and feature logiclevel conversion using only one supply voltage (VCC). The input-signal high level (VIH) can exceed the VCC supply voltage when these devices are used for logic-level conversions. These devices are intended for use as CMOS to DTL/TTL converters and can drive directly two DTL/TTL loads. (VCC = 5V, VOL 0.4V, and IOL 3.3mA.)

Applications
CMOS to DTL/TTL Hex Converter CMOS Current Sink or Source Driver CMOS High-To-Low Logic Level Converter

[ /Title (CD40 49UB, CD405 The CD4049UB and CD4050B are designated as 0B) replacements for CD4009UB and CD4010B, respectively. Because the CD4049UB and CD4050B require only one /Subpower supply, they are preferred over the CD4009UB and ject CD4010B and should be used in place of the CD4009UB (CMO and CD4010B in all inverter, current driver, or logic-level S Hex conversion applications. In these applications the Buffer/ CD4049UB and CD4050B are pin compatible with the CD4009UB and CD4010B respectively, and can be Consubstituted for these devices in existing as well as in new verters) designs. Terminal No. 16 is not connected internally on the /Autho CD4049UB or CD4050B, therefore, connection to this terminal is of no consequence to circuit operation. For r () applications not requiring high sink-current or voltage /Keyconversion, the CD4069UB Hex Inverter is recommended. words (Harris Features Semi- CD4049UB Inverting con CD4050B Non-Inverting ductor, High Sink Current for Driving 2 TTL Loads CD400 High-To-Low Level Logic Conversion 100% Tested for Quiescent Current at 20V 0, Maximum Input Current of 1A at 18V Over Full Package metal Temperature Range; 100nA at 18V and 25oC gate, 5V, 10V and 15V Parametric Ratings CMOS

Ordering Information
PART NUMBER CD4049UBF3A CD4050BF3A CD4049UBD CD4049UBDR CD4049UBDT CD4049UBDW CD4049UBDWR CD4049UBE CD4049UBNSR CD4049UBPW CD4049UBPWR CD4050BD CD4050BDR CD4050UBDT CD4050BDW CD4050BDWR CD4050BE CD4050NSR CD4050BPW CD4050BPWR TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld CERDIP 16 Ld CERDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld PDIP 16 Ld SOP 16 Ld TSSOP 16 Ld TSSOP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld PDIP 16 Ld SOP 16 Ld TSSOP 16 Ld TSSOP

NOTE: When ordering, use the entire part number. The sufx R denotes tape and reel. The sufx T denotes a small-quantity reel of 250.

Pinouts
CD4049UB (PDIP, CERDIP, SOIC, SOP, TSSOP) TOP VIEW
VCC 1 G=A 2 A 3 H=B 4 B 5 I=C 6 C 7 VSS 8 16 NC 15 L = F 14 F 13 NC 12 K = E 11 E 10 J = D 9 D

CD4050B (PDIP, CERDIP, SOIC, SOP) TOP VIEW

VCC 1 G=A 2 A 3 H=B 4 B 5 I=C 6 C 7 VSS 8 16 NC 15 L = F 14 F 13 NC 12 K = E 11 E 10 J = D 9 D

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. Copyright 2004, Texas Instruments Incorporated

CD4049UB, CD4050B Functional Block Diagrams

CD4049UB CD4050B

G=A

G=A

H=B

H=B

I=C

I=C

10

J=D

10

J=D

11

12

K=E

11

12

K=E

F VCC VSS

14 1 8

15

L=F

F VCC VSS

14 1 8

15

L=F

NC = 13 NC = 16

NC = 13 NC = 16

Schematic Diagrams
VCC VCC

P R IN N OUT IN R

OUT N N

VSS

VSS

FIGURE 1A. SCHEMATIC DIAGRAM OF CD4049UB, 1 OF 6 IDENTICAL UNITS

FIGURE 1B. SCHEMATIC DIAGRAM OF CD4050B, 1 OF 6 IDENTICAL UNITS

CD4049UB, CD4050B
Absolute Maximum Ratings
Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . -0.5V to 20V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . 10mA

Thermal Information
Package Thermal Impedance, JA (see Note1): E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/W D (SOIC) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73oC/W DW (SOIC) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57oC/W NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W Maximum Junction Temperature (Plastic Package) . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . . 65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .265oC SOIC - Lead Tips Only

Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specication is not implied.

NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7.

DC Electrical Specications
LIMITS AT INDICATED TEMPERATURE (oC) TEST CONDITIONS PARAMETER Quiescent Device Current IDD (Max) VO (V) Output Low (Sink) Current IOL (Min) 0.4 0.4 0.5 1.5 Output High (Source) Current IOH (Min) 4.6 2.5 9.5 13.5 Out Voltage Low Level VOL (Max) Output Voltage High Level VOH (Min) Input Low Voltage, VIL (Max) CD4049UB 4.5 9 13.5 Input Low Voltage, VIL (Max) CD4050B 0.5 1 1.5 VIN (V) 0,5 0,10 0,15 0,20 0,5 0,5 0,10 0,15 0,5 0,5 0,10 0,15 0,5 0,10 0,15 0,5 0,10 0,15 VCC (V) 5 10 15 20 4.5 5 10 15 5 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 -55 1 2 4 20 3.3 4 10 26 -0.81 -2.6 -2.0 -5.2 0.05 0.05 0.05 4.95 9.95 14.95 1 2 2.5 1.5 3 4 -40 1 2 4 20 3.1 3.8 9.6 25 -0.73 -2.4 -1.8 -4.8 0.05 0.05 0.05 4.95 9.95 14.95 1 2 2.5 1.5 3 4 85 30 60 120 600 2.1 2.9 6.6 20 -0.58 -1.9 -1.35 -3.5 0.05 0.05 0.05 4.95 9.95 14.95 1 2 2.5 1.5 3 4 125 30 60 120 600 1.8 2.4 5.6 18 -0.48 -1.55 -1.18 -3.1 0.05 0.05 0.05 4.95 9.95 14.95 1 2 2.5 1.5 3 4 MIN 2.6 3.2 8 24 -0.65 -2.1 -1.65 -4.3 4.95 9.95 14.95 25 TYP 0.02 0.02 0.02 0.04 5.2 6.4 16 48 -1.2 -3.9 -3.0 -8.0 0 0 0 5 10 15 MAX 1 2 4 20 0.05 0.05 0.05 1 2 2.5 1.5 3 4 UNITS A A A A mA mA mA mA mA mA mA mA V V V V V V V V V V V V

CD4049UB, CD4050B
DC Electrical Specications
(Continued) LIMITS AT INDICATED TEMPERATURE (oC) TEST CONDITIONS PARAMETER Input High Voltage, VIH Min CD4049UB VO (V) 0.5 1 1.5 Input High Voltage, VIH Min CD4050B 4.5 9 13.5 Input Current, IIN Max VIN (V) 0,18 VCC (V) 5 10 15 5 10 15 18 -55 4 8 12.5 3.5 7 11 0.1 -40 4 8 12.5 3.5 7 11 0.1 85 4 8 12.5 3.5 7 11 1 125 4 8 12.5 3.5 7 11 1 MIN 4 8 12.5 3.5 7 11 25 TYP 10-5 MAX 0.1 UNITS V V V V V V A

AC Electrical Specications
PARAMETER Propagation Delay Time Low to High, tPLH CD4049UB

TA = 25oC, Input tr , tf = 20ns, CL = 50pF, RL = 200k TEST CONDITIONS VIN 5 10 10 15 15 VCC 5 10 5 15 5 5 10 5 15 5 5 10 5 15 5 5 10 5 15 5 5 10 15 5 10 15 LIMITS (ALL PACKAGES) TYP 60 32 45 25 45 70 40 45 30 40 32 20 15 15 10 55 22 50 15 50 80 40 30 30 20 15 MAX 120 65 90 50 90 140 80 90 60 80 65 40 30 30 20 110 55 100 30 100 160 80 60 60 40 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Propagation Delay Time Low to High, tPLH CD4050B

5 10 10 15 15

Propagation Delay Time High to Low, tPHL CD4049UB

5 10 10 15 15

Propagation Delay Time High to Low, tPHL CD4050B

5 10 10 15 15

Transition Time, Low to High, tTLH

5 10 15

Transition Time, High to Low, tTHL

5 10 15

CD4049UB, CD4050B
AC Electrical Specications
PARAMETER Input Capacitance, CIN CD4049UB Input Capacitance, CIN CD4050B TA = 25oC, Input tr , tf = 20ns, CL = 50pF, RL = 200k (Continued) TEST CONDITIONS VIN VCC LIMITS (ALL PACKAGES) TYP 15 5 MAX 22.5 7.5 UNITS pF pF

Typical Performance Curves

TA = 25oC SUPPLY VOLTAGE (VCC) = 5V VO , OUTPUT VOLTAGE (V) 5 4 MINIMUM 3 2 1 MAXIMUM VO , OUTPUT VOLTAGE (V) 5 4 3 2 1 MINIMUM MAXIMUM TA = 25oC SUPPLY VOLTAGE (VCC) = 5V

VI , INPUT VOLTAGE (V)

VI , INPUT VOLTAGE (V)

FIGURE 2. MINIMUM AND MAXIMUM VOLTAGE TRANSFER CHARACTERISTICS FOR CD4049UB

FIGURE 3. MINIMUM AND MAXIMUM VOLTAGE TRANSFER CHARACTERISTICS FOR CD4050B

IOL, OUTPUT LOW (SINK) CURRENT (mA)

IOL, OUTPUT LOW (SINK) CURRENT (mA)

TA = 25oC 70 60 50 40 30 GATE TO SOURCE VOLTAGE (VGS) = 5V 20 10 15V 10V

TA = 25oC 70 60 50 40 30 20 GATE TO SOURCE VOLTAGE (VGS) = 5V 10 15V 10V

VDS , DRAIN TO SOURCE VOLTAGE (V)

VDS , DRAIN TO SOURCE VOLTAGE (V)

FIGURE 4. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS

FIGURE 5. MINIMUM OUTPUT LOW (SINK) CURRENT DRAIN CHARACTERISTICS

CD4049UB, CD4050B Typical Performance Curves

VDS, DRAIN TO SOURCE VOLTAGE (V) -8 TA = 25oC OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS -5 GATE TO SOURCE VOLTAGE VGS = -5V -10 -15 -20 -25 -10V -30 -15V -35 -7 -6 -5 -4 -3 -2 -1 0

(Continued)
VDS, DRAIN TO SOURCE VOLTAGE (V) -8 -7 -6 -5 -4 -3 -2 TA = 25oC -5 VGS = -5V -10V -15V -25 -30 -35 -10 -15 -20 OUTPUT HIGH (SOURCE) GATE TO SOURCE VOLTAGE CURRENT CHARACTERISTICS 108

-1

FIGURE 6. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS

FIGURE 7. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS

10 VO, OUTPUT VOLTAGE (V) VO, OUTPUT VOLTAGE (V) 9 8 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8 9 10 VI , INPUT VOLTAGE (V) 125oC -55oC VCC = 5V TA = -55oC 125oC SUPPLY VOLTAGE VCC = 10V

10 9 8 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8 9 10 VI , INPUT VOLTAGE (V) 125oC -55oC VCC = 5V TA = -55oC 125oC SUPPLY VOLTAGE VCC = 10V

FIGURE 8. TYPICAL VOLTAGE TRANSFER CHARACTERISTICS AS A FUNCTION OF TEMPERATURE FOR CD4049UB

105

FIGURE 9. TYPICAL VOLTAGE TRANSFER CHARACTERISTICS AS A FUNCTION OF TEMPERATURE FOR CD4050B

POWER DISSIPATION PER INVERTER (W)

POWER DISSIPATION PER INVERTER (W)

TA = 25oC

104

103

SU

Y PL

GE TA L VO

VC

5 =1

V
10 V V 10 5V

TA = 25oC 105 104 15V; 1MHz 15V; 100kHz 10V; 100kHz 15V; 10kHz 10V; 10kHz 15V; 1kHz

103 102

102

10 10

LOAD CAPACITANCE CL = 50pF (11pF FIXTURE + 39pF EXT) CL = 15pF (11pF FIXTURE + 4pF EXT) 102 103 104 f, INPUT FREQUENCY (kHz) 105

10 SUPPLY VOLTAGE VCC = 5V FREQUENCY (f) = 10kHz 10 102 103 104 105 106 107 tr, tf , INPUT RISE AND FALL TIME (ns)

FIGURE 10. TYPICAL POWER DISSIPATION vs FREQUENCY CHARACTERISTICS

FIGURE 11. TYPICAL POWER DISSIPATION vs INPUT RISE AND FALL TIMES PER INVERTER FOR CD4049UB

CD4049UB, CD4050B Typical Performance Curves

POWER DISSIPATION PER INVERTER (W) 106 105 104 103 102 10 SUPPLY VOLTAGE VCC = 5V FREQUENCY (f) = 10kHz 1 10 102 103 104 105 106 107 tr, tf , INPUT RISE AND FALL TIME (ns) 108 15V; 1MHz 15V; 100kHz 10V; 100kHz 15V; 10kHz 10V; 10kHz 15V; 1kHz

(Continued)

TA = 25oC

FIGURE 12. TYPICAL POWER DISSIPATION vs INPUT RISE AND FALL TIMES PER INVERTER FOR CD4050B

Test Circuits
VCC INPUTS INPUTS VIH VSS VCC VCC OUTPUTS

+
DVM

VIL IDD VSS VSS

NOTE: Test any one input with other inputs at VCC or VSS. FIGURE 13. QUIESCENT DEVICE CURRENT TEST CIRCUIT FIGURE 14. INPUT VOLTAGE TEST CIRCUIT

CMOS 10V LEVEL TO DTL/TTL 5V LEVEL VCC = 5V VCC INPUTS VCC I VSS VSS 10V = VIH 0 = VIL VSS OUTPUTS COS/MOS IN CD4049 INPUTS 5V = VOH 0 = VOL OUTPUT TO DTL/TTL

NOTE: Measure inputs sequentially, to both VCC and VSS connect all unused inputs to either VCC or VSS. FIGURE 15. INPUT CURRENT TEST CIRCUIT

In Terminal - 3, 5, 7, 9, 11, or 14 Out Terminal - 2, 4, 6, 10, 12 or 15 VCC Terminal - 1 VSS Terminal - 8 FIGURE 16. LOGIC LEVEL CONVERSION APPLICATION

CD4049UB, CD4050B Test Circuits

(Continued)

VDD 0.1F 500F

I

10kHz, 100kHz, 1MHz

CL INCLUDES FIXTURE CAPACITANCE

FIGURE 17. DYNAMIC POWER DISSIPATION TEST CIRCUITS

CD4049UB

CL

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9

CD4049UB, CD4050B

PACKAGE OPTION ADDENDUM

www.ti.com 15-Oct-2009

PACKAGING INFORMATION
Orderable Device CD4049UBD CD4049UBDE4 CD4049UBDG4 CD4049UBDR CD4049UBDRE4 CD4049UBDRG4 CD4049UBDT CD4049UBDTE4 CD4049UBDTG4 CD4049UBDW CD4049UBDWE4 CD4049UBDWG4 CD4049UBDWR CD4049UBDWRE4 CD4049UBDWRG4 CD4049UBE CD4049UBEE4 CD4049UBF CD4049UBF3A CD4049UBF3AS2283 CD4049UBF3AS2534 CD4049UBM CD4049UBM96 CD4049UBNSR CD4049UBNSRE4 CD4049UBNSRG4 CD4049UBPW Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE OBSOLETE OBSOLETE OBSOLETE OBSOLETE ACTIVE ACTIVE ACTIVE ACTIVE Package Type SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC PDIP PDIP CDIP CDIP CDIP CDIP SOIC SOIC SO SO SO TSSOP Package Drawing D D D D D D D D D DW DW DW DW DW DW N N J J J J D D NS NS NS PW Pins Package Eco Plan (2) Qty 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 40 40 40 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU A42 A42 Call TI Call TI Call TI Call TI CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp (3) Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type Call TI Call TI Call TI Call TI Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM

2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 250 250 250 40 40 40 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)

2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 25 25 1 1 Pb-Free (RoHS) Pb-Free (RoHS) TBD TBD TBD TBD TBD TBD 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 90 Green (RoHS & no Sb/Br)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com 15-Oct-2009

Orderable Device CD4049UBPWE4 CD4049UBPWG4 CD4049UBPWR CD4049UBPWRE4 CD4049UBPWRG4 CD4050BD CD4050BDE4 CD4050BDG4 CD4050BDR CD4050BDRE4 CD4050BDRG4 CD4050BDT CD4050BDTE4 CD4050BDTG4 CD4050BDW CD4050BDWE4 CD4050BDWG4 CD4050BDWR CD4050BDWRE4 CD4050BDWRG4 CD4050BE CD4050BEE4 CD4050BF CD4050BF3A CD4050BF3AS2283 CD4050BF3AS2534 CD4050BM CD4050BNSR

Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE OBSOLETE OBSOLETE OBSOLETE ACTIVE

Package Type TSSOP TSSOP TSSOP TSSOP TSSOP SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC PDIP PDIP CDIP CDIP CDIP CDIP SOIC SO

Package Drawing PW PW PW PW PW D D D D D D D D D DW DW DW DW DW DW N N J J J J D NS

Pins Package Eco Plan (2) Qty 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 90 90 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)

Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU A42 A42 Call TI Call TI Call TI CU NIPDAU

MSL Peak Temp (3) Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type Call TI Call TI Call TI Level-1-260C-UNLIM

2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 40 40 40 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)

2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 250 250 250 40 40 40 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)

2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 25 25 1 1 Pb-Free (RoHS) Pb-Free (RoHS) TBD TBD TBD TBD TBD 2000 Green (RoHS & no Sb/Br)

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com 15-Oct-2009

Orderable Device CD4050BNSRE4 CD4050BNSRG4 CD4050BPW CD4050BPWE4 CD4050BPWG4 CD4050BPWR CD4050BPWRE4 CD4050BPWRG4 JM38510/05553BEA JM38510/05554BEA
(1)

Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE

Package Type SO SO TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP CDIP CDIP

Package Drawing NS NS PW PW PW PW PW PW J J

Pins Package Eco Plan (2) Qty 16 16 16 16 16 16 16 16 16 16 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 90 90 90 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)

Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU A42 A42

MSL Peak Temp (3) Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type N / A for Pkg Type

2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 1 1 TBD TBD

The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 3

PACKAGE MATERIALS INFORMATION

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19-Mar-2008

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins Type Drawing SOIC SOIC SO TSSOP SOIC SOIC SO TSSOP D DW NS PW D DW NS PW 16 16 16 16 16 16 16 16

SPQ

Reel Reel Diameter Width (mm) W1 (mm) 330.0 330.0 330.0 330.0 330.0 330.0 330.0 330.0 16.4 16.4 16.4 12.4 16.4 16.4 16.4 12.4

A0 (mm)

B0 (mm)

K0 (mm)

P1 (mm) 8.0 12.0 12.0 8.0 8.0 12.0 12.0 8.0

W Pin1 (mm) Quadrant 16.0 16.0 16.0 12.0 16.0 16.0 16.0 12.0 Q1 Q1 Q1 Q1 Q1 Q1 Q1 Q1

CD4049UBDR CD4049UBDWR CD4049UBNSR CD4049UBPWR CD4050BDR CD4050BDWR CD4050BNSR CD4050BPWR

2500 2000 2000 2000 2500 2000 2000 2000

6.5 10.75 8.2 7.0 6.5 10.75 8.2 7.0

10.3 10.7 10.5 5.6 10.3 10.7 10.5 5.6

2.1 2.7 2.5 1.6 2.1 2.7 2.5 1.6

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

19-Mar-2008

*All dimensions are nominal

Device CD4049UBDR CD4049UBDWR CD4049UBNSR CD4049UBPWR CD4050BDR CD4050BDWR CD4050BNSR CD4050BPWR

Package Type SOIC SOIC SO TSSOP SOIC SOIC SO TSSOP

Package Drawing D DW NS PW D DW NS PW

Pins 16 16 16 16 16 16 16 16

SPQ 2500 2000 2000 2000 2500 2000 2000 2000

Length (mm) 333.2 346.0 346.0 346.0 333.2 346.0 346.0 346.0

Width (mm) 345.9 346.0 346.0 346.0 345.9 346.0 346.0 346.0

Height (mm) 28.6 33.0 33.0 29.0 28.6 33.0 33.0 29.0

Pack Materials-Page 2

MECHANICAL DATA
MTSS001C JANUARY 1995 REVISED FEBRUARY 1999

PW (R-PDSO-G**)
14 PINS SHOWN

PLASTIC SMALL-OUTLINE PACKAGE

0,65 14 8

0,30 0,19

0,10 M

0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 A 7 0 8 0,75 0,50

Seating Plane 1,20 MAX 0,15 0,05 0,10

PINS ** DIM A MAX

14

16

20

24

28

3,10

5,10

5,10

6,60

7,90

9,80

A MIN

2,90

4,90

4,90

6,40

7,70

9,60

4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

24-Jan-2013

PACKAGING INFORMATION
Orderable Device CD4049UBD CD4049UBDE4 CD4049UBDG4 CD4049UBDR CD4049UBDRE4 CD4049UBDRG4 CD4049UBDT CD4049UBDTE4 CD4049UBDTG4 CD4049UBDW CD4049UBDWE4 CD4049UBDWG4 CD4049UBDWR CD4049UBDWRE4 CD4049UBDWRG4 CD4049UBE CD4049UBEE4 Status
(1)

Package Type Package Pins Package Qty Drawing SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC PDIP PDIP D D D D D D D D D DW DW DW DW DW DW N N 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 40 40 40 2500 2500 2500 250 250 250 40 40 40 2000 2000 2000 25 25

Eco Plan
(2)

Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU

MSL Peak Temp

(3)

Op Temp (C) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125

Top-Side Markings
(4)

Samples

ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE

Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Pb-Free (RoHS)

Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type N / A for Pkg Type

CD4049UBM CD4049UBM CD4049UBM CD4049UBM CD4049UBM CD4049UBM CD4049UBM CD4049UBM CD4049UBM CD4049UBM CD4049UBM CD4049UBM CD4049UBM CD4049UBM CD4049UBM CD4049UBE CD4049UBE

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

24-Jan-2013

Orderable Device CD4049UBF CD4049UBF3A CD4049UBF3AS2283 CD4049UBF3AS2534 CD4049UBM CD4049UBM96 CD4049UBNSR CD4049UBNSRE4 CD4049UBNSRG4 CD4049UBPW CD4049UBPWE4 CD4049UBPWG4 CD4049UBPWR CD4049UBPWRE4 CD4049UBPWRG4 CD4050BD CD4050BDE4 CD4050BDG4 CD4050BDR CD4050BDRE4

Status
(1)

Package Type Package Pins Package Qty Drawing CDIP CDIP CDIP CDIP SOIC SOIC SO SO SO TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP SOIC SOIC SOIC SOIC SOIC J J J J D D NS NS NS PW PW PW PW PW PW D D D D D 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 2000 2000 2000 90 90 90 2000 2000 2000 40 40 40 2500 2500 1 1

Eco Plan
(2)

Lead/Ball Finish A42 A42 Call TI Call TI Call TI Call TI CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU

MSL Peak Temp

(3)

Op Temp (C) -55 to 125 -55 to 125

Top-Side Markings
(4)

Samples

ACTIVE ACTIVE OBSOLETE OBSOLETE OBSOLETE OBSOLETE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE

TBD TBD TBD TBD TBD TBD Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)

N / A for Pkg Type N / A for Pkg Type Call TI Call TI Call TI Call TI Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM

CD4049UBF CD4049UBF3A

-55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 CD4049UB CD4049UB CD4049UB CM049UB CM049UB CM049UB CM049UB CM049UB CM049UB CD4050BM CD4050BM CD4050BM CD4050BM CD4050BM

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

24-Jan-2013

Orderable Device CD4050BDRG4 CD4050BDT CD4050BDTE4 CD4050BDTG4 CD4050BDW CD4050BDWE4 CD4050BDWG4 CD4050BDWR CD4050BDWRE4 CD4050BDWRG4 CD4050BE CD4050BEE4 CD4050BF CD4050BF3A CD4050BF3AS2283 CD4050BF3AS2534 CD4050BM CD4050BNSR CD4050BNSRE4

Status
(1)

Package Type Package Pins Package Qty Drawing SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC PDIP PDIP CDIP CDIP CDIP CDIP SOIC SO SO D D D D DW DW DW DW DW DW N N J J J J D NS NS 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 2000 2000 2500 250 250 250 40 40 40 2000 2000 2000 25 25 1 1

Eco Plan
(2)

Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU A42 A42 Call TI Call TI Call TI CU NIPDAU CU NIPDAU

MSL Peak Temp

(3)

Op Temp (C) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125

Top-Side Markings
(4)

Samples

ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE OBSOLETE OBSOLETE OBSOLETE ACTIVE ACTIVE

Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Pb-Free (RoHS) TBD TBD TBD TBD TBD Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)

Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type Call TI Call TI Call TI Level-1-260C-UNLIM Level-1-260C-UNLIM

CD4050BM CD4050BM CD4050BM CD4050BM CD4050BM CD4050BM CD4050BM CD4050BM CD4050BM CD4050BM CD4050BE CD4050BE CD4050BF CD4050BF3A

-55 to 125 -55 to 125 -55 to 125 CD4050B CD4050B

Addendum-Page 3

PACKAGE OPTION ADDENDUM

www.ti.com

24-Jan-2013

Orderable Device CD4050BNSRG4 CD4050BPW CD4050BPWE4 CD4050BPWG4 CD4050BPWR CD4050BPWRE4 CD4050BPWRG4 JM38510/05553BEA JM38510/05554BEA M38510/05553BEA M38510/05554BEA

Status
(1)

Package Type Package Pins Package Qty Drawing SO TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP CDIP CDIP CDIP CDIP NS PW PW PW PW PW PW J J J J 16 16 16 16 16 16 16 16 16 16 16 2000 90 90 90 2000 2000 2000 1 1 1 1

Eco Plan
(2)

Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU A42 A42 A42 A42

MSL Peak Temp

(3)

Op Temp (C) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125

Top-Side Markings
(4)

Samples

ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE

Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) TBD TBD TBD TBD

Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type

CD4050B CM050B CM050B CM050B CM050B CM050B CM050B JM38510/ 05553BEA JM38510/ 05554BEA JM38510/ 05553BEA JM38510/ 05554BEA

(1)

The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Addendum-Page 4

PACKAGE OPTION ADDENDUM

www.ti.com

24-Jan-2013

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Only one of markings shown within the brackets will appear on the physical device.

(4)

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD4049UB, CD4049UB-MIL, CD4050B, CD4050B-MIL :

Catalog: CD4049UB, CD4050B Military: CD4049UB-MIL, CD4050B-MIL

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product Military - QML certified for Military and Defense Applications

Addendum-Page 5

PACKAGE MATERIALS INFORMATION

www.ti.com 8-Apr-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins Type Drawing SOIC SOIC TSSOP SOIC SOIC TSSOP D DW PW D DW PW 16 16 16 16 16 16

SPQ

Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 330.0 330.0 330.0 330.0 330.0 16.4 16.4 12.4 16.4 16.4 12.4 6.5 10.75 6.9 6.5 10.75 6.9

B0 (mm) 10.3 10.7 5.6 10.3 10.7 5.6

K0 (mm) 2.1 2.7 1.6 2.1 2.7 1.6

P1 (mm) 8.0 12.0 8.0 8.0 12.0 8.0

W Pin1 (mm) Quadrant 16.0 16.0 12.0 16.0 16.0 12.0 Q1 Q1 Q1 Q1 Q1 Q1

CD4049UBDR CD4049UBDWR CD4049UBPWR CD4050BDR CD4050BDWR CD4050BPWR

2500 2000 2000 2500 2000 2000

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 8-Apr-2013

*All dimensions are nominal

Device CD4049UBDR CD4049UBDWR CD4049UBPWR CD4050BDR CD4050BDWR CD4050BPWR

Package Type SOIC SOIC TSSOP SOIC SOIC TSSOP

Package Drawing D DW PW D DW PW

Pins 16 16 16 16 16 16

SPQ 2500 2000 2000 2500 2000 2000

Length (mm) 333.2 367.0 367.0 333.2 367.0 367.0

Width (mm) 345.9 367.0 367.0 345.9 367.0 367.0

Height (mm) 28.6 38.0 35.0 28.6 38.0 35.0

Pack Materials-Page 2

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CD4049UBNSR CD4049UBE CD4050BNSR CD4049UBDW CD4049UBDR CD4050BE CD4050BDWR CD4049UBDG4 CD4049UBDRG4 CD4049UBDTG4 CD4049UBPWG4 CD4049UBPWRG4 CD4050BDG4 CD4050BDRG4 CD4050BDTG4 CD4050BDWG4 CD4050BDWRG4 CD4050BPWG4 CD4050BPWRG4 CD4049UBNSRG4 CD4050BNSRG4 CD4049UBD CD4050BD CD4049UBDE4 CD4049UBDRE4 CD4049UBDT CD4049UBDTE4 CD4049UBDWE4 CD4049UBDWG4 CD4049UBDWR CD4049UBDWRE4 CD4049UBDWRG4 CD4049UBEE4 CD4049UBNSRE4 CD4049UBPW CD4049UBPWE4 CD4049UBPWR CD4049UBPWRE4 CD4050BDE4 CD4050BDR CD4050BDRE4 CD4050BDT CD4050BDTE4 CD4050BDW CD4050BDWE4 CD4050BDWRE4 CD4050BEE4 CD4050BNSRE4 CD4050BPW CD4050BPWE4 CD4050BPWR CD4050BPWRE4