Lecture28,29&30 CMOS Inverter

Jagannadha Naidu K
Outline
Pass Transistors
DC Response
Logic Levels and Noise Margins
Pass Transistors
We have assumed source is grounded
What if source > 0?
e.g. pass transistor passing V
DD
V
g
= V
DD
If V
s
> V
DD
-V
t
, V
gs
< V
t
Hence transistor would turn itself off
nMOS pass transistors pull no higher than V
DD
-V
tn
Called a degraded 1
Approach degraded value slowly (low I
ds
)
pMOS pass transistors pull no lower than V
tp
Transmission gates are needed to pass both 0 and
1
V
DD
V
DD
Pass Transistor Ckts
DC Response
DC Response: V
out
vs. V
in
for a gate
Ex: Inverter
When V
in
= 0 -> V
out
= V
DD
When V
in
= V
DD
-> V
out
= 0
In between, V
out
depends on
transistor size and current
By KCL, must settle such that
I
dsn
= |I
dsp
|
We could solve equations
But graphical solution gives more insight
I
dsn
I
dsp
V
out
V
DD
V
in
Transistor Operation
Current depends on region of transistor
behavior
For what V
in
and V
out
are nMOS and pMOS in
Cutoff?
Linear?
Saturation?
nMOS Operation
V
gsn
> V
tn
V
in
> V
tn
V
dsn
> V
gsn
V
tn
V
out
> V
in
- V
tn
V
gsn
> V
tn
V
in
> V
tn
V
dsn
< V
gsn
V
tn
V
out
< V
in
- V
tn
V
gsn
< V
tn
V
in
< V
tn
Saturated Linear Cutoff
I
dsn
I
dsp
V
out
V
DD
V
in
V
gsn
= V
in
V
dsn
= V
out
pMOS Operation
V
gsp
< V
tp
V
in
< V
DD
+ V
tp
V
dsp
< V
gsp
V
tp
V
out
< V
in
- V
tp
V
gsp
< V
tp
V
in
< V
DD
+ V
tp
V
dsp
> V
gsp
V
tp
V
out
> V
in
- V
tp
V
gsp
> V
tp
V
in
> V
DD
+ V
tp
Saturated Linear Cutoff
I
dsn
I
dsp
V
out
V
DD
V
in
V
gsp
= V
in
- V
DD
V
dsp
= V
out
- V
DD
V
tp
< 0
I-V Characteristics
Make pMOS is wider than nMOS such that
n
=
p
Current vs. V
out
, V
in
V
in5
V
in4
V
in3
V
in2
V
in1
V
in0
V
in1
V
in2
V
in3
V
in4
I
dsn
, |I
dsp
|
V
out
V
DD
Load Line Analysis
V
in5
V
in4
V
in3
V
in2
V
in1
V
in0
V
in1
V
in2
V
in3
V
in4
I
dsn
, |I
dsp
|
V
out
V
DD
For a given V
in
:
Plot I
dsn
, I
dsp
vs. V
out
V
out
must be where |currents| are equal in
I
dsn
I
dsp
V
out
V
DD
V
in
Load Line Analysis
V
in0
V
in0
I
dsn
, |I
dsp
|
V
out
V
DD
V
in1
V
in1
I
dsn
, |I
dsp
|
V
out
V
DD
V
in2
V
in2
I
dsn
, |I
dsp
|
V
out
V
DD
V
in3
V
in3
I
dsn
, |I
dsp
|
V
out
V
DD
V
in4
V
in4
I
dsn
, |I
dsp
|
V
out
V
DD
in5
dsn dsp
out
DD
V
in5
V
in4
V
in3
V
in2
V
in1
V
in0
V
in1
V
in2
V
in3
V
in4
V
out
V
DD
0.2V
DD
0.4V
DD
0.6V
DD
0.8V
DD
V
DD
DC Transfer Curve
Transcribe points onto V
in
vs. V
out
plot
V
in5
V
in4
V
in3
V
in2
V
in1
V
in0
V
in1
V
in2
V
in3
V
in4
V
out
V
DD
C
V
out
0
V
in
V
DD
V
DD
A B
D
E
V
tn
V
DD
/2 V
DD
+V
tp
V
in0
V
in1
V
in2
V
in3
V
in4
V
in5
Operating Regions
Revisit transistor operating
regions
C
V
out
0
V
in
V
DD
V
DD
A B
D
E
V
tn
V
DD
/2 V
DD
+V
tp
Cutoff Linear E
Saturation Linear D
Saturation Saturation C
Linear Saturation B
Linear Cutoff A
pMOS nMOS Region
Beta Ratio
If
p
/
n
1, switching point will move from V
DD
/2
Called skewed gate
Other gates: collapse into equivalent inverter
V
out
0
V
in
V
DD
V
DD
0.5
1
2
10
p
n

=
0.1
p
n

=
Noise Margins
How much noise can a gate input see before
it does not recognize the input?
Indeterminate
Region
NM
L
NM
H
Input Characteristics Output Characteristics
V
OH
V
DD
V
OL
GND
V
IH
V
IL
Logical High
Input Range
Logical Low
Input Range
Logical High
Output Range
Logical Low
Output Range
V
DD
V
in
V
out
V
OH
V
DD
V
OL
V
IL
V
IH
V
tn
Unity Gain Points
Slope = -1
V
DD
-
|V
tp
|

p
/
n
> 1
V
in
V
out
0
Logic Levels
To maximize noise margins, select logic levels at
unity gain point of DC transfer characteristic