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CHAPTER VIII-1
CHAPTER VIII
CHAPTER VIII
FINITE STATE MACHINES (FSM)
STATE MACHINES
STATE MACHINES
-INTRODUCTION
INTRODUCTION
The goal now is to use the memory elements to hold the running state of
the machine.
The state of the machine can be used to perform sequential operations.
This chapter will discuss how to represent the state of the machine for
design and communication purposes.
STATE MACHINES
STATE MACHINES
-INTRODUCTION
Mealy machine
Sequential system where
output depends on current
Input
Sequential System
Combinational
Logic
Output
Memory
(state)
Moore machine
Sequential system where
output depends only on
current state.
Input
Sequential System
Combinational
Logic
Memory
(state)
Output
STATE MACHINES
SYNC. & ASYNC. SYSTEMS
STATE MACHINES
-INTRODUCTION
-MEALY & MOORE MACH.
STATE DIAGRAMS
ELEMENTS OF DIAGRAMS
STATE MACHINES
-INTRODUCTION
-MEALY & MOORE MACH.
-SYNC. & ASYNC SYSTEMS
Sk
State
Sj
b /q
Input/Output
Input:
x ( t ) { a, b }
Output:
z ( t ) { p, q }
State:
s ( t ) { S k, S j }
Initial state:
s ( 0 ) = Sk
STATE DIAGRAMS
PROPERTIES
STATE MACHINES
STATE DIAGRAMS
-ELEMENTS OF DIAGRAMS
STATE DIAGRAMS
STATE MACHINES
STATE DIAGRAMS
-ELEMENTS OF DIAGRAMS
-PROPERTIES
The following is a simple example. What does this state machine do?
0/1
0/0
S0
S1
1/0
Input:
x ( t ) { 0, 1 }
Output:
z ( t ) { 0, 1 }
State:
s ( t ) { S 0, S 1 }
Initial state:
s ( 0 ) = S0
1/0
S0
0/1, 1/0
S1
0/0,1/0
STATE DIAGRAMS
STATE DIAGRAMS
-ELEMENTS OF DIAGRAMS
-PROPERTIES
-STATE DIAGRAM EX.
Consider the simple bit flipper looked at the in previous chapter. How
would a state diagram be formed?
Below is one possible way of drawing the state diagram for the bit flipper.
-/1
S0
S1
-/0
Since the bit flipper is a Moore machine, the state diagram can also be
S0 0
S1 1
-
STATE DIAGRAMS
PATTERN DETECT EXAMPLE
STATE DIAGRAMS
-PROPERTIES
-STATE DIAGRAM EX.
-BIT FLIPPER EX.
z ( t ) { 0, 1 }
Function:
x1
z(t) = x
x0
if x ( t 3, t ) = 1101
otherwise
Effectively, the system should output a 1 when the last set of four inputs
have been 1101.
For instance, the following output z(t) is obtained for the input x(t)
0123456789...t
x(t)
z(t)
100100100100110101101101001101001
???000000000000100001001000001000
STATE DIAGRAMS
STATE DIAGRAMS
-STATE DIAGRAM EX.
-BIT FLIPPER EX.
-PATTERN DETECT EX.
The following state diagram gives the behaviour of the desired 1101 pattern
detector.
Consider S 0 to be the initial state, S 1 when first symbol detected (1), S 2
when subpattern 11 detected, and S 3 when subpattern 110 detected.
0/0
1/0
1/0
S0
1/0
S1
S2
0/0
1/1
0/0
R.M. Dansereau; v.1.0
0/0
S3
STATE TABLES
INTRODUCTION
STATE DIAGRAMS
-STATE DIAGRAM EX.
-BIT FLIPPER EX.
-PATTERN DETECT EX.
STATE TABLES
STATE DIAGRAMS
STATE TABLES
-INTRODUCTION
S1 1
-
Input
Next State
Output
S 0 or 0
S 1 or 1
STATE TABLES
TRANSLATE FROM DIAGRAM
STATE DIAGRAMS
STATE TABLES
-INTRODUCTION
-BIT FLIPPER EX.
STATE TABLES
STATE TABLES
-INTRODUCTION
-BIT FLIPPER EX.
-TRANSLATE DIAGRAM
Input
X
Next State
N1 N0
Output
Z
S 0 or
S 0 or
S 0 or
S 1 or
S 1 or
S 0 or
S 1 or
S 2 or
S 2 or
S 3 or
S 2 or
S 2 or
S 3 or
S 0 or
S 3 or
S 1 or
STATE TABLES
TRANSLATE TO DIAGRAM
STATE TABLES
-BIT FLIPPER EX.
-TRANSLATE DIAGRAM
-PATTERN DETECT EX.
SEQ. CIRCUITS
INTRODUCTION
STATE TABLES
-TRANSLATE DIAGRAM
-PATTERN DETECT EX.
-TRANSLATE TO DIAGRAM
With the descriptions of a FSM as a state diagram and a state table, the
next question is how to develop a sequential circuit, or logic diagram from
the FSM.
Combinational
Network
Outputs
(Mealy machine)
State
FF
1 2
Present State
Next State
FF
1 2
Outputs
(Moore machine)
SEQ. CIRCUITS
FROM STATE TABLE
STATE TABLES
SEQUENTIAL CIRCUITS
-INTRODUCTION
The procedure for developing a logic circuit from a state table is the same
as with a regular truth table.
Generate Boolean functions for
each external outputs using external inputs and present state bits
each next state bit using external inputs and present state bits
Use Boolean algebra, Karnaugh maps, etc. as normal to simplify.
Draw a register for each state bit.
Draw logic diagram components connecting external outputs to external
inputs and outputs of state bit registers (which have the present state).
Draw logic diagram components connecting inputs of state bits (for next
state) to the external inputs and outputs of state bit registers (which have
the present state).
SEQ. CIRCUITS
STATE TABLES
SEQUENTIAL CIRCUITS
-INTRODUCTION
-DEVEL. LOGIC CIRCUITS
P1P0
X00 01 11 10
P1P0
X00 01 11 10
N1
N0
N 1 = XP 1 + XP 1 P 0
N 0 = XP 1 P 0 + XP 1 P 0 + XP 1 P 0 = XP 1 P 0 + X ( P 1 P 0 )
Z = XP 1 P 0
SEQ. CIRCUITS
PATTERN DETECT EXAMPLE
SEQUENTIAL CIRCUITS
-INTRODUCTION
-DEVEL. LOGIC CIRCUITS
-PATTERN DETECT EX.
Notice that the previous Boolean functions can also be expressed with time
as follows.
N1 ( t ) = P1 ( t + 1 ) = X ( t ) P1 ( t ) + X ( t ) P1 ( t ) P0 ( t )
N0 ( t ) = P0 ( t + 1 ) = X ( t ) P1 ( t ) P0 ( t ) + X ( t ) P1 ( t ) P0 ( t )
+ X ( t ) P 1 ( t ) P0 ( t )
= X ( t ) P1 ( t ) P0 ( t ) + X ( t ) P1 ( t ) P0 ( t )
Z ( t ) = X P 1 ( t ) P0 ( t )
SEQ. CIRCUITS
PATTERN DETECT EXAMPLE
SEQUENTIAL CIRCUITS
-INTRODUCTION
-DEVEL. LOGIC CIRCUITS
-PATTERN DETECT EX.
N0
P0
1 2
N1
P1
1 2
X
R.M. Dansereau; v.1.0
FSM EXAMPLES
EXAMPLE #1
SEQUENTIAL CIRCUITS
-INTRODUCTION
-DEVEL. LOGIC CIRCUITS
-PATTERN DETECT EX.
FSM EXAMPLES
EXAMPLE #1
SEQUENTIAL CIRCUITS
FSM EXAMPLES
-EXAMPLE #1
Note that this machine can be a Moore machine. So, we can associate the
output with each state.
FSM EXAMPLES
EXAMPLE #1
SEQUENTIAL CIRCUITS
FSM EXAMPLES
-EXAMPLE #1
S EE p
S EO q
S OO p
S OE p
FSM EXAMPLES
EXAMPLE #1
SEQUENTIAL CIRCUITS
FSM EXAMPLES
-EXAMPLE #1
Finally, for each state, consider the effect for each possible input.
For instance, starting with state S EE , the next state for the three input a,
b, and c are determined as follows.
S EE p
S EO q
S OO p
S OE p
FSM EXAMPLES
EXAMPLE #1
SEQUENTIAL CIRCUITS
FSM EXAMPLES
-EXAMPLE #1
S EE p
S EO q
S OO p
c
a
a
b
S OE p
FSM EXAMPLES
EXAMPLE #1
SEQUENTIAL CIRCUITS
FSM EXAMPLES
-EXAMPLE #1
A state table can also be formed for this state diagram as follows.
First, assign a binary number to each state
S EE = 00 , S EO = 01 , S OO = 10 , S OE = 11
Assign a binary number to each input
a = 00, b = 01, c = 10
Assign a binary number to each output
p = 0, q = 1
Then for each state, find the next state for each input. In this case there
are three possible input values, so, three possible state transitions from
each state.
The state table on the following slide shows the results for this example.
FSM EXAMPLES
EXAMPLE #1
Present State
P1 P0
SEE =
SEE =
SEE =
SEO =
SEO =
SEO =
SOO =
SOO =
SOO =
SOE =
SOE =
SOE =
0
0
0
0
0
0
1
1
1
1
1
1
SEQUENTIAL CIRCUITS
FSM EXAMPLES
-EXAMPLE #1
Input
X
0
0
0
1
1
1
0
0
0
1
1
1
a = 00
b = 01
c = 10
a = 00
b = 01
c = 10
a = 00
b = 01
c = 10
a = 00
b = 01
c = 10
Next State
N1 N0
SOE =
SEO =
SEE =
SOO =
SEE =
SEO =
SEO =
SOE =
SOO =
SEE =
SOO =
SOE =
1
0
0
1
0
0
0
1
1
0
1
1
Output
Z
1
1
0
0
0
1
1
1
0
0
0
1
p=0
p=0
p=0
q=1
q=1
q=1
p=0
p=0
p=0
p=0
p=0
p=0
FSM EXAMPLES
EXAMPLE #1
SEQUENTIAL CIRCUITS
FSM EXAMPLES
-EXAMPLE #1
The Boolean function for the output can be determined from a Karnaugh
map as follows.
Note that an input of 11 is not possible since we only have three inputs
that we have assigned to 00, 01, and 10. We can therefore use dont
cares for this possible input.
P1P0
X1X0 00 01 11 10
00
01
11
XXXX
10
Z = P 1 P0
FSM EXAMPLES
EXAMPLE #1
SEQUENTIAL CIRCUITS
FSM EXAMPLES
-EXAMPLE #1
The Boolean function for the next state bit can also be determined from
Karnaugh maps as follows.
P1P0
X1X0 00 01 11 10
P1P0
X1X0 00 01 11 10
00
00
01
01
11
XXXX
11
XXXX
10
10
N1 = P1 X1 X0
N0 = P0 X1 + P0 X1 = P0 X1
FSM EXAMPLES
EXAMPLE #1
SEQUENTIAL CIRCUITS
FSM EXAMPLES
-EXAMPLE #1
The following logic circuit can be made with these Boolean functions.
N1 = P1 X1 X0
N0 = P0 X1
Z = P 1 P0
N0
X1
P0
1 2
X0
N1
1 2
P1
FSM EXAMPLES
EXAMPLE #2
SEQUENTIAL CIRCUITS
FSM EXAMPLES
-EXAMPLE #1
FSM EXAMPLES
EXAMPLE #2
SEQUENTIAL CIRCUITS
FSM EXAMPLES
-EXAMPLE #1
-EXAMPLE #2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Input
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Next State
N2 N1 N0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Output
Z
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
FSM EXAMPLES
EXAMPLE #2
SEQUENTIAL CIRCUITS
FSM EXAMPLES
-EXAMPLE #1
-EXAMPLE #2
0/0
0/0
1/0
S1
1/0
0/0
1/0
S2
S3
0/0
0/0
1/1
0/0
S4
S5
S6
1/0
1/1
S7
0/0
0/0
R.M. Dansereau; v.1.0