Atmel 11269 32 Bit Cortex A5 Microcontroller SAMA5D3 Xplained User Guide

ARM-based Embedded MPUs
SAMA5D3 Xplained
USER GUIDE
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Introduction
This user guide introduces the Atmel SAMA5D3 Xplained evaluation kit and describes the development and debugging capabilities for applications running on a SAMA5D36 ARM-based embedded microprocessor unit (eMPU).
11269AATARM20-Feb-14
Scope
This guide provides details on the SAMA5D3 Xplained evaluation kit. It is made up of four main sections:

Section 1. describes the evaluation kit content and its main features. Section 2. provides instructions to power up the SAMA5D3 Xplained board. Section 3. provides an overview of the SAMA5D3 Xplained board. Section 4. describes the SAMA5D3 Xplained board components.
Contents
Boards
One SAMA5D3 Xplained board One micro-AB type USB cable
Cables
A welcome letter
Related Items

Atmel SAMA5D3 Series Datasheet SAMA5D3 Xplained Getting Started
SAMA5D3 Xplained User Guide [USER GUIDE]

Table of Contents
1. Evaluation Kit Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 1.2 Electrostatic Warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Power Supply Warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2. Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 2.2 Power up the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Sample Code and Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3. Hardware Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 3.2 3.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Equipment List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Board features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4. Board Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1 4.2 4.3 4.4 Board Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Function Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Other Connector Details and PIO Usage Summary . . . . . . . . . . . . . . . . . . . . 34 SAMA5D3 Xplained Board Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

1.
Evaluation Kit Specifications

Table 1-1. Evaluation Kit Specifications Specifications
Characteristic Temperature: - Operating - Storage Relative Humidity RoHS status Ordering code
0C to +70C -40C to +85C 0 to 90% (non-condensing) Compliant ATSAMA5D3-XPLD
1.1
Electrostatic Warning
Warning:
ESD-Sensitive Electronic Equipment!
Electrostatic sensitive device
The evaluation kit is shipped in a protective anti-static package. The board system must not be subject to high electrostatic potentials.
We strongly recommend using a grounding strap or similar ESD protective device when handling the board in hostile ESD environments (offices with synthetic carpet, for example). Avoid touching the component pins or any other metallic element on the board.
1.2
Power Supply Warning

Warning: Hardware Power Supply Limitation
Using a power adapter greater than 5Vcc (e.g. the 12Vcc power adapters from other kits such as Arduino kits) may damage the board.
Warning:Hardware Power Budget
Using the USB as the main power source (max. 500 mA) is acceptable only with the use of the on-board peripherals and low-power LCD extension. When external peripheral or add-on boards need to be powered, we recommend the use of an external power adapter connected to a J2 DC Jack (can provide up to 1.2A on the 3.3V node).

2.
Power Up
Several power source options are available to power up the SAMA5D3 Xplained board. The board can be:

USB-powered through the USB Micro-AB connector (J6 connector - default configuration) Powered through an external AC-to-DC adapter connected via a 2.1 mm center-positive plug into the optional power jack of the board. The recommended output voltage range of the power adapter is 5V at 2A. Powered through the Arduino shield.
Warning:
Unlike Arduino Uno boards, the SAMA5D3 Xplained board runs at 3.3V. The maximum voltage that the I/O pins can tolerate is 3.3V. Providing higher voltages (e.g. 5V) to an I/O pin could damage the board.
2.1
Power up the Board

Unpack the board, taking care to avoid electrostatic discharge. Simply connect the USB Micro-AB cable to the connector (J6).Then, connect the other end of the cable to a free USB port of your PC.
Table 2-1.
Electrical Characteristics Values 5 VCC 6 VCC 1.2A 3.3V only
Electrical Parameter Input voltage Maximum input voltage Max DC 3.3V current available I/O Voltage
2.2
Sample Code and Technical Support

After booting up the board, you can run sample code or your own application on the board. You can download sample code and get technical support from the Atmel website. Linux software and demos can be found on the website Linux4SAM.

3.
3.1
Hardware Introduction
Introduction
The Atmel SAMA5D3 Xplained board is a fully-featured evaluation platform for Atmel SAMA5D3 series microcontrollers. It allows users to extensively evaluate, prototype and create application-specific designs.
3.2
Equipment List
The SAMA5D3 Xplained board is built around the integration of a Cortex-A5-based microcontroller (BGA 324 package) with external memory, dual Ethernet physical layer transceiver, two SD/MMC interfaces, two host USB ports and one device USB port, one 24-bit RGB LCD interface and one debug interface. Seven headers, compatible with Arduino R3, are available for various shield connections.

3.3
Board features
Table 3-1. Board Specifications Specifications 125 x 75 x 20mm (10-layers) SAMA5D36 (324-ball BGA package) ARM Cortex-A5 Processor with ARM v7-A Thumb2 instruction set, core frequency up to 536 MHz. 12-MHz crystal oscillator 32.768-kHz crystal oscillator 2x 1Gb DDR2 (16M x 16 bits x 8 banks) 1x 2Gb SLC NAND Flash (256M x 8 bits) One Serial EEPROM SPI One 1-Wire EEPROM One 8-bit SD card connector One optional 4-bit Micro-SD card connector Two USB Hosts with power switch One Micro-AB USB device One LCD interface connector, LCD TFT Controller with overlay, alphablending, rotation, scaling and color space conversion One Gigabit Ethernet PHY (GRMII 10/100/1000) One Ethernet PHY (RMII 10/100) One JTAG interface connector One serial DBGU interface (3.3V level) Arduino R3 compatible set of headers Expansion connectors The SAMA5D36 GPIO,TWI, SPI, USART, UART, Audio and ISI interfaces are accessible through these headers. 5V from USB or power jack or Arduino shield Board supply voltage Battery User interface On-board power regulation is performed by a Power Management Unit (PMU) On-board optional power Cap for CMOS backup Reset, wakeup and free user pushbutton One red user/power LED and one blue user LED
Characteristics PCB characteristics Processor Processor clock sources
Memory
Optional on-board memory
SD/MMC
USB Display interface Ethernet
Debug port

4.
4.1
Board Components
Board Overview
The full-featured SAMA5D3 Xplained board integrates several peripherals and interface connectors, as shown in Figure 4-1.
Figure 4-1.
SAMA5D3 Xplained Board Overview

J18 PIO Expansion J20 PIO Expansion SPI Interface J19 PIO Expansion
2Gb Nand Flash Memory J15 PIO Expansion
USB A Device Supply Input
USB Host Interfaces
1Gb DDR2 Memory SAMA5D36
ATSAMA5D36 CU
1401 A XX XXXXXXXXXX
ARM
1Gb DDR2 Memory
GigaBit Ethernet
t Optional Supply Input Ethernet 10/100 Voltages and Reset Interface
Free User Push Button A ADC Inputs and CAN Interfaces ector LCD Connector Debug Interface
System Buttons JTAG Interface ADC Inputs Expansion

The SAMA5D3 Xplained board is equipped with the following interface connectors:

J2: Main power supply J6: USB A device, that supports USB device using a Micro-AB connector J7 (upper): USB B Host, that supports USB host using a type A connector J7 (lower): USB C Host, that supports USB host using a type A connector J23: Serial DBGU 3.3V level J24: JTAG, 20-pin IDC connector J11: Micro-SD connector J10: SD/MMC connector J12: Gigabit Ethernet ETH0 J13: Ethernet ETH1 J22: Expansion connector with all LCD controller signals for display module connection (QTouch, TFT LCD display with Touch Screen and backlight C41: Optional SuperCap J14 to J21: Seven expansion connectors with Arduino R3 compatible PIO signals Various test points located throughout the board
4.2
Function Blocks
Evaluation Kit Architecture
Push Buttons Reset Force PwrOn
Figure 4-2.
Single PMU Solution
5V INPUT USB DEVICE USB Host x2 JTAG DBGU
5V & 3V3 USB A,B,C Power rails
ATMEL SAMA5D36 CORTEX-A5 PROCESSOR

EBI
JTAG & DBGU USER LEDS PIO
VBAT
2Gb DDR2 SDRAM

(Up to 4Gb)
Expansion Headers
ANALOG Reference
2Gb NAND FLASH

(Up to 4Gb)
PIO A,...E
PIO A,...E
LCD Connector
SD CARD
Micro SD CARD
SERIAL DATA FLASH
10/100/1000 FAST ETHERNET ETH0
10/100 ETHERNET ETH1

4.2.1
Processor
The SAMA5D3 Xplained board is built around the SAMA5D36, a Cortex-A5 application processor which combines highperformance computing device with low-power consumption and a wide range of communication peripherals. It features a combination of user interface functionalities and high data rate IOs, including LCD controller, touchscreen, camera interface, Gigabit and 10/100 Ethernet ports, high-speed USB and SDIO. The ARM Cortex-A5 supports the latest generation of DDR2 and NAND Flash memory interfaces for program and data storage. An internal 166-MHz multi-layer bus architecture associated with 24 DMA channels and two 64-Kbyte SRAM blocks, sustains the high bandwidth required by the processor and the high-speed peripherals.
4.2.2
Clock Circuitry
The SAMA5D3 Xplained evaluation board features four clock sources:

Two clocks are alternatives for the SAMA5D3 series processor main clock Two crystal oscillators are used for the GETH and Ethernet MII/RMII chip
Main Components Associated with the Clock Systems Description Crystal for internal clock, 12 MHz Crystal for RTC clock, 32.768 kHz Oscillator for ethernet clock RGMII, 25 MHz Oscillator for ethernet clock RMII, 25 MHz Component Assignment Y1 Y2 Y3 Y4
Table 4-1. Quantity 1 1 1 1
4.2.3
Power Supplies
The on-board power supply generation is based on the Active-Semi Power Management Unit (PMU) featuring a 3channel (3.3V / 1.8V /1.2V or 1.0V) topology. For a maximum efficiency, these supply channels are generated by three integrated step-down converters. In addition to these 3 DCDC channels, 4 LDO channels with low noise and high PSRR performance are available for the application. These channels are disabled at startup by default and can be turned on and adjusted under software control through an IC link. They are also used to supply the 2.5V VDDFUSE and the 3.3V VDDANA power inputs of the processor. The power supply sequencing of the three primary channels is controlled by the PMU itself in perfect compliance with the SAMAD3 requirements. The turn-on sequence is: 3.3V first, then 1.8V and finally 1.2V. Table 4-2 summarizes the power specifications.
Table 4-2. Nominal 3.0V 3.3V 3.3V 3.3V 3.3V 3.3V 1.2V Supply Group Configuration Name VDDBU VDDIOP0 VDDIOP1 VDDUTMII VDDOSC VDDANA VDDCORE Power domains The slow clock oscillator, the internal 32K RC, the internal 12M RC and a part of the system controller A part of peripheral I/O lines A part of peripheral I/O lines The three USB interfaces The main oscillator cells The analog-to-digital converter The core, including the processor, the embedded memories and the peripherals PMU Power source Optional on-board battery

10
Table 4-2. Nominal 1.2V 1.2V 1.8V 1.8V 3.0V to 3.3V 2.5V
Supply Group Configuration (Continued) Name VDDUTMIC VDDPLLA VDDIODDR VDDIOM ADVREF VDDFUSE Power domains The USB UTMI + core The PLLA cell DDR2 interface I/O lines NAND, NOR Flash and SMC interface I/O lines ADC reference voltage Fuse box for programming J15 header PMU PMU Power source
Note:
Jumper footprints are available on board to measure power consumption on main power lines. By default, the jumpers are not implemented. They are short-circuited by a thin PCB wire. To use this functionality, open the short circuit and mount a 2-pin jumper.
Figure 4-3.
Board Power Management Schematic

JP1 DNP(JUMPER) VDDCORE
1 2
AVDDL_PLL L1 1
2 180ohm at 100MHz
AVDDL
L2 1
2 180ohm at 100MHz
DVDDL
5V_MAIN MN1 3V3 3V3 C1 4.7uF C2 4.7uF C3 4.7uF R4 1R C6 1uF ACT8865
5V_MAIN
L3 1
2 180ohm at 100MHz
31 26 16 25 23
VP1 VP2 VP3 NC2 VDDREF
INL45 INL67
5 6
C4 1uF L5 C5 1uF 2.2uH C8 10uF C9 10uF C10 100nF (1V8) R5 JP2 DNP(JUMPER) VDDIODDR 2R2
L4 10uH60mA
VDDPLLA C7 4.7uF
R6 1.5K 1% [5,9,10,11] NRST [7] PC31 [5] WKUP [7] PE30 [5] SHDN R18 1K
R7 1.5K 1%
R8 10K
SW1 OUT1 11 12 13 20 18 10 17 21 22 nRST0 nIRQ nPBSTAT VSEL NC1 PWRHLD PWREN SCL SDA
30 1
1 2
L6 R10 2R2 10uH60mA C11 4.7uF JP3 DNP(JUMPER) 3V3 L7 2.2uH C12 10uF C13 10uF C14 100nF (1V2)
VDDUTMIC
R186 R9
0R DNP(0R) R11 0R
SW2 OUT2
27 24
VDDIOP0
[7] TWCK_PMIC [7] TWD_PMIC
PC27 PC26
SW3 OUT3
15 19
C15 10uF
C16 10uF
C17 100nF FUSE_2V5
1 2
L9
2.2uH
(3V3)
L8 1
2 180ohm at 100MHz
VDDIOP1
R14 50K
Auto PWRON (option) R12
C18 47nF
32
REFBP OUT4 OUT5
L10 1
3 4 7 8
C21 2.2uF C22 2.2uF C23 2.2uF C24 2.2uF
(2V5) VDDANA (3V3) C19 100nF JP4 DNP(JUMPER)
2 180ohm at 100MHz
VDDIOM
C20 100nF
49.9K
nPBIN OUT6
R13 R16
0R 0R
TP1 SMD TP2 SMD
C25 100nF
1 2
L11 1
2 180ohm at 100MHz
Q1 3
GNDP1
GNDP2
GNDP3
EXPAD
R15 0R
OUT7 GNDA
L12 R17 2R2 10uH60mA C26 4.7uF
VDDOSC
BP1
1
R19 100K 1% IRLML2502 C130 10nF
BP2
29
28
14
2
BP2
BP1
WAKUP or Force Power ON
RESET
33

11
4.2.3.1
Power Options Several power options are available to configure the SAMA5D3 Xplained board powering scheme. The power sources are selected by a set of 0R resistors. The USB-powered operation is the default configuration. The power source is the USB device port (J6) connected to a PC or a mini-AB 5V DC supply. The USB supply is sufficient to power the board in most applications if USB host ports are not used. If USB host ports are used, it is recommended to use a DC supply source. Schematic diagrams of various power options are illustrated in Figure 4-4.
Figure 4-4.
Input Powering Scheme Option Schematic
[5] Vbus
R1 R175
0R 0R DNP(0R) DNP(0R) DNP(0R) DNP(0R)
5V_MAIN
[11] 5V_Ext J2
R2 R176
2
D4 P4SMAJ5.0A
3 2 1
DNP(DC JACK)
R3 R177
Note:
USB-powered operation is a good single cable solution because it combines powering and board control through a unique cable. Consequently, it eliminates the need for other wires and batteries. This power option is suitable for most projects that only require 5 volts at up to 500 mA.
4.2.3.2
Mains Power Adapter A mains power supply adapter can be used to provide power to the board. A regulated 5V DC supply of typically 2A is required but a current range of 3A is recommended if the USB ports and expansion headers are likely to be used. It needs a 2.1 mm plug with a center-hot configuration. If you are using the USB host ports or expansion board Arduino shields, a higher current is required. To supply the full 500 mA per port, a mains power adapter must be used.
4.2.3.3
VBAT By default, VDDBU is delivered through the 3.3V node. An optional SuperCap (C41), used for real-time clock backup, is provided. The board does not come equipped with the SuperCap. When the SuperCap is not installed, an R185 must be installed. You must make sure that the R185 is removed prior to installing the SuperCap.
Figure 4-5.
VBAT Powering Scheme Option Schematic

3V3 TP4 SMD
1
(Super)-Capacitor energy storage
Place TP4 to Bottom
C27 10nF
D1
R20
100R
Populate R185 if no Super Cap (C41)
3
BAT54CLT1 R185 C41 1.5K 1% 3V3 DNP(0.2F/3V3) R21 100K 1%
VDDBU C28 100nF
R22 DNP(100K)
[11] VBat
R23 1.5K 1% [4,9,10,11] NRST NRST
[11] TDI [11] TMS [11] TCK [11] TDO [11] NTRST
TDI TMS TCK TDO NTRST
T9 R8 N10 P9 M11 P11 V9

10K
JTAGSEL TDI TMS TCK TDO NTRST NRST TST BMS
R25
U15 U9

VDDBU
V15
12
4.2.4
Reset Circuitry
The reset sources for the SAMA5D3 Xplained board are:

Power-on reset from the Power Management Unit (PMU), Reset Pushbutton BP2, JTAG reset from an in-circuit emulator (through JTAG interface)
4.2.5
Memory Organization
The SAMA5D3x-series processor features a DDR2/SDRAM memory interface and an External Bus Interface (EBI) to interface with a wide range of external memories and to almost any kind of parallel peripherals. The memory devices that equip the SAMA5D3 Xplained evaluation kit are as follows:
Two DDR2/SDRAM (MT47H64M16HR) used as main system memory (256 MByte). The board includes 2 Gbits of on-board soldered DDR2 (double data rate) SDRAM. The footprints can also host two DDR2 (MT47H128M16RT) from Micron for a total of 512 MBytes of DDR2 memory. The memory bus is 32 bits wide and operates with a frequency of up to 166 MHz (See Figure 4-6). One NAND Flash (MT29F2G08ABAEAWP) connected to the processor. The default size is 256 MBytes. The footprint can also host a 4-Gbit Micron chip for a total of 512 MBytes of NAND Flash memory (See Figure 4-7).
Figure 4-6.
DDR_D[0..31]
DDR2 Schematic
MN5 MN4 DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13 DDR_BA0 DDR_BA1 DDR_BA2 VDDIODDR R36 R38 DNP(1K) 0R DDR_CKE DDR_CLK DDR_CLKN DDR_CS DDR_CAS DDR_RAS DDR_WE DDR_DQS1 R40 4.7K DDR_DQS0 R42 4.7K DDR_DQM1 DDR_DQM0
DDR_A[0..13]
M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2 R8 L2 L3 L1 K9
A0 DDR2 SDRAM A1 A2 MT47H64M16HR A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 BA0 BA1 BA2 ODT
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 VDD VDD VDD VDD VDD VDDL
G8 G2 H7 H3 H1 H9 F1 F9 C8 C2 D7 D3 D1 D9 B1 B9 A1 E1 J9 M9 R1 J1 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 J2 A3 E3 J3 N1 P9 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 J7
DDR_D0 DDR_D1 DDR_D2 DDR_D3 DDR_D4 DDR_D5 DDR_D6 DDR_D7 DDR_D8 DDR_D9 DDR_D10 DDR_D11 DDR_D12 DDR_D13 DDR_D14 DDR_D15 VDDIODDR C67 C69 C71 C73 C75 100nF 100nF 100nF 100nF 100nF
DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13 DDR_BA0 DDR_BA1 DDR_BA2 VDDIODDR R35 DNP(1K) R37 0R
M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2 R8 L2 L3 L1 K9
A0 DDR2 SDRAM A1 A2 MT47H64M16HR A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 BA0 BA1 BA2 ODT
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 VDD VDD VDD VDD VDD VDDL
G8 G2 H7 H3 H1 H9 F1 F9 C8 C2 D7 D3 D1 D9 B1 B9 A1 E1 J9 M9 R1 J1 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 J2 A3 E3 J3 N1 P9 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 J7
DDR_D16 DDR_D17 DDR_D18 DDR_D19 DDR_D20 DDR_D21 DDR_D22 DDR_D23 DDR_D24 DDR_D25 DDR_D26 DDR_D27 DDR_D28 DDR_D29 DDR_D30 DDR_D31 VDDIODDR C66 C68 C70 C72 C74 100nF 100nF 100nF 100nF 100nF
DDR_CKE DDR_CLK DDR_CLKN DDR_CS DDR_CAS DDR_RAS DDR_WE DDR_DQS3 R39 4.7K
K2 J8 K8 L8 L7 K7 K3 B7 A8 F7 E8 B3 F3
K2 J8 K8 L8 L7 K7 K3 B7 A8 F7 E8 B3 F3
CKE CK CK CS CAS RAS WE UDQS UDQS LDQS LDQS UDM LDM VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VREF VSS VSS VSS VSS VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSDL
CKE CK CK CS CAS RAS WE UDQS UDQS LDQS LDQS UDM LDM VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VREF VSS VSS VSS VSS VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSDL
C76 100nF C78 C80 C82 C84 C86 C88 C90 C92 C94 C96 DDR_VREF C98 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF
C77 100nF C79 C81 C83 C85 C87 C89 C91 C93 C95 C97 DDR_VREF C100 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF
DDR_DQS2 R41 4.7K DDR_DQM3 DDR_DQM2
A2 E2 R3 R7
RFU1 RFU2 RFU3 RFU4
VDDIODDR L16 10uH60mA C101 4.7uF R45 1R C102 100nF TP3 R46 SMD 1.5K 1%
A2 E2 R3 R7
RFU1 RFU2 RFU3 RFU4
DDR_VREF C103 4.7uF C104 100nF
R47 1.5K 1%

13
Figure 4-7.
NAND Flash Schematic

VDDIOM PE22 PE21 NRD NWE (NANDCLE) 16 (NANDALE) 17 8 18 (NANDCE) 9 MN6 MT29F2G08ABAEAWP
R48 100K 1% NANDRDY
R49 100K 1%
R50 100K 1%
CLE ALE RE WE CE R/B WP N.C1 N.C2 N.C3 N.C4 N.C5 N.C6 N.C7 N.C8 N.C9 N.C10 N.C11 N.C12 N.C13 N.C14 DNU1 DNU2 DNU3
7 19 1 2 3 4 5 6 10 11 14 15 20 23 24 35 21 22 38
JP5 NCS3
1 2
JUMPER
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8_N.C I/O9_N.C I/O10_N.C I/O11_N.C I/O12_N.C I/O13_N.C I/O14_N.C I/O15_N.C VCC VCC VCC_N.C VCC_N.C VSS VSS VSS_N.C VSS_N.C
29 30 31 32 41 42 43 44 26 27 28 33 40 45 46 47 12 37 34 39 13 36 25 48
M_EBI_D0 M_EBI_D1 M_EBI_D2 M_EBI_D3 M_EBI_D4 M_EBI_D5 M_EBI_D6 M_EBI_D7
VDDIOM
C105 100nF
C106 100nF
The following memory part numbers are recommended:

Table 4-3. Part Number MT47H128M16 MT47H128M32 MT29F2G08 MT29F4G08 Recommended Memories Supplier Micron Micron Micron Micron Size 2 Gb (16 M x 16 x 8 banks) 4 Gb (32 M x 16 x 8 banks) 2 Gb 4 Gb Type DDR2 - BGA DDR2 - BGA NAND Flash - TSOP NAND Flash - TSOP
4.2.6
SD/MMC Interface
The SAMA5D3 Xplained board features two high-speed Multimedia Card Interfaces (MCI).

The first interface is used as an 8-bit interface (MCI0), connected to a SD/MMC card slot (J10) located on the bottom side of the PCB. The second interface is used as a 4-bit interface (MCI1), connected to an optional Micro-SD card connector (J11) located on the top side of the PCB. The power source is VCC (3.3 volts).
The MCI0 SD card power line is enabled by default. It is PIO-controlled through a MOSFET transistor. Note: 4.2.6.1
J10 SD Card Slot When a card is inserted into the SD/MMC connector, the Card Detect pin (PE0) is tied to ground.
Figure 4-8.
J10 SD Card Schematic

VDD_MCI0 Q3 IRLML6402 VDDIOP1
VDDIOP1
2
R53 100K 1%
1
PE2 [7]
R121 R122 R123 R124 R125 R126 R127 R128 R54
VDDIOM R55 C108 10uF C109 100nF DNP(4.7K) R56 10K
68K
68K
68K
68K
68K
68K
68K
[7] PE0 [7] PD2 [7] PD1 [7] PD9 [7] PD0 [7] PD4 [7] PD3
(MCI0_CD) J10 (MCI0_DA1) (MCI0_DA0) (MCI0_CK) (MCI0_CDA) (MCI0_DA3) (MCI0_DA2) R182 22R
68K
10K
8 7 6 5 4 3 2 1 9
7SDMM-B0-2211
16 15 14
R57 0R
(MCI0_WP)
13 12 11 10
[7] [7] [7] [7]
PD5 PD6 PD7 PD8
(MCI0_DA4) (MCI0_DA5) (MCI0_DA6) (MCI0_DA7)

14
4.2.6.2
J11 SD Card Slot (optional) When a card is inserted into the Micro SD connector, the Card Detect pin is tied to ground. This is detected on pin PE1 of the main processor.
Figure 4-9.
J11 Micro SD Card Schematic

VDDIOP1 VDDIOM R130 R131 R132 R129 R112 R58
68K
68K
68K
68K
10K
DNP(68K)
R59 10K J11
[7] [7] [7] [7]
PB20 PB21 PB22 PB23
(MCI1_DA0) (MCI1_DA1) (MCI1_DA2) (MCI1_DA3) (MCI1_CDA) (MCI1_CK) R183 22R
7 8 1 2 3 5 4 6
DAT0 DAT1 DAT2 DAT3 CMD CLK VDD VSS CD PGND

DNP(MCTF-0403)
[7] PB19 [7] PB24
PGND PGND PGND NC NC
11 12 13 14 15
[7] PE1
(MCI1_CD)
9 10
C110 10uF C111 100nF
Micro SD CARD INTERFACE - MCI1
4.2.7
Serial Peripheral Interface (SPI)

The SAMA5D3X-series processor features two high-speed Serial Peripheral Interfaces. One port is used to interface with the optional on-board serial DataFlash. There are four main signals used in the SPI interface; Clock, Data In, Data Out, and Chip Select.
Figure 4-10.
Optional Serial DataFlash Schematic

VDDIOP1 R52 100K 1% MN8 PD11 PD10 PD12 PD13 (SPI0_MOSI) (SPI0_MIS0) (SPI0_SPCK) (SPI0_CS) VDDIOP1
5 2 6 1
VCC DQO DQ1 C W/Vpp/DQ2 HOLD/DQ3 S GND
8 3 7 4
C107 100nF
1 2
DNP(N25Q032A13ESE40F) JP6 JUMPER

15
4.2.8
Optional 1-Wire EEPROM

The SAMA5D3 Xplained board can use a 1-Wire device as soft label to store data such as chip type, manufacturers name, production date, etc.
Figure 4-11.
Optional One-Wire EEPROM Schematic

VDDIOM R51 1.5K MN11 PE23
IO GND 3
NC
DNP(DS28E05) MN7
GND
IO
NC1 NC2 NC3 NC4
3 4 5 6
DNP(DS2431)
4.2.9
10/100/100 Ethernet Port

The SAMA5D3 Xplained board features a MICREL PHY device (KSZ9031RN) operating at 10/100/1000 Mb/s. The board supports the RGMII interface mode. The Ethernet interface consists of four pairs of low-voltage differential pair signals designated from GRX and GTX plus control signals for link activity indicators. These signals are routed to the 10/100/1000 BaseT RJ45 connector (J12). For monitoring and control purposes, LEDs are integrated in the RJ45 connectors to indicate activity, link, and speed status information for the corresponding ports. For more information about the Ethernet controller device, refer to the MICREL KSZ9031RN datasheet.
Figure 4-12.
Gigabit Ethernet Schematic

10Base-T/100Base-TX/1000BASE-T
C112 20pF XI AVDDL_PLL Y3 25MHz + C113 10uF XO VDDIOP1 L17 1 180ohm at 100MHz 2 + C117 10uF VDDIOP1 C118 10nF C119 10nF AVDDH C120 10nF R62 22R VDDIOP1 C121 10nF C122 10nF C123 10nF + C126 10uF G125CK PB18 INT_GETHR PB10 PB17 GMDIO C114 10nF C115 10nF R60 R61 4.7K 1K VDDIOP1 NRST [4,5,10,11] PB[0..31] [7,8,10,11]
2 3
C116
20pF
R63
12.1K 1%
R71
R72
470R
470R
J12 ETH0_A+ ETH0_AETH0_B+ ETH0_BETH0_C+ ETH0_CETH0_D+ ETH0_DAVDDH R111 DNP(0R) C125 DNP(10uF 0805)
48 47 46 45 44 43 42 41 40 39 38 37
49
AVDDL + C127 10uF C128 10nF C129 10nF
XI XO
MN10 KSZ9031RN R64 R65 R66 R67 4.7K 4.7K 4.7K 4.7K
VDDIOP1
1 2 3 4 7 8 9 10 5 6
C124 100nF
TD1+ TD1TD2+ TD2TD3+ TD3TD4+ TD4TCT RCT
GRLA GRLC
11 12 Left Green LED 13 14 Right Yellow LED 15 16 17 18
ETH0_LED2 LINK
ISET AVDDH XI XO AVDDL_PLL LDO_O RESET_N CLK125_NDO DVDDH DVDDL INT_N MDIO
P_GND
YELC YELA
ETH0_LED1 ACT
ETH0_A+ ETH0_AETH0_B+ ETH0_BETH0_C+ ETH0_CETH0_D+ ETH0_D-
GND GND GND GND
48F-01GY2DPL2NL EARTH_ETH0
1 2 3 4 5 6 7 8 9 10 11 12
AVDDH TXRXP_A TXRXM_A AVDDL TXRXP_B TXRXM_B TXRXP_C TXRXM_C AVDDL TXRXP_D TXRXM_D AVDDH
KSZ9031RNI 48-pin QFN
MDC RX_CLK DVDDH RX_DV RXD0 RXD1 DVDDL VSS RXD2 RXD3 DVDDL TX_EN
36 35 34 33 32 31 30 29 28 27 26 25
R68
22R
GMDC GRXCK GRX_CTL GRX0 GRX1 GRX2 GRX3 GTX_CTL
PB16 PB11 PB13 PB4 PB5 PB6 PB7 PB9
ETH0_GND
VDDIOP1 R69 4.7K L18 1 180ohm at 100MHz 2 EARTH_ETH0
DVDDL + C132 10uF C133 10nF C134 10nF C135 10nF C136 10nF C137 10nF C138 10nF
13 14 15 16 17 18 19 20 21 22 23 24
VSS_PS DVDDL LED2 DVDDH LED1 DVDDL TXD0 TXD1 TXD2 TXD3 DVDDL GTX_CLK
R70
22R
R73 ETH0_GND
0R
ETH0_LED2 ETH0_LED1
GTXCK GTX3 GTX2 GTX1 GTX0
PB8 PB3 PB2 PB1 PB0

16
4.2.10 Ethernet 10/100 Port

The SAMA5D3 Xplained board features a MICREL PHY device (KSZ8081RNB) operating at 10/100 Mb/s. The board supports RMII interface modes. The Ethernet interface consists of two pairs of low-voltage differential pair signals designated from GRX and GTX plus control signals for link activity indicators. These signals are routed to the 10/100 BaseT RJ45 connector (J13). For monitoring and control purposes, a LED functionality is added on the RJ45 connectors to indicate activity, link, and speed status information for the corresponding ports. For more information about the Ethernet controller device, refer to the MICREL KSZ8081RNB controller manufacturer's datasheet.
Figure 4-13. RMII Ethernet Schematic
VDDIOP1 VDDIOP0 10K R113 10K R114 R74 1K R75 1K 10K R115
10Base-T/100Base-TX
13F-64GYD2PL2NL J13 MN9
TX+
TD+ CT
1 4 2
TX+
TX+
RXC/B-CAST_OFF TXP TXD1 TXD0 TXEN RXD3/PHYAD0 RXD2/PHYAD1 RXD1/PHYAD2 RXD0/DUPLEX RXDV/CONFIG2 RXER/ISO CRS/CONFIG1 COL/CONFIG0
19 25 24 23 13 14 15 16 18 20 29 28
ETH1_PC7 ETH1_PC1 ETH1_PC0 ETH1_PC4 [7] [7] [7] [7]
TX-
TD-
TX-
TX-
TXM
RX+
RD+ CT
3 5 6
C139 100nF C140 100nF
RX+
RX+
RXP
ETH1_PC3 [7] ETH1_PC2 [7] ETH1_PC5 [7] ETH1_PC6 [7]
RX-
RD-
RX-
RXC141 C142 2.2uF 100nF
4 2 1 33 22 26 27 R76 10
RXM VDD_1V2 GND PADDLE TXC TXD2 TXD3 REXT MDC MDIO INTRP/NAND 12 11 21
E1_AVDDT L19 10K R116 10K R117 10K R118 10K R119 10K R120 VDDIOP0 ETH1_PC8 [7] ETH1_PC9 [7] PB12 [7]
4 5
75
75
75 NC
7
GND_ETH1
13 14
EARTH_ETH1
7 8
75
1nF
8
6.49k/1% EARTH_ETH1
VDDA_3V3
1
C143 + C144 100nF 10uF
2 180ohm at 100MHz
15 16
Right yellow LED
Left Green LED

VDDIOP0 ETH1_XO R77 10K ETH1_LED1 R78 10K ETH1_XI
8 9 30 31
XO XI LED0/NWAYEN LED1/SPEED VDDIO 17

C145 + C146 100nF 10uF
12
11
10
VDDIOP0 R79 R80 470R 470R
ACT LINK
ETH1_LED0 ETH1_LED1
ETH1_LED0
RESET
KSZ8081RNB
32
NRST [4,5,9,11]
C147 VDDIOP0
20pF
ETH1_XI
1
Y4 25MHz
3 2 180ohm at 100MHz
EARTH_ETH1 C149
R81 GND_ETH1
0R
L20 1
+ C148 10uF
ETH1_XO 20pF
4.2.11 Indicators
Two LEDs are available on the SAMA5D3 Xplained board. Both can be software-controlled by the user.

The red LED indicates that power is applied to the board (by default). It can be controlled via software. The blue LED is mainly controlled by one GPIO line.
LED Indicators Schematic
3V3 [4,7,8,11] PE[0..31] PE23 R32 470R D2
Figure 4-14.
BLUE
PE24 1
R33
100K 1%
LED
D3
2
Q2 IRLML2502
R34 470R
RED

17
4.2.12 USB
The SAMA5D3 Xplained board features three USB communication ports:

Port A: High-speed (EHCI) and full-speed (OHCI) host multiplexed with high-speed USB device Micro-AB connector (J6) Port B: High-speed (EHCI) and full-speed (OHCI) host, standard type A connector (J7 upper port) Port C: Full-speed OHCI host, standard type A connector (J7 lower port)
The two USB host ports are equipped with 500-mA high-side power switch for self-powered and bus-powered applications. The USB device port A (J6) features a VBUS insert detection function through the ladder-type resistors R26 and R27.
Figure 4-15. USB Interface Schematic
[7,11] PE9 (VBUS_SENSE) R26 R27 200K C53 C5 3 [4] Vbus 20pF p 100K 1% 12MHz
C51 C5 1
20pF p
V8
VDDOSC XOUT
MN2H SAMA5D3x_BGA324
VDDUTMII VDDPLLA
U16 4
32.768K Y2
XIN32
J6 UBAF-1015P VBUS DM DP ID GND
C56 C5 6
20pF
USB A DEVICE INTERFACE
V16 U6 V6 V10 U10 V12 U12 V14 U14 R11
XOUT32 DIBN DIBP HHSDMA HHSDPA HHSDMB HHSDPB GNDCORE_1 GNDCORE_2 GNDCORE_3 GNDCORE_4 GNDCORE_5 GNDCORE_6 GNDUTMI_1 GNDIOM_1 GNDIOM_2 HHSDMC HHSDPC GNDPLL GNDBU VBG GNDIODDR_1 GNDIODDR_2 GNDIODDR_3 GNDIODDR_4 GNDIODDR_5 VDDANA
VDDUTMIC
1 2 3 4 5
HHSDMA HHSDPA HHSDMB HHSDPB HHSDMC HHSDPC
GNDIOP_1 GNDIOP_2 GNDIOP_3 GNDIOP_4
GNDOSC GNDFUSE
GNDANA
R31
EARTH_USB_A L21 1 180ohm at 100MHz 2
ADVREF
P10
T11 P4
A16 C9 N13 N1 3 T8 T14 V17
E14 F10 F13 F15 H14 H1 4
J7 N11 N11 U7 E5
J11 J1 1 T17
EARTH_USB_A
R30 C60 5.62K 1% 10pF 0R
GNDUTMI MN3 GNDUTMI J7 Dual USB A 5V_USBC L13 1 C61 100nF C62 10uF
J7_USB_A_Up
5V_USBB HHSDMB HHSDPB
J7_USB_B_Down
1 2 3 4
5V_USBC HHSDMC HHSDPC 5V_USBB
5 6 7 8
A B
8 2 180ohm at 100MHz 5V_MAIN 7 C63 100nF 6
OUTA IN GNG OUTB
ENA FLGA FLGB ENB
1 2 3 4
EN5V_USBC OVCUR_USB
PE4 [7] PE5 [7]
L14 1 C64 100nF C65 10uF
L15 1
9 10 2 180ohm at 100MHz
EARTH_USB
1112
2 180ohm at 100MHz
EN5V_USBB
PE3 [7]
SP2526A-2E
EARTH_USB
4.2.13 Pushbutton Switches

The following pushbuttons switches are available:

One board reset button (BP2). When pressed and released, this pushbutton causes a power-on reset of the whole board. One wakeup pushbutton that brings the processor out of Low-power mode (BP1) One user pushbutton (BP3)

R12
T13
L4
18
Figure 4-16.
Pushbutton Schematic
R14 50K Auto PWRON (option) R12 C18 47nF
32
REFBP
C20 100nF
49.9K
nPBIN
C25 100nF
Q1 3
GNDP1
GNDP2
R15 0R BP1 BP2
TP5 SMD
1
R19 100K 1% IRLML2502 C130 10nF
GNDA
BP3
[7,11] PE29
29
28
2
BP2
Place TP5 to Bottom
USER BUTTON
BP1
RESET WAKUP or Force Power ON
4.2.14 LCD
The SAMA5D36 processor drives 24 bits of data and control signals to the LCD interface. Other signals are used to control the LCD and are also routed to the J22 connector: TWI, SPI, 2 GPIOs for interrupt, ID for 1-Wire EEPROM (ID_SYS) and power supply lines. 4.2.14.1 LCD Connector One 1.27 mm pitch 50-pin header is provided to gain access to the LCD signals.
Figure 4-17. LCD Expansion Header Interface Schematic
5V_MAIN 3V3 R92 R93 DNP(0R) 0R
LCD Connector
J22 PA24 (LCDPWM) PE8 (IRQ2) PE7 IRQ1) TWCK_LCD TWD_LCD PA25 (LCDDISP)
NRST PE6 (RST_LCD)
R94 R99
0R DNP(0R)
PD20 (AD0) PD12 (SPI0_SPCK) PD21 (AD1) PD11 (SPI0_MOSI) PD22 (AD2) PD10 (SPI0_MISO)
R95 R96 R100 R97 R98 R101
DNP(0R) 22R DNP(0R) 22R DNP(0R) 22R DNP(0R) 22R 22R
PD23 (AD3) R102 PD16 (SPI0_NPCS3) R103 PA28 (LCDPCK) R184
PA29 (LCDDEN) PA27 (LCDHSYNC) PA26 (LCDVSYNC) PE28 PE27 PC15 PC10 PC11 PC12 PC13 PC14 PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 (LCDDAT23) (LCDDAT22) (LCDDAT21) (LCDDAT20) (LCDDAT19) (LCDDAT18) (LCDDAT17) (LCDDAT16) (LCDDAT15) (LCDDAT14) (LCDDAT13) (LCDDAT12) (LCDDAT11) (LCDDAT10) (LCDDAT9) (LCDDAT8) (LCDDAT7) (LCDDAT6) (LCDDAT5) (LCDDAT4) (LCDDAT3) (LCDDAT2) (LCDDAT1) (LCDDAT0)
[7] TWCK_LCD [7] TWD_LCD
TWCK_LCD TWD_LCD
PE23 (ID_SYS)
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
52 51
FP520T1-50SR04
4.2.14.2
LCD Power To operate correctly with various LCD modules, regardless of the processor, two voltage lines are available: 3V3 by default and 5V_MAIN, both selected by 0R resistors R92 and R93.

19
4.2.15 Debug JTAG/ICE and DBGU

4.2.15.1 Debug JTAG/ICE A 2x10-pin JTAG header is implemented on the SAMA5D3 Xplained board to enable the software development and debugging of the board by using various JTAG emulators. The interface signals have a voltage level of 3.3V.
Figure 4-18. JTAG/ICE Interface Schematic
JTAG
VDDIOP0 3V3 R104 100K 1% J24 R105 100K 1% R106 100K 1% R107 100K 1%
2 4 6 8 10 12 14 16 18 20
1 3 5 7 9 11 13 15 17 19
R108 TDI TMS TCK RTCK TDO
0R
R109 R110
0R 0R
NTRST [5] TDI [5] TMS [5] TCK [5] TDO [5] NRST [4,5,9,10]
4.2.15.2
DBGU The SAMA5D3 Xplained board has a dedicated serial port for debugging, which is accessible through the 6-pin male header J23. Various interfaces can be used as USB/Serial DBGU port bridge, such as FTDI TTL-232R-3V3 USB to TTL serial cable or basic breakout board for the 232/USB converter. These interfaces are available on the following websites:

Adafruit: http://www.adafruit.com/products/284 Sparkfun: https://www.sparkfun.com/products/9873
Figure 4-19.
DBGU Interface Schematic

3V3 R189 3V3 5V_MAIN 68K R190 DNP(0R) R171 DNP(0R) R172
68K
J23
PE13 [7] PB31 [7] PB30 PE14
R173 (TXD) (RXD) R174
0R
0R
1 2 3 4 5 6
DEBUG
P101-1*06SGF-116A-NX
R171 and R172 are optional (not implemented) resistors that can be used for power selection. Power can be delivered either by the SAMA5D3 Xplained board or by the debug interface tool. To avoid a contention between your debug interface (e.g. FTDI) and the on-board power system, be careful during the installation of one of this resistor.
4.2.16 Expansion Ports

Five 8-pin, one 10-pin, one 6-pin and one 2x18-pin headers (J14 to J21) are implemented on the board to enable the PIO connection of various expansion cards that could be developed by users or by other sources. Due to multiplexing, different signals can be provided on each pin. These connectors are mechanically and footprint compatible with the

20
Arduino R3 shields. As the SAMA5D3 signals have a voltage level of 3.3V, 5-V level shields must not be used on the SAMA5D3 Xplained. In addition to its standard IO functionality, the SAMA5D3 processor can provide alternate functions to external IO lines available on the J14 to J21 headers. These alternate functions are:

UARTs: UART0, UART1 USARTs: USART0, USART1, USART2, USART3 SPI: SPI1 IC: TWI0, TWI1 Timer capture and compare: TIOA, TIOB Clock out: PCK0, PCK1, PCK2 PWMs: PWML0, PWMH0, PWML1, PWMH1 DIGITAL AUDIO: TD0, TK0, TF0, RD0, RK0, RF0 ISI: ISI[D0:D11], ISI_HSYNC, ISI_VSYNC, ISI_PCK CAN: CAN-RX0, CANTX0, CANRX1, CAN_TX1 Analog: AD[0:11], ADTRG, ADREF GPIO: MISC RESET VBAT
To get further details on the PIO multiplexing and alternate function selection, refer to the SAMA5D3 series datasheet.

21
4.2.16.1
Functions available through the Arduino Headers The following tables illustrate the functionalities provided by the SAMA5D3 Xplained board. They show the pins used to implement each functionality. Note: Some pins are multiplexed for different functionalities, which means that only one at a time can be active for each pin.
Function by PIO (part 1) PCK -----PCK0 PCK0/PCK2 PCK1 -----------------------ISI ----------------ISI_D11/VSYNC ISI_D10/HSYNC ISI_D9 ISI_D8 ISI_D7 ISI_D6 ISI_D5 ISI_D4 ISI_D3 ISI_D2 ISI_D1 ISI_D0 ISI_PCK ISI_VSYNC ISI_HSYNC SSC TK0 TF0 TD0 RF0 RD0 RK0 -------------------------CAN --------CANRX1 CANRX0 CANTX1 CANTX0 -------------------SPI ------------SPI1_MISO SPI1_SPCK SPI1_MOSI SPI1_NPCS0 SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS3 -------------
Table 4-4. PIO NAME PC16 PC17 PC18 PC20/PD28 PC21/PD29 PC19/PD30 PD30/PC15 PD31 PB14 PD14 PB15 PD15 PC22/PC1 PC24/PC0 PC23/PC2 PC25 PC26/PA30 PC27/PA31 PC28 PC29 PA23 PA22 PA21 PA20 PA19 PA18 PA17 PA16 PC30 PA30 PA31

22
Table 4-5. PIO NAME 3V3/5V nRTS GND AREF 5V PC18 PD21 PD22 PD23 PD24 PD25 PD26 PD27 PC20/PD28 PC21/PD29 PC19/PD30 PD31 PD19/PB15 PA19 PA18 PC26 PA30 PA31 PC26/PA30 PC27/PA31 PC30 PC29 PD14 PD15 PD18 PD17 PB25 PB26 PB29 PB28
Function by PIO (part 2) TWI ------------------TWCK2 TWD2 TWD1 TWD0 TWCK0 TWD0/TWD1 TWCK0/TWCK1 ----------UART/USART ---------------------URXD1 UTXD1 URXD1 URTD1 UTXD0 URXD0 SCK0 CTS0 TXD0 RXD0 SCK1 CTS1 TXD1 RXD1 ANALOG ---AREF -AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 ADTRG -----------------MISC 3V3/5V nRTS GND -5V ---------------------PWMFI2 ---------

23
Table 4-5. PIO NAME PB27 PE20 PE23 PE26 PE25 PE24 PE15 PE16 PE19 PE18 PE17 PC22/PC1 PC23/PC2 PC24/PC0 PC9 PE9 PE10 PE11 PE12 PE16 PE31 PC28 PA20 PA22 PA21 PA23 PE29 PC5 PC8 PC3 PC6 PC4 PC7
Function by PIO (part 2) (Continued) TWI ---------------------------------UART/USART RTS1 SCK2 CTS2 TXD2 RXD2 RTS2 SCK3 CTS3 TXD3 RXD3 RTS3 ----------------------ANALOG ---------------------------------MISC PWMH1 ----------GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO IRQ/PWML1 PWMFI0 PWMH0 PWMH1 PWML0 PWML1 TCLK2 TCLK4 TCLK5 TIOA4 TIOA5 TIOB4 TIOB5

24
4.2.16.2
J15 Header
J15 Header
Figure 4-20.
Table 4-6. Silkscreen SCL0 SDA0 ARFE GND 13 12 11 10 9 8
J15 Header IOs PIO PA31 PA30 --PC24 PC22 PC23 PC25 PC3 PC4 Function 1 TWCK0 TWD0 --SPI1_SPCK SPI1_MISO SPI1_MOSI SPI1_NPCS0 ERX1 ETXEN Function 2 UTXD1 URXD1 ------TIOA4 TIOB4 Function 3 ISI_HSYNC ISI_VSYNC --------PIO ----PC0 PC1 PC2 ---Function 4 ----ETX0 ETX1 ERX0 ---Function 5 ----TIOA3 TIOB3 TCLK3 ----

25
4.2.16.3
J18 Header
J18 Header
Figure 4-21.
Table 4-7. Silkscreen 7 6 5 4 3 2 1 0
J18 Header IOs PIO PC5 PC6 PC7 PC28 PC8 PC9 PC30 PC29 Function 1 ECRSDV ERXER EREFCK SPI1_NPCS3 EMDC EMDIO UTXD0 URXD0 Function 2 TCLK4 TIOA5 TIOB5 PWMFI0 TCLK5 -ISI_PCK PWMFI2 Function 3 ---ISI_D9 ---ISI_D8

26
4.2.16.4
J20 Header
J20 Header
Figure 4-22.
Table 4-8. Silkscreen TXD3 14 RXD3 15 TXD1 16 RXD1 17 TXD0 18 RXD0 19 SDA 20 SCL 21
J20 Header IOs PIO PE19 PE18 PB29 PB28 PD18 PD17 PC26 PC27 Function 1 A19 A18 TXD1 RXD1 TXD0 RXD0 SPI1_NPCS1 SPI1_NPCS2 Function 2 TXD3 RXD3 ----TXWD1 TWCK1 Function 3 ------ISI_D11 ISI_D10 PIO ------PA30 PA31 Function 4 ------TWD0 TWCK0 Function 5 ------URXD1 UTXD1 Function 6 ------ISI_VSYNC ISI_HSYNC

27
4.2.16.5
J19 Header
J19 Header
Figure 4-23.
Table 4-9. Silkscreen PD30 PC17 PB26 PE9 PA17 PA19 PA21 PA23 PE15 PE17 PE11 PE23 PE25 PE13
J19 Header IOs PIO PD30 PC17 PB26 PE9 PA17 PA19 PA21 PA23 PE15 PE17 PE11 PE23 PE25 PE13 Function 1 AD10 TF0 CTS1 A9 LCDDAT17 LCDDAT19 LCDDAT21 LCDDAT23 A15 A17 A11 A23 A25 A13 Function 2 PCK0 -GRX7 -ISI_D1 TWCk2 PWML0 PWML1 SCK3 RTS3 -CTS2 RXD2 -Function 3 -----ISI_D3 ISI_D5 ISI_D7 ------PIO PC15 -------------Function 4 PCI2_CK -------------Function 5 PCK2 --------------

28
Table 4-9. Silkscreen PE29 PC26 PC16 PB25 PB27 PE10 PA16 PA18 PA20 PA22 PE16 PE20 PE12 PE24 PE26 PE14 PE31 PB15
J19 Header IOs (Continued) PIO PE29 PC26 PC16 PB25 PB27 PE10 PA16 PA18 PA20 PA22 PE16 PE20 PE12 PE24 PE26 PE14 PE31 PB15 Function 1 NWR1/NBS1 SPI1_NPCS1 TK0 SCK1 RTS1 A10 LCDDAT16 LCDDAT18 LCDDAT20 LCDDAT22 A16 A20 A12 A24 NCS0 A14 IRQ GCOL Function 2 TCLK2 TXWD1 -GRX6 PWMH1 -ISI_D0 TWD2 PWMH0 PWMH1 CTS3 SCK2 -RTS2 TXD2 -PWML1 CANTX1 Function 3 -ISI_D11 -----ISI_D2 ISI_D4 ISI_D6 --------PIO ------------------Function 4 ------------------Function 5 -------------------

29
4.2.16.6
J16 Header
J16 Header
Figure 4-24.
Table 4-10. Silkscreen MISO1 5V/3V3 SPCK MOSI1 RST GND
J16 Header IOs PIO PC22 -PC24 PC23 NRST -Function 1 SPI1_MISO Power supply SPI1_SPCK SPI1_MOSI System reset Power ground

30
4.2.16.7
J14 Header
J14 Header Position
Figure 4-25.
Table 4-11. Silkscreen VBAT 3V3 RST 3V3 5V GND GND NC
J14 Header IOs Function VBAT supply AREF. Reference voltage for the analog inputs of the SAMA5D36 processor. System reset Main 3.3V supply - generated by the on-board regulator. Maximum sourced current is 1.2A. This regulator also provides the power supply to the SAMA5D36 microcontroller and components. Main 5.0V supply System ground System ground Not connected

31
4.2.16.8
J17 Header
J17 Header
Figure 4-26.
Table 4-12. Silkscreen A0 A1 A2 A3 A4 A5 A6 A7
J17 Header IOs PIO PC18 PD21 PD22 PD23 PD24 PD25 PD26 PD27 Function 1 TD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 Function 2 --------Function 3 --------PIO PD20 -------Function 4 AD0 -------Function 5 ---------

32
4.2.16.9
J21 Header
J21 Header
Figure 4-27.
Table 4-13. Silkscreen A8 A9 A10 A11 ** ** CANRX0 CANTX0
J21 Header IO PIO PC20 PC21 PC19 PD31 PB14 PD19 PD14 PD15 Function 1 RF0 RD0 RK0 PCK1 GCRS ADTRG SCK0 CTS0 Function 2 ----CANRX1 -SPO_NPCS1 SPI0_NPCS2 Function 3 ------CANRX0 CANTX0 PIO PD28 PD29 PD30 --PB15 --Function 4 AD8 AD9 AD10 --GCOL --Function 5 --PCK0 --CANTX1 ---

33
4.3
4.3.1
Other Connector Details and PIO Usage Summary

Power Supply
Power Supply Connector J2 (Optional)
Figure 4-28.
Table 4-14. Pin 1 2 3
Power Supply Connector J2 Signal Description Mnemonic Center --Signal Description +5V GND Floating

34
4.3.2
JTAG/ICE Connector
JTAG port J24
Figure 4-29.
10
12
14
16 18
20
11
13
15 17
19
Table 4-15. Pin
JTAG/ICE Connector J24 Signal Descriptions Mnemonic Signal Description This is the target reference voltage. It is used to check if the target has power, to create the logic-level reference for the input comparators, and to control the output logic levels to the target. It is normally fed from VDD on the target board and must not have a series resistor. This pin is not connected in SAM-ICE. It is reserved for compatibility with other equipment. Connect to VDD or leave open in target system. JTAG Reset. Output from SAM-ICE to the reset signal on the target JTAG port. Typically connected to nTRST on the target CPU. This pin is normally pulled High on the target to avoid unintentional resets when there is no connection. Common ground. JTAG data input of target CPU. It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TDI on target CPU. Common ground. JTAG mode set input of target CPU. This pin should be pulled up on the target. Typically connected to TMS on target CPU. Output signal that sequences the target's JTAG state machine, sampled on the rising edge of the TCK signal. Common ground. JTAG clock signal to target CPU. It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TCK on target CPU. Common ground. Some targets must synchronize the JTAG inputs to internal clocks. To fulfill this requirement, a returned and resynchronized TCK can be used to dynamically control the TCK rate. SAM-ICE supports adaptive clocking which waits for TCK changes to be echoed correctly before making further changes. Connect to RTCK if available, otherwise to GND. Common ground. JTAG data output from target CPU. Typically connected to TDO on target CPU. Common ground Active-low reset signal. Target CPU reset signal. Common ground
VTref 3.3V power
Vsupply 3.3V power
nTRST Target Reset - Active-low output signal that resets the target. GND TDI Test Data Input - Serial data output line, sampled on the rising edge of the TCK signal. GND
4 5 6
TMS Test Mode Select.
8 9 10
GND TCK Test Clock - Output timing signal, for synchronizing test logic and control register access. GND
11
RTCK - Input Return Test Clock signal from the target.
12 13 14 15 16
GND TDO JTAG Test Data Output Serial data input from the target. GND nSRST RESET GND

35
Table 4-15. Pin 17 18 19 20
JTAG/ICE Connector J24 Signal Descriptions (Continued) Mnemonic RFU GND RFU GND Signal Description This pin is not connected. Common ground This pin is not connected. Common ground
4.3.3
USB Type A Dual Port

USB Type A Dual Port J19
Figure 4-30.
Table 4-16. Pin A1 A2 A3 A4 B1 B2 B3 B4 Mechanical pins
USB Type A Dual Port J19 Signal Descriptions Mnemonic Vbus - USB_A DM - USB_A DP - USB_A GND Vbus - USB_A DM - USB_A DP - USB_A GND -Signal Description 5V power Data minus Data plus Common ground 5V power Data minus Data plus Common ground Shield

36
4.3.4
USB Micro-AB
USB Host/Device Micro-AB Connector J6
Figure 4-31.
1 2 3 4 5
Table 4-17. Pin 1 2 3 4 5
USB Device Micro-AB Connector J6 Signal Descriptions Mnemonic Vbus DM DP ID GND Signal Description 5V power Data minus Data plus On-the-go identification Common ground
4.3.5
DEBUG Connector
DEBUG Connector J23
Figure 4-32.
Table 4-18. Pin 1 2 3 4 5 6
DEBUG Connector J23 Signal Descriptions Mnemonic -TXD (transmitted data) RXD (transmitted data) --GND PIO PE13 PB31 PB30 -PE14 -Signal Description -RS232 serial data input signal RS232 serial data output signal Power line (5V/3V3) -Common ground
4.3.6
SD/MMC Plus MCI0

SD/MMC Socket J10
Figure 4-33.

37
Table 4-19. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SD/MMC Socket J10 Signal Descriptions Mnemonic DAT3 CMD VSS VCC CLK CD DAT0 DAT1 DAT2 DAT4 DAT5 DAT6 DAT7 WP VSS VSS PIO PD4 PD0 --PD9 PE0 PD1 PD2 PD3 PD5 PD6 PD7 PD8 R57 --Signal Description Data bit Command line Command line Supply voltage 3.3V Clock / command line Card detect Data bit Data bit Data bit Data bit Data bit Data bit Data bit Protect Common ground Common ground

38
4.3.7
MicroSD MCI1
MicroSD Socket J11
Figure 4-34.
Table 4-20. Pin 1 2 3 4 5 6 7 8 9 10
MicroSD Socket J11 Signal Descriptions Mnemonic DAT2 CD/DAT3 CMD VCC CLK VSS DAT0 DAT1 SW1 CARD DETECT PIO PB22 PB23 PB19 -PB24 -PB20 PB21 -PE1 Signal Description Data bit 2 Card detect / data bit 3 Command line Supply voltage 3.3V Clock / command line Common ground Data bit 0 Data bit 1 Not used, grounded Card detect
4.3.8
Gigabit Ethernet ETH0 RJ45 Socket J12

Gigabit Ethernet RJ45 Socket J12 12345678
Figure 4-35.
RJ-45
4.3.9
Ethernet ETH1 RJ45 Socket J13

Ethernet RJ45 Socket J13 12345678
Figure 4-36.
RJ-45

39
4.3.10 LCD Socket J22

Figure 4-37. LCD Socket J22
Table 4-21. PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
LCD Socket J22 Signal Descriptions Signal ID_SYS GND D0 D1 D2 D3 GND D4 D5 D6 D7 GND D8 D9 D10 D11 GND D12 D13 D14 D15 GND D16 D17 D18 D19 GND D20 Display Module Interface Function Extension module identification (connected to 1-wire EEPROM available on LCD display module) GND Data line Data line Data line Data line GND Data line Data line Data line Data line GND Data line Data line Data line Data line GND Data line Data line Data line Data line GND Data line Data line Data line Data line GND Data line MCU Interface Function Extension module identification GND Data line Data line Data line Data line GND Data line Data line Data line Data line GND Data line Data line Data line Data line GND Data line Data line Data line Data line GND Data line Data line Data line Data line GND Data line

40
Table 4-21. PIN 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
LCD Socket J22 Signal Descriptions (Continued) Signal D21 D22 D23 GND PCLK VSYNC/CS HSYNC/WE DATA_ENABLE/ RE SPI_SCK SPI_MOSI SPI_MISO SPI_CS ENABLE TWI_SDA TWI_SCL IRQ1 IRQ2 PWM RESET VCC VCC GND Display Module Interface Function Data line Data line Data line GND Pixel clock Vertical sync Horizontal sync Data enable ----Display enable signal I2C data line (maXTouch) I2C clock line (maXTouch) maXTouch interrupt line Interrupt line for other I2C devices Backlight control Reset for both display and maXTouch 3.3V or 5V supply (0R) 3.3V or 5V supply (0R) GND MCU Interface Function Data line Data line Data line GND -Chip select Write enable Read enable SPI_SCK SPI_MOSI SPI_MISO SPI_CS Display enable signal I2C data line (maXTouch) I2C clock line (maXTouch) maXTouch interrupt line Interrupt line for other I2C devices Backlight control Reset for both display and maXTouch 3.3V supply 3.3V supply GND
4.3.11 PIO Usage

Most signals can also be configured as simple inputs or outputs from the processor.
Table 4-22. Power Rail VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 PIO A Pin Assignment and Signal Description PIO PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 Signal LCDDAT0 LCDDAT1 LCDDAT2 LCDDAT3 LCDDAT4 LCDDAT5 LCDDAT6 LCDDAT7 LCDDAT8 Signal Signal Main Board Function Extended Function LCDDAT0 LCDDAT1 LCDDAT2 LCDDAT3 LCDDAT4 LCDDAT5 LCDDAT6 LCDDAT7 LCDDAT8

41
Table 4-22. Power Rail VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0
PIO A Pin Assignment and Signal Description PIO PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 Signal LCDDAT9 LCDDAT10 LCDDAT11 LCDDAT12 LCDDAT13 LCDDAT14 LCDDAT15 LCDDAT16 LCDDAT17 LCDDAT18 LCDDAT19 LCDDAT20 LCDDAT21 LCDDAT22 LCDDAT23 LCDPWM LCDDISP LCDVSYNC LCDHSYNC LCDPCK LCDDEN TWD0 TWCK0 Signal ISI_D0 ISI_D1 TWD2 TWCK2 PWMH0 PWML0 PWMH1 PWML1 URXD1 UTXD1 Signal ISI_D2 ISI_D3 ISI_D4 ISI_D5 ISI_D6 ISI_D7 ISI_VSYN C ISI_HSYN C Main Board Function TWD0 TWCK0 Extended Function LCDDAT9 LCDDAT10 LCDDAT11 LCDDAT12 LCDDAT13 LCDDAT14 LCDDAT15 ISI_D0 ISI_D1 TWD2/ISI_D2 TWCK2/ISI_D3 ISI_D4 ISI_D5 ISI_D6 ISI_D7 LCDPWM LCDDISP LCDVSYNC LCDHSYNC LCDPCK LCDDEN URXD1/ISI_VSYNC UTXD1/ISI_HSYNC
Table 4-23. Power Rail VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1
PIO B Pin Assignment and Signal Description PIO PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 Signal GTX0 GTX1 GTX2 GTX3 GRX0 GRX1 GRX2 GRX3 Signal PWMH0 PWML0 TK1 TF1 PWMH1 PWML1 TD1 RK1 Signal Main Board Function GTX0 GTX1 GTX2 GTX3 GRX0 GRX1 GRX2 GRX3 Extended Function

42
Table 4-23. Power Rail VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP0 VDDIOP0
PIO B Pin Assignment and Signal Description (Continued) PIO PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 Signal GTXCK GTXEN GTXER GRXCK GRXDV GRXER GCRS GCOL GMDC GMDIO G125CK MCI1_CDA MCI1_DA0 MCI1_DA1 MCI1_DA2 MCI1_DA3 MCI1_CK SCK1 CTS1 RTS1 RXD1 TXD1 DRXD DTXD Signal PWMH2 PWML2 RF1 RD1 PWMH3 PWML3 CANRX1 CANTX1 GTX4 GTX5 GTX6 GTX7 GRX4 GRX5 GRX6 GRX7 PWMH1 Signal Main Board Function GTXCK GTXEN INT_GETH GRXCK INT_ETH GRXER GMDC GMDIO G125CK MCI1_CDA MCI1_DA0 MCI1_DA1 MCI1_DA2 MCI1_DA3 MCI1_CK DRXD (DBGU) DTXD (DBGU) Extended Function -- CANRX1 CANTX1 - - -- SCK1 CTS1 RTS1 RXD1 TXD1 ---
PIO C Pin Assignment and Signal Description PIO PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 Signal ETX0 ETX1 ERX0 ERX1 ETXEN ECRSDV ERXER EREFCK Signal TIOA3 TIOB3 TCLK3 TIOA4 TIOB4 TCLK4 TIOA5 TIOB5 Signal Main Board Function ETX0 ETX1 ERX0 ERX1 ETXEN ECRSDV ERXER EREFCK Extended Function ETX0/TIOA3 ETX1/TIOB3 ERX0/TCLK3 ERX1/TIOA4 ETXEN/TIOB4 ECRSDV/TCLK4 ERXER/TIOA5 EREFCK/TIOB5

43
Table 4-24. Power Rail VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0
PIO C Pin Assignment and Signal Description (Continued) PIO PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 Signal EMDC EMDIO MCI2_CDA MCI2_DA0 MCI2_DA1 MCI2_DA2 MCI2_DA3 MCI2_CK TK0 TF0 TD0 RK0 RF0 RD0 SPI1_MISO SPI1_MOSI SPI1_SPCK SPI1_NPCS0 SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS3 URXD0 UTXD0 FIQ Signal TCLK5 -LCDDAT20 LCDDAT19 TIOA1 TIOB1 TCLK1 PCK2 TWD1 TWCK1 PWMFI0 PWMFI2 ISI_PCK PWMFI1 Signal LCDDAT18 LCDDAT17 LCDDAT16 LCDDAT21 ISI_D11 ISI_D10 ISI_D9 ISI_D8 Main Board Function EMDC EMDIO IRQ_PMIC Extended Function EMDC/TCLK5 EMDIO LCDDAT20 LCDDAT19 LCDDAT18 LCDDAT17 LCDDAT16 LCDDAT21/PCK2 TK0 Audio TF0 Audio TD0 Audio RK0 Audio RF0 Audio RD0 Audio SPI1_MISO SPI1_MOSI SPI1_SPCK SPI1_NPCS0 SPI1_NPCS1/TWD1 SPI1_NPCS2/TWCK1 SPI1_NPCS3/ISI_D9 URXD0/ISI_D8 UTXD0/ISI_PCK
PIO D Pin Assignment and Signal Description PIO PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 Signal MCI0_CDA MCI0_DA0 MCI0_DA1 MCI0_DA2 MCI0_DA3 MCI0_DA4 MCI0_DA5 MCI0_DA6 Signal TIOA0 TIOB0 TCLK0 Signal PWMH2 PWML2 PWMH3 Main Board Function MCI0_CDA MCI0_DA0 MCI0_DA1 MCI0_DA2 MCI0_DA3 MCI0_DA4 MCI0_DA5 MCI0_DA6 Extended Function

44
Table 4-25. Power Rail VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDANA VDDANA VDDANA VDDANA VDDANA VDDANA VDDANA VDDANA VDDANA VDDANA VDDANA VDDANA
PIO D Pin Assignment and Signal Description (Continued) PIO PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 PD24 PD25 PD26 PD27 PD28 PD29 PD30 PD31 Signal MCI0_DA7 MCI0_CK SPI0_MISO SPI0_MOSI SPI0_SPCK SPI0_NPCS0 SCK0 CTS0 RTS0 RXD0 TXD0 ADTRG AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 Signal PWML3 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 PCK0 PCK1 Signal CANRX0 CANTX0 PWMFI3 Main Board Function MCI0_DA7 MCI0_CK SPI0_MISO SPI0_MOSI SPI0_SPCK SPI0_NPCS0 - Extended Function SPI0_MISO SPI0_MOSI SPI0_SPCK SCK0/SPI0_NPCS 0/CANRX0 CST0/SPI0_NPCS 2/CANTX0 SPI0_NPCS3 RXD0 TXD0 ADTRG (HSYNC) AD0/LCD TSC AD1/LCD TSC AD2/LCD TSC AD3/LCD TSC AD4 AD5 AD6 AD7 AD8 AD9 AD10/PCK0 AD11/PCK1
Table 4-26. Power Rail VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM
PIO E Pin Assignment and Signal Description PIO PE0 PE1 PE2 PE3 PE4 PE5 PE6 Signal A0/NBS0 A1 A2 A3 A4 A5 A6 Signal Signal Main Board Function MCI0_CD MCI1_CD PWR_MCI0 EN5V_USBB EN5V_USBC OVCUR_USB Extended Function RST_LCD

45
Table 4-26. Power Rail VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM
PIO E Pin Assignment and Signal Description (Continued) PIO PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PE16 PE17 PE18 PE19 PE20 PE21 PE22 PE23 PE24 PE25 PE26 PE27 PE28 PE29 PE30 PE31 Signal A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21/NANDALE A22/NANDCLE A23 A24 A25 NCS0 NCS1 NCS2 NWR1/NBS1 NWAIT IRQ Signal SCK3 CTS3 RTS3 RXD3 TXD3 SCK2 CTS2 RTS2 RXD2 TXD2 TIOA2 TIOB2 TCLK2 PWML1 Signal LCDDAT22 LCDDAT23 USER_PB nPBSTA_PMIC Main Board Function VBUS_SENSE A21/NANDALE A22/NANDCLE 1-Wire / User LED Power LED Extended Function IRQ1 / ChgMXT IRQ2/ChgQT A9 A10 A11 A12 A13 A14 A15/SCK3 A16/CTS3 A17/RTS3 A18/RXD3 A19/TXD3 A20/SCK2 A23/1-Wire/CTS2 A24/RTS2 A25/RXD2 NCS0/TXD2 LCDDAT22 LCDDAT23 NWR1/NBS1/TCLK2 IRQ/PWML1

46
4.4
SAMA5D3 Xplained Board Schematics

This section contains the following schematics:

General information Block Diagram PIO Multiplexing Table Power Supplies SAMA5D3 Device and USB Interfaces DDR2 Memory NAND Flash and Optional Memories SD and Micro-SD Interfaces Gigabit Ethernet Ethernet 10/100 LCD, JTAG, DEBUG and Extended Connectors

47
Figure 4-38.
5 4
Schematic: SAMA5D3 Xplained

SHEET NAME Title & Revision History Block Diagram PIO Assignment Power Supply SAMA5D3x-I & USB SAMA5D3x-II & DDR2 SAMA5D3x-II & NAND HSMCI Ethernet_ETH0_10/100/1000 Ethernet_ETH1_10/100 Connectors
C
General information
SHEET
19 Feb 2014 SAMA5D3 Xplained RevA Official Release
DATE
REVISION
DESCRIPTION
01
02
03
04
05
06
07
08
09
10
11
A A
REV
RevA
INIT EDIT MODIF.
Embest 19-Feb-14 PPn 27-Sep-13

DES.
XXX XX-XXX-XX XXX XX-XXX-XX

DATE
VER.
DATE
SAMA5D3 Xplained Title & Revision History

4 3 2
SCALE
1/1
1
REV.
SHEET
1 11
48
Figure 4-39.
5 4
Push Buttons Reset Force PwrOn Single PMU Solution 5V INPUT USB DEVICE USB A,B,C Power rails ATMEL SAMA5D36 CORTEX(R)-A5 PROCESSOR USER LEDS PIO 2/4Gb DDR2 SDRAM EBI 2Gb NAND FLASH JTAG & DBGU USB Host x2 JTAG DBGU
Block diagram
5V & 3V3
VBAT ANALOG Reference
Extention boards connectors

PIO A,...E
PIO A,...E
LCD Connector
SD CARD
Micro SD CARD
SERIAL DATA FLASH
10/100/1000 FAST ETHERNET ETH0
10/100 FAST ETHERNET ETH1

A
A A
REV
RevA
INIT EDIT MODIF.

DES.

DATE
VER.
DATE
SAMA5D3 Xplained Block Diagram

4 3 2
SCALE
1/1
1
REV.
SHEET
2 11
49
Figure 4-40.
5 4
PIO MUXING
PIOA PA0 1 PA1 PA2 PA3 PA19 PB19 PB20 PB21 PB22 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 LCDDAT18 LCDDAT17 LCDDAT16 LCDDAT21/PCK2 LCDDAT19 LCDDAT20 EMDIO EMDC EREFCK PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 PIOE PE16 PE17 PE18 PE19 PE20 PE21 PE22 PE24 PE25 PE26 PE27 PE28 PE29 PE30 PE31 A20/SCK2 A21/NANDALE A22/NANDCLE Power led/A24/RTS2 A25/RXD2 NCS0/TXD2 LCDDAT22 LCDDAT23 NWR1/NBS1/TCLK2 STA_PMIC ADTRG/PWML1
B
LCD
LCDDAT0 PA16 PB16 PB17 PB18 PC2 PC3 PC4 PC5 ECRSDV PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 ECRSDV PC21 ETXEN PC20 RF0 RD0 SPI1_MISO SPI1_MOSI SPI1_SPCK SPI1_NPCS0 ERX1 PC19 RK0 PC18 MCI1_CDA MCI1_DA0 MCI1_DA1 MCI1_DA2 MCI1_DA3 MCI1_CK SCK1 CTS1 RTS1 RXD1 TXD1 DRXD DTXD USAGE A16/CTS3 A17/RTS3 A18/RXD3 A19/TXD3 G125CK ERX0 TD0 GMDIO PC1 PC17 ETX1 TF0 PA17 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 GTXEN INT_GETH GRXCK INT_ETH GRXER CANRX1 CANTX1 USAGE MCI0_CD MCI1_CD PWR_MCI0 EN5V_USBB EN5V_USBC OVCUR_USB RST_LCD IRQ1 IRQ2 VBUS_SENSE/A9 A10 A11 A12 A13 A14 A15/SCK3 PB10 PB11 PB12 PB13 PB14 PB15 PIOE PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 GTXCK GRX3 GRX2 GRX1 GRX0 GTX3 GTX2 PA18 ISI_D3 ISI_D4 ISI_D5 ISI_D6 ISI_D7 LCDPWM LCDDISP LCDVSYNC LCDHSYNC LCDPCK LCDDEN ISI_VSYNC/URXD1 ISI_HSYNC/UTXD1 USAGE SPI0_NPCS3 RXD0 TXD0 ADTRG AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10/PCK0 /PCK1 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 PIOD PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 PD24 PD25 PD26 PD27 PD28 PD29 PD30 PD31 ISI_D2 ISI_D1 GTX1 PB0 GTX0 PC0 PC16 LCDDAT1 LCDDAT2 LCDDAT3 LCDDAT4 LCDDAT5 LCDDAT6 LCDDAT7 LCDDAT8 LCDDAT9 LCDDAT10 LCDDAT11 LCDDAT12 LCDDAT13 LCDDAT14 LCDDAT15 USAGE MCI0_CDA MCI0_DA0 MCI0_DA1 MCI0_DA2 MCI0_DA3 MCI0_DA4 MCI0_DA5 MCI0_DA6 MCI0_DA7 MCI0_CK SPI0_MISO SPI0_MOSI SPI0_SPCK SPI0_NPCS0 SCK0/CANRX0 CTS0/CANTX0 ISI_D0 GMDC ETX0 TK0 2 3 4 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PIOD PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
SAMA5D3 Xplained PIO Assignment
4 3 2 1
USAGE PIOA PIOB PIOB PIOC PIOC
USAGE
USAGE
USAGE
USAGE
USAGE
ID_SYS
GND
LCDDAT0
LCDDAT1
LCDDAT2
LCDDAT3
GND
PIO Multiplexing Table
LCDDAT4
LCDDAT5
LCDDAT6
SPI1_NPCS1/TWD1/ISI_D11 SPI1_NPCS2/TWCK1/ISI_D10 SPI1_NPCS3/ISI_D9 URXD0/ISI_D8 UTXD0/ISI_PCK IRQ_PMIC

C
LCDDAT7
GND
LCDDAT8
LCDDAT9
LCDDAT10
LCDDAT11
GND
LCDDAT12
LCDDAT13
LCDDAT14
LCDDAT15
GND
JUMPER DESCRIPTION
PART JP1 JP2 JP3 JP4 JP5 JP6 DEFAULT SHORT SHORT SHORT SHORT CLOSE CLOSE FUNCTION I_CORE Measurement I_IODDR Measurement I_IOP Measurement I_IOM Measurement CS Nand flash memory CS Serial flash memory
LCDDAT16
LCDDAT17
LCDDAT18
PE23 1-Wire/User led1/A23/CTS2
LCDDAT19
GND
LCDDAT20
LCDDAT21
LCDDAT22
LCDDAT23
GND
LCDPCK
LCDVSYNC
LCDHSYNC
LCDDEN
SPI0_NPCS3/AD3_YM
SPI0_MISO/AD2_YP
SPI0_MOSI/AD1_XM
SPI0_SPCK/AD0_XP
LCDDISP
TWD1
TWCK1
IRQ1
IRQ2
LCDPWM
Reset
VCC
VCC
A A
REV
RevA
INIT EDIT MODIF.
SCALE

DES.

DATE
VER.
DATE
GND
1/1
REV.
SHEET
3 11
50
Figure 4-41.
5 4
R1 R2 R3 R175 R176 R177 0R 0805

[5] Vbus R175 [11] 5V_Ext R176 D4 J2 R3 DNP(0R) DNP(0R) R2 DNP(0R) 0R
D
R1
0R
5V_MAIN
Power supplies
JP1 DNP(JUMPER) VDDCORE
3 2 1
R177 DNP(0R) P4SMAJ5.0A DNP(DC JACK)
1 2
AVDDL_PLL L1 1
2 180ohm at 100MHz
AVDDL L2 1
2 180ohm at 100MHz
DVDDL L3 1
5V_MAIN 5V_MAIN MN1 3V3 R4 1R 3V3 C1 4.7uF C2 4.7uF C3 4.7uF ACT8865
2 180ohm at 100MHz
31 26 16 25 VP1 VP2 VP3 NC2 INL45 INL67

C4 1uF L5 C8 10uF C9 10uF C10 100nF 2.2uH (1V8) C5 1uF JP2 DNP(JUMPER) VDDIODDR
5 6
R5 2R2
L4 10uH 60mA
VDDPLLA C7 4.7uF
C
23
R7 1.5K 1% R8 10K C6 1uF
VDDREF SW1 OUT1 30 1 1 2
R6 1.5K 1%
[5,9,10,11] NRST [7] PC31 R186 R9 1K R11 0R DNP(0R) 0R
L6 R10 2R2 10uH 60mA C11 4.7uF JP3 DNP(JUMPER) 3V3 L7 (1V2) C12 10uF C13 10uF C14 100nF 2.2uH
VDDUTMIC
[5] WKUP [7] PE30
[5] SHDN
R18
11 12 13 20 18 10 17 nRST0 nIRQ nPBSTAT VSEL NC1 PWRHLD PWREN SW2 OUT2 27 24 SCL SDA
C15 10uF C16 10uF C17 100nF L9 2.2uH (3V3)
VDDIOP0
[7] TWCK_PMIC [7] TWD_PMIC
PC27 PC26
1 2
21 22 SW3 OUT3
15 19
L8 1
2 180ohm at 100MHz
FUSE_2V5 VDDIOP1 L10 1
32 REFBP OUT4 OUT5 4 7 8

C21 2.2uF C22 2.2uF C23 2.2uF C24 2.2uF
R14 49.9K Auto PWRON (option) R12 49.9K C18 47nF
3
(3V3)
(2V5) VDDANA JP4 DNP(JUMPER)
2 180ohm at 100MHz
VDDIOM
C20 100nF
1 2
L11 1 R13 R16 0R 0R TP1 SMD TP2 SMD R17 2R2 C19 100nF
9 nPBIN OUT6
2 180ohm at 100MHz
C25 100nF Q1 3 R15 0R
OUT7 GNDA GNDP1 GNDP2 GNDP3 EXPAD
L12 10uH 60mA C26 4.7uF
VDDOSC
B
BP1
BP2
1 29 28 14
R19 C130 10nF BP1 BP2
100K 1%
WAKUP or Force Power ON
RESET
SMD TP6 SMD TP7 BP2
BP1
Place TP6 TP7 to Bottom

A
33
IRLML2502
A A
REV
RevA
INIT EDIT MODIF.

DES.

DATE
VER.
DATE
SAMA5D3 Xplained Power Supply

4 3 2
SCALE
1/1
1
REV.
SHEET
4 11
51
Figure 4-42.
5 4
3V3 TP4 SMD
Place TP4 to Bottom
R20 D1 VDDCORE VDDBU R185 C41 1.5K 1% DNP(0.2F/3V3) 100nF 100nF R21 100K 1% R22 DNP(100K) C28 100nF C29 100nF C40 1uF C31 100nF C34 100nF C35 100nF C36 100nF C37 100nF C38 100nF C30 C33 100nF C39 100nF C32
100R
C27 10nF BAT54C
Populate R185 if no Super Cap (C41)
(Super)-Capacitor energy storage
VDDIOP1
VDDIOP0
V15
L11 M4
G7 V11
[11] VBat 3V3
C5 C7 D14 T7 T15 U17 V7
VDDBU
VDDIOM
VDDIOP1_1 VDDIOP1_2
VDDIOP0_1 VDDIOP0_2
[4,9,10,11] NRST R25 R24 10K 100K 1%
NRST
[11] TDI [11] TMS [11] TCK [11] TDO [11] NTRST
TDI TMS TCK TDO NTRST
T9 R8 N10 P9 M11 P11 V9 JTAGSEL TDI TMS TCK TDO NTRST NRST VDDIOM_1 VDDIOM_2
C42 100nF C43 100nF
VDDCORE_1 VDDCORE_2 VDDCORE_3 VDDCORE_4 VDDCORE_5 VDDCORE_6 VDDCORE_7
R23 1.5K 1%
P12 T16
VDDIODDR C44 100nF C45 100nF C46 100nF C47 100nF C48 100nF
U15 U9 TST BMS WKUP SHDN

FUSE_2V5
VDDIOP0 WKUP SHDN
[4] WKUP [4] SHDN C49 20pF
T10 T12 R3
VDDIODDR_1 VDDIODDR_2 VDDIODDR_3 VDDIODDR_4 VDDIODDR_5
D13 F14 G10 G13 H11
U8 XIN VDDOSC XOUT

MN2H SAMA5D3x_BGA324 Y1 12MHz CL=15pF
VDDFUSE
C50 100nF top/bot 3V3
VDDOSC
[7,11] PE9
(VBUS_SENSE)
R26
100K 1%
C51
20pF
U11 U13
V8 VDDUTMII VDDPLLA
32.768KHz CL=12.5pF Y2 V16
SAMA5D3 Device and USB Interfaces
R27 200K C53 20pF
C52 100nF VDDPLLA C54 100nF C55 100nF VDDUTMIC
U16 XIN32 R10 4
[4] Vbus
XOUT32
2
C56 20pF
USB DEVICE A INTERFACE

7
J6 UBAF-1015P
U6 V6 DIBN DIBP
VDDUTMIC
V13
C57 100nF VDDANA GNDUTMI
8
HHSDMB HHSDPB top/bot top/bot
HHSDMA HHSDPA top/bot
V10 U10 HHSDMA HHSDPA HHSDMB HHSDPB HHSDMC HHSDPC GNDBU GNDPLL GNDOSC GNDFUSE GNDCORE_1 GNDCORE_2 GNDCORE_3 GNDCORE_4 GNDCORE_5 GNDCORE_6 VBG T13 T11 P4 P10 A16 C9 N13 T8 T14 V17 E14 F10 F13 F15 H14 V12 U12 V14 U14 GNDIODDR_1 GNDIODDR_2 GNDIODDR_3 GNDIODDR_4 GNDIODDR_5 R11
VBUS DM DP ID GND
1 2 3 4 5
VDDANA
L6
C58 100nF R28 0R
HHSDMC HHSDPC
GNDIOP_1 GNDIOP_2 GNDIOP_3 GNDIOP_4
GNDIOM_1 GNDIOM_2
GNDUTMI_1
GNDANA
EARTH_USB_A
ADVREF
L5
ADVREF C59 100nF
R29
DNP(0R)
AREF [11]
J7 N11 U7 E5
J11 T17
L21 1
180ohm at 100MHz 2
Routing USB
R30 C60 5.62K 1% 10pF
R12
L4
3V3 R31 0R [4,7,8,11] PE[0..31] PE23 GNDUTMI R32 470R D2
EARTH_USB_A
Max trace-length mismatch between USB signals pairs should be no greater than 3.8mm
GNDUTMI R&C as close as possible
BLUE
90 ohms differential trace impedance Routing top or bottom
A copper plan for GNDUTMI cover all USB compoments

2
MN3
PE24 1
R33
100K 1%
LED
R34 Q2 IRLML2502 TP5 SMD
470R
D3
RED
J7_USB_A_Up
C61 100nF C62 10uF 5V_USBC HHSDMC HHSDPC 5V_USBB C64 100nF C65 10uF L14 1
J7 USB8S-AR2HF-NBW-S2
5V_USBC
L13 1
J7_USB_B_Down
OUTA IN 6 GNG
ENA FLGA FLGB
1 2 3
EN5V_USBC OVCUR_USB
PE4 [7] PE5 [7] [7,11] PE29
5V_USBB HHSDMB HHSDPB
8 2 180ohm at 100MHz 5V_MAIN 7 C63 100nF
BP3
5 6 7 8 1112
1 2 3 4
Place TP5 to Bottom

2 180ohm at 100MHz 5 OUTB ENB
SP2526A-2E
USER BUTTON
4
EN5V_USBB PE3 [7]
A
L15 1 EARTH_USB
9 10 2 180ohm at 100MHz
EARTH_USB
USB HOST B&C INTERFACE

SAMA5D3 Xplained SAMA5D3x-I & USB
4 3 2
A A
REV
RevA
INIT EDIT MODIF.
SCALE

DES.

DATE
VER.
DATE
1/1
1
REV.
SHEET
5 11
52
Figure 4-43.
5 4
MN2F SAMA5D3x_BGA324 DDR_A[0..13]
DDR2 Memory
DDR2 SDRAM
DDR_D[0..31]
DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13
DDR_A[0..13] MN4 MN5 DDR_D[0..31] DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13
B10 C11 A9 D11 B9 E10 D10 A8 C10 B8 F11 A7 D9 A6 M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2 R8 A0 DDR2 SDRAM A1 A2 MT47H64M16HR A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 L2 L3 L1 K9
R37 0R DDR_CKE DDR_CLK DDR_CLKN DDR_CS DDR_CAS DDR_RAS DDR_WE
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
VDDIODDR DDR_BA0 DDR_BA1 DDR_BA2 VDDIODDR R35 DNP(1K)
DDR_BA0 DDR_BA1 DDR_BA2
L2 L3 L1 BA0 BA1 BA2 ODT K9
G8 G2 H7 H3 H1 H9 F1 F9 C8 C2 D7 D3 D1 D9 B1 B9
DDR_D0 DDR_D1 DDR_D2 DDR_D3 DDR_D4 DDR_D5 DDR_D6 DDR_D7 DDR_D8 DDR_D9 DDR_D10 DDR_D11 DDR_D12 DDR_D13 DDR_D14 DDR_D15
M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2 R8
A0 DDR2 SDRAM A1 A2 MT47H64M16HR A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 BA0 BA1 BA2 ODT
G8 G2 H7 H3 H1 H9 F1 F9 C8 C2 D7 D3 D1 D9 B1 B9
DDR_D16 DDR_D17 DDR_D18 DDR_D19 DDR_D20 DDR_D21 DDR_D22 DDR_D23 DDR_D24 DDR_D25 DDR_D26 DDR_D27 DDR_D28 DDR_D29 DDR_D30 DDR_D31 VDDIODDR
C
VDDIODDR R36 DNP(1K) 0R DDR_CKE R38
K2 CKE VDDL CK CK CS CAS RAS WE VREF UDQS UDQS LDQS LDQS VSS VSS VSS VSS VSS A3 E3 J3 N1 P9 J2 J1
C77 100nF
VDD VDD VDD VDD VDD
A1 E1 J9 M9 R1
C67 C69 C71 C73 C75 100nF 100nF 100nF 100nF 100nF
K2 J8 K8 L8 L7 K7 K3
DDR_DQS3 R39 4.7K
VDD VDD VDD VDD VDD CKE VDDL CK CK CS CAS RAS WE B7 A8 UDQS UDQS
A1 E1 J9 M9 R1 J1
C66 C68 C70 C72 C74
100nF 100nF 100nF 100nF 100nF C76 100nF
DDR_CLK DDR_CLKN
J8 K8 L8 L7 K7 K3 B7 A8 F7 E8
DDR_CS Differencial 100 Ohms Top/Bottom DDR_CAS DDR_RAS DDR_WE
DDR_D0 DDR_D1 DDR_D2 DDR_D3 DDR_D4 DDR_D5 DDR_D6 DDR_D7 DDR_D8 DDR_D9 DDR_D10 DDR_D11 DDR_D12 DDR_D13 DDR_D14 DDR_D15 DDR_D16 DDR_D17 DDR_D18 DDR_D19 DDR_D20 DDR_D21 DDR_D22 DDR_D23 DDR_D24 DDR_D25 DDR_D26 DDR_D27 DDR_D28 DDR_D29 DDR_D30 DDR_D31 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
DDR_VREF C100 100nF
H12 H17 H13 G17 G16 H15 F17 G15 F16 E17 G14 E16 D17 C18 D16 C17 B16 B18 C15 A18 C16 C14 D15 B14 A15 A14 E12 A11 B11 F12 A10 E11 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9
C79 C81 C83 C85 C87 C89 C91 C93 C95 C97 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF Differencial 100 Ohms Top/Bottom DDR_BA0 DDR_BA1 DDR_BA2 DDR_DQS1 R40 4.7K DDR_DQS0 R42 4.7K DDR_RAS DDR_CAS DDR_CKE DDR_CLK DDR_CLKN DDR_DQM1 DDR_DQM0 DDR_CS DDR_WE DDR_DQM0 DDR_DQM1 DDR_DQM2 DDR_DQM3 Differencial 100 Ohms Top/Bottom
DDR_D0 DDR_D1 DDR_D2 DDR_D3 DDR_D4 DDR_D5 DDR_D6 DDR_D7 DDR_D8 DDR_D9 DDR_D10 DDR_D11 DDR_D12 DDR_D13 DDR_D14 DDR_D15 DDR_D16 DDR_D17 DDR_D18 DDR_D19 DDR_D20 DDR_D21 DDR_D22 DDR_D23 DDR_D24 DDR_D25 DDR_D26 DDR_D27 DDR_D28 DDR_D29 DDR_D30 DDR_D31
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VREF
A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 J2
DDR_VREF
C78 C80 C82 C84 C86 C88 C90 C92 C94 C96
100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF
DDR_BA0 DDR_BA1 DDR_BA2
E9 B6 F9
C98 100nF DDR_DQS2 R41 4.7K DDR_DQM3 DDR_DQM2
DDR_RAS DDR_CAS
G11 A5
F7 E8 B3 F3
LDQS LDQS UDM LDM
VSS VSS VSS VSS VSS
A3 E3 J3 N1 P9
DDR_CKE DDR_CLK DDR_CLKN B3 F3 UDM LDM
B7 B12 A12
DDR_CS DDR_WE A2 E2 R3 R7 RFU1 RFU2 RFU3 RFU4
C8 B5
DDR_DQM0 DDR_DQM1 DDR_DQM2 DDR_DQM3

DDR_DQS0 DDR_DQS1 DDR_DQS2 DDR_DQS3 C99 100nF DDR_VREF R43 VDDIODDR C101 4.7uF 200R 1% 10uH 60mA R45 1R TP3 R46 SMD 1.5K 1% C102 100nF L16 VDDIODDR
G12 E15 B15 D12
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSDL
A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 J7
A2 E2 R3 R7
RFU1 RFU2 RFU3 RFU4
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSDL
A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 J7
DDR_DQS0 DDR_DQSN0 DDR_DQS1 DDR_DQSN1 DDR_DQS2 DDR_DQSN2 DDR_DQS3 DDR_DQSN3
E18 D18 G18 F18 B17 A17 B13 A13
Keep nets as short as possible, therefore, DDR2 devices have to be placed close as possible of SAMA5D36 The layout EBI DDR2 should use controlled impedance traces of ZO= 50ohm characteristic impedance. Address, control and data traces may not exceed 1.3 inches (33.0 mm). Address, control and data traces must be length-matched to within 0.1 inch (2.54mm). Address, control and data traces must match the data group trace lengths to within 0.25 inches (6.35mm).
DDR_VREF
C13
DDR_CALN
C12
DDR_CALP
R44 200R 1%
E13
DDR_VREF
A
C103 4.7uF
C104 100nF
R47 1.5K 1%
A A
REV
RevA
INIT EDIT MODIF.

DES.

DATE
VER.
DATE
SAMA5D3 Xplained SAMA5D3x-II & DDR2

4 3 2
SCALE
1/1
1
REV.
SHEET
6 11
53
Figure 4-44.
5 4
MN2A SAMA5D3x_BGA324 MN2D SAMA5D3x_BGA324
PA[0..31] [11] PD[0..31] [8,11]
VDDIOM PE22 PE21 NRD NWE (NANDCLE) 16 (NANDALE) 17 8 18 9 (NANDCE)
PA30 PA31 R156 R157 J15_TWD [11] J15_TWCK [11] TWD_LCD [11] TWCK_LCD [11] 3V3 NANDRDY R48 100K 1% R49 100K 1% R50 100K 1% R158 R159 DNP(22R) DNP(22R) 22R 22R
MN6 MT29F2G08ABAEAWP
CLE ALE RE WE CE R/B WP
7 19
PC26 PC27 R162 R163 JP5 NCS3 JUMPER R164 R165 TWD_ISI [11] TWCK_ISI [11] 22R 22R DNP(22R) DNP(22R)
R160 R161
22R 22R
R180 R181
3.3K 3.3K
1 2
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8_N.C I/O9_N.C I/O10_N.C I/O11_N.C I/O12_N.C I/O13_N.C I/O14_N.C I/O15_N.C
VDDIOM
29 30 31 32 41 42 43 44 26 27 28 33 40 45 46 47 12 37 34 39 VCC VCC VCC_N.C VCC_N.C

C105 100nF
R166 R167 TWD_PMIC [4] TWCK_PMIC [4] 3V3 R178 R179 3.3K 3.3K
22R 22R
PA0_LCDDAT0 PA1_LCDDAT1 PA2_LCDDAT2 PA3_LCDDAT3 PA4_LCDDAT4 PA5_LCDDAT5 PA6_LCDDAT6 PA7_LCDDAT7 PA8_LCDDAT8 PA9_LCDDAT9 PA10_LCDDAT10 PA11_LCDDAT11 PA12_LCDDAT12 PA13_LCDDAT13 PA14_LCDDAT14 PA15_LCDDAT15 PA16_LCDDAT16 PA17_LCDDAT17 PA18_LCDDAT18 PA19_LCDDAT19 PA20_LCDDAT20 PA21_LCDDAT21 PA22_LCDDAT22 PA23_LCDDAT23 PA24_LCDPWM PA25_LCDDISP PA26_LCDVSYNC PA27_LCDHSYNC PA28_LCDPCK PA29_LCDDEN PA30_TWD0 PA31_TWCK0 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 PD24 PD25 PD26 PD27 PD28 PD29 PD30 PD31 1 2 3 4 5 6 10 11 14 15 20 23 24 35 21 22 38 N.C1 N.C2 N.C3 N.C4 N.C5 N.C6 N.C7 N.C8 N.C9 N.C10 N.C11 N.C12 N.C13 N.C14 DNU1 DNU2 DNU3
C106 100nF
E3 F5 D2 F4 D1 J10 G4 J9 F3 J8 E2 K8 F2 G6 E1 H5 H3 H6 H4 H7 H2 J6 G2 J5 F1 J4 G3 J3 G1 K4 H1 K3 K5 P1 K6 R1 L7 P2 L8 R2 K7 U2 K9 M5 K10 N4 L9 N3 L10 N5 M6 T1 N2 M3 M2 L3 M1 N1 L1 L2 K1 K2 J1 J2 VSS VSS VSS_N.C VSS_N.C 13 36 25 48

PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 PD24 PD25 PD26 PD27 PD28 PD29 PD30 PD31
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31
MN2B SAMA5D3x_BGA324 MN2E SAMA5D3x_BGA324 PE[0..31] [4,5,8,11]
PB[0..31] [8,9,10,11]
NAND Flash and Optional Memories
OPTIONAL
VDDIOM R51 1.5K 1% PE23
MN11
IO GND 2 NC
DNP(DS28E05) MN7
GND
IO
PB0_GTX0 PB1_GTX1 PB2_GTX2 PB3_GTX3 PB4_GRX0 PB5_GRX1 PB6_GRX2 PB7_GRX3 PB8_GTXCK PB9_GTXEN PB10_GTXER PB11_GRXCK PB12_GRXDV PB13_GRXER PB14_GCRS PB15_GCOL PB16_GMDC PB17_GMDIO PB18_G125CK PB19_GTX4 PB20_GTX5 PB21_GTX6 PB22_GTX7 PB23_GRX4 PB24_GRX5 PB25_GRX6 PB26_GRX7 PB27 PB28 PB29 PB30 PB31 PE0_A0/NBS0 PE1_A1 PE2_A2 PE3_A3 PE4_A4 PE5_A5 PE6_A6 PE7_A7 PE8_A8 PE9_A9 PE10_A10 PE11_A11 PE12_A12 PE13_A13 PE14_A14 PE15_A15_SCK3 PE16_A16_CTS3 PE17_A17_RTS3 PE18_A18_RXD3 PE19_A19_TXD3 PE20_A20_SCK2 PE21_A21/NANDALE PE22_A22/NANDCLE PE23_A23_CTS2 PE24_A24_RTS2 PE25_A25_RXD2 PE26_NCS0_TXD2 PE27_NCS1_TIOA2 PE28_NCS2_TIOB2 PE29_NWR1/NBS1_TCLK2 PE30_NWAIT PE31_IRQ_PWML1
PC[0..31] [4,11]
P13 R14 R13 V18 P14 U18 T18 R15 P17 P15 P18 R16 N16 R17 N17 R18 N18 P16 M18 N15 M15 N14 M17 M13 M16 N12 M14 M12 L13 L15 L14 L16
PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PE16 PE17 PE18 PE19 PE20 PE21 (NANDALE) PE22 (NANDCLE) PE23 PE24 PE25 PE26 PE27 PE28 PE29 PE30 PE31
T2 N7 T3 N6 P5 T4 R4 U1 R5 P3 R6 V3 P6 V1 R7 U3 P7 V2 V5 T6 N8 U4 M7 U5 M8 T5 N9 V4 M9 P8 M10 R9
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31
NC1 NC2 NC3 NC4
3 4 5 6
DNP(DS2431)
MN2C SAMA5D3x_BGA324 PC24 PC0 J15_Pin6 [11] ETH1_PC0 [10] J15_Pin5 [11] ETH1_PC1 [10] MN2G SAMA5D3x_BGA324 PC22 PC1 R154 R135 R136 22R DNP(22R) 22R R153 R133 R134 22R DNP(22R) 22R
VDDIOP1 R52 100K 1% MN8 PD11 PD10 PD12 PD13 (SPI0_MOSI) (SPI0_MIS0) (SPI0_SPCK) (SPI0_CS) VDDIOP1
PC23 PC2 R155 R137 R138 J15_Pin4 [11] ETH1_PC2 [10] J15_PC3 [11] ETH1_PC3 [10] R139 R140 22R 22R 22R DNP(22R) 22R
5 2 6 1 1 2
8 3 7 4
DNP(N25Q032A13ESE40F) JP6 JUMPER C107 100nF
PC3
DQO VCC DQ1 C W/Vpp/DQ2 HOLD/DQ3 S GND
PC4 PC5 J15_PC4 [11] ETH1_PC4 [10] J18_PC5 [11] ETH1_PC5 [10]
R141 R142 R143 R144
22R 22R 22R 22R
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D16 NCS3
K12 K15 K14 K16 K13 K17 J12 K18 J14 J16 J13 J17 J15 J18 H16 H18 L12 NRD NWE_NWR0 NANDRDY L17 K11 L18
NCS3 NRD NWE NANDRDY A A

REV
PC6 PC7 R145 R146 R147 R148 22R 22R 22R 22R
J18_PC6 [11] ETH1_PC6 [10] J18_PC7 [11] ETH1_PC7 [10]
RevA
INIT EDIT MODIF.
PC8 PC9

DES.

DATE
VER.
DATE
PC0_ETX0 PC1_ETX1 PC2_ERX0 PC3_ERX1 PC4_ETXEN PC5_ECRSDV PC6_ERXER PC7_EREFCK PC8_EMDC PC9_EMDIO PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31
R149 R150 R151 R152 22R 22R 22R 22R J18_PC8 [11] ETH1_PC8 [10] J18_PC9 [11] ETH1_PC9 [10]
D8 A4 E8 A3 A2 F8 B3 G8 B4 F7 A1 D7 C6 E7 B2 F6 B1 E6 C3 D6 C4 D5 C2 G9 C1 H10 H9 D4 H8 G5 D3 E4
PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31
SAMA5D3 Xplained SAMA5D3x-II & NAND

4 3 2
SCALE
1/1
1
REV.
SHEET
7 11
54
Figure 4-45.
5 4
VDD_MCI0 Q3 IRLML6402
VDDIOP1
VDDIOP1 R53 100K 1%
PE2 [7] VDDIOM R55 C108 10uF DNP(4.7K) R56 10K C109 100nF R121 R122 R123 R124 R125 R126 R127 R128 R54
68K
68K
68K
68K
68K
68K
68K
[7] PE0 J10 (MCI0_DA1) (MCI0_DA0) R57 (MCI0_CK) (MCI0_CDA) (MCI0_DA3) (MCI0_DA2) 7SDMM-B0-2211 [7] [7] [7] [7] PD5 PD6 PD7 PD8 (MCI0_DA4) (MCI0_DA5) (MCI0_DA6) (MCI0_DA7) R182 22R [7] PD2 [7] PD1 [7] PD9 [7] PD0 [7] PD4 [7] PD3 (MCI0_WP)
(MCI0_CD)
68K
10K
SD and Micro-SD Interfaces
8 7 6 5 4 3 2 1 9 13 12 11 10
16 15 14 0R
SD/MMCPlus CARD INTERFACE - MCI0
VDDIOP1 VDDIOM R130 R131 R132 R129 R58 R112
68K
68K
68K
68K
10K
R59 10K
B
[7] [7] [7] [7] [7] PB19 [7] PB24 R183 22R (MCI1_CDA) (MCI1_CK)
PB20 PB21 PB22 PB23
(MCI1_DA0) (MCI1_DA1) (MCI1_DA2) (MCI1_DA3)
DNP(68K)
J11
7 8 1 2 3 5 4 6
DAT0 DAT1 DAT2 DAT3 CMD CLK VDD VSS 9 10 CD PGND PGND PGND PGND NC NC 11 12 13 14 15
[7] PE1
(MCI1_CD)
C110 10uF
C111 100nF
DNP(MCTF-0403)
Micro SD CARD INTERFACE - MCI1

A
A A
REV
RevA
INIT EDIT MODIF.
Embest 19-Feb-14 XXX XX-XXX-XX PPn 27-Sep-13 XXX XX-XXX-XX

DES.
DATE
VER.
DATE
SAMA5D3 Xplained HSMCI

4 3 2
SCALE
1/1
1
REV.
SHEET
8 11
55
Figure 4-46.
5 4
ETH0
10Base-T/100Base-TX/1000BASE-T
C112 20pF top/bot XI AVDDL_PLL Y3 25MHz NRST [4,5,10,11] + C113 10uF C114 10nF R60 R61 VDDIOP1 L17 1 XI XO + C117 10uF C118 10nF R63 12.1K 1% C121 10nF C122 10nF C123 10nF + C126 10uF C119 10nF C120 10nF 180ohm at 100MHz 2 AVDDH R62 22R VDDIOP1 4.7K 1K C115 10nF top/bot XO PB18 G125CK INT_GETHR PB10 PB17 GMDIO VDDIOP1 PB[0..31] [7,8,10,11]
Gigabit Ethernet
2 3
C116 20pF
49
48 47 46 45 44 43 42 41 40 39 38 37
AVDDL VDDIOP1 C128 10nF C129 10nF
MN10 KSZ9031RN R64 R65 R66 R67 4.7K 4.7K 4.7K 4.7K R68 22R
VDDIOP1
C
R71
ISET AVDDH XI XO AVDDL_PLL LDO_O RESET_N CLK125_NDO DVDDH DVDDL INT_N MDIO
J12 470R 470R ETH0_A+ ETH0_Atop/bot top/bot
R72
P_GND
+ C127 10uF
GMDC GRXCK GRX_CTL GRX0 GRX1 GRX2 GRX3 GTX_CTL
PB16 PB11 PB13 PB4 PB5 PB6 PB7 PB9
ETH0_A+ ETH0_AETH0_B+ ETH0_B-
1 2 3 4 TD1+ TD1TD2+ TD2ETH0_LED2 LINK
GRLA GRLC
11 12 Left Green LED

ETH0_LED1 ACT ETH0_D+ ETH0_Dtop/bot top/bot ETH0_B+ ETH0_BETH0_C+ ETH0_Ctop/bot top/bot top/bot top/bot
ETH0_C+ ETH0_CETH0_D+ ETH0_D-
7 8 9 10 TD3+ TD3TD4+ TD4YELC YELA
13 14 Right Yellow LED
1 2 3 4 5 6 7 8 9 10 11 12 AVDDH TXRXP_A TXRXM_A AVDDL TXRXP_B TXRXM_B TXRXP_C TXRXM_C AVDDL TXRXP_D TXRXM_D AVDDH
KSZ9031RNI 48-pin QFN
MDC RX_CLK DVDDH RX_DV RXD0 RXD1 DVDDL VSS RXD2 RXD3 DVDDL TX_EN
36 35 34 33 32 31 30 29 28 27 26 25
AVDDH
R111
DNP(0R)
5 6 TCT RCT
C125 48F-01GY2DPL2NL EARTH_ETH0 VDDIOP1 DVDDL
C124
GND GND GND GND
15 16 17 18
ETH0_GND R69 4.7K + C132 10uF C133 10nF C134 10nF C135 10nF C136 10nF C137 10nF C138 10nF R70 22R top/bot GTXCK GTX3 GTX2 GTX1 GTX0 PB8 PB3 PB2 PB1 PB0
B
ETH0_LED2 ETH0_LED1
R73 EARTH_ETH0
0R
L18 1
180ohm at 100MHz 2 RGMII Routing Constraints (Reduced Gigabit Media Independent Interface): The RGMII signals must be length-matched by TX and RX groups. That is, the TX group should be matched within 0.25 inch (6.35 mm), and the RX group should be matched within 0.25 inch (6.35 mm). Total length should not exceed 1.75 inch (44.5 mm). There is no requirement to match the TX and RX groups because their clocks are not related.
ETH0_GND
13 14 15 16 17 18 19 20 21 22 23 24
VSS_PS DVDDL LED2 DVDDH LED1 DVDDL TXD0 TXD1 TXD2 TXD3 DVDDL GTX_CLK
DNP(10uF 0805)
100nF
A A
REV
RevA
INIT EDIT MODIF.
Embest 19-Feb-14 XXX XX-XXX-XX PPn 27-Sep-13 XXX XX-XXX-XX

DES.
DATE
VER.
DATE
SAMA5D3 Xplained Ethernet_ETH0_10/100/1000

4 3 2
SCALE
1/1
1
REV.
SHEET
9 11
56
Figure 4-47.
5 4
Ethernet 10/100
ETH1
10Base-T/100Base-TX
R74 R75 1K 1K J13 TD+ 13F-64GYD2PL2NL MN9 10K R113
VDDIOP1
VDDIOP0
10K R114
TX+
1 TXP 4 2 TXM
TXTXtop/bot
TX+
TX+
top/bot
RXC/B-CAST_OFF
19
ETH1_PC7 ETH1_PC1 ETH1_PC0 ETH1_PC4 [7] [7] [7] [7]
CT TD-
TX-
3 RD+
RX+
3 RXP 5 6 RXM VDD_1V2

C139 100nF C141 2.2uF C140 100nF RXtop/bot RX-
RX+ top/bot
RX+
10K R115
CT RD-
RX-
4 2 MDC MDIO INTRP/NAND
TXD1 TXD0 TXEN RXD3/PHYAD0 RXD2/PHYAD1 RXD1/PHYAD2 RXD0/DUPLEX RXDV/CONFIG2 RXER/ISO CRS/CONFIG1 COL/CONFIG0
25 24 23 13 14 15 16 18 20 29 28
ETH1_PC3 ETH1_PC2 ETH1_PC5 ETH1_PC6
[7] [7] [7] [7]
75 NC
75
75
7
GND_ETH1
C142
100nF
12 11 21
E1_AVDDT
ETH1_PC8 [7] ETH1_PC9 [7] PB12 [7]
5 75 1nF
10K R116
10K R117
10K R118
10K R119
EARTH_ETH1 Left Green LED VDDIOP0 ETH1_XO
GND PADDLE TXC TXD2 TXD3 REXT VDDA_3V3 3
C143 + C144 100nF 10uF
EARTH_ETH1
15 16 8 XO XI 9
Right yellow LED
R77
R78 10K
ETH1_XI
VDDIO
17
C145 + C146 100nF 10uF
12
11
VDDIOP0 ETH1_LED1 ETH1_LED0 LINK ACT
10
10K ETH1_LED0 ETH1_LED1
30 31 LED0/NWAYEN LED1/SPEED
R79
470R
R80
470R KSZ8081RNB
RESET
32
NRST [4,5,9,11]
10K R120
13 14
6.49K 1% R76
VDDIOP0 L19 180ohm at 100MHz 1 2
1 33 22 26 27 10
C147 VDDIOP0
20pF
ETH1_XI
1
Y4 25MHz
3
C149 20pF
180ohm at 100MHz
R81
0R
L20 1
2
EARTH_ETH1
+ C148 10uF ETH1_XO
GND_ETH1
A A
REV
RevA
INIT EDIT MODIF.

DES.

DATE
VER.
DATE
SAMA5D3 Xplained Ethernet_ETH1_10/100

4 3 2
SCALE
1/1
1
REV.
SHEET
10 11
57
Figure 4-48.
5 4
PA[0..31] [7] PD[0..31] [7,8] J14 SPI1_SPCK NRST 3V3 5V_Ext J15_TWCK [7] J15_TWD [7] AREF [5] SPI1_MISO PC24 PC22 [5] VBat [4,5,9,10] 5V_Ext J16 P101-2*03SGF-116A-NX NRST 3V3 [4] 5V_Ext PA31 TWCK0 PA30 TWD0 AREF J15_Pin6 [7] J15_Pin5 [7] J15_Pin4 [7] J15_PC3 [7] J15_PC4 [7] J15
DNP(0R) R169
DNP(0R) R170
1 2 3 4 5 6 7 8 6 4 2 5 3 1
ETX0 ETX1 ERX0 PC25 SPI1_NPCS0 ERX1 ETXEN FH2543-08GT10 PC23 PC26 PD30 PC15 SPI1_MOSI FH2543-10GT10 J18 R84 DNP(0R) PC28 SPI1_NPCS3 PC30 UTXD0 PC29 URXD0 PE29 PE13 PE25 PE23 PE11 PE17 PE15 PA23 PA21 PA19 PA17 PE9 PB26 PC17 5V_Ext
10 9 8 7 6 5 4 3 2 1
R82 R85 R168 0R DNP(0R) R83
0R DNP(0R)
J17
J18_PC5 [7] J18_PC6 [7] J18_PC7 [7] J18_PC8 [7] J18_PC9 [7]
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7
PC18 PD20 PD21 PD22 PD23 PD24 PD25 PD26 PD27
1 2 3 4 5 6 7 8 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
FH2543-08GT10 J21 J19 J20 FH2543-08GT10
1 2 3 4 5 6 7 8
PB[0..31] [7,8,9,10] FH2543-08GT10
PE[0..31] [4,5,7,8]
PC20 AD8 PD28 PC21 AD9 PD29 PC19 AD10 PD30 PD31 CANRX1 PB14 PD19 PB15 CANRX0 PD14 CANTX0 PD15
R187 R188
0R DNP(0R)
PB15 PE31 PE14 PE26 PE24 PE12 PE20 PE16 PA22 PA20 PA18 PA16 PE10 PB27 PB25 PC16 JT254-DS180-850-218-001
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 PD24 PD25 PD26 PD27 PD28 PD29 PD30 PD31
36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
R86 R87 R88 R89 R91 R90
0R DNP(0R) 0R DNP(0R) 0R DNP(0R)
1 2 3 4 5 6 7 8
FH2543-08GT10
1 2 3 4 5 6 7 8
PE19 PE18 PB29 PB28 PD18 PD17 PC26 PC27
TXD3 RXD3 TXD1 RXD1 TXD0 RXD0 TWD1 TWCK1
Extention boards connectors

TWD_ISI [7] TWCK_ISI [7]
C
5V_MAIN R92 R93 0R DNP(0R)
3V3
LCD Connector
J22
LCD, JTAG, DEBUG and Extended Connectors
NRST PE6 (RST_LCD) [7] TWCK_LCD [7] TWD_LCD PD20 (AD0) PD12 (SPI0_SPCK) PD21 (AD1) PD11 (SPI0_MOSI) PD22 (AD2) PD10 (SPI0_MISO) PD23 (AD3) R102 PD16 (SPI0_NPCS3) R103 PA28 (LCDPCK) R184 R98 R101 DNP(0R) 22R DNP(0R) 22R 22R R100 R97 DNP(0R) 22R R95 R96 DNP(0R) 22R TWCK_LCD TWD_LCD
R94 R99
0R DNP(0R) PA24 (LCDPWM) PE8 (IRQ2) PE7 IRQ1) TWCK_LCD TWD_LCD PA25 (LCDDISP)
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 PA29 (LCDDEN) PA27 (LCDHSYNC) PA26 (LCDVSYNC)
PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PE16 PE17 PE18 PE19 PE20 PE21 PE22 PE23 PE24 PE25 PE26 PE27 PE28 PE29 PE30 PE31
PC[0..31] [4,7]
PE28 (LCDDAT23) PE27 (LCDDAT22) PC15 (LCDDAT21) PC10 (LCDDAT20) PC11 PC12 PC13 PC14 (LCDDAT19) (LCDDAT18) (LCDDAT17) (LCDDAT16)
3V3 R189
3V3 5V_MAIN
68K R190 DNP(0R) R171 68K
DNP(0R) R172 PE13 [7] PB31 [7] PB30 PE14 0R PA15 PA14 PA13 PA12 (LCDDAT15) (LCDDAT14) (LCDDAT13) (LCDDAT12) R173 (TXD) (RXD) R174 0R
JTAG
VDDIOP0 3V3 R104 100K 1% 100K 1% J24 R108 0R 100K 1% 100K 1% R105 R106 R107
J23
PA11 PA10 PA9 PA8 NTRST [5] TDI [5] TMS [5] TCK [5]
(LCDDAT11) (LCDDAT10) (LCDDAT9) (LCDDAT8)
1 2 3 4 5 6
DEBUG
P101-1*06SGF-116A-NX
TDI TMS TCK RTCK TDO R109 R110 0R 0R
PA7 PA6 PA5 PA4 TDO [5] NRST [4,5,9,10] PA3 PA2 PA1 PA0
(LCDDAT7) (LCDDAT6) (LCDDAT5) (LCDDAT4) (LCDDAT3) (LCDDAT2) (LCDDAT1) (LCDDAT0) PE23 (ID_SYS)
2 4 6 8 10 12 14 16 18 20
P101-2*10SGF-116A-NX
1 3 5 7 9 11 13 15 17 19
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
52 51
RevA FP520T1-50SR04 SAMA5D3 Xplained Connectors
REV
A A

INIT EDIT MODIF.
SCALE
DES.

DATE
VER.
DATE
PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31
1/1
4 3 2 1
REV.
SHEET
11 11
58
5.
Revision History
Table 5-1. Doc. Rev. 11269A SAMA5D3 Xplained User Guide Rev. 11269A Revision History Changes First issue

59
Atmel Corporation 1600 Technology Drive San Jose, CA 95110 USA Tel: (+1) (408) 441-0311 Fax: (+1) (408) 487-2600 www.atmel.com
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2014 Atmel Corporation. All rights reserved. / Rev.: 11269AATARM20-Feb-14 Atmel, Atmel logo and combinations thereof, Enabling Unlimited Possibilities, QTouch and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. ARM and Cortex are registered trademarks or trademarks of ARM Ltd. Other terms and product names may be trademarks of others.
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.

Atmel 11269 32 Bit Cortex A5 Microcontroller SAMA5D3 Xplained User Guide

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Atmel 11269 32 Bit Cortex A5 Microcontroller SAMA5D3 Xplained User Guide

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ARM-based Embedded MPUs

One SAMA5D3 Xplained board One micro-AB type USB cable

Atmel SAMA5D3 Series Datasheet SAMA5D3 Xplained Getting Started

SAMA5D3 Xplained User Guide [USER GUIDE]

SAMA5D3 Xplained User Guide [USER GUIDE]

Evaluation Kit Specifications

0C to +70C -40C to +85C 0 to 90% (non-condensing) Compliant ATSAMA5D3-XPLD

ESD-Sensitive Electronic Equipment!

Electrostatic sensitive device

Power Supply Warning

SAMA5D3 Xplained User Guide [USER GUIDE]

Power up the Board

Electrical Characteristics Values 5 VCC 6 VCC 1.2A 3.3V only

Sample Code and Technical Support

SAMA5D3 Xplained User Guide [USER GUIDE]

SAMA5D3 Xplained User Guide [USER GUIDE]

Characteristics PCB characteristics Processor Processor clock sources

Optional on-board memory

USB Display interface Ethernet

SAMA5D3 Xplained User Guide [USER GUIDE]

SAMA5D3 Xplained Board Overview

2Gb Nand Flash Memory J15 PIO Expansion

USB A Device Supply Input

USB Host Interfaces

1Gb DDR2 Memory SAMA5D36

1Gb DDR2 Memory

t Optional Supply Input Ethernet 10/100 Voltages and Reset Interface

System Buttons JTAG Interface ADC Inputs Expansion

SAMA5D3 Xplained User Guide [USER GUIDE]

Single PMU Solution

5V INPUT USB DEVICE USB Host x2 JTAG DBGU

5V & 3V3 USB A,B,C Power rails

ATMEL SAMA5D36 CORTEX-A5 PROCESSOR

JTAG & DBGU USER LEDS PIO

2Gb DDR2 SDRAM

2Gb NAND FLASH

SERIAL DATA FLASH

10/100/1000 FAST ETHERNET ETH0

10/100 ETHERNET ETH1

SAMA5D3 Xplained User Guide [USER GUIDE]

Table 4-1. Quantity 1 1 1 1

SAMA5D3 Xplained User Guide [USER GUIDE]

Board Power Management Schematic

5V_MAIN MN1 3V3 3V3 C1 4.7uF C2 4.7uF C3 4.7uF R4 1R C6 1uF ACT8865

VP1 VP2 VP3 NC2 VDDREF

[7] TWCK_PMIC [7] TWD_PMIC

C17 100nF FUSE_2V5

Auto PWRON (option) R12

REFBP OUT4 OUT5

(2V5) VDDANA (3V3) C19 100nF JP4 DNP(JUMPER)

TP1 SMD TP2 SMD

L12 R17 2R2 10uH60mA C26 4.7uF

WAKUP or Force Power ON

SAMA5D3 Xplained User Guide [USER GUIDE]

Input Powering Scheme Option Schematic

0R 0R DNP(0R) DNP(0R) DNP(0R) DNP(0R)

VBAT Powering Scheme Option Schematic

Place TP4 to Bottom

Populate R185 if no Super Cap (C41)

VDDBU C28 100nF

R23 1.5K 1% [4,9,10,11] NRST NRST

TDI TMS TCK TDO NTRST

T9 R8 N10 P9 M11 P11 V9