07 Combinational circuits

- Multiplexers (MUXs or selectors)

- Crossbar and LUT examples
- Decoders
- One-hot decoder with enable
- Demultiplexers (DeMUX)
- Encoders/Priority Encoders
- Arithmetic comparators
- Verilog for combinational circuits
Multiplexers:
A Multiplexer (mux for short) or a selector
selects the output to follow one of many
inputs:
Example 1: a 2-to-1 mux:
Graphical symbol
f
s
w
0
w
1
0
1
Truth table
0
1
f
s
w
0
w
1
f
s
w
0
w
1
Sum-of-products circuit
[BV]
Multiplexers (cont):
Example 2: a 4-to-1 mux
Truth table
w
0
w
1
0
0
1
1
1
0
1
f s
1
0
s
0
w
2
w
3
f
s
1
w
0
w
1
00
01
s
0
w
2
w
3
10
11
Graphic symbol
f
Circuit
s
1
w
0
w
1
s
0
w
2
w
3
[BV]
0
w
0
w
1
0
1
w
2
w
3
0
1
f
0
1
s
1
s
Building a 4-to-1 MUX using 2-to-1 MUXs:
w0
w1
w3
s

f
0
1
3
2
A select line (s) which is 2-bit wide
means s can have 4 different values
selects from w0 w3 (4 inputs)
[BV]
[K]
w
8
w
11
s
1
w
0
s
0
w
3
w
4
w
7
w
12
w
15
s
3
s
2
f
Building a 16-to-1 MUX using 4-to-1 MUXs:
w0
w1
w15
s

f
0
1
15
4
A select line (s) which is 4-bit wide
means s can have 16 different values
selects from w0 w15 (16 inputs)
[BV]
[K]
A mux with n-bit select lines:
w0
w1
w2
n
-1
s

f
0
1
2
n
-1
n
A select line (s) which is n-bit wide
means s can have 2
n
different values
selects from w0 w2
n
-1 (2
n
inputs)
Ex: 2
6
= 64 or 6 = log
2
(64), so
a 64-to-1 mux has 6-bit wide select line
[K]
Application of multiplexers:
A crossbar: - very widely used in digital
telecommunications
x
1
x
2
y
1
y
2
A 2x2 crossbar switch
s
Behavioral description:
always @(s or x1 or x2)
begin
if (s == 0)
begin
y1 = x1;
y2 = x2;
end
else // s == 1
begin
y1 = x2;
y2 = x1;
end
end
Verilog comment
[BV]
x
1
0
1
x
2
0
1
s
y
1
y
2
Implementation using muxes
x
1
x
2
y
1
y
2
A 2x2 crossbar switch
s
Crossbar using multiplexers:
In telecomm. applications, crossbar size is much bigger:

x0
x7
y0
y7
config
A 2x2 crossbar has 2!
= 2 permutations
need 1-bit config line
A 8x8 crossbar has 8!
= 40320 permutations.
need log
2
(8!) = 15.3
16 bits config line
16
[BV]
Implementing truth table using MUX:
Implementation using a 4-to-1 multiplexer
f
w
1
0
1
0
1
w
2
1
0
0
0
1
1
1
0
1
f w
1
0
w
2
1
0
can be extended to a function of more than 2 variables:
1
1
1
1
0
0
0
0
x
1 1 1
0 0 1
0 1 0
1 0 0
0 1 1
1 0 1
1 1 0
0 0 0
f z y
0
1
1

f
0
1
7
x y z
[BV]
Look-up table (LUT):
f
w
1
0
1
0
1
w
2
1
0
0
0
1
1
1
0
1
f w
1
0
w
2
1
0
- The above can implement ANY function of 2 variables.
(no need to do any function minimization at all)
- Extension to > 2 variables possible.
- Efficient implementation of this method is called LUT
- Look-up table can be used to implement any function:
x[0]
x[n-1]

f(x[0], , x[n-1])
n input lines
2
n
possible
input
combinations
2
n
entries
LUT
function of n variables
[BV]
Decoders:
One-hot decoder with enable:
0
0
1
1
1
0
1
y
0
w
1
0
w
0
x x
1
1
0
1
1
En
0
0
0
1
0
y
1
1
0
0
0
0
y
2
0
1
0
0
0
y
3
0
0
1
0
0
w
0
En
y
0
w
1
y
1
y
2
y
3
Truth table Graphical symbol
2 inputs can have 2
2
= 4 possible input combinations
if (not enable) then all outputs are zero,
else (this means enable is 1)
assert one output indexed by input
[BV]
Decoders:
One-hot decoder with enable:
0
w
n 1
n
inputs
En
Enable
2
n
outputs
y
0
y
2
n
1
w
- n inputs can have 2
n
possible input combinations
- if (enable is 0)
All output lines are zero
else (this means enable is 0)
Assert only one y output indexed by the input.
This is why its called one-hot. The rest of output is 0.
[BV]
Decoder tree:
w
0
En
y
0
w
1
y
1
y
2
y
3
y
8
y
9
y
10
y
11
w
2
w
0
y
0
y
1
y
2
y
3
w
0
En
y
0
w
1
y
1
y
2
y
3
w
0
En
y
0
w
1
y
1
y
2
y
3
y
4
y
5
y
6
y
7
w
1
w
0
En
y
0
w
1
y
1
y
2
y
3
y
12
y
13
y
14
y
15
w
0
En
y
0
w
1
y
1
y
2
y
3
w
3
En
w
(1)
First stage decoder
selects which of the
4 decoders in second
stage will be active.
w2 and w3 are upper
2 bits.
(2)
Second stage decoders
select the lower 2 bits.
Only one decoder in
second stage will be enabled.
one-hot 4 to 16 decoder
(1)
(2)
[BV]
Demultiplexer (demux):
Mux selects one output from many inputs
Demux selects which output to copy input to
Demux is actually a one-hot encoder with enable.
0
0
1
1
1
0
1
y
0
w
1
0
w
0
x x
1
1
0
1
1
En
0
0
0
1
0
y
1
1
0
0
0
0
y
2
0
1
0
0
0
y
3
0
0
1
0
0
w
0
En
y
0
w
1
y
1
y
2
y
3
Truth table Encoder symbol
Truth table
w
0
w
1
0
0
1
1
1
0
1
f s
1
0
s
0
w
2
w
3
f
s
1
w
0
w
1
00
01
s
0
w
2
w
3
10
11
Graphic symbol
En
w
0
y
0
y
1
00
01
w
1
y
2
y
3
10
11
Demultiplexer symbol
[BV]
Encoders:
Decoder: code to one-hot output:
Binary encoder: one-hot input to code:
0
0
1
1
1
0
1
y
0
w
1
0
w
0
x x
1
1
0
1
1
En
0
0
0
1
0
y
1
1
0
0
0
0
y
2
0
1
0
0
0
y
3
0
0
1
0
0
w
0
En
y
0
w
1
y
1
y
2
y
3
0
0
1
1
1
0
1
w
3
y
1
0
y
0
0
0
1
0
w
2
0
1
0
0
w
1
1
0
0
0
w
0
0
0
0
1
Truth table
y
0
w3
y
1
w2
w1
w0
Graphical symbol
[BV]
Binary encoder:
0
0
1
1
1
0
1
w
3
y
1
0
y
0
0
0
1
0
w
2
0
1
0
0
w
1
1
0
0
0
w
0
0
0
0
1
Truth table
y
0
w3
y
1
w2
w1
w0
Graphical symbol
A BIG flaw in binary encoder:
input that is not one hot is an invalid input.
Solution: A priority encoder
- No input {w3,w2,w1,w0} = 0000 means output is
not valid
- Gives priority to w3 over w2, w2 over w1,
w1 over w0. All input combinations are valid
[BV]
z
d
0
0
1
0
1
0
w
0
y
1
d
y
0
1 1
0
1
1
1
1
z
1
x
x
0
x
w
1
0
1
x
0
x
w
2
0
0
1
0
x
w
3
0
0
0
0
1
y
0
w3
y
1
w2
w1
w0
Graphical symbol
Priority encoder:
z indicates output y is valid
w3 has highest priority, w0 has lowest priority.
Real life example: We have only one server to
serve 4 important people.
w3 = most important, , w0 = least important
z == 1 we need to serve someone,
y is the code of the most important person to serve.
[BV]
Arithmetic comparators:
Compare the size of two numbers:
Example: 4-bit comparators
a
b
4 4
compare
aLTb
aGTb
aEQb
Only 3 outcomes are possible:
1. a < b (aLTb) Ex: a = 4b1011, b = 4b1101
2. a > b (aGTb) Ex: a = 4b1000, b = 4b0101
3. a = b (aEQb) Ex: a = 4b0110, b = 4b0110
usually compares
unsigned numbers.
[K]
Arithmetic comparators:
Consider 2 one-bit inputs:
1
a>b
1
a<b
1 1 1
0 1
1 0
1 0 0
a=b b a
a = b is this:
a
b
a = b
a > b is this:
a
b
a > b
a < b is
a
b
a < b
or a < b = (aGTb + aEQb)
a > b
a = b
a < b
[BV]
i
0
i
1
i
2
i
3
b
0
a
0
b
1
a
1
b
2
a
2
b
3
a
3
AeqB
AgtB
AltB
The 4-bit comparator:
(1) each bit equal
(2) all bits equal
(3) a3 > b3
(4) a3 = b3, and a2 > b2
(5) a > b
(6) a < b from (2) & (5)
(1)
(2)
(3)
(4)
(5)
[BV]
The cascading comparator:
Outputs Cascade inputs a and b
=
in
<
in
>
in
=
in
<
in
>
in
a=b 00
11
0 1 0 x x x a<b 01
0 0 1 x x x a>b 10
= < > = < > note a,b
>
<
=
>
<
=
a0 b0
a>b
a<b
a=b
>
<
=
>
<
=
a1 b1
>
<
=
>
<
=
a2 b2
0
0
1
[K]
The cascading comparator examples:
>
<
=
>
<
=
1 0
a>b
a<b
a=b
>
<
=
>
<
=
0 1
>
<
=
>
<
=
1 1
0
0
1
a = 101, b = 110 (a < b)
>
<
=
>
<
=
0 0
a>b
a<b
a=b
>
<
=
>
<
=
1 0
>
<
=
>
<
=
0
0
0
1
a = 010, b = 000 (a > b)
0
[K]
Verilog for combinational logic:
cascading comparator:
module comp (a, b, gti, lti, eqi, gto, lto, eqo);
input a, b, gti, lti, eqi;
output gto, lto, eqo;
reg gto, lto, eqo;
always @ (a or b or gti or lti or eqi)
case({a,b})
2b10: {gto, lto, eqo} = 3b100; // a > b
2b01: {gto, lto, eqo} = 3b010; // a < b
default: {gto, lto, eqo} = {gti, lti, eqi};
endcase
endmodule
Dont forget these in your
sensitivity list
Verilog for combinational logic:
The functionality of the 74381 ALU.
ALU: Arithmetic and logic unit
ALU
4
4
A
B
4
F
s
3
operation
operands
output
[BV]
ALU:
The functionality of the 74381 ALU.
// 74381 ALU
module alu(s, A, B, F);
input [2:0] s;
input [3:0] A, B;
output [3:0] F;
reg [3:0] F;
always @(s or A or B)
case (s)
0: F = 4'b0000;
1: F = B - A;
2: F = A - B;
3: F = A + B;
4: F = A ^ B;
5: F = A | B;
6: F = A & B;
7: F = 4'b1111;
endcase
endmodule
[BV]
ALU simulation result:
B A (6-A)
0110 (6)
-1010 (A)
1100 (C)
A ^ B (A ^ 6)
bitwise xor
1010 (A)
^0110 (6)
1100 (C)
A & B (A & 6)
bitwise and
1010 (A)
&0110 (6)
0010 (2)
propagation delay
Propagation delay for subtraction is longest, followed by
XOR. Propagation delay for AND operation is not very long.
explain
why
[BV]
A 4-to-1 MUX:
module mux4to1 (w, s, f);
input [3:0] w;
input [1:0] s;
output f;
reg f;
always @(w or s)
case (s)
0: f = w[0];
1: f = w[1];
2: f = w[2];
3: f = w[3];
endcase
endmodule [BV/K]
This is almost like Fig. 6.34
From Brown and Vranesic
text, with a couple of changes.
These changes are to made
coding more consistent and
easier to debug.
1. When creating a bus,
always run the bit index
from MSB to LSB (from
high number to low number)
(text used [0:3])
2. Always use lowercase letters
for signal names. (text used
W and S instead of w and s)
module dec2to4 (w, y, en);
input [1:0] w;
input en;
output [3:0] y;
reg [3:0] y;
always @ (w or en)
begin
if (en = = 0)
y = 4'b0000;
else
case (w)
0: y = 4'b0001;
1: y = 4'b0010;
2: y = 4'b0100;
3: y = 4'b1000;
endcase
end
endmodule
A 2-to-4 decoder:
[BV/K]
Again, a modification from Fig
6.36 in B&V.
Most real-world designs stick
to the rules stated on previous
slide.
1. bit index goes from [hi:lo]
2. signal names are lowercase
Where to use uppercase?
There are used in defining
constants in text macros or
constants in parameters
Just like C programming
practices.
Again, a modification from Fig
6.41 in B&V.
casex statement:
A casex statement is like a
regular case statement,
with the additional capability
that you can use x in the
case value as dont care
CAREFUL: x will only work
with binary (bx), octal (ox),
and hex (hx), X does not work
with decimal (dx) number.
A priority encoder:
[BV/K]
module priority (w, y, z);
input [3:0] w;
output [1:0] y;
output z;
reg [1:0] y;
reg z;
always @(w)
begin
z = 1;
casex(w)
4'b1xxx: y = 3;
4'b01xx: y = 2;
4'b001x: y = 1;
4'b0001: y = 0;
default: begin
z = 0;
y = 2'b0;
end
endcase
end
endmodule
Again, a modification from Fig
6.41 in B&V.
casex statement:
So, this case is taken whenever w
is 1xxx, meaning w is 1000, 1001, ...,
1111
This case is taken when w is 01xx
(or 0100, 0101, 0110, 0111)
When all other case checks fail, casex
will take the default clause
A priority encoder:
[BV/K]
module priority (w, y, z);
input [3:0] w;
output [1:0] y;
output z;
reg [1:0] y;
reg z;
always @(w)
begin
z = 1;
casex(w)
4'b1xxx: y = 3;
4'b01xx: y = 2;
4'b001x: y = 1;
4'b0001: y = 0;
default: begin
z = 0;
y = 2'b0;
end
endcase
end
endmodule
Again, a modification from Fig
6.41 in B&V.
One more change:
1. bit index goes from [hi:lo]
2. signal names are lowercase
3. Dont assign X to your design
output.
Why not? X is unknown.
Your design output should be
known when all the inputs are
known. Real circuits dont
have X, your design should not
have X explicitly assigned.
A priority encoder:
[BV/K]
module priority (w, y, z);
input [3:0] w;
output [1:0] y;
output z;
reg [1:0] y;
reg z;
always @(w)
begin
z = 1;
casex(w)
4'b1xxx: y = 3;
4'b01xx: y = 2;
4'b001x: y = 1;
4'b0001: y = 0;
default: begin
z = 0;
y = 2'b0;
end
endcase
end
endmodule
Another suggestion Fig 6.41
in B&V:
Some synthesis tools dont
synthesize casex correctly.
AVOID USING casex
unless you know exactly
what synthesis tools will do
Use cascaded if-else-if-else
instead.
This is preferable to casex
implementation.
case is good, but casex is not
A priority encoder:
[BV/K]
module priority (w, y, z);
input [3:0] w;
output [1:0] y; output z;
reg [1:0] y; reg z;
always @(w)
begin
z = 1;
if (w[3])
y = 3;
else if (w[2])
y = 2;
else if (w[1])
y = 1;
else if (w[0])
y = 0;
else begin
z = 0;
y = 2'b0;
end
end
endmodule
Again, a modification from Fig
6.45 in B&V.
One change:
1. Signal names are lowercase
If you need to concatenate words
in signal names, you can use
the underscore ( _ ) to do so
Example:
Dont write AltB ( A less than B)
Write a_lt_b (a less than b)
A 4-bit comparator:
[BV/K]
module compare
(a, b, a_eq_b, a_gt_b, a_lt_b);
input [3:0] a, b;
output a_eq_b, a_gt_b, a_lt_b;
reg a_eq_b, a_gt_b, a_lt_b;
always @ (a or b)
begin
a_eq_b = 0;
a_gt_b = 0;
a_lt_b = 0;
if (a = = b)
a_eq_b = 1;
else if (a > b)
a_gt_b = 1;
else
a_lt_b = 1;
end
endmodule
Exercise: Write a cascading
comparator from this code.