Lab2NewComputerProcessorinstructionextensions 1. Introduction Modernprocessorsuseextremelycomplexdigitalcircuits,butinthislabexercise,amuchsimplerprocessorbasedonthedatapathstudiedinlecturesisconsidered.The designuseforDigitaldesignstudiedlastsemesterhasbeenextendedtohaveadatafileandinstructionsallowingittoloop.Theblockdiagramofwhichisshownbelow. Thedatalinesareshowninblueandtheyareall9bitwide,figure1.

Figure1Datapathof8bitcomputercoupledtotheprogrammememory


Theinstructionbitfieldis

Bits23:2019:16 15:12 11:147:4 3:0

IIII,xWWW,Reg/data,RRR,DDDD,xAluOpRd/Wd,IOen,xxxx

WhereBits23:20aretheinstructioncodetakenfromtable1,bits18:16isthewriteaddress.,bit15istheReg/Data(regDat)line,bits14:12isthereadaddress,bits11:8 DDDDisthedataaddress,bit6isAluOpbit,bit5Readdata/WriteDatalinebit4isIOenline.Allxbitsarenotcurrentlyinuse.NoteIOenlineisnotcurrentinusesoalso cansettozero.Threejumpinstructionshavenowbeenadded.

Table 1 Mnemonicdescription.PandQareregisternumberswithlegalvalues07,pisthedestinationregisterinbitsqisthesourceaddressinbits.
Fortheloadinstructionthesourceisthedataaddress,D.Ciscontrolcomprisingof3bits:Aluoperation(1bit)/ReadDatanotWritedata(1bit)IOena ble(1bit).TheR/Dline(1bit)controlswhetherdataisfromthealu,1,orfromthedatafile,0.Xareunusedbitsandtheirdefaultvalueshouldbesetto 0
Mnemonic Control code IIII 23:20 xWWW 19:16 R/D RRR 15: 12 DDDD 11: 8 xA/Rd/Wd /IOen 7:4 Not in u se 3:0 Comments

LD Rp,Dq

1PQ DC 3pq 4p1 5p1 6pq 7pq AQ BQ CQ

0001 0010 0011 0100 0101 0110 0111 1010 1100 1011

xppp xppp xppp xppp xppp xppp xppp QQQQ QQQQ QQQQ

0000 1qqq 1qqq 1ppp 1ppp 1qqq 1qqq QQQQ QQQQ QQQQ

qqqq 0000 0000 0000 0000 0000 0000

0010 0110 0110 0110 0110 0010 0110

xxxx xxxx xxxx xxxx xxxx xxxx xxxx

Load register P with contents of data address Q Rp = Rp + Rq Rp = Rp - Rq Rp = Rp + 1 Rp = Rp -1 Rp = Rq Rp = Rp * Rq Jump relative to current location to Q where Q is a 2complimen t number + 127 forward, -128 back Jump if Zero flag set to Q location or get next instruction Jump if Greater than flag set to Q location or get next instruction

ADD Rp,Rq 2pq SUB Rp,R q INC Rp DEC Rp COP Rp,Rq MUL Rp,R q JUMP Q JZ JG

The instruction mnemonics are defined thus: LD Rp ,Dq - load register Rp,with contents of Dq LD Dp, Rq - store data in register q in data location p COP Rp, Rq - copy, Rq into Rp ADD, Rp, Rq - arithmetically add contents Rp and Rq and store the result in Rp SUB , Rp,Rq - arithmetically subtract contents Rq from Rp and store the result in Rp INC, Rp increment Rp by 1 DEC, Rp - decrement Rp by 1 MUL Rp,Rq . multiply contents of Rp by contents of Rq and store in Rp where p is a 3 bit address and q is 4 bit address It is also legally possible to have these instructions ADD Rp,Rp - arithmetically add contents Rp to itself and store the resultant in Rp MUL Rp,Rp . multiply contents of Rp by itself and store in Rp JUMP Q : always jump relative to current location to new programme location Q. Q is set as a 2s compliment nu mber allowing jumps to occur + 127 forward and -128 back from location JZ Q : jump relative to location if Zero flag is set. Q is set as in JUMP instruction JG Q ; jump relative to location if Less than flag set. . Q is set as in JUMP instruction

TheIOmodule.

Figure2IOportdetail

TheIOmoduleworksinconjunctionwiththedataregister.Youwillseefromtheverilogcodedescribingtheioport infigure2thatwhenthedataaddress=0xFtheIOrequestgoeshighswitchingthedataregisterportoffforIOport reads.

LabInstructions 1. LoadAlteraQuartis 2. Using:File>NewProjectWizard,createanewprojectinanewfolderonyourH:\drive.(selectCycloneII EP2C20F484C7device) 3. Oncethewizardiscompleteandtheprojectiscreated,addasourcefilebyselecting:File>New,andselecta Verilogsourcefilecpu29Shell.v(doesnotcontainthejumpinstruction). 4. Implementanewinstructionwithajumpifgreaterthancondition(inredintheinstructionmnemoniclist) andthenwriteasmallprogrammeinassemblertodemonstratethishighlevelprogrammefragment incorporatingthenewinstruction. count=0; For(i=0;I<12;i++) { if(IN==3)count=count+1; } 5. Whatmodificationwouldyoumaketothemachinetoallowpointersorarrayindicestotheused? 6. Uploadyourworktothereportsectionsforlab2.

Ancillaryinformation
PleasereadChapter8inDigitalDesignbyVahidandthelectureslidesprog_processor2014_part1andpart2.pdf.Furt herresourcesforverilogprogrammingaregivenintheweblinksonthecomputerarchitecturepagesgivenonVision . Uploadyourworkviathevisionportalbyansweringtwosections: Section1:AMSworddocument(*.docxfile)thatdescribeshowyoualteredthecodetoaddthejumpinstruction withascreenshotshowingthetimingdiagramdemonstratingfromprogrammedfunction.Alsoaddyouranswerto question5 Section2.:Theverilogsourcefile(s)(extension.v)withthecodefullycommented.

IfthisisajointeffortIwanttoknowthecontributionfromeach.NoteIwillonlyallow jointeffortfromNOMOREthanTWOindividuals.

Thismustbesubmittedbyuploadingtovision.Fillinginbothsections Criteriaforassessment a) Concisedescriptionofthecpuchanges b) Codecomments c) Functioningcode

Copying other students code is easy to detect and you will be penalized for doing as such. Please make sure you submit your own work.

This should be submitted by 23:59 on or before 31st March 2014