PCI Local Bus Technical Summary

Table of Contents
1.0 PCI Overview

2.0 PCI ocuments

2.1 PCI S!ecifications 2.2 PCI Boo"s

#.0 PCI Bus Protocol

$.0 PCI Si%nal escri!tions

$.1 System Pins $.2 &''ress an' ata Pins $.# Interface Control Pins $.$ &rbitration Pins (Initiator Only) $.* +rror ,e!ortin% Pins $.- Interru!t Pins $.. Cache Su!!ort Pins (O!tional) $./ &''itional Pins $.0 -$1Bit Bus +2tension Pins (O!tional) $.10 3T&45Boun'ary Scan Pins (O!tional)

*.0 PCI Bus Timin% ia%rams

*.1 ,ea' Transaction *.2 6rite Transaction

-.0 PCI Connector Pinout

1.0 PCI Overview

The PCI Local Bus is a high performance bus for interconnecting chips, expansion boards, and processor/memory subsystems. It originated at Intel in the early 1 !s as a standard method of interconnecting chips on a board. It "as later adopted as an industry standard administered by the PCI Special Interest Group, or #PCI $I%#. &nder the PCI $I% the definition of PCI "as extended to define a standard expansion bus interface connector for add'in boards. PCI "as first adopted for use in personal computers in about 1 ( "ith Intel)s introduction of the #$aturn# chipset and #*lfredo# motherboard for the (+, processor. -ith introduction of chipsets and motherboards for the Intel Pentium processor, PCI largely replaced earlier bus architectures such as .I$*, /L, and 0icro Channel. The I$* bus has initially continued to co'exist "ith PCI for support of #legacy# add'in boards that don)t re1uire the high performance of the PCI bus. But as legacy boards are redesigned, PCI is expected to completely replace I$* as "ell. 2n $eptember 11, 1 + the PCI $I% announced that Compa1, 3e"lett'Pac4ard, and IB0 had submitted a ne" specification for re5ie" called #PCI'6#. The proposed standard allo"s for increases in PCI bus speed up to 177 038. It also includes suggested changes in the PCI communications protocol affecting data transfer rates and electrical timing re1uirements. The PCI'$I% has appro5ed the formation of a "or4ing group to re5ie" the proposal.

2.0 PCI ocuments

2.1 PCI S!ecifications
Copies of the PCI Local Bus Specifications may be ordered for a fee from the PCI $I%. The follo"ing is the release history of the PCI specification9 :e5ision 1.! ' 2riginal issue. :eleased ,/;;/ ;. Component le5el specification only. <id not define the expansion board connector. :e5ision ;.! ' :eleased (/7!/ 7. Incorporated the connector and expansion board specification. :e5ision ;.1 ' :eleased ,/1/ =. <efined ,, 038 option and added many clarifications. :e5ision ;.; ' :eleased 1;/1+/ +. Incorporates many minor clarifications and enhancements. The PCI $I% also maintains the follo"ing PCI related documents9

PCI to PCI Bridge Architecture Specification

PCI Mobile Design Guide PCI Bus Power Management Interface Specification PCI Hot Plug Specification PCI BI!S Specification Small PCI Specification

2.2 PCI Boo"s

T"o recommended boo4s on PCI are9 PCI Hardware " Software Architecture and Design by .d"ard $olari > %eorge -illse ?*nnaboo4s@ ?I$BA !' ; 7 ;'= '!@ PCI S#stem Architecture by Tom $hanley ?0ind$hare@ ?I$BA !';!1'(! 7'7@

#.0 PCI Bus Protocol

PCI is a synchronous bus architecture "ith all data transfers being performed relati5e to a system cloc4 ?CLB@. The initial PCI specification permitted a maximum cloc4 rate of 77 038 allo"ing one bus transfer to be performed e5ery 7! nanoseconds. Later, :e5ision ;.1 of the PCI specification extended the bus definition to support operation at ,, 038, but the 5ast maCority of today)s personal computers continue to implement a PCI bus that runs at a maximum speed of 77 038. PCI implements a 7;'bit multiplexed *ddress and <ata bus ?*<D719!E@. It architects a means of supporting a ,('bit data bus through a longer connector slot, but most of today)s personal computers support only 7;'bit data transfers through the base 7;'bit PCI connector. *t 77 038, a 7;'bit slot supports a maximum data transfer rate of 17; 0Bytes/sec, and a ,('bit slot supports ;,( 0Bytes/sec. The multiplexed *ddress and <ata bus allo"s a reduced pin count on the PCI connector that enables lo"er cost and smaller pac4age si8e for PCI components. Typical 7;'bit PCI add'in boards use only about =! signals pins on the PCI connector of "hich 7; are the multiplexed *ddress and <ata bus. PCI bus cycles are initiated by dri5ing an address onto the *<D719!E signals during the first cloc4 edge called the address phase. The address phase is signaled by the acti5ation of the F:*0.G signal. The next cloc4 edge begins the first of one or more data phases in "hich data is transferred o5er the *<D719!E signals. In PCI terminology, data is transferred bet"een an initiator "hich is the bus master, and a target "hich is the bus sla5e. The initiator dri5es the C/B.D79!EG signals during the address phase to signal the type of transfer ?memory read, memory "rite, I/2 read, I/2 "rite, etc.@. <uring data phases the C/B.D79!EG signals ser5e as byte enable to indicate "hich data bytes are 5alid. Both the initiator and target may insert "ait states into the data transfer by deasserting the I:<HG and T:<HG signals. /alid data transfers occur on each cloc4 edge in "hich both I:<HG and T:<HG are asserted.

* PCI bus transfer consists of one address phase and any number of data phases. I/2 operations that access registers "ithin PCI targets typically ha5e only a single data phase. 0emory transfers that mo5e bloc4s of data consist of multiple data phases that read or "rite multiple consecuti5e memory locations. Both the initiator and target may terminate a bus transfer se1uence at any time. The initiator signals completion of the bus transfer by deasserting the F:*0.G signal during the last data phase. * target may terminate a bus transfer by asserting the $T2PG signal. -hen the initiator detects an acti5e $T2PG signal, it must terminate the current bus transfer and re'arbitrate for the bus before continuing. If $T2PG is asserted "ithout any data phases completing, the target has issued a retr#. If $T2PG is asserted after one or more data phases ha5e successfully completed, the target has issued a disconnect. Initiators arbitrate for o"nership of the bus by asserting a :.IG signal to a central arbiter. The arbiter grants o"nership of the bus by asserting the %ATG signal. :.IG and %ATG are uni1ue on a per slot basis allo"ing the arbiter to implement a bus fairness algorithm. *rbitration in PCI is #hidden# in the sense that it does not consume cloc4 cycles. The current initiator)s bus transfers are o5erlapped "ith the arbitration process that determines the next o"ner of the bus. PCI supports a rigorous auto configuration mechanism. .ach PCI de5ice includes a set of configuration registers that allo" identification of the type of de5ice ?$C$I, 5ideo, .thernet, etc.@ and the company that produced it. 2ther registers allo" configuration of the de5ice)s I/2 addresses, memory addresses, interrupt le5els, etc. *lthough it is not "idely implemented, PCI supports ,('bit addressing. &nli4e the ,('bit data bus option "hich re1uires a longer connector "ith an additional 7;'bits of data signals, ,('bit addressing can be supported through the base 7;'bit connector. Dual Address C#cles are issued in "hich the lo" order 7;'bits of the address are dri5en onto the *<D719!E signals during the first address phase, and the high order 7;'bits of the address ?if non'8ero@ are dri5en onto the *<D719!E signals during a second address phase. The remainder of the transfer continues li4e a normal bus transfer. PCI defines support for both = /olt and 7.7 /olt signaling le5els. The PCI connector defines pin locations for both the = /olt and 7.7 /olt le5els. 3o"e5er, most early PCI systems "ere = /olt only, and did not pro5ide acti5e po"er on the 7.7 /olt connector pins. 25er time more use of the 7.7 /olt interface is expected, but add'in boards "hich must "or4 in older legacy systems are restricted to using only the = /olt supply. * #4eying# scheme is implemented in the PCI connectors to pre5ent inserting an add'in board into a system "ith incompatible supply 5oltage. *lthough used most extensi5ely in PC compatible systems, the PCI bus architecture is processor independent. PCI signal definitions are generic allo"ing the bus to be used in systems based on other processor families. PCI includes strict specifications to ensure the signal 1uality re1uired for operation at 77 and ,, 038. Components and add'in boards must include uni1ue bus dri5ers that are specifically designed for use in a PCI bus en5ironment. Typical TTL de5ices used in

pre5ious bus implementations such as I$* and .I$* are not compliant "ith the re1uirements of PCI. This restriction along "ith the high bus speed dictates that most PCI de5ices are implemented as custom *$ICs. The higher speed of PCI limits the number of expansion slots on a single bus to no more than 7 or (, as compared to , or J for earlier bus architectures. To permit expansion buses "ith more than 7 or ( slots, the PCI $I% has defined a PCI to PCI Bridge mechanism. PCI' to'PCI Bridges are *$ICs that electrically isolate t"o PCI buses "hile allo"ing bus transfers to be for"arded from one bus to another. .ach bridge de5ice has a #primary# PCI bus and a #secondary# PCI bus. 0ultiple bridge de5ices may be cascaded to create a system "ith many PCI buses.

$.0 PCI Si%nal escri!tions

Required Pins ------------| <===AD[31:0]=====>| <===!"#$[3:0]%===>| <---PAR---------->| | <----RA.$%------->| <---0RD1%-------->| <---&RD1%-------->| <---30OP%-------->| <---D$43$2%------>| ----&D3$2-------->| | <---P$RR%-------->| <---3$RR%-------->| | <---R$,%----------| ----650%--------->| | ----!2/---------->| ----R30%--------->| | | ---------------P!& !o)pliant De*i+e Optional Pins ------------| |<===AD[63:3 ]====> |<===!"#$[':(]%===> |<---PAR6(--------> |<---R$,6(%-------> |<---A!/6(%-------> | |<---2O!/%--------> | |----&50A%--------> |----&50#%--------> |----&50!%--------> |----&50D%--------> | |<---3#O%---------> |<---3DO5$--------> | |<---0D&----------|----0DO----------> |<---0!/----------|<---0.3----------|<---0R30%---------

----------------

$.1 System Pins

CLB Cloc$ pro5ides the timing reference for all transfers on the PCI bus. *ll PCI signals except reset and interrupts are sampled on the rising edge of the CLB signal. *ll bus timing specifications are defined relati5e to the rising edge. For most PCI systems the CLB signal operates at a maximum fre1uency of 77 038. :e5ision ;.1 of the PCI specification defined a ,, 038 operating mode, but this mode is not yet "idely

implemented. To operate at ,,038, both the PCI system and the PCI add'in board must be specifically designed to support the higher CLB fre1uency. *dd'in boards indicate to the system if they are ,, 038 capable through the 0,,.A signal. * ,, 038 system "ill supply a ,, 038 CLB if the add'in board supports it, and supply a default 77 038 CLB if the add'in board does not support the higher fre1uency. Li4e"ise, if a system is capable of pro5iding only a 77 038 cloc4, then a ,, 038 add'in board must be able to operate using the lo"er fre1uency. The minimum fre1uency of the CLB signal is specified at ! 38 permitting CLB to be #suspended# for po"er sa5ing purposes. :$TG %eset is dri5en acti5e lo" to cause a hard"are reset of a PCI de5ice. The reset shall cause a PCI de5ice)s configuration registers, state machines, and output signals to be placed in their initial state. :$TG is asserted and deasserted asynchronously to the CLB signal. It "ill remain acti5e for at least 1!! microseconds after CLB becomes stable.

$.2 &''ress an' ata Pins

*<D719!E Address and Data are multiplexed onto these pins. *<D719!E transfers a 7;'bit physical address during #address phases#, and transfers 7;'bits of data information during #data phases#. *n address phase occurs during the cloc4 follo"ing a high to lo" transition on the F:*0.G signal. * data phase occurs "hen both I:<HG and T:<HG are asserted lo". <uring "rite transactions the initiator dri5es 5alid data on *<D719!E during each cycle it dri5es I:<HG lo". The target dri5es T:<HG lo" "hen it is able to accept the "rite data. -hen both I:<HG and T:<HG are lo", the target captures the "rite data and the transaction is completed. For read transactions the opposite occurs. The target dri5es T:<HG lo" "hen 5alid data is dri5en on *<D719!E, and the initiator dri5es I:<HG lo" "hen it is able to accept the data. -hen both I:<HG and T:<HG are lo", the initiator captures the data and the transaction is completed. Bit 71 is the most significant *< bit. Bit ! is the least significant *< bit. C/B.D79!EG Bus Command and B#te &nables are multiplexed onto these pins. <uring the address phase of a transaction these signals carry the bus command that defines the type of transfer to be performed. $ee the table belo" for a list of 5alid bus command codes. <uring the data phase of a transaction these signals carry byte enable information. C/B.D7EG is the byte enable for the most significant byte ?*<D719;(E@ and C/B.D!EG is the byte enable for the lease significant byte ?*<DJ9!E@. The C/B.D79!EG signals are dri5en only by the initiator and are acti5ely dri5en through the all address and data phases of a transaction. C5B+7#809: Comman' Ty!es !!!! !!!1 !!1! Interrupt *c4no"ledge $pecial Cycle I/2 :ead

C5B+7#809: Comman' Ty!es !!11 !1!! !1!1 !11! !111 1!!! 1!!1 1!1! 1!11 11!! 11!1 111! 1111 P*: Parit# is e5en parity o5er the *<D719!E and C/B.D79!EG signals. .5en parity implies that there is an e5en number of )1)s on the *<D719!E, C/B.D79!EG, and P*: signals. The P*: signal has the same timings as the *<D719!E signals, but is delayed by one cycle to allo" more time to calculate 5alid parity. I/2 -rite :eser5ed :eser5ed 0emory :ead 0emory -rite :eser5ed :eser5ed Configuration :ead Configuration -rite 0emory :ead 0ultiple <ual *ddress Cycle 0emory :ead Line 0emory -rite and In5alidate

$.# Interface Control Pins

F:*0.G C#cle 'rame is dri5en lo" by the initiator to signal the start of a ne" bus transaction. The address phase occurs during the first cloc4 cycle after a high to lo" transition on the F:*0.G signal. If the initiator intends to perform a transaction "ith only a single data phase, then it "ill return F:*0.G bac4 high after only one cycle. If multiple data phases are to be performed, the initiator "ill hold F:*0.G lo" in all but the last data phase. The initiator signals its intent to perform a master initiated termination by dri5ing F:*0.G high during the last data phase of a transaction. <uring a target initiated termination the initiator "ill continue to dri5e F:*0.G lo" through the end of the transaction. I:<HG Initiator %ead# is dri5en lo" by the initiator as an indication it is ready to complete the current data phase of the transaction. <uring "rites it indicates the initiator has placed 5alid data on *<D719!E. <uring reads it indicates the initiator is ready to accept data on *<D719!E. 2nce asserted, the initiator holds I:<HG lo" until T:<HG is dri5en lo" to complete the transfer, or the target uses the $T2PG signal to terminate "ithout performing the data transfer. I:<HG permits the initiator to insert "ait states as needed to slo" the data transfer. T:<HG

(arget %ead# is dri5en lo" by the target as an indication it is read to complete the current data phase of the transaction. <uring "rites it indicates the target is ready to accept data on *<D719!E. <uring reads it indicates the target has placed 5alid data on the *<D719!E signals. 2nce asserted, the target holds T:<HG lo" until I:<HG is dri5en lo" to complete the transfer. T:<HG permits the target to insert "ait states as needed to slo" the data transfer. $T2PG Stop is dri5en lo" by the target to re1uest the initiator terminate the current transaction. In the e5ent that a target re1uires a long period of time to respond to a transaction, it may use the $T2PG signal to suspend the transaction so the bus can be used to perform other transfers in the interim. -hen the target terminates a transaction "ithout performing any data phases it is called a retr#. If one or more data phases are completed before the target terminates the transaction, it is called a disconnect. * retry or disconnect signals the initiator that it must return at a later time to attempt performing the transaction again. In the e5ent of a fatal error such as a hard"are problem the target may use $T2PG and <./$.LG to signal an abnormal termination of the bus transfer called a target abort. The initiator can use the target abort to signal system soft"are that a fatal error has been detected. L2CBG Loc$ may be asserted by an initiator to re1uest exclusi5e access for performing multiple transactions "ith a target. It pre5ents other initiators from modifying the loc4ed addresses until the agent initiating the loc4 can complete its transaction. 2nly a specific region ?a minimum of 1, bytes@ of the target)s addresses are loc4ed for exclusi5e access. -hile L2CBG is asserted, other non'exclusi5e transactions may proceed "ith addresses that are not currently loc4ed. But any non'exclusi5e accesses to the target)s loc4ed address space "ill be denied 5ia a retry operation. L2CBG is intended for use by bridge de5ices to pre5ent deadloc4s. I<$.L Initiali)ation De*ice Select is used as a chip select during during PCI configuration read and "rite transactions. I<$.L is dri5en by the PCI system and is uni1ue on a per slot basis. This allo"s the PCI configuration mechanism to indi5idually address each PCI de5ice in the system. * PCI de5ice is selected by a configuration cycle only if I<$.L is high, *<D19!E are #!!# ?indicating a type ! configuration cycle@, and the command placed on the C/B.D79!EG signals during the address phase is either a #configuration read# or #configuration "rite#. *<D1!9+E may be used to select one of up to eight #functions# "ithin the PCI de5ice. *<DJ9;E select indi5idual configuration registers "ithin a de5ice and function. <./$.LG De*ice Select is dri5en acti5e lo" by a PCI target "hen it detects its address on the PCI bus. <./$.LG may be dri5en one, t"o, or three cloc4s follo"ing the address phase. <./$.LG must be asserted "ith or prior to the cloc4 edge in "hich the T:<HG signal is asserted. 2nce <./$.LG has been asserted, it cannot be deasserted until the last data phase has completed, or the target issues a target abort. If the initiator ne5er recei5es an acti5e <./$.LG it terminates the transaction in "hat is termed a master abort.

$.$ &rbitration Pins (Initiator Only)

:.IG %e+uest is used by a PCI de5ice to re1uest use of the bus. .ach PCI de5ice has its o"n uni1ue :.IG signal. The arbiter in the PCI system recei5es the :.IG signals from each de5ice. It is important that this signal be tri'stated "hile :$TG is asserted to pre5ent a system hang. This signal is implemented only be de5ices capable of being an initiator. %ATG Grant indicates that a PCI de5ice)s re1uest to use the bus has been granted. .ach PCI de5ice has its o"n uni1ue %ATG signal from the PCI system arbiter. If a de5ice)s %ATG signal is acti5e during one cloc4 cycle, then the de5ice may begin a transaction in the follo"ing cloc4 cycle by asserting the F:*0.G signal. This signal is implemented only be de5ices capable of being an initiator.

$.* +rror ,e!ortin% Pins

P.::G Parit# &rror is used for reporting data parity errors during all PCI transactions except a #$pecial Cycle#. P.::G is dri5en lo" t"o cloc4 periods after the data phase "ith bad parity. It is dri5en lo" for a minimum of one cloc4 period. P.::G is shared among all PCI de5ices and is dri5en "ith a tri'state dri5er. * pull'up resistor ensures the signal is sustained in an inacti5e state "hen no de5ice is dri5ing it. *fter being asserted lo", P.::G must be dri5en high one cloc4 before being tri' stated to restore the signal to its inacti5e state. This ensures the signal does not remain lo" in the follo"ing cycle because of a slo" rise due to the pull'up. $.::G S#stem &rror is for reporting address parity errors, data parity errors during a $pecial Cycle, or any other fatal system error. $.::G is shared among all PCI de5ices and is dri5en only as an open drain signal ?it is dri5en lo" or tri'stated by PCI de5ices, but ne5er dri5en high@. It is acti5ated synchronously to CLB, but "hen released "ill float high asynchronously through a pull'up resistor.

$.- Interru!t Pins

IAT*G, IATBG, IATCG, IAT<G Interrupts are dri5en lo" by PCI de5ices to re1uest attention from their de5ice dri5er soft"are. They are defined as #le5el sensiti5e# and are dri5en lo" as an open drain signal. 2nce asserted, the IATxG signals "ill continue to be asserted by the PCI de5ice until the de5ice dri5er soft"are clears the pending re1uest. * PCI de5ice that contains only a single function shall use only IAT*G. 0ulti'function de5ices ?such as a combination L*A/modem add'in board@ may use multiple IATxG lines. * single function de5ice uses IAT*G. * t"o function de5ice uses IAT*G and IATBG, etc. *ll PCI de5ice dri5ers must be capable of sharing an interrupt le5el by chaining "ith other de5ices using the interrupt 5ector.

$.. Cache Su!!ort Pins (O!tional)

These pins are architected to permit cacheable memory to be implemented on a PCI bus. They transfer status information bet"een the bridge/cache and the target of the memory re1uest. If a PCI transaction results in a hit on a #dirty# cache line, the bridge/cache "ill signal #snoop bac4off# to the cacheable target. *s a result, the target "ill issue retries on all accesses to the modified cache line until the bridge/cache completes a "ritebac4 operation. The target "ill then permit the access to complete. These cache support pins are rarely if e5er implemented in today)s PCI systems. For performance reasons, cacheable memory is typically coupled 5ery closely "ith a host processor bus that runs at a higher fre1uency than PCI. $B2G Snoop Bac$off indicates a hit to a modified line "hen asserted. -hen $B2G is deasserted and $<2A. is asserted, it indicates a #CL.*A# snoop result. $<2A. Snoop Done indicates the status of the snoop for the current access. -hen deasserted, it indicates the result of the snoop is still pending. -hen asserted, it indicates the snoop is complete.

$./ &''itional Pins

P:$ATD19;EG Present signals are used for t"o purposes9 1@ to indicate that an add'in board is physically present, and ;@ to indicate the po"er re1uirements of an add'in board. These are static signals that are either grounded or left open on the add'in board. :efer to the follo"ing table for the encoding of these signals. P,S;T1: P,S;T2: &''1in Boar' Confi%uration 2pen %round 2pen 2pen 2pen %round Ao board present Board present, ;=- maximum Board present, 1=- maximum

%round %round Board present, J.=- maximum CLB:&AG Cloc$ %unning is an optional signal used to facilitate stopping of the CLB signal for po"er sa5ing purposes. CLB:&AG is intended only for the #mobile# en5ironment "here po"er consumption is critical. It is not defined on the PCI connector used for regular add'in boards. CLB:&AG is dri5en as an open drain signal. The PCI system dri5es CLB:&AG lo" "hen it is propagating a normal CLB signal. It releases CLB:&AG so it floats to a high le5el 5ia a pull'up resistor as a re1uest to stop the CLB for a specific PCI de5ice. The de5ice may then pulse CLB:&AG lo" to indicate to the system that it should continue to dri5e CLB, or allo" CLB:&AG to remain high as confirmation that CLB can be stopped. If the CLB has been stopped

and a PCI de5ice "ants to resume normal operation, it dri5es CLB:&AG lo" as a re1uest that the system should start dri5ing CLB again. 0,,.A ,,MH- &nable is left #open# or disconnected on add'in boards that support operation "ith a ,, 038 CLB, and grounded on add'in boards that support operation "ith only a 77 038 CLB. ,, 038 systems place a pull'up resistor on this signal to detect if the add'in board is ,, 038 capable. If the signal is high, a CLB "ith a maximum fre1uency of ,, 038 is supplied. If it is lo", a CLB "ith a maximum fre1uency of 77 038 is supplied. 77 038 systems attach this signal to ground. ,, 038 operation "ill ta4e place only if both the system and the add'in board support it.

$.0 -$1Bit Bus +2tension Pins (O!tional)

*<D,797;E Address and Data are multiplexed on the same pins and pro5ide 7; additional bits "hen operating in a ,('bit bus en5ironment. <uring data phases these bits transfer an additional 7;'bits of data "hen both :.I,(G and *CB,(G are asserted. <uring address phases, "hen a <ual *ddress Cycle is being issued and the :.I,(G signal is asserted, these bits transfer the upper 7;'bits of the address. C/B.DJ9(EG Bus Command and B#te &nables are multiplexed onto the same pins and pro5ide ( additional bits "hen operating in a ,('bit bus en5ironment. <uring data phases these bits transfer byte enables for the upper 7;'bits of the data bus ?*<D,797;E@ "hen both :.I,(G and *CB,(G are asserted. <uring address phases, "hen a <ual *ddress Cycle is being issued and the :.I,(G signal is asserted, these bits transfer the bus command. :.I,(G %e+uest ,. bit (ransfer is asserted lo" by the initiator to indicate it desires a ,('bit transfer. This signal is dri5en "ith the same timings as F:*0.G. *CB,(G Ac$nowledge ,. bit (ransfer is asserted lo" by a target as an indication that it has decoded its address as the target of the current access, and is capable of performing a ,('bit transfer. P*:,( Parit# /pper D0!%D is the e5en parity bit that protects *<D,797;E and C/B.DJ9(EG.

$.10 3T&45Boun'ary Scan Pins (O!tional)

PCI de5ices may optionally support KT*%/Boundary $can as defined in I... $tandard 11( .1, (est Access Port and Boundar# Scan Architecture. KT*% allo"s components installed on a PCI add'in board to be exhausti5ely tested by serially scanning test patterns through each component. The follo"ing signals are defined by the KT*% standard. If KT*% is not implemented by an add'in board, the T<I and T<2 signals must be connected to preser5e the scan path.

TCB (est Cloc$ T<I (est Data Input T<2 (est !utput T0$ (est Mode Select T:$TG (est %eset

*.0 PCI Bus Timin% ia%rams

*.1 ,ea' Transaction ,ea' Transaction
The follo"ing timing diagram illustrates a read transaction on the PCI bus9
!2/ -RA.$% AD !"#$% &RD1% 0RD1% D$43$2% 177 77 377 (77 877 677 '77 977 :77 77| |77| |77| |77| |77| |77| |77| |77| |77| 7777 777777777777 |77777777777777777777777777777777777| 77777 77777 77777 7777 7777777777 ----<77777>-----<77777>77777><7777><7777777777>-----Address Data1 Data Data3 77777 7777777777777777777777777777777777 ----<77777><7777777777777777777777777777777777>-----#us-!)d #$%;s 7777777777 77777 777777 |77777777777777777777777| |77777| 7777777777777777 77777 777777 |77777| |77777777777777777| 7777777777777777 777777 |77777|77777777777777777777777777777| |<--->|<--------->|<--------->|<--------->| Address Data Data Data P<ase P<ase P<ase P<ase |<--------------------------------------->| #us 0ransa+tion

The follo"ing is a cycle by cycle description of the read transaction9 Cycle 1 ' The bus is idle. Cycle ; ' The initiator asserts a 5alid address and places a read command on the C/B.G signals. This is the address phase. Cycle 7 ' The initiator tri'states the address in preparation for the target dri5ing read data. The initiator no" dri5es 5alid byte enable information on the C/B.G signals. The initiator asserts I:<HG lo" indicating it is ready to capture read data. The target asserts <./$.LG lo" ?in this cycle or the next@ as an ac4no"ledgment it has

positi5ely decoded the address. The target dri5es T:<HG high indicating it is not yet pro5iding 5alid read data. Cycle ( ' The target pro5ides 5alid data and asserts T:<HG lo" indicating to the initiator that data is 5alid. I:<HG and T:<HG are both lo" during this cycle causing a data transfer to ta4e place. The initiator captures the data. This is the first data phase. Cycle = ' The target deasserts T:<HG high indicating it needs more time to prepare the next data transfer. Cycle , ' The second data phase occurs as both I:<HG and T:<HG are lo". The initiator captures the data pro5ided by the target. Cycle J ' The target pro5ides 5alid data for the third data phase, but the initiator indicates it is not ready by deasserting I:<HG high. Cycle + ' The initiator re'asserts I:<HG lo" to complete the third data phase. The initiator captures the data pro5ided by the target. The initiator dri5es F:*0.G high indicating this is the final data phase ?master termination@. Cycle ' F:*0.G, *<, and C/B.G are tri'stated, as I:<HG, T:<HG, and <./$.LG are dri5en inacti5e high for one cycle prior to being tri'stated.

*.2 6rite Transaction

The follo"ing timing diagram illustrates a "rite transaction on the PCI bus9
!2/ -RA.$% AD !"#$% &RD1% 0RD1% D$43$2% 177 77 377 (77 877 677 '77 977 :77 77| |77| |77| |77| |77| |77| |77| |77| |77| 7777 777777777777777777777777 |77777777777777777777777| 77777 7777 7777 77777 7777777777777 ----<77777><7777><7777>77777><7777777777777>--------Address Data1 Data Data3 77777 7777 7777 7777777777777777777777 ----<77777><7777><7777><7777777777777777777777>-----#us-!)d #$-1 #$#$-3 7777777777 77777 777777 |77777777777| |77777777777777777| 7777777777 77777777777777777 777777 |77777777777| |77777| 7777777777777777 777777 |77777|77777777777777777777777777777| |<--->|<--->|<--->|<--------------------->| Address Data Data Data P<ase P<ase P<ase P<ase |<--------------------------------------->| #us 0ransa+tion

The follo"ing is a cycle by cycle description of the read transaction9 Cycle 1 ' The bus is idle. Cycle ; ' The initiator asserts a 5alid address and places a "rite command on the C/B.G signals. This is the address phase. Cycle 7 ' The initiator dri5es 5alid "rite data and byte enable signals. The initiator asserts I:<HG lo" indicating 5alid "rite data is a5ailable. The target asserts

<./$.LG lo" as an ac4no"ledgment it has positi5ely decoded the address ?the target may not assert T:<HG before <./$.LG@. The target dri5es T:<HG lo" indicating it is ready to capture data. The first data phase occurs as both I:<HG and T:<HG are lo". The target captures the "rite data. Cycle ( ' The initiator pro5ides ne" data and byte enables. The second data phase occurs as both I:<HG and T:<HG are lo". The target captures the "rite data. Cycle = ' The initiator deasserts I:<HG indicating it is not ready to pro5ide the next data. The target deasserts T:<HG indicating it is not ready to capture the next data. Cycle , ' The initiator pro5ides the next 5alid data and asserts I:<HG lo". The initiator dri5es F:*0.G high indicating this is the final data phase ?master termination@. The target is still not ready and 4eeps T:<HG high. Cycle J ' The target is still not ready and 4eeps T:<HG high. Cycle + ' The target becomes ready and asserts T:<HG lo". The third data phase occurs as both I:<HG and T:<HG are lo". The target captures the "rite data. Cycle ' F:*0.G, *<, and C/B.G are tri'stated, as I:<HG, T:<HG, and <./$.LG are dri5en inacti5e high for one cycle prior to being tri'stated.

-.0 PCI Connector Pinout

The follo"ing table illustrates the pinout definition for the PCI connector. The PCI specification defines t"o types of connectors that may be implemented at the system board le5el9 2ne for systems that implement = /olt signaling le5els, and one for systems that implement 7.7 /olt signaling le5els. In addition, PCI systems may implement either the 7;'bit or ,('bit connector. 0ost PCI buses implement only the 7;'bit portion of the connector "hich consists of pins 1 through ,;. *d5anced systems "hich support ,('bit data transfers implement the full PCI bus connector "hich consists of pins 1 through (. Three types of add'in boards may be implemented9 #= /olt add'in boards# include a 4ey notch in pin positions =! and =1 to allo" them to be plugged only into = /olt system connectors. #7.7 /olt add'in boards# include a 4ey notch in pin positions 1; and 17 to allo" them to be plugged only into 7.7 /olt system connectors. #&ni5ersal add'in boards# include both 4ey notches to allo" them to be plugged into either = /olt or 7.7 /olt system connectors. &ni5ersal boards must be able to adapt to operation at either signaling le5el. *< System +nvironment Pin Si'e B 1 ; 7 ( '1;/ TCB %round T<2 Si'e & T:$TG L1;/ T0$ T<I 1 ; 7 ( #.#< System +nvironment Pin Si'e B '1;/ TCB %round T<2 Si'e & T:$TG L1;/ T0$ T<I Comments 7;'bit start

*< System +nvironment Pin Si'e B = , J + L=/ L=/ IATBG IAT<G P:$AT1G 1! :eser5ed 11 P:$AT;G 1; %round 17 %round 1( :eser5ed 1= %round 1, CLB 1J %round 1+ :.IG 1 L=/ ?I/2@ ;! *<D71E ;1 *<D; E ;; %round ;7 *<D;JE ;( *<D;=E ;= L7.7/ ;, C/B.D7EG ;J *<D;7E ;+ %round ; *<D;1E 7! *<D1 E 71 L7.7/ 7; *<D1JE 77 C/B.D;EG 7( %round 7= I:<HG 7, L7.7/ Si'e & L=/ IAT*G IATCG L=/ :eser5ed L=/ ?I/2@ :eser5ed %round %round :eser5ed :$TG L=/ ?I/2@ %ATG %round :eser5ed *<D7!E L7.7/ *<D;+E *<D;,E %round *<D;(E I<$.L L7.7/ *<D;;E *<D;!E %round *<D1+E *<D1,E L7.7/ F:*0.G %round T:<HG = , J +

#.#< System +nvironment Pin Si'e B L=/ L=/ IATBG IAT<G P:$AT1G 1! :eser5ed 11 P:$AT;G 1; 17 Si'e & L=/ IAT*G IATCG L=/ :eser5ed L7.7/ ?I/2@ :eser5ed 7.7/ 4ey 7.7/ 4ey Comments

Connector Bey Connector Bey :eser5ed :$TG L7.7/ ?I/2@ %ATG %round :eser5ed *<D7!E L7.7/ *<D;+E *<D;,E %round *<D;(E I<$.L L7.7/ *<D;;E *<D;!E %round *<D1+E *<D1,E L7.7/ F:*0.G %round T:<HG

1( :eser5ed 1= %round 1, CLB 1J %round 1+ :.IG 1 L7.7/ ?I/2@ ;! *<D71E ;1 *<D; E ;; %round ;7 *<D;JE ;( *<D;=E ;= L7.7/ ;, C/B.D7EG ;J *<D;7E ;+ %round ; *<D;1E 7! *<D1 E 71 L7.7/ 7; *<D1JE 77 C/B.D;EG 7( %round 7= I:<HG 7, L7.7/

*< System +nvironment Pin Si'e B 7J <./$.LG 7+ %round 7 L2CBG (! P.::G (1 L7.7/ (; $.::G (7 L7.7/ (( C/B.D1EG (= *<D1(E (, %round (J *<D1;E (+ *<D1!E ( =! =1 %round Si'e & %round $T2PG 7.7/ $<2A. $B2G %round P*: *<D1=E L7.7/ *<D17E *<D11E %round *<D! E

#.#< System +nvironment Pin Si'e B 7J <./$.LG 7+ %round 7 L2CBG (! P.::G (1 L7.7/ (; $.::G (7 L7.7/ (( C/B.D1EG (= *<D1(E (, %round (J *<D1;E (+ *<D1!E ( 0,,.A =! %round =1 %round =; *<D!+E =7 *<D!JE =( L7.7/ == *<D!=E =, *<D!7E =J %round =+ *<D!1E = L7.7/ ?I/2@ ,! *CB,(G ,1 L=/ ,; L=/ Si'e & %round $T2PG 7.7/ $<2A. $B2G %round P*: *<D1=E L7.7/ *<D17E *<D11E %round *<D! E %round %round C/B.D!EG L7.7/ *<D!,E *<D!(E %round *<D!;E *<D!!E L7.7/ ?I/2@ :.I,(G L=/ L=/ Connector Bey Connector Bey ,7 :eser5ed ,( %round ,= C/B.D,EG ,, C/B.D(EG %round C/B.DJEG C/B.D=EG L7.7/ ?I/2@ 7;'bit end ,('bit spacer ,('bit spacer ,('bit start =/ 4ey =/ 4ey Comments

Connector Bey Connector Bey C/B.D!EG L7.7/ *<D!,E *<D!(E %round *<D!;E *<D!!E L=/ ?I/2@ :.I,(G L=/ L=/ Connector Bey Connector Bey

=; *<D!+E =7 *<D!JE =( L7.7/ == *<D!=E =, *<D!7E =J %round =+ *<D!1E = L=/ ?I/2@ ,! *CB,(G ,1 L=/ ,; L=/

,7 :eser5ed ,( %round ,= C/B.D,EG ,, C/B.D(EG

%round C/B.DJEG C/B.D=EG L=/ ?I/2@

*< System +nvironment Pin Si'e B ,J %round ,+ *<D,7E , *<D,1E J! L=/ ?I/2@ J1 *<D= E J; *<D=JE J7 %round J( *<D==E J= *<D=7E J, %round JJ *<D=1E J+ *<D( E J L=/ ?I/2@ +! *<D(JE +1 *<D(=E +; %round +7 *<D(7E +( *<D(1E += %round +, *<D7 E +J *<D7JE ++ L=/ ?I/2@ + *<D7=E ! *<D77E 1 %round ; :eser5ed 7 :eser5ed ( %round Si'e & P*:,( *<D,;E %round *<D,!E *<D=+E %round *<D=,E *<D=(E L=/ ?I/2@ *<D=;E *<D=!E %round *<D(+E *<D(,E %round *<D((E *<D(;E L=/ ?I/2@ *<D(!E *<D7+E %round *<D7,E *<D7(E %round *<D7;E :eser5ed %round :eser5ed

#.#< System +nvironment Pin Si'e B ,J %round ,+ *<D,7E , *<D,1E J! L7.7/ ?I/2@ J1 *<D= E J; *<D=JE J7 %round J( *<D==E J= *<D=7E J, %round JJ *<D=1E J+ *<D( E J L7.7/ ?I/2@ +! *<D(JE +1 *<D(=E +; %round +7 *<D(7E +( *<D(1E += %round +, *<D7 E +J *<D7JE ++ L7.7/ ?I/2@ + *<D7=E ! *<D77E 1 %round ; :eser5ed 7 :eser5ed ( %round Si'e & P*:,( *<D,;E %round *<D,!E *<D=+E %round *<D=,E *<D=(E L7.7/ ?I/2@ *<D=;E *<D=!E %round *<D(+E *<D(,E %round *<D((E *<D(;E L7.7/ ?I/2@ *<D(!E *<D7+E %round *<D7,E *<D7(E %round *<D7;E :eser5ed %round :eser5ed ,('bit end Comments

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