702075

TMS320DM6437 Evaluation Module
Technical Reference
2006
DSP Development Systems
Downloaded from Elcodis.com electronic components distributor
TMS320DM6437 Evaluation Module Technical Reference
509105-0001 Rev. C December 2006
SPECTRUM DIGITAL, INC. 12502 Exchange Drive, Suite 440 Stafford, TX. 77477 Tel: 281.494.4505 Fax: 281.494.5310 sales@spectrumdigital.com www.spectrumdigital.com
IMPORTANT NOTICE Spectrum Digital, Inc. reserves the right to make changes to its products or to discontinue any product or service without notice. Customers are advised to obtain the latest version of relevant information to verify that the data being relied on is current before placing orders. Spectrum Digital, Inc. warrants performance of its products and related software to current specifications in accordance with Spectrum Digitals standard warranty. Testing and other quality control techniques are utilized to the extent deemed necessary to support this warranty. Please be aware that the products described herein are not intended for use in life-support appliances, devices, or systems. Spectrum Digital does not warrant nor is Spectrum Digital liable for the product described herein to be used in other than a development environment. Spectrum Digital, Inc. assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does Spectrum Digital warrant or represent any license, either express or implied, is granted under any patent right, copyright, or other intellectual property right of Spectrum Digital, Inc. covering or relating to any combination, machine, or process in which such Digital Signal Processing development products or services might be or are used. WARNING This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures necessary to correct this interference.
Copyright 2006 Spectrum Digital, Inc.
Contents
Introduction to the DM6437 Evaluation Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Provides you with a description of the DM6437 Evaluation Module, key features, and block diagram. 1.1 Key Features .......................................................... 1.2 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Configuration Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 Power Supply ......................................................... 1.7 Power Measurement ................................................... 2 Board Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Describes the operation of the major board components on the DM6437 Evaluation Module. 2.1 EMIF Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1 DDR2 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.2 Flash, NAND Flash, SRAM Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Peripheral Interfaces ................................................. 2.2.1 VLYNQ Interface .................................................. 2.2.2 UART Interface .................................................. 2.2.3 CAN Interface ..................................................... 2.3 Video Interfaces ........................................................ 2.3.1 Input Video Port Interfaces ............................................. 2.3.2 On Chip Video Output DACs ............................................ 2.4 AIC33 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.1 Audio PLL/VCXO Circuit/PLL1705 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Ethernet Interface ....................................................... 2.6 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.1 I/O Expanders ........................................................ 2C EEPROM ........................................................ 2.6.2 I 2.7 S/PDIF Analog, and Optical Interfaces .................................... 2.8 Daughter Card Interface ................................................ 2.9 DM6437 Core CPU Clock .............................................. 2.10 DM6437 Core Voltage Select ..........................................
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Physical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Describes the physical layout of the DM6437 Evaluation Module and its connectors. 3.1 Board Layout ........................................................ 3.2 Connectors ........................................................ 3.2.1 J1, DAC A Video Out ................................................. 3.2.2 J2, DAC B Video Out .................................................. 3.2.3 J3, DAC C Video Out .................................................. 3.2.4 J4, DAC A Video Out .................................................. 3.2.5 J5, Video In .......................................................... 3.2.6 J10, S/PDIF Out ..................................................... 3.2.7 J16, +5V Input ....................................................... 3.2.8 J20, Mini PCI Interface ................................................ 3.2.9 J501, Embedded Mini USB Emulation Interface ............................ 3.2.10 P1, Video Out ...................................................... 3.2.11 P2, Video In ....................................................... 3.2.12 P3, Ethernet Interface ............................................... 3.2.13 P4, PCI Interface ................................................... 3.2.14 P7, CAN Connector ................................................. 3.2.15 P8, RS-232 UART .................................................. 3.2.16 P10, Stereo Line In ................................................ 3.2.17 P11, Microphone In ................................................. 3.2.18 P12, Headphone Out .............................................. 3.2.19 P13, Stereo Line Out ................................................ 3.2.20 P14, S/PDIF Out ................................................... 3.2.21 DC_P1, Memory/Video Expansion ..................................... 3.2.22 DC_P2, Peripheral Expansion ........................................ 3.2.23 DC_P3, VLYNQ Connector .......................................... 3.3 Jumpers ............................................................ 3.3.1 JP1 Jumper ......................................................... 3.3.2 JP2 Jumper ......................................................... 3.3.3 JP3 Jumper ......................................................... 3.3.4 JP4 Jumper ........................................................ 3.4 LEDs ................................................................ 3.5 Switches ............................................................. 3.5.1 SW1, Bootload Mode Selections ....................................... 3.5.2 SW2, Bootload Configuration Select .................................... 3.5.3 SW3, EMDATA Select ................................................ 3.5.4 SW4, 4 Position User Readable ........................................ 3.5.5 SW5, Power On Reset Switch .......................................... 3.5.6 SW6, Reset Switch .................................................. 3.5.7 SW7, Slide Switch .................................................. 3.6 Test Points ........................................................ A Schematics .............................................................. Contains the schematics for the DM6437 Evaluation Module B Mechanical Information .................................................. Contains the mechanical information about the DM6437 Evaluation Module
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About This Manual This document describes the board level operations of the DM6437 Evaluation Module (EVM). The EVM is based on the Texas Instruments TMS320DM6437 Processor. The DM6437 Evaluation Module is a table top card that allows engineers and software developers to evaluate certain characteristics of the DM6437 processor to determine if the processor meets the designers application requirements. Evaluators can create software to execute on board or expand the system in a variety of ways. Notational Conventions This document uses the following conventions. The DM6437 Evaluation Module will sometimes be referred to as the DM6437 EVM or EVM. Program listings, program examples, and interactive displays are shown in a special italic typeface. Here is a sample program listing. equations !rd = !strobe&rw;
Information About Cautions This book may contain cautions. This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software, or hardware, or other equipment. The information in a caution is provided for your protection. Please read each caution carefully.
Related Documents, Application Notes and User Guides Information regarding this device can be found at the following Texas Instruments website: http://www.ti.com
Table 1: Manual History Revision A B Alpha Release Beta Release History
Table 2: Board History Revision A B Alpha Release Beta Release History
Chapter 1 Introduction to the DM6437 EVM
Chapter One provides a description of the DM6437 EVM along with the key features and a block diagram of the circuit board.
Topic
1.1 1.2 1.3 1.4 1.5 1.6 1.7 Key Features Functional Overview Basic Operation Memory Map Configuration Switch Settings Power Supply Power Measurement
Page
1-2 1-3 1-4 1-5 1-6 1-6 1-6
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Spectrum Digital, Inc

1.1 Key Features The DM6437 EVM is a PCI based or standalone development platform that enables users to evaluate and develop applications for the TI DaVinciTM processor family. Schematics, list of materials, and application notes are available to ease hardware development and reduce time to market.
Figure 1-1, DM6437 EVM The EVM comes with a full complement of on board devices that suit a wide variety of application environments. Key features include: A Texas Instruments DM6437 processor operating up to 600 Mhz. 1 TVP5146M2 video decoder, supports composite or S video 4 video DAC outputs - component, RGB, composite (3 populated) 128 Mbytes of DDR2 DRAM UART, CAN I/O Interfaces 16 Mbytes of non-volatile Flash memory, 64 Mbytes NAND Flash, 2 Mbytes SRAM AIC33 stereo codec I2C Interface with onboard eeprom and expanders 10/100 MBS Ethernet Interface Configurable boot load options Embedded JTAG emulation interface 4 user LEDs and 4 position user switch 1-2 DM6437 EVM Technical Reference

Single voltage power supply (+5V) Expansion connectors for daughter card use VLYNQ Interface S/PDIF Interface, analog, and optical 1.2 Functional Overview of the DM6437 EVM
DAC Out
1 2 3 4
DIP LEDs NAND Flash
RST
POR
ENET RJ45
Ext JTAG
USB EMU
CAN
RS-232
DDR2
DDR2
SRAM
DAC B DAC C DAC D
DC_P1
EMIF
SVHS OUT SVHS IN Video IN 1234
AEM2 AEM1 AEM0 AEAW2
NOR Flash
BM0 BM1 BM2 BM3 FASTB
32
DC_P2
PCI Connector
Figure 1-2, Block Diagram DM6437 EVM The DM6437 on the EVM interfaces to on-board peripherals through integrated device interfaces and a 8-bit wide EMIF bus. The DDR2 memory is connected to its own dedicated 32 bit wide bus. The EMIF bus is jumper selectable to be connected to the Flash, SRAM, NAND, and daughter card expansion connectors which are used for add-on boards. On board video decoder and on chip encoders interface video streams to the DM6437 processor. One TVP5146M2 decoder and 4 on chip DAC channels are standard on the EVM (only 3 output connectors are populated so that the board can fit in a PCI slot). On screen display functions are implemented in software on the DM6437 processor. An on-board AIC33 codec allows the DSP to transmit and receive analog audio signals. The I2C bus is used for the codec control interface, while the McBSP controls the audio stream. Signal interfacing is done through 3.5mm audio jacks that correspond to microphone input, line input, line output, and headphone outputs. The EVM includes 4 user LEDs, and 4 position user DIP switch which can be used to provide the user with interactive feedback. These interfaces are implemented via I2C expanders.
PWR
DAC A
UART/CAN Switches ENET PHY Embedded JTAG Emulator MIC IN LINE IN LINE OUT HP Out JTAG McBSP0 SPI ROM
UARTs MII
AIC33 Codec
DM6437 Video Port PCI
McBSP1 or McASP0
1.8V Supply S/PDIF
(optical)
1234567
Video Decoder
I2C Bus
VLNQ Mini PCI
1.2V Core Supply S/PDIF 3.3V I/O Supply
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VLYNQ, and ethernet MAC interfaces are integrated peripherals on the DM6437 processor exploiting its system on a chip architecture. VLYNQ is available when the PCI is not used. An included 5V external power supply is used to power the board. On-board switching voltage regulators provide the +1.2V CPU core voltage and +3.3V for peripherals and +1.8V DDR2 memory. The board is held in reset until these supplies are within operating specifications. Code Composer communicates with the EVM through an embedded emulator or via the 14 pin external JTAG connector.
1.3 Basic Operation The EVM is designed to work with TIs Code Composer Studio development. Code Composer communicates with the board through the embedded emulator or an external JTAG emulator. To start, follow the instructions in the Quick Start Guide to install Code Composer. This process will install all of the necessary development tools, documentation and drivers. Detailed information about the EVM including examples and reference material is available on the EVMs CD-ROM.
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DM6437 EVM Technical Reference

1.4 Memory Map The DaVinci family of processors have a large byte addressable address space, some limitations to byte addressing are determined by peripheral interconnection to the DM6437 device. Program code and data can be placed anywhere in the unified address space. Addresses are multiple sizes depending on hardware implementation. Refer to the appropriate device data sheets for more details. The memory map shows the address space of a DM6437 processor on the left with specific details of how each region is used on the right. By default, the internal memory sits at the beginning of the address space. Portions of memory can be remapped in software as L2 cache rather than fixed RAM. The part incorporates a dual EMIF interface. One dedicated EMIF directly interfaces to the DDR2 memory. The Flash, NAND Flash, or SRAM are mapped into CS2 space and selectable via JP2. When CS2 is used for daughter card interfacing JP2 must be set appropriately. Address 0x10800000 0x42000000 CS2 0x44000000 CS3 0x46000000 CS4 0x48000000 CS5 0x4C000000 VLNQ 0x80000000 DDR Figure 1-3, Memory Map, DM6437 EVM DM6437 EVM Cache/RAM
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1.5 Configuration Switch Settings The EVM has a two configuration switches that allow users to control the operational state of the processor when it is released from reset. The configuration switches are labeled SW1 and SW2 on the EVM board. Switch SW1 configures the boot mode that will be used when the DSP starts executing. By default the switches are configured to EMIF boot (out of 8-bit Flash). The DM6437 EVM only supports little endian mode and is not configurable. Refer to section 3.5.1 for the boot load options using switch SW1.
1.6 Power Supply The EVM operates from a single +5V external power supply connected to the main power input (J16), a 2.5 MM. barrel-type plug. Internally, the +5V input is converted into +1.2V, +1.8V and +3.3V using Texas Instruments swift voltage regulators. The +1.2V supply is used for the DSP core while the +3.3V supply is used for the DSP's I/O buffers and other chips on the board. The +1.8 volt supply is used for DM6437 DDR2 interface, and DDR2 memory. There are three power test points on the EVM; TP23, TP34, and TP38. These test points provide a convenient mechanism to check the EVMs multiple power supplies. The table below shows the voltages for each test point and what the supply is used for. Table 1: Power Test Points Test Point TP23 TP34 TP38 Voltage +1.2 V +3.3V +1.8 V Voltage Use DM6437 Core DSP I/O and logic DDR2 Memory, DSP I/O, and logic
1.7 Power Measurement The EVM supports power test points to allow measurement of the various power rails on the DM6437 device. Series resistors are used in the devices power domains thereby measuring the voltage across these resistors. The current can be calculated via V = I * R. Refer to the test point section in chapter 3 for detailed information on measuring current on the DM6437 device.
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Chapter 2 Board Components
This chapter describes the operation of the major board components on the DM6437 EVM.
Topic
2.1 2.1.1 2.1.2 2.2 2.2.1 2.2.2 2.2.3 2.3 2.3.1 2.3.2 2.4 2.4.1 2.5 2.6 2.6.1 2.6.2 2.7 2.8 2.9 2.10 EMIF Interfaces DDR2 Memory Interface Flash, NAND Flash, SRAM Memory Interface Peripheral Interfaces VLYNQ Interface UART Interface CAN Interface Video Interfaces Input Video Port Interfaces On Chip Video Output DACs AIC33 Interface Audio PLL/VCXO Circuit/PLL1705 Clock Generator Ethernet Interface I2C Interface I/O Expanders I2C EEPROM S/PDIF Analog, and Optical Interfaces Daughter Card Interface DM6437 Core CPU Clock DM6437 Core Voltage Select
Page
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2-1

2.1 EMIF Interfaces A separate 8 bit EMIF with multiple chip selects divide up the address space and allow for asynchronous accesses on the EVM. On board the CS2 is used for Flash, NAND Flash, or SRAM.
2.1.1 DDR2 Memory Interface The DM6437 device incorporates a dedicated 32 bit wide DDR2 memory bus. The EVM uses two 512 megabit 16 bit wide memories on this bus, for a total of 128 megabytes of memory for program, data, and video storage. The internal DDR controller uses a PLL to control the DDR memory timing. The interface supports rates up to 166 Mhz., and is clocked on differential edges for optimal performance. Memory refresh for DDR2 is handled automatically by the DM6437 internal DDR controller.
2.1.2 Flash, NAND Flash, SRAM Memory Interface The DM6437 has 16 megabytes of NOR Flash, or 64 megabytes of NAND Flash, or 2 megabyte of SRAM memory mapped into the CS2 space. This NOR Flash memory, and NAND Flash memory are used primarily for boot loading. SRAM is used for debugging application code. The CS2 space is configured as 8 bits wide on the DM6437 EVM for NOR Flash, SRAM, or NAND flash usage.
2.2 Peripheral Interfaces The DM6437 has several peripheral interfaces which allow the user to interface to external devices. These interfaces are outlined in the following sections.
2.2.1 VLYNQ Interface The DM6437 brings its internal VLYNQ interface out to a mini PCI connector J20 and small 20 pin connector DC_P3. The VLYNQ interface is multiplexed on the PCI/EM bus and this bus must be reconfigured after boot up to support VLYNQ. A multiplexer is used to minimize board layout stubs and allow as direct as possible interface for the VLYNQ signals. VLYNQ is not operational if the board is used in a PCI slot.
2.2.2 UART Interface The internal UART0 on the DM6437 device is driven to connector P8. The UARTs interface is routed to a Texas Instruments MAX3221 RS-232 line driver prior to being brought out to a male DB-9 connector, P8. The on board UART signals can be disabled by pulling the RS232_ENABLEn signal high via the daughter card connectors.
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2.2.3 CAN Interface The internal CAN controller on the DM6437 device is driven to connector P7. The controller is routed to a Texas Instruments SN65HVD235 CAN controller prior to being routed to female DB-9 connector, P7. The on board CAN signals can be disabled by pulling CAN_ENABLEn high via the daughter card connector.
2.3 Video Interfaces The DM6437 EVM has video input and output ports to support a variety of user applications. These are discussed in the two sections below.
2.3.1 Input Video Port Interfaces The DM6437 EVM supports video capture via the devices internal video ports. A Texas Instruments TVP5146M2 is used to decode composite video or S-video inputs into the device. P2 is used for the S-video inputs and J5 for the composite inputs on the EVM. User inputs can be driven via daughter card connector DC_P1 when the on board CBTs are disabled by driving control TVP5146_ENABLEn signal high on DC_P1.
2.3.2 On Chip Video Output DACs The DM6437 incorporates 4 output DACs to interface to various output standards. The DACs are buffered via opamps and driven to four RCA jacks, J1-J4. The outputs of the DACs are programmable to support composite video, component video, or RGB. S-video output is available from connector P1. This connector is driven by video DACs B and C from the DM6437. Video DAC B is the chroma and video DAC C is the luma.
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2.4 AIC33 Interface The EVM uses a Texas Instruments TLV320AIC33 stereo codec for input and output of audio signals. The codec samples analog signals on the microphone or line inputs and converts them into digital data so it can be processed by the DSP. When the DSP is finished with the data it uses the codec to convert the samples back into analog signals on the line output so the user can hear the output. The codec communicates using two serial channels, one to control the codecs internal configuration registers and one to send and receive digital audio samples. The I2C bus is used as the unidirectional control channel. The control channel is generally only used when configuring the codec, it is typically idle when audio data is being transmitted, The default configuration is to use the McBSP is used as the bi-directional data channel. However, optionally the McASP can be used to drive the data channel. Data channel selection is controller via an on board I2C expander. All audio data flows through the data channel. Many data formats are supported based on the three variables of sample width, clock signal source and serial data format. The EVM examples generally use a 16-bit sample width with the codec in master mode so it generates the frame sync and bit clocks at the correct sample rate without effort on the DSP side. The codec has a programmable clock from a PLL1705 PLL device. The default system clock is 18.432 Mhz. The internal sample rate generate subdivides the 18.432 MHz clock to generate common frequencies such as 48KHz and 8KHz. The sample rate is set by a codec register. The figure below shows the codec interface on the DM6437 EVM.
AIC33 Codec I2C

SCL SDA Control I2C Format Digital SCL SDA Control Registers Analog LINE OUT MIC IN
LINE IN
McASP or McBSP
AXR[0] AXR[1] ACLKR ACLKX AFSR AFSX DX DR CLKR CLKX FSR FSX I2S Format DOUT DIN BCLK WCLK ADC MIC IN LINE IN DAC LINE OUT HP OUT HP OUT
Figure 2-2, DM6437 EVM CODEC INTERFACE
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2.4.1 Audio PLL/VCXO Circuit/PLL1705 Clock Generator The DM6437 EVM implements a multiple PLL clock generator for creating the Audio clocks for the board. In streaming video applications the audio and video sequences can lose synchronization. The DM6437 uses a VCXO interpolation circuit to incrementally speed up or slow down the STCLK input to allow for this synchronization to remain locked. The PWM1 and timer inputs on DM6437 are used to control this feature. The PWM0 pin drives a PICX100-27W Voltage Controlled Oscillator which is and fed back into the timer input pin. The STCLK is also a source clock for the PLL1705 programmable PLL device. This device creates the clocks for the AIC33 Codec, daughter card VIDCLK an AUDIOCLK. The PLL1705 is programmable via an I2C and Expander U13. Software sequencing on the I/O expander is required to interface correctly to the PLL1705s programmable inputs. The diagram below is a simplified diagram of this clocking scheme. To I/O Expander P L L M S P P L L L L MM CD
PLL1705 DM6437 XT1
SCK03 SCK02 SCK01 SCK00 MCK02 MCK01
AUDIO_CLK
VID_CLK
TIMER PWM1 IN
STCLK VCXO Circuit Using PICX100-27
Figure 2-3, Audio PLL/VCXO Circuit/PLL1705 Clock Generator
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2.5 Ethernet Interface The DM6437 integrates an ethernet MAC on chip. This interface is routed to the PHY via CBT switches. The EVM uses an Micrel KS8001L PHY. The 10/100 Mbit interface is isolated and brought out to a RJ-45 standard ethernet connector, P3. The PHY directly interfaces to the DM6437. The ethernet address is stored in the I2C serial ROM during manufacturing. The RJ-45 has 2 LEDs integrated into its connector. The LEDs are green and yellow and indicate the status of the ethernet link. The green LED, when on, indicates link and when blinking indicates link activity. The yellow LED, when illuminated, indicates full duplex mode.
2.6 I2C Interface The I2C bus on the DM6437 is ideal for interfacing to the control registers of many devices. On the DM6437 EVM the I2C bus is used to configure the video decoder, stereo Codec, I/O expanders. An I2C ROM is also interfaced via the serial bus. The format of the bus is shown in the figure below. Start Slave Address W ACK Sub Address ACK-S Data ACK-S Stop Write Sequence Start Slave Address R Data STOP Read Sequence Figure 2-4, I2C Bus Format The addresses of the on board peripherals are shown in the table below. Table 1: I2C Memory Map Device TVP5146M2 PCF 8574A PCF 8574A PCF 8574A PCF8574A TLV320AIC33 24WC256 Address 0x5D 0x38 0x39 0x3A 0x3B 0x1B 0x50 R/W R/W R/W R/W R/W R/W R/W R/W Device U50 U10 U11 U13 U64 U43 U25 Function Video Decoder User Input User LEDs PLL, User I/O User I/O CODEC I2C EEPROM
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2.6.1 I/O Expanders The DM6437 EVM uses four I2C expanders to handle various bit I/O functions. Each of these is an 8 bit I/O expander, a PCF8574A. At Power Up Reset the expanders are initialized to 0xFF, all ones. The functions for each of the I/O expanders are shown in the tables below. Table 2: U10 I/O Expander Pin Number P0 P1 P2 P3 P4 P5 P6 P7 Function JP1 NTSC/PAL Select SW7 Slide Switch Reserved Reserved SW4-1 SW4-2 SW4-3 SW4-4 Decription Read only video mode,1=NTSC,0=PAL Read only slide switch None None Read only user switch Read only user switch Read only user switch Read only user switch
Table 3: U11 I/O Expander Pin Number P0 P1 P2 P3 P4 P5 P6 P7 Function User LED DS1 User LED DS2 User LED DS3 User LED DS4 VLYNQ Reset Reserved User I/O DC_P2 User I/O DC_P2 Description 0=Turns LED on, 1=Turns LED off 0=Turns LED on, 1=Turns LED off 0=Turns LED on, 1=Turns LED off 0=Turns LED on, 1=Turns LED off 0=Removes Reset, 1=Applies Reset None To daughter card, DC_P2 Pin 81 To daughter card, DC_P2 Pin 82
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Table 4: U13 I/O Expander Pin Number P0 P1 P2 P3 P4 P5 P6 P7 Function User I/O User I/O User I/O User I/O PLL -SR PLL - FS2 PLL - FS1 PLL-CSEL Mode RW RW RW RW W W W W Description Daughter Card, DC_P2 Pin 87 Daughter Card, DC_P2 Pin 88 Daughter Card, DC_P2 Pin 85 Daughter Card, DC_P2 Pin 84 Write PLL1705 SR Pin Write PLL1705 FS2 Pin Write PLL1705 FS1 Pin Write PLL1705 CSEL Pin
Table 5: U64 I/O Expander Pin Number P0 P1 P2 P3 P4 P5 P6 P7 Function McBSP_Enable to AIC23 McASP_Enable to AIC23 SPDIF Enable Reserved Reserved Reserved Reserved Core Voltage Select Description * 1=Enable, 0=Disable * 0=Enable, 1=Disable * 0=Enable, 1=Disable None None None None 0 = 1.05 Volt, 1 = 1.2 Volt
* only one should be enabled at a time
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2.6.2 I2C EEPROM The DM7436 EVM incorporates an I2C eeprom that can be used for booting or general purpose storage. This eeprom is also used to store the ethernet MAC address and the boards revision. The MAC address is also labeled on the board. Care should be taken not to erase these items when user information is stored in the eeprom. Spectrum Digital uses addresses 0x7F00 to 0x7FFF for manufacturing information. This information is shown in the table below. Table 6: DM6437 MAC Addresses Address 0x7F00 0x7F01 0x7F02 0x7F03 0x7F04 0x7F05 0x7F06 0x7F07 Contents EMAC Address 0 (most significant) EMAC Address 1 EMAC Address 2 EMAC Address 3 EMAC Address 4 EMAC Address 5 Reserved Board Revision
2.7 S/PDIF Analog, and Optical Interfaces The McBSPs FSR pin on the DM6437 can be configured to operate as a S/PDIF transmitter. The DM6437 EVM supports both analog and optical interfaces. The analog S/PDIF output pin is routed to a driver and filter circuit before being output on J10. I2C Expander U64 output P2 is used to enable the S/PDIF interface. When S/PDIF is selected on the expamder (P2=0), the McASP enable should be disabled and the McBSP enable should be disabled.Another driver is used to interface the optical transmitter P14. When the S/PDIF interface is enabled the TLV320AIC33 codec is disabled, the WCLK should be disabled prior to enabling the S/PDIF output. The McBSP interface can be disabled for daughter card use by pulling the AIC_ENABLEn signal high from the daughter card connector.
2-9

2.8 Daughter Card Interfaces The EVM provides expansion connectors that can be used to accept plug-in daughter cards. The daughter card allows users to build on their EVM platform to extend its capabilities and provide customer and application specific I/O. The expansion connectors are for all major interfaces including memory, peripherals, and video expansion. The pin outs for this interface are documented in Section 3. The connectors provide access to the DSPs EMIF signals to interface with memories and memory mapped devices. The video capture port is brought out to the daughter card interface. Several signals are used to disable the on board video peripherals so that they can be used by the expansion connector. The table below indicates the operation of these signals. Table 7: Daughter Card Interface Signal AIC33_ENABLEn CI_EMA_ENABLEn MEM_EMD7-0_ENABLEn VIC_TINPOL_ENABLEn ENET_ENABLEn CAN_ENABLEn RS232_ENABLEn TVP5146_ENABLEn Function Disconnects CPU from on board codec Disables CI0 to CI7 from upper on board EMIF address lines Disables CPU from on board data bus Disable CPU TINPOL pin from on board use Disconnects CPU from on board ethernet PHY Disconnects CPU from on board CAN Disconnects CPU from on board UART Disconnects CPU from on board video decoder
Other than the buffering, most daughter card signals are not modified on the board.
2.9 DM6437 Core CPU Clock The DM6437 EVM uses a 27 Megahertz crystal to generate the input clock. The DM6437 has an internal PLL which can multiply the input clock to generate the internal clock. The PLL multiplier is set via software on the DM6437 device.
2.10 DM6437 Core Voltage Select The DM6437 EVM has the ability to adjust the core voltage between 1.2 volts and 1.05 volts. an I/O expander is used to control this I2C feature.
2-10
Chapter 3 Physical Description
This chapter describes the physical layout of the DM6437 EVM and its interfaces.
Topic
3.1 3.2 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.2.7 3.2.8 3.2.9 3.2.10 3.2.11 3.2.12 3.2.13 3.2.14 3.2.15 3.2.16 3.2.17 3.2.18 3.2.19 3.2.20 3.2.21 3.2.22 3.2.23 Board Layout Connectors J1, DAC A Video Out J2, DAC B Video Out J3, DAC C Video Out J4, DAC D Video Out J5, Video In J10, S/PDIF Out J16, +5V Input J20, Mini PCI Interface J501, Embedded Mini USB Emulation Interface P1, Video Out P2, Video In P3, Ethernet Interface P4, PCI Connector P7, CAN Connector P8, RS-232 UART P10, Stereo Line In P11, Microphone In P12, Headphone Out P13, Stereo Line Out P14, S/PDIF Out (Optical) DC_P1, Memory/Video Expansion DC_P2, Peripheral Expansion DC_P3, VLYNQ Connector
Page
3-3 3-4 3-5 3-5 3-5 3-6 3-6 3-7 3-7 3-8 3-9 3-9 3-10 3-10 3-11 3-13 3-15 3-15 3-15 3-15 3-16 3-16 3-17 3-18 3-19
3-1
Topic
3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.4 3.5 3.5.1 3.5.2 3.5.3 3.5.4 3.5.5 3.5.6 3.5.7 3.6 Jumpers JP1 Jumper JP2 Jumper JP3 Jumper JP4 Jumper LEDs Switches SW1, Bootload Mode Selections SW2, Bootload Configuration Select SW3, EMIF Data Select SW4, 4 Position User Readable SW5, Power On Reset Switch SW6, Reset Switch SW7, Slide Switch Test Points
Page
3-19 3-20 3-20 3-21 3-21 3-21 3-22 3-22 3-23 3-23 3-23 3-23 3-23 3-24 3-25
3-2

3.1 Board Layout The DM6437 EVM is a 8.75 x 4.5 inch (210 x 115 mm.) ten (10) layer printed circuit board which is powered by an external +5 volt only power supply. Figure 3-1 shows the layout of the DM6437 EVM. P10 P11 P13 P8 J5 J10 P14 P12 J16 DS5
P7 DC_P3 DS501 J20 J501 J6
P3 SW3 SW7 JP4 SW5 SW6 JP3 JP2 JP1 SW4 DS1-DS4 J1 P1 P2 J4 J5 J2 J3 Figure 3-1, DM6437 EVM, Interfaces Top Side 3-3 SW2 SW1 P4 DC_P1 DC_P2

3.2 Connectors The EVM has twenty three (23) connectors providing interfaces to various peripherals. These connectors are described in the following sections. Table 1: Connectors
Connector J1 J2 J3 J4 J5 J6 J10 J16 J20 J501 P1 P2 P3 P4 P7 P8 P10 P11 P12 P13 P14 DC_P1 DC_P2 DC_P3 Size RCA RCA RCA RCA RCA 14 RCA 2.5 mm 2 x 62 Mini USB 4 Pin DIN 4 Pin DIN RJ-45 PCI 9 Pin D-sub 9 Pin D-sub 3.5 mm 3.5 mm 3.5 mm 3.5 mm Optical 2x50 2x45 2x10 Function DAC A * DAC B DAC C DAC D Video In External Emulation Header S/PDIF Out +5V In Mini PCI Interface Embedded USB Emulation Interface S-Video Out S-Video In Ethernet PCI CAN RS-232 UART Stereo Line In Microphone In Headphone Out Stereo Line Out S/PDIF Out Expansion Expansion Expansion
* Not populated
3-4

3.2.1 J1, DAC A Video Out J1 is an RCA jack used to interface to DAC A of the DM6437 to a video device. This connector is driven directly by the VPSS back end via an opamp. This connector is not installed for clearance reasons when using the PCI bus. The pinout of this connector is shown below.
Shield (ground) Signal Output Figure 3-2, J1, RCA Jack
3.2.2 J2, DAC B Video Out J2 is an RCA jack used to interface to DAC B of the DM6437 to a video device. This connector is driven directly by the VPSS back end via an opamp. This connector is not installed for clearance reasons when using the PCI bus. The pinout of this connector is shown below.
3.2.3 J3, DAC C Video Out J3 is an RCA jack used to interface to DAC C of the DM6437 to a video device. This connector is driven directly by the VPSS back end via an opamp. This connector is not installed for clearance reasons when using the PCI bus. The pinout of this connector is shown below.
3-5

3.2.4 J4, DAC D Video Out J1 is an RCA jack used to interface to DAC D of the DM6437 to a video device. This connector is driven directly by the VPSS back end via an opamp. This connector is not installed for clearance reasons when using the PCI bus. The pinout of this connector is shown below.
3.2.5 J5, Video In J5 is an RCA jack used as a video input to the TVP5146M2 video decoder. This connector brings in a video signal to the TVP5146M2. Do NOT plug into this connector with the power on. The figure below shows this connector as viewed from the card edge. Pin 2, Shield (ground) Pin 1, Signal Input Figure 3-6, J5, Video In RCA Jack
Table 2: J5, Video In, RCA Jack Pin # 1 2 Signal Name Pin 8, TVP5146M2 GND
3-6

3.2.6 J10, S/PDIF Out J10 is an RCA jack used as an analog output from the McBSP FSR signal on the DSP. This connector brings out the SPDIF signal. Do NOT plug into this connector with the power on. The figure below shows this connector as viewed from the card edge. Pin 2, Shield (ground) Pin 1, Signal Output Figure 3-7, J10, S/PDIF Out, RCA Jack
Table 3: J10, S/PDIF, RCA Jack Pin # 1 2 Signal Name S/PDIF Analog output GND
3.2.7 J16, +5V Input Connector J16 is the input power connector. This connector bring in +5 volts to the EVM. This is a 2.5 mm. jack. The figure below shows this connector as viewed from the card edge. +5V J14 Ground PC Board Front View Figure 3-8, J16, +5 Volt Input Connector
3-7

3.2.8 J20, Mini PCI Interface Connector J20 provides a mini-PCI on the DM6437 EVM. Do NOT plug into this connector with the power on. The table below shows the signals on this connector. Table 4: J16, VLYNQ Card Interface
Pin # 2,3,4,5,6,7,8,10,11, 12,13,15,17,18,29, 30,38,39,47,49,51, 53,55,57,71,73,75, 77,80,82,84,86,93, 98,100,104,105, 106,107,108,109, 113,115,116,117, 118,120,122,123, 124 9,14,20,23,25,27 32,33,34,35,37,41, 42,44,45,46,48,50, 52,54,56,58,60,62, 64,66,68,69,72,74, 76,78,79,81,83,85, 87,90,91,92,94,95, 96,99,101,102, 110,114,119 111 1,19,28,31,40,63, 70,88,89 97,103 16 21 22 24 26 59 61 36 65 67 43 Signal
NC
GND
VCC_1.8V VCC_3.3V VCC_5V VLYNQ_CLK VLYNQ_RXD0 VLYNQ_RXD1 VLYNQ_SCRUN VLYNQ_RESET VLYNQ_RXD2 VLYNQ_RXD3 VLYNQ_TXD0 VLYNQ_TXD2 VLYNQ_TXD3 VLYNQ_TXD1
3-8

3.2.9 J501, Embedded Mini USB Emulation Interface This connector allows the user to run software development tools and emulation without an external emulator. The signals on this connector are shown in the table below. Table 5: J501, Embedded Mini USB Emulation Interface Pin # 1 2 3 4 5 Signal Name VBUS DD+ ID (not used) Ground
3.2.10 P1, Video Out Connector P1 is a four pin mini din connector which interfaces to an S-video output display device. This connector brings out the DAC B and DAC C. Do NOT plug into this connector with the power on. The figure below shows this connector as viewed from the card edge. Pin 3 Pin 1 Pin 4 Pin 2
Figure 3-9, P1, Front View, Mini Din Connector
Table 6: P1, Video Out, Mini Din Connector Pin # 1 2 3 4 Signal Name Ground Ground DAC_IOUTB, Luma DAC_IOUTC, Chroma
3-9

3.2.11 P2, Video In Connector P2 is a four pin mini din S-video connector which interfaces to the TVP5146M2 encoder. This connector brings in a video signal (LUMA) to pin 9 on the TVP5146M2. Do NOT plug into this connector with the power on. The figure below shows this connector as viewed from the card edge. Pin 3 Pin 1 Pin 4 Pin 2
Figure 3-10, P2,Front View, Mini Din Connector
Table 7: J11, Video In, Mini Din Connector Pin # 1 2 3 4 Signal Name GND GND LUMA Chroma
3.2.12 P3, Ethernet Interface The P3 connector is used to provide an 10/100 Mbps Ethernet interface. This is a standard RJ-45 connector. The pinout for the P3 connector is shown in the table below. Table 8: P3, Ethernet Interface
Pin # 1 3 5 7 Signal LXT_TDP LXT_RDP NC NC Pin # 2 4 6 8 Signal LXT_TDM LXT_TDCT LXT_RDM GND
Two LEDs are embedded into the connector to report link status. Table 9: Ethernet LEDs
LED # LED1 LED2 Color Green Yellow
3-10

3.2.13 P4, PCI Connector The P4 connector is a card edge PCI interface. This connector has an A and B side. Because of the card seating notches the pin numbers are not contiguous. The B side is the top component side. The I/O direction field is referenced from the PCI slot. Table 10: P4, PCI Connector, A Side
Pin
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61
Signal
TRSTTMS +5 Volts INTCRsvd.0 Rsvd.1 Key.2 RSTGNTPME+3.3 Volts AD26 AD24 +3.3 Volts AD20 AD18 +3.3 Volts GND GND +3.3 Volts SBOPAR +3.3 Volts AD11 AD9 Key.4 +3.3 Volts AD4 AD2 +V I/O +5 Volts
I/O
Description
Not Used Not Used +5 Volts Power
Pin
2 4 6 8 10 12 14 16 18 20
Signal
+12 Volts TDI INTA+5 Volts +V I/O Key.1 +3.3 Vaux +V I/O GND AD30 AD28 GND IDSEL AD22 GND AD16 FRAMETRDYSTOPSDONE GND AD15 AD13 GND Key.3 C/BE0 AD6 GND AD0 REQ64+5 Volts
I/O
I/O O
Description
Not Used Tied to TDO Interrupt Out +5 Volts Power Not Used Key Not Used
Interrupt Out Not Used Not Used Key
I O
PCI_Resetn Grant-
Not Used Ground
I/O/Z I/O/Z
Address/Data 30 Address/Data 28
Not Used I/O/Z I/O/Z Address/Data 26 Address/Data 24 Not Used I/O/Z I/O/Z Address/Data 20 Address/Data 18 Not Used Ground Ground Not Used
22 24 26 28 30 32 34 36 38 40 42
I I/O/Z
Initialization Device Select Address/Data 22 Ground
I/O/Z I I/O/Z I/O/Z O
Address/Data 16 Frame Target Ready Stop Direction Done Ground
I/O/Z
Parity Not Used
44 46 48 50 52 54 56 58 60 62
I/O/Z I/O/Z
Address/Data 15 Address/Data 13 Ground Key Command/Byte Enable0
I/O/Z I/O/Z
Address/Data 11 Address/Data 9 Key Not Used
I/O/Z
Address/Data 6 Ground
I/O/Z I/O/Z
Address/Data 4 Address/Data 2 Not Used +5 Volts Power
I/O/Z
Address/Data 0 Not Used +5 Volts Power
3-11

The signals on the B side of the connector are shown in the table below. Table 11: P4, PCI Connector, B Side
Pin
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61
Signal
-12 Volts GND +5 Volts INTBPRSNT1PRSNT2Key.6 GND GND +V I/O AD29 AD27 +3.3 Volts AD23 AD21 +3.3 Volts C/BE2IRDYDEVSELLOCK+3.3 Volts +3.3 Volts AD14 AD12 M66EN Key.8 AD7 AD5 GND +V I/O +5 Volts
I/O
Description
Not Used Ground +5 Volt Power Interrupt OUT
Pin
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62
Signal
TCK TDO +5 Volts INTDRsvd.2 Key.5 Rsvd.3 CLK REQAD31 GND AD25 C/BE3 GND AD19 AD17 GND +3.3 Volts GND PERRSERRC/BE1GND AD10 Key.7 AD8 +3.3 Volts AD3 AD1 ACK64+5 Volts
I/O
I I I
Description
Not Used Tied to TDO +5 Volt Power Interrupt Out
O O
Power Requirement Power Requirement Key Ground Ground Not Used
Key
System Clock
I/O/Z
Address/Data 31 Ground
I/O/Z I/O/Z
Address/Data 29 Address/Data 27 Not Used
I/O/Z I/O/Z
Address/Data 25 Command/Byte Enable 3 Ground
I/O/Z I/O/Z
Address/Data 23 Address/Data 21 Not Used
I/O/Z I/O/Z
Address/Data 19 Address/Data 17 Ground Not Used Ground
I/O/Z I I/O/Z I
Command/Byte Enable 2 Initiator Ready Device Select Resource Locked Not Used Not Used
I/O/Z O I/O/Z
Parity Error System Error Command/Byte Enable 1 Ground
I/O/Z I/O/Z O
Address/Data 14 Address/Data 12 66 Mhz Enable Key
I/O/Z
Address/Data 10 Key
I/O/Z
Address/Data 8 Not Used
I/O/Z I/O/Z
Address/Data 7 Address/Data 5 Ground Not Used +5 Volt Power
I/O/Z I/O/Z
Address/Data 3 Address/Data 1 Not Used +5 Volt Power
3-12

3.2.14 P7, CAN Connector The DM6437 EVM has a 9 Pin female D-connector which brings out the CAN transmit and receive signals. This CAN interface uses the SN65HVD235 CAN driver. The pin positions for the P7 connector as viewed from the edge of the printed circuit board are shown below.
5 9 4 8 3 7 2 6 1
Figure 3-11, P7, DB9 Female Connector The pin numbers and their corresponding signals are shown in the table below. Table 12: P7, CANA Pinout
Pin # 1 2 3 4 5 6 7 8 9 Signal Name No Connect CANL GND No Connect No Connect No Connect CANH No Connect No Connect
3-13

3.2.15 P8, RS-232 UART Connector The DM6437 EVM has an RS-232 connector which brings out the SCI transmit and receive signals to be used as UART. This UART uses the MAX3221 RS-232 line driver and is routed to a male 9 pin D-connector, P8. The pin positions for the P8 connector as viewed from the edge of the printed circuit board are shown below.
5 9 4 8 3 7 2 6 1
Figure 3-12, P8, DB9 Male Connector The pin numbers and their corresponding signals are shown in the table below. This corresponds to a standard dual row to DB-9 connector interface used on personal computers. Table 13: P8, RS-232 UART Pinout
Pin # 1 2 3 4 5 6 7 8 9 Signal Name No Connect RXD TXD No Connect GND No Connect No Connect No Connect No Connect
3-14

3.2.16 P10, Audio Line In Connector The audio line in is a stereo input. The input connector is a 3.5 mm stereo jack. The signals on the mating plug are shown in the figure below.
Ground Right Line In Left Line In Figure 3-13, Audio Line In Stereo Jack 3.2.17 P11, Microphone Connector The input is a 3.5 mm. stereo jack. Both inputs are connected to the microphone so it is monaural. The signals on the plug are shown in the figure below.
Ground Microphone In Microphone Bias Figure 3-14, Microphone Stereo Jack
3.2.18 P12, Headphone Connector Connector P12 is a headphone/speaker jack. It can drive standard headphones or a high impedance speaker directly. The standard 3.5 mm jack is shown in the figure below.
Ground Right Headphone Left Headphone Figure 3-15, Headphone Jack
3-15

3.2.19 P12, Audio Line Out Connector The audio line out is a stereo output. The output connector is a 3.5 mm stereo jack. The signals on the mating plug are shown in the figure below.
Ground Right Line Out Left Line Out Figure 3-16, Audio Line Out Stereo Jack
3.2.20 P14, S/PDIF Out (Optical) P14 is an optical transmitter connector used as an output from the McBSP FSR signal on the DM6437 DSP. This connector brings out an optical S/PDIF signal. Do NOT plug into this connector with the power on. The figure below shows this connector as viewed from the card edge.
3-16

3.2.21 DC_P1, Memory/Video ExpansionTable 14: DC_P1, Memory/Video Expansion
Pin
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99
Signal
GROUND PCLK_GP[54] TVP5146_ENABLEn YI3_(CCD3)_GP39] YI2_(CCD2)_GP[38] TI1_(CCD1)_GP[37] YI0_(CCD0_GP[36] GROUND C_WE_RNW_GP[35] VD_GP[53] CI3_(CDD11)_EM_A[17]_EM_D[04]_GP[47] CI2_(CDD10)_EM_A[18]_EM_D[05]_GP[46] CI1_(CDD9)_EM_A[19]_EM_D[06]_GP[45] CI0_(CDD8)_EM_A[20]_EM_D[07]_GP[44] GROUND VCLK_GP[31] GROUND VPBECLK_GP[30] GROUND YOUT3_GP[25]_BOOTMODE3 YOUT2_GP[24]_BOOTMODE2 YOUT1_GP[23]_BOOTMODE1 YOUT0_GP[22]_BOOTMODE0 GROUND COUT3_EM_D[3]_GP[17] COUT2_EM_D[2]_GP[16] COUT1_EM_D[1]_GP[15] COUT0_EM_D[0]_GP[14] GROUND B0_LCD_FIELD_EM_A[3]_GP[11] G1_EM_A[1]_(ALE)_GP[9]_(AEAW1) R2_EM_BA[0]_GP[6]_(AEM1) B2_EM_BA[1]_GP[6]_(AEM0) EM_WAIT_(RDY/BSTn) GROUND EM_A[5]_GP[96] EM_A[6]_GP[95] EM_A[7]_GP[94] EM_A[8]_GP[93] EM_WEn GROUND MEM_EMD7-7_ENABLEn CI_EMA_ENABLEn RESETn SYS_RESETn VCC_1V8 GROUND VCC_3V3 GROUND VCC_5V
Conn
Pin
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100
Signal
GROUND Y1_EMD_ENABLEn GROUND YI4_(CCD4)_GP40] YI5_(CCD5)_GP[41] TI6_(CCD6_GP[42] YI7_(CCD7)_GP[43] GROUND C_FIELD_EM_A[21]_GP[34] HD_GP[52] CI4_(CDD12)_EM_A[16]_EM_D[03]_GP[48] CI5_(CDD13)_EM_A[15]_EM_D[02]_GP[49] CI6_(CDD14)_EM_A[14]_EM_D[01]_GP[50] CI7_(CDD15)_EM_A[13]_EM_D[00]_GP[51] GROUND VSYNC_EM_CS4n_GP[32] GROUND HSYNC_EM_CS5n_GP[33] GROUND YOUT4_GP[26]_FASTBOOT YOUT5_GP[27] YOUT6_GP[28] YOUT7_GP[29] GROUND COUT4_EM_D[4]_GP[18] COUT5_EM_D[5]_GP[19] COUT6_EM_D[6]_GP[20] COUT7_EM_D[7]_GP[21] GROUND R0_EM_A[4]_GP[10]_(AEAW2) B1_EMA[2]_(CLE)_GP[8]_(AEAW0) R1_EM_A[0]_GP[7]_(AEM2) G0_EM_CS2n__GP[12] LCD_OE_EM_CS3n_GP[13] GROUND EM_A[9]_GP[92] EM_A[10]_GP[91] EM_A[11]_GP[90] EM_A[12]_GP[89] EM_OEn GROUND CLK_OUT_PWM2_GP[84] GROUND GP[4]_PWM1 I2C_INT_ENABLEn VCC_1V8 GROUND VCC_3V3 GROUND VCC_5V
Conn
3-17

3.2.22 DC_P2, Peripheral Expansion Table 15: DC_P2, Peripheral Expansion
Pin
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89
Signal
GROUND VCC_5V VCC_3V3 VIC_TINPOL_ENABLEn CLKS1_TINPOL_GP[98] GP[00] GP[02] RS232_ENABLEn URXD0_GP[85] UTXD0_GP[86] GROUND HECC_RX_TINP1L_URXD1_GP[56] GROUND AUDIO_CLK AXR0[3]_FSR0_GP[102] AFSR0_DR0_GP[100] AHCLKR0_CLKR0_GP[101] GROUND I2C_CLK AIC33_ENABLEn AXR0_FSR1_GP[106] AMUTE0_DR1_GP[110] ACLKX0_CLKX1_GP[106] GROUND RESET_OUTn SPARE HDS1n_RXD1_GP[79] HINTn_RXD3_GP[82] GROUND HHWIL_RXDV_GP[74] HD10_CRS_GP[68] GROUND HCSnMDC_GP[81] GROUND HD11_TXD3_GP[69] HD13_TXD1_GP[71] HCNTL1_TXEN_GP[75] GROUND SPARE GROUND USER_I2C_IO.A0P6 SPARE USER_I2C_IO.A1P2 USER_I2C_IO.A1P0 GROUND
Conn
Pin
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90
Signal
GROUND VCC_5V VCC_3V3 GROUND CLKS0_TINPOL_GP[97] GP[01] GP[03] GROUND URTS0_PWM0_GP[88] UCTS0_GP[87] GROUND HECC_tX_TOUT1L_UTXD1_GP[55] CAN_ENABLEn GROUND AXR0[2]_FSX0_GP[103] AXR0[1]_DX0_GP[104] ACLKR0_CLKX0_GP[99] GROUND I2C_DATA GROUND AMUTEIN0_FSX1_GP[109] ACHLKX0_CLKR1_GP[108] AFSX0_DX1_GP[107] GROUND SPARE HCNTL0_MRXER_GP[76] HDS2n_RXD0_GP[78] HRDYn_RXD2_GP[80] HD09_COL_GP[67] GROUND HRNW_RXCLK_GP[77] GROUND HASn_MDIO_GP[83] GROUND HD12_TXD2_GP[70] HD14_TXD0_GP[72] ENET_ENABLEn GROUND HD15_TXCLK_GP[73] GROUND USER_I2C_IO.A0P7 SPARE USER_I2C_IO.A1P3 USER_I2C_IO.A1P1 GROUND
Conn
3-18

3.2.23 DC_P3, VLYNQ Connector The DC_P3 connector allows the user to connect the VLYNQ interface to other logic. The pinout for the DC_P3 connector is shown in the table below. Table 16: DC_P3, VLYNQ Header
Pin # 1 3 5 7 9 11 13 15 17 19 Signal HD00_VLYNQ_SCRUN_GP[58] GROUND HD01_VLYNQ_RXD0_GP[59] HD02_VLYNQ_RXD1_GP[60] GROUND VCC_3V3 HD03_VLYNQ_RXD2_GP[61] HD04_VLYNQ_RXD3_GP[62] GROUND VCC_5V Conn Pin # 2 4 6 8 10 12 14 16 18 20 Signal VLYNQ_CLOCK_GP[57] GROUND HD05_VLYNQ_TXD0_GP[63] HD06_VLYNQ_TXD1_GP[64] GROUND DC_P3_VLYNQ_RESETn HD07_VLYNQ_TXD2_GP[65] HD08_VLYNQ_TXD3_GP[66] GROUND VCC_5V Conn
3.3 Jumpers The DM6437 EVM has four (4) jumpers which are used to make certain logic or feature determinations on the board. The function of each jumper is described in the table below. Table 17: Jumpers
Jumper # JP1 JP2 JP3 * JP4 * Function NTSC/PAL Select CS2 Select Reset Power Up Reset Size 1x3 2x4 1x2 1x2
* Not populated
3-19

3.3.1 JP1 Jumper Jumper JP1 is used to select the display output format, NTSC or PAL. This jumper must be populated in one of the two configurations. When the center to NTSC is selected the display output will be NTSC format. When the center to PAL is selected the display output will be in PAL format. These positions are shown in the figure below. Board edge
PAL Selection Board edge
NTSC Selection Figure 3-18, JP1 Jumper
3.3.2 JP2 Jumper Jumper JP2 is a jumper bank used to select the routing of the CS2 signal. It can be routed to Flash ROM, SRAM, NAND Flash, and daughter card connector. Only one of these 1-2 selections should be made. The positions are shown in the figure below. 1 2 FLASH CS2-SEL SRAM NAND DC JP2 Figure 3-19, JP2 Jumper
3-20

3.3.3 JP3 Jumper Jumper JP3 is a jumper used to allow external switches to interface to the DM6437 power up reset signal.
3.3.4 JP4 Jumper Jumper JP4 is a jumper used to allow external switches to interface to the DM6437 reset signal.
3.4 LEDs The DM6437 EVM has eight (8) LEDs. Four of these LEDs (DS1-4) are under user control and addressed over the I2C bus. LED DS5 indicates the presence of +5 volts on the board. The remaining LEDs, DS501 and DS502 indicate embedded USB status. DS502 is on when embedded USB emulation is selected and off when the external JTAG emulator is plugged into connector J6. DS501 blinks as packets are sent to and from the embedded USB emulator. The LED functions are summarized in the table below. Table 18: LEDs LED # DS1 DS2 DS3 DS4 DS5 DS501 DS502 Use User Defined User Defined User Defined User Defined +5V present Embedded Emulation Status Embedded/external EMU Color Green Green Green Green Red Green Green
3-21

3.5 Switches The DM6437 EVM has seven (7) switches. These switches are used to create certain actions on the board or to select certain functions on the board. The switch functions are summarized in the table below. Table 19: Switches SW # SW1 SW2 SW3 SW4 SW5 SW6 SW7 Function Bootload Mode Select DM6437 Muxing Configuration EMIF Data Select 4 position user readable Power On Reset Reset Slide Switch
3.5.1 SW1, Bootload Mode Select Switch SW1 is an 8 position switch used to select the source of the bootload. Five (5) of the eight (8) positions are used. The selections are shown in the table below. Table 20: SW1, Bootload Mode Select
SW1[4:1] SW1[5] Auto Detected x Boot Description Emulation Boot In this mode, FASTBOOT setting is dont care (not used by bootloader code) HPI Boot PCI Boot without autoinitialization PCI Boot with autoinitialization HPI Boot EMIFA ROM Direct Boot EMIFA ROM Fast Boot I2C Boot SPI Boot (McBSP peripheral) NAND Flash UART EMAC Boot through secondary bootloader Notes DSPBOOTADDR default 0x0010 0000
0000
DM6437 is master
0001 0001 0010 0010 0100 0100 0101 0110 0111 1000 1011
1* 1* 1* 1* 0 1 x 1* 1* x x
0 1 0 1 x x x x x x x
DM6437 is slave DM6437 is slave DM6437 is slave DM6437 is slave DM6437 is master DM6437 is master DM6437 is master DM6437 is master DM6437 is master DM6437 is master DM6437 is slave
0x0010 0000 0x0010 0000 0x0010 0000 0x0010 0000 0x4200 0000 0x0010 0000 0x0010 0000 0x0010 0000 0x0010 0000 0x0010 0000 0x0010 0000
x = dont care, * these boot modes must be accompanied with FASTBOOT = 1. 3-22 DM6437 EVM Technical Reference

3.5.2 SW2, Bootload Configuration Select Switch SW2 is an 4 position switch used to select the DM6437 multiplexing options at reset. The selection are shown in the table below. Table 21: SW2, Bootload Configuration Select Position 1 2 3 4 Function AEM2 AEM1 AEM0 AEAW2 Description Specifies EMIF mode at reset Specifies EMIF mode at reset Specifies EMIF mode at reset Specifies EMIF mode at reset
3.5.3 SW3, EMIF Data Select Switch SW3 is used to select between data bus pins for the asynchronous EMIF controller. The functions of this switch are shown in the table below. Table 22: SW3, EMDATA Select Position 1 2 Function Not used MEM_EMD7-0_SELECT Description Not Used 0=Selects CI0-7 as EMIF data bus D0:D7 pins 1=Selects CI0-7 as COUT data bus D0:D7 pins
3.5.4 SW4, 4 Position User Readable Switch SW4 is a 4 position bank of user readable switches via the I2C expander. The individual switches can be placed in any position and read by the user software from the expander. See the section on I2C expanders for more information.
3.5.5 SW5, Power On Reset Switch Switch SW5 is a momentary switch that asserts power on reset to the DM6437 device.
3.5.6 SW6, Reset Switch Switch SW6 is a momentary switch that asserts a reset to the DM6437 processor.
3-23

3.5.7 SW7, Slide Switch Switch SW7 is a 2 position slide switch used by demonstration software. The switch is read via a I2C expander. Refer to the I2C section for more information.
3-24

3.6 Test Points The EVM has 51 test points. All test points appear on the top of the board. The following figure identifies the position of each test point. the next table list each test point and the signal appearing on that test point.
TP36 TP18 TP17 TP15 TP16 TP21 TP14 TP13 TP29 TP37 TP31 TP27 TP25 TP26 TP28 TP38 TP32 TP34 TP33 TP23 TP22 TP12 TP7 TP30 TP47 TP46 TP8 TP59 TP10 TP41 TP1 TP40 TP64 TP42 TP43 TP48,TP49
TP69 TP70
TP4,TP5 TP6,TP2
TP58 TP19 TP20
Figure 3-20, DM6437 EVM, Test Points 3-25

Table 23: DM6437 EVM Test Points
Test Point #
TP1 TP2 TP6 TP7 TP8 TP10 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20 TP21 TP25 TP26
Signal
RESETOUTn RSV4 RSV5 GND GND GND Ethernet PHY Interrupt Pin CAN Driver Output B_CANH CAN Driver Output B_CANL Codec MFP2 Pin Codec MPF3 Pin Codec GPIO1 Pin Codec GPIO2 Pin VIDEO DECODER AVID/GPIO Pin VIDEO DECODER INTREQ Pin CORE_PWR_OK GND GND
Test Point #
TP27 TP28 TP29 TP30 TP31 TP32 TP36 TP40 TP41 TP52 TP53 TP58 TP59 TP61 TP64 TP69 TP70
Signal
GND GND GND GND VCC_5V 3V3_PWR_OK 1V8_PWR_OK DM6437 I2CCLK DM6437 I2CDATA VDD_1P1V VDD_1P1V VIDEO DECODER GLCO/I2C Pin VIC INPUT CLOCK DM6437 HECC_RX DM6437 HECC_TX DM6437 PWM1 DM6437CLK_OUT
Table 24: Power Pair Test Points

Power Pairs Input1 Input2
TP4 TP22 TP33 TP37 TP42 TP47 TP48 TP52 TP54 TP5 TP23 TP34 TP38 TP43 TP46 TP49 TP53 TP55
Power Domain
DDR_VDDL DSP_CORE_VDD VCC_3V3 VCC_1V8 DVD_3V3 DVDD_1V8 PLLPWR18 VDDA_1P1V VDDA_1P8V
Resistance Between Inputs

0.1 ohms 0.025 ohms 0.025 ohms 0.025 ohms 0.025 ohms 0.025 ohms 0.1 ohms 0.1 ohms 0.1 ohms
3-26
Appendix A Schematics
This appendix contains the schematics for the DM6437 EVM.
A-1
A-2
4 3 2 1
SCHEMATIC CONTENTS
I2C Address Table ADDRESS HEX BINARY 00111000B 00111001B 00111010B 00111011B 01010000B CAT24C256 AIC33 TVP5146 00011011B 01011101B PCF8574 PCF8574 PCF8574 PCF8574 0x38 0x39 0x3A 0x3B 0x50 0x1B 0x5D DEVICE FUNCTION USER INPUT Expander - 0111(A2)(A1)(A0) LED Expander - 0111(A2)(A1)(A0) VIC PLL Expander - 0111(A2)(A1)(A0) VLYNQ IO Expander - 0111(A2)(A1)(A0) EEPROM - 1010(A2)(A1)(A0) AUDIO CODEC - 00110(MFP1)(MFP0) VIDEO DECODER - 101110(I2CA)
C

SHEET01 SHEET02 SHEET03 SHEET04 SHEET05 SHEET06 SHEET07 SHEET08 SHEET09 TITLE BLOCK DIAGRAM DSP CLKS/RST/EMU EMULATION DSP Serial/CAN/I2C DSP VP/EMIF/PCI/ENET DSP DDR Interface DSP DACS/GND-pins DSP Power Pins SHEET10 SHEET11 SHEET12 SHEET13 SHEET14 SHEET15 SHEET16 SHEET17 SHEET18 SHEET19 Boot DIP Switches VIC I2C Expanders I2C Expanders 2 DDR2 Memories EMIF Muxing NAND-Flash/SRAM NOR-Flash/EEPROM ENET Muxing ENET SHEET20 SHEET21 SHEET22 SHEET23 SHEET24 SHEET25 SHEET26 SHEET27 SHEET28 SHEET29 SHEET30 SHEET31 SHEET32 SHEET33 SHEET34 VIDEO DC Conn. EMAC/MCBSP DC Conn. VLYNQ/EMIF DC Conn. RESET SUPERVISOR POWER CAN RS232 PCI-Mux PCI-Mux II PCI-Connector VLYNQ AIC33 SPDIF/TVP5146-Switch TVP5146 Video Out
B
REVISION STATUS OF SHEETS DWN R.R.P. T.W.K. CHK C 27 A 17 A A 9

4
31 A 28 A 18 A A 10 APPLICATION NEXT ASSY USED ON 8 19 20 A A 29 30 ENGR A A
32
33
34
REV
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22
23
24
25
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TMS320DM6437 Evaluation Module TITLE SHEET DWG NO 509102-0001 Wednesday, December 06, 2006
1
REV
SH
11
12
13
14
15
16
REV 7
Revision: C Sheet 1 of 34
SH
R.R.P. ENGR-MGR R.R.P. QA C.M.D. MFG R.R.P. RLSE R.R.P.
DATE 06/01/2006 DATE 06/01/2006 DATE 06/01/2006 DATE 06/01/2006 DATE 06/01/2006 DATE 06/01/2006 DATE 06/01/2006
VIC McBSP DC Connector

SPI EEPROM Socket
D
GIO/PCI Audio Switch I2C Expanders I2C McBSP1/MCASP0 S/PDIF Out
PWM1
Timer0
McBSP0/McASP0 Stereo Codec
I2C EEPROM
Video In DC Connector Timer1/HECC/ UART1 CCDC/EMIF/ McASP1/PCI Video Switch DACs EMIF-Ctrl DDR2 IF EMIF-Addr/PCI Boot DIP Switches PLL UART0/PWM0
DSP
CAN Switch
CAN XCVR
Video Decoder
UART Switches
RS-232 XCVR
C
NAND/NOR/SRAM
EMIF Switch
Video Out Connectors
DDR2 SDRAM
Crystal/Osc
Video Out DC Connector ENET Switches UHPI/PCI/EMAC PCI AD
VENC/EMIF
Emulator
EMU Muxes
EMU Header
B
ENET XCVR
VLYNQ/PCI/ UHPI
Embedded EMU
EMAC DC Connector
PCI Switches/Mux VLYNQ DC Connector VLYNQ mPCI Connector Power Supplies MISC DC Connector Reset Logic
Title: Page Contents: Size: B Date:
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PCI Edge Conn
Revision: A Sheet 2 of 34
A-3
A-4
4 3 2 1
JP3
1 2
VCC_3V3
D
HEADER 2 NO-POP
SW6
R1 10K
A AA
C1 1uF
B BB
33
R2

4,22,30 RESETn DM6437 U1A TP1 TP30
C
PUSHBUTTON SW
M4 RESETn RESETOUTn
17,19,26,28,30,33 SYS_RESETn
N3
TP2 TP30
RESET_OUTn 22,31
N4 PORn
23
PCIEN
T3 PCIEN RSV4
L15
OPTIONAL OSCILLATOR POPULATION
CRYSTAL AND CAPS REMOVED WHEN OSCILLATOR IS USED
L1 C2 18 pF
VCC_1V8
RSV3 J19 MXO RSV2 K19 MXI/CLKIN MXVSS

NO-POP C4 18 pF
L5
2 1 BLM21PG221SN1D
Y1 27MHz R3 C3 .1uF U2
K5
1 EN GND
R5 NO-POP
ASFL3-27.000MHZ-EK-T 102229-0027
VCC OUT
0
4 3
NO-POP R4
K18
R19
NO-POP
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Revision: C Sheet 3 of 34
VCC_3V3 VCC_3V3 C164 0.1uF VCC_3V3
R6 1K U38 DS502
R149 USB 150 EMBEDDED EMU ON VCC_3V3 R148 C166 VCC_3V3 0.1uF U41 NO POP
0.1uF J6 XDS_TRST# T_TDO XDS_TDI XDS_TCK T_TCK XDS_EMU1 T_TMS XDS_TMS XDS_TDO
2A 3A 4A GND
VCC_3V3
1 15 S OE 8
SN74CBTLV3257PWR
VCC_3V3 C167 0.1uF U539 T_EMU0 XDS_EMU1 T_EMU1 XDS_TRST# T_TRSTn XDS_TCK_RTN T_TCK_RET EMU_STS DSP_EMU0 XDS_EMU0 C168 0.1uF
2 3 5 6 11 10 14 13 1A 2A 3A 4A 7 9 12 4 1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2 1 15 S OE GND 8 SN74CBTLV3257PWR
VCC_3V3 VCC_3V3 VCC_3V3 VCC_5V Embedded_USB_1 R150 R151

2
C165 SN74AHC1G14DCKRG4 Green
VCC_3V3
JTAG MULTIPLEXERS
VCC 1A 7 9 1
DSP_TMS DSP_TDI
16 4
DSP_TDO U35 C163 0.1uF
C169 NO POP
XDS_TMS XDS_TDI T_TDI
1 3 XDS_TVD 5 XDS_TDO 7 XDS_TCK_RTN 9 XDS_TCK 11 XDS_EMU0 13 2 4 6 8 10 12 14 1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2 12 2
TMS TRST TDI GND PD nc TDO GND TCKRET GND TCK GND EMU0 EMU1
2 3 5 6 11 10 14 13
R8 SN74LVC1G32
33
DSP_TCK
TSW-107-14-G-D-006
VCC
16
U37
1
DSP_EMU1 DSP_TRST#
4 2
SN74LVC1G32
R9
33
DM6437 DSP_TRST# DSP_TMS DSP_TDI DSP_TDO 10K DSP_TCK DSP_EMU0 DSP_EMU1
U1F
R2 R3 P4 P3 N1 P2 N2
TRSTn TMS TDI TDO
5V
10K
R152
10K
3.3V PONRSn
33 EMU_SYS_RESETn
T_TRSTn T_TCK T_TMS T_TDI T_TDO T_EMU0 T_EMU1
T_TRSTn T_TCK T_TMS T_TDI T_TDO T_EMU0 T_EMU1
TCK EMU0 EMU1
VCC_3V3
3,22,30 RESETn
USB_DSP_RSTn T_TCK_RET CLK_12MHZ CLK_24MHZ GND

T_TCK_RET R10 R12 NO-POP NO-POP R11 R13 1K 1K
26 ALT_AIC33_CLK
Embedded_USB Title: Page Contents: Size: B Date:

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Revision: B Sheet 4 of 34
A-5
VCC_3V3 12 I2C_INT
NO-POP
30 I2C_INT_ENABLEn R251 10K DM6437 TOUT1L R429 R430 R431 TINP1L R14 33 PWM1 11,30 CLK_OUT 6,11,30 20,21,31 R432 0 0 0 0 20,21,31
C
A-6
4 3 2 1
VCC_3V3
C7 .1uF
D
U3
PWM1_I2C_INT
R18
74LVC1G125DCKRG4
TP64 TP-60 U1E

F1 G2 G1 G3 F2 H2 ACLKX0/CLKX1/GP[106] AFSX0/DX1/GP[107] AHCLKX0/CLKR1/GP[108] AMUTE0/DR1/GP[110] GP[4]/PWM1 AMUTEIN0/FSX1/GP[109] CLK_OUT/PWM2/GP[84] AXR0[0]/FSR1/GP[105] HECC_TX/TOUT1L/UTXD1/GP[55] HECC_RX/TINP1L/URXD1/GP[56] F3 M1 K4 L4
TP40 TP-30 TP61 TP-60 VCC_3V3 R433 R434 33 33
26,31 26,31 26,31 26,31 26,31 26,31
CLKX1 DX1 CLKR1 DR1 FSX1 FSR1
31 17,26,31 17,31 31 17,26,31 17,26,31
CLKR0 DX0 FSX0 FSR0 CLKX0 DR0
J2 J3 H3 G4 H1 H4 AHCLKR0/CLKR0/GP[101] AXR0[1]/DX0/GP[104] AXR0[2]/FSX0/GP[103] AXR0[3]/FSR0/GP[102] ACLKR0/CLKX0/GP[99] AFSR0/DR0/GP[100] I2C_CLK I2C_DATA AD[0]/GP[0] AD[1]/GP[1] AD[2]/GP[2] AD[3]/GP[3]
TP41 TP-30
URTS0/PWM0/GP[88] UCTS0/GP[87] UTXD0/GP[86] URXD0/GP[85] M2 M3
L3 L1 K3 L2
URTS0 UCTS0 UTXD0 URXD0 31 31 21,31 21,31
R15 2.2K
R16 2.2K I2C_CLK 12,13,17,26,28,31 I2C_DATA 12,13,17,26,28,31
11,31 TINP0L 31 TOUT0L
R435 R436
33 33
K2 J4 CLKS1/TINP0L/GP[98] CLKS0/TOUT0L/GP[97]
GIO000 GIO001 GIO002 GIO003 23 23 23 23
E1 E2 E3 E4

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RN 14H 8
A B
DM6437 R168 NO-POP NO-POP R166 R167 20K 20K U1G VCC_3V3
9 RPACK8-22
16,17,30 READ_OE 16,17,30 WRITE_WE 16,30 WAIT_BSYn
RN1 4F 6 RN14G 7
A B A B
R165 RN2

11 RPACK8-22 D15 10 RPACK8-22 E14 E15 EM_OEn EM_WEn EM_WAIT/(RDY/BSYn)
RN1
WAIT_BSYn PULL UP ON PAGE 16
15,30 15,30 15,30 15,30 15,30 15,30 15,30 15,30
COUT0 COUT1 COUT2 COUT3 COUT4 COUT5 COUT6 COUT7
9 10 11 12 13 14 15 16 COUT0/EM_D[0]/GP[14] COUT1/EM_D[1]/GP[15] COUT2/EM_D[2]/GP[16] COUT3/EM_D[3]/GP[17] COUT4/EM_D[4]/GP[18] COUT5/EM_D[5]/GP[19] COUT6/EM_D[6]/GP[20] COUT7/EM_D[7]/GP[21] EM_A[5]/AD19/GP[96] EM_A[6]/AD20/GP[95] EM_A[7]/AD22/GP[94] EM_A[8]/AD21/GP[93] EM_A[9]/PIDSEL/GP[92] EM_A[10]/AD23/GP[91] EM_A[11]/AD24/GP[90] EM_A[12]/PCBE3/GP[89] B8 D8 C9 B9 D9 A9 C10 D10
RPACK8-22
8 RPACK8-22 7 6 5 4 3 2 1 D16 D18 D17 E16 E18 E17 F16 F17
R2/EM_BA[0]/GP[6]/(AEM1) B2/EM_BA[1]/GP[5]/(AEM0) R1/EM_A[0]/GP[7]/(AEM2) G1/EM_A[1]/(ALE)/GP[9]/(AEAW1) B1/EM_A[2]/(CLE)/GP[8]/(AEAW0) B0/LCD_FIELD/EM_A[3]/GP[11] R0/EM_A[4]/GP[10]/AEAW2) C_FIELD/EM_A[21]/GP[34]
C17 C16 B17 A16 B16 B18 A17 D12 9 10 11 12 13 14 15 16
RPACK8-22 8 7 6 5 4 3 2 1
EM_BA0 10,16,17,30 EM_BA1 10,16,17,30 EM_A00 10,16,17,30 EM_A01_ALE 16,17,30 EM_A02_CLE 16,17,30 EM_A03 16,17,30 EM_A04 10,16,17,30 C_FIELD 15,30
RN4 Y I7 Y I6 Y I5 Y I4 Y I3 Y I2 Y I1 Y I0
27,30 27,30 27,30 27,30 27,30 27,30 27,30 27,30
YI7 YI6 YI5 YI4 YI3 YI2 YI1 YI0
1 2 3 4 5 6 7 8 A12 B13 C13 D14 B14 C14 B15 C15 YI7(CCD7)/GP[43] YI6(CCD6)/GP[42] YI5(CCD5)/GP[41] YI4(CCD4)/GP[40] YI3(CCD3)/GP[39] YI2(CCD2)/GP[38] YI1(CCD1)/GP[37] YI0(CCD0)/GP[36]
RN6
16 15 14 13 12 11 10 9
EM_A05 EM_A06 EM_A07 EM_A08 EM_A09 EM_A10 EM_A11 EM_A12
22 22 22 22 22 22 22 22
30 YOUT7 10,30 YOUT6 10,30 YOUT5 10,30 YOUT4_FASTBOOT 10,30 YOUT3_BOOTMODE3 10,30 YOUT2_BOOTMODE2 10,30 YOUT1_BOOTMODE1 10,30 YOUT0_BOOTMODE0 R183 R268 R184 R27 R311 R312 R313 0 22 0 0 0 NO-POP NO-POP
16 15 14 13 12 11 10 9 H15 H16 H17 G17 G16 G15 F15 F18 YOUT7/GP[29] YOUT6/GP[28] YOUT5/GP[27] YOUT4/GP[26]/(FASTBOOT) YOUT3/GP[25]/(BOOTMODE3) YOUT2/GP[24]/(BOOTMODE2) YOUT1/GP[23]/(BOOTMODE1) YOUT0/GP[22]/(BOOTMODE0) VPBECLK/GP[30] VCLK/GP[31] HD/GP[52] PCLK/GP[54] VD/GP[53] C_WE/RNW/GP[35] G0/EM_CS2n/GP[12] LCD_OE/EM_CS3n/GP[13] VSYNC/EM_CS4n/GP[32] HSYNC/EM_CS5n/GP[33] G19 D19 A15 A14 A13 D13 C19 C18 E19 F19
RPACK8-10 1 2 3 4 5 6 7 8
CI7(CCD15)/EM_A[13]/AD25/EM_D[0]/GP[51] CI6(CCD14)/EM_A[14]/AD27/EM_D[1]/GP[50] CI5(CCD13)/EM_A[15]/AD29/EM_D[2]/GP[49] CI4(CCD12)/EM_A[16]/PGNTn/EM_D[3]/GP[48] CI3(CCD11)/EM_A[17]/AD31/EM_D[4]/GP[47] CI2(CCD10)/EM_A[18]/PRSTn/EM_D[5]/GP[46] CI1(CCD9)/EM_A[19]/PREQn/EM_D[6]/GP[45] CI0(CCD8)/EM_A[20]/PINTAn/EM_D[7]/GP[44]
B10 A10 B11 C11 A11 D11 B12 C12
CI7 CI6 CI5 CI4 CI3 CI2 CI1 CI0
22 22 22 22 22 22 22 22
5,11,30 CLK_OUT 11 VID_CLK
30 VPBECLK 30 VCLK 27,30 HD 27 PCLK 27,30 VD
RPACK8-22 RPACK8-22 RPACK8-22 RPACK8-22 RPACK8-22
15 16 14 13 12
B B B B B
A A A A A
2 1 3 4 5
RN14B RN14A RN14C RN14D RN14E
C_W EN EM_CS2 LCD_OE VSYNC HSYNC
30 15 30 30 30
AD26 AD28 AD30
E10 E11 E12
AD26 AD28 AD30
22 22 22
22 PCICLK 22 AD18 22 AD16 22 AD17 22 PCBE2n 22 PFRAMEn 22 PIDRDYn 23 PTRDYn 23 PDEVSELn 23 PPERn
A7 C8 D7 A8 B7 C7 A6 D6 B6 A5 VLYNQ_CLOCK/PCICLK/GP[57] HD0/VLYNQ_SCRUN/AD18/GP[58] HD1/VLYNQ_RXD0/AD16/GP[59] HD2/VLYNQ_RXD1/AD17/GP[60] HD3/VLYNQ_RXD2/PCBE2n/GP[61] HD4/VLYNQ_RXD3/PFRAMEn/GP[62] HD5/VLYNQ_TXD0/PIRDYn/GP[63] HD6/VLYNQ_TXD1/PTRDYn/GP[64] HD7/VLYNQ_TXD2/PDEVSELn/GP[65] HD8/VLYNQ_TXD3/PPERRn/GP[66]
HRNW/MRXCLK/AD8/GP[77] HINTn/MRXD3/AD6/GP[82] HRDYn/MRXD2/PCBE0/GP[80] HDS1n/MRXD1/AD7/GP[79] HDS2n/MRXD0/AD9/GP[78] HCNTL0/MRXER/AD10/GP[76] HCNTL1/MTXEN/AD11/GP[75] HHWIL/MRXDV/AD13/GP[74] HCSn/MDCLK/AD5/GP[81] HASn/MDIO/AD3/GP[83]
A3 C2 D2 B2 C3 B3 D3 C4 C1 D1
RXCLK RXD3 RXD2 RXD1 RXD0 RXER TXEN RXDV MDC MDIO
23 23 23 23 23 23 23 23 23 23
23 23 23 23 23
COL CRS TXD3 TXD2 TXD1
C6 B5 C5 D5 B4 HD9/MCOL/PSTOPn/GP[7] HD10/MCRS/PSERRn/GP[68] HD11/MTXD3/PCBE1/GP[69] HD12/MTXD2/PPAR/GP[70] HD13/MTXD1/AD14/GP[71] HD14/MTXD0/AD15/GP[72] HD15/MTXCLK/AD12/GP[73] D4 A4
23 23
TXD0 TXCLK

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A-7
A-8
4 3 2 1
14 DDR_D[0:31] RN7 DM6437 U1C RPACK4-22
DDR_A[0:12] 14
D
4 3 2 1
RN8
5 6 7 8
DDR_A0 DDR_A1 DDR_A2 DDR_A3
DDR_A[0] DDR_A[1] DDR_A[2] DDR_A[3] DDR_A[4] DDR_A[5] DDR_A[6] DDR_A[7] DDR_A[8] DDR_A[9] DDR_A[10] DDR_A[11] DDR_A[12]
RN9
W13 U13 V13 U12 V12 W12 W11 V11 V10 U11 U10 W10 W9 4 3 2 1 4 3 2 1
RPACK4-22 5 DDR_A4 6 DDR_A5 7 DDR_A6 8 DDR_A7 RPACK4-22 5 DDR_A8 6 DDR_A9 7 DDR_A10 8 DDR_A11
BDDR_A0 BDDR_A1 BDDR_A2 BDDR_A3 BDDR_A4 BDDR_A5 BDDR_A6 BDDR_A7 BDDR_A8 BDDR_A9 BDDR_A10 BDDR_A11 BDDR_A12

DDR_BS[0] DDR_BS[1] DDR_BS[2] DDR_CASn DDR_RASn DDR_WEn DDR_CKE DDR_CSn T9
BD DR_CS R29 22 DDR_ CS DDR_ CS
U8 V9 U9
DDR_BS00 14 DDR_BS01 14 DDR_BS02 14
BDDR_BS00 BDDR_BS01 BDDR_BS02 BDDR_CAS BDDR_RAS BDDR_WE BDDR_CKE RPACK4-22 DD R_CAS DD R_RAS DDR_WE DD R_CKE DDR_CAS DDR_RAS DDR_WE DDR_CKE 14 14 14 14 14
RN10 4 3 2 1 RN11 5 6 7 8
RPACK4-22 5 DDR_A12 DDR_BS00 6 DDR_BS01 7 DDR_BS02 8
T7 U7 T8 V8 4 3 2 1
VCC_1V8
DDR _D0 DDR _D1 DDR _D2 DDR _D3 DDR _D4 DDR _D5 DDR _D6 DDR _D7 DDR _D8 DDR _D9 D DR_D10 D DR_D11 D DR_D12 D DR_D13 D DR_D14 D DR_D15 D DR_D16 D DR_D17 D DR_D18 D DR_D19 D DR_D20 D DR_D21 D DR_D22 D DR_D23 D DR_D24 D DR_D25 D DR_D26 D DR_D27 D DR_D28 D DR_D29 D DR_D30 D DR_D31
T1 T2 U1 U2 V2 U3 V3 W3 V4 W4 U5 V5 W5 V6 W6 V7 W14 V14 W15 V15 U15 W16 V16 T17 V17 U17 T18 W17 U18 V18 U19 T19 DDR_D[0] DDR_D[1] DDR_D[2] DDR_D[3] DDR_D[4] DDR_D[5] DDR_D[6] DDR_D[7] DDR_D[8] DDR_D[9] DDR_D[10] DDR_D[11] DDR_D[12] DDR_D[13] DDR_D[14] DDR_D[15] DDR_D[16] DDR_D[17] DDR_D[18] DDR_D[19] DDR_D[20] DDR_D[21] DDR_D[22] DDR_D[23] DDR_D[24] DDR_D[25] DDR_D[26] DDR_D[27] DDR_D[28] DDR_D[29] DDR_D[30] DDR_D[31] DDR_DQM[0] DDR_DQM[1] DDR_DQM[2] DDR_DQM[3] DDR_CLK0n DDR_CLK0 DDR_ZN DDR_ZP
TP4 TP-30
T4 T6 T14 T16 W8 W7 T10 T11 T12 T13

R34 0 DDR_PADREFN R32 D DR_PADREFP R33 200 200 BDDR_CLK_N BDDR_C LK R30 R31 10 10 DDR_CLK_N DDR_CLK
BDDR_DQM0 BDDR_DQM1 BDDR_DQM2 BDDR_DQM3
R86 R84 R87 R85
22 22 22 22
DDR_DQM0 DDR_DQM1 DDR_DQM2 DDR_DQM3
DDR_DQM0 DDR_DQM1 DDR_DQM2 DDR_DQM3
14 14 14 14 DDR_CLK_N 14 DDR_CLK 14 VCC_1V8
C111
R76 1K 1%
14 14 14 14
DDR_DQS0 DDR_DQS1 DDR_DQS2 DDR_DQS3
DDR_DQS0 DDR_DQS1 DDR_DQS2 DDR_DQS3
U4 U6 U14 U16 DDR_DQS[0] DDR_DQS[1] DDR_DQS[2] DDR_DQS[3]
0.1uF VREF_STL
TP5 TP-30 L3
14 VREF_STL
T15 DDR_VREF RSV5 R13

TP6 TP-30 C8 0.1uF
DDR_VDDDLL DDR_VSSDLL
C5 R77 1K 1% C9 0.1uF R35 0.00X
0.1uF
2 BLM21PG221SN1D
C10 1uF
Designers must use routing techniques from DDR2 PCB Layout Application Note
TP7 TP-60 TP8 TP-60 TP9 TP-60 TP10 TP-60 Title: Page Contents: Size: B Date:
4 3 2
SPECTRUM DIGITAL INCORPORATED TMS320DM6437 Evaluation Module DSP DDR Interface DWG NO 509102-0001 Wednesday, December 06, 2006
1
VCC_3V3
R36 1K DM6437 R37 VREF_0.5V 7.5K 1% U1D

N19 DAC_VREF DAC_IOUT_B
C11 .1uF 29 DAC_RBIAS
DAC_IOUT_A P18 N18 N17 P15 P16
P19
DAC_IOUT_A 29 DAC_IOUT_B 29 DAC_IOUT_C 29 DAC_IOUT_D 29
R38 0
R39 4.99K 1%
N16 DAC_RBIAS DAC_IOUT_D DAC_IOUT_C
1
C12 1uF
2 N15 VDDA_1P1V VDDA_1P8V VSSA_1P8V VSSA_1P1V P17
VREF =1.24 VOLTS
U4 TLV431ADBV
R41 NO-POP
DSP_CORE_VDD L4 R322 DM6437

+
0.1 U1H C15 10uF C13 .1uF C14 .001uF
1 2 BLM21PG221SN1D
TP52 TP-30
TP53 TP-30
VCC_1V8 R323
+
L5 0.1 C16 10uF C17 .1uF C18 .001uF
1 2 BLM21PG221SN1D
TP54 TP-30
TP55 TP-30
A19 B1 B19 E13 E7 E9 F10 F12 F14 F4 F6 F8 G11 G13 G18 G5 G7 G9 H10 H12 H14 H19 H6 H8 J11 J13 J15 J17 J18 J5 J7 J9 K1 K10 K12 K14 K16 Vss.1 Vss.2 Vss.3 Vss.4 Vss.5 Vss.6 Vss.7 Vss.8 Vss.9 Vss.10 Vss.11 Vss.12 Vss.13 Vss.14 Vss.15 Vss.16 Vss.17 Vss.18 Vss.19 Vss.20 Vss.21 Vss.22 Vss.23 Vss.24 Vss.25 Vss.26 Vss.27 Vss.28 Vss.29 Vss.30 Vss.31 Vss.32 Vss.33 Vss.34 Vss.35 Vss.36 Vss.37
Vss.38 Vss.39 Vss.40 Vss.41 Vss.42 Vss.43 Vss.44 Vss.45 Vss.46 Vss.47 Vss.48 Vss.49 Vss.50 Vss.51 Vss.52 Vss.53 Vss.54 Vss.55 Vss.56 Vss.57 Vss.58 Vss.59 Vss.60 Vss.61 Vss.62 Vss.63 Vss.64 Vss.65 Vss.66 Vss.67 Vss.68 Vss.69 Vss.70 Vss.71 Vss.72 Vss.73 Vss.74 Vss.75 Vss.76 Vss.77
K6 K8 L11 L13 L17 L19 L7 L9 M10 M12 M14 M16 M17 M18 M19 M6 M8 N11 N13 N14 N5 N7 N9 P10 P12 P14 P6 P8 R1 R11 R15 R17 R18 R19 R5 R7 R9 V19 W1 W2
SPECTRUM DIGITAL INCORPORATED Title: Page Contents: Size: B Date: TMS320DM6437 Evaluation Module DSP DACS/GND-pins DWG NO 509102-0001 Wednesday, December 06, 2006 Sheet 8 of Revision: A 34
A-9
A-10
4 3 2 1
VCC_3V3 DVDD_3V3 R317 DM6437 U1J C27 33uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF C28 33uF DVDD_3V3
+ +
0.025 C19 C20 C21 C22 C23 C24 C25 C26
TP42 TP-60 DVDD_3V3

+
TP43 TP-60 C29 C39 33uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF C30 C31 C32 C33 C34 C35 C36 C37

D
A1 A18 A2 E6 E8 F11 F13 F5 F7 F9 G14 G6 H18 H5 J1 J14 J16 J6 DVdd33.1 DVdd33.2 DVdd33.3 DVdd33.4 DVdd33.5 DVdd33.6 DVdd33.7 DVdd33.8 DVdd33.9 DVdd33.10 DVdd33.11 DVdd33.12 DVdd33.13 DVdd33.14 DVdd33.15 DVdd33.16 DVdd33.17 DVdd33.18
C VDD_CORE
+
DVdd33.19 DVdd33.20 DVdd33.21 DVdd33.22 DVdd33.23 DVdd33.24 DVdd33.25 DVdd33.26 DVdd33.27 DVdd33.28
K15 K17 L6 M15 M5 N6 P1 G8 G10 G12

C42 C41 33uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
C
DSP_CORE_VDD C VDD_CORE DM6437 U1I
C43
C44
C45
C46
C47
C48
POWER TEST POINT AT THE REGULATOR FOR 1.2 V
C VDD_CORE
+ +
C49 C56 33uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
C50
C51
C52
C53
C54
C189
C190 0.1uF
M7 M9 M11 M13 L8 L10 L12 K7 K9 K11 CVdd.1 CVdd.2 CVdd.3 CVdd.4 CVdd.5 CVdd.6 CVdd.7 CVdd.8 CVdd.9 CVdd.10
C55 33uF
CVdd.11 CVdd.12 CVdd.13 CVdd.14 CVdd.15 CVdd.16 CVdd.17 CVdd.18 CVdd.19 CVdd.20 CVdd.21
K13 J8 J10 J12 H7 H9 H11 H13 N12 N10 N8
VCC_1V8 DM6437 R319 C57 33uF 0.1uF 0.1uF C69 33uF 0.1uF DVDD_1V8
+ +
Place near DDR side of package
U1B C58 C59 C60
DVDD_1V8 C61 0.1uF C62 0.1uF C63 0.1uF C64 0.1uF C65 0.1uF C66 0.1uF C67 0.1uF C70 0.1uF C188 0.1uF
B
0.025
TP47 TP-60
TP46 TP-60
L14 L18 P11 P13 P5 P7 P9 R10 R12 DVDDR2.1 MXVDD DVDDR2.2 DVDDR2.3 DVDDR2.4 DVDDR2.5 DVDDR2.6 DVDDR2.7 DVDDR2.8 DVDDR2.9 DVDDR2.10 DVDDR2.11 DVDDR2.12 DVDDR2.13 DVDDR2.14 DVDDR2.15 DVDDR2.16 DVDDR2.17
R14 R16 R4 R6 R8 T5 V1 W18 W19
L6 0.00x R320
VCC_1V8
2 1 BLM21PG221SN1D
DM6437 U1K C71 1000pF C72 0.1uF C73 1uF TP48 TP-30 TP49 TP-30
DM6437
U1L
RSV1 PLLPWR18 L16
E5
MH1
MH4
MH2
MH5
5
4 3 2 A
MH3
MH6
6
TMS320DM6437 Evaluation Module DSP Power Pins DWG NO 509102-0001 Wednesday, December 06, 2006
1
9 10 11 12 13 14 15 16
8 7 6 5 4 3 2 1

VCC_3V3 R258 20K
D
RN12 RPACK8-20K VCC_3V3 SW1 RN13

ON
1 2 3 4 5 6 7 8
RPACK8-1.5K
6,30 YOUT0_BOOTMODE0 6,30 YOUT1_BOOTMODE1 6,30 YOUT2_BOOTMODE2 6,30 YOUT3_BOOTMODE3 6,30 YOUT4_FASTBOOT 6,30 YOUT5 6,30 YOUT6 DIP_SWITCH-8 R364 20K
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
YOUT0 YOUT1 YOUT2 YOUT3 YOUT4
-> -> -> -> ->
BootMode0 BootMode1 BootMode2 BootMode3 FASTB
VCC_3V3 R42 20K R43 20K R175 20K R176 20K
SW2
ON
1 2 3 4
R173 R44 R45 R174
1.5K 1.5K 1.5K 1.5K
8 7 6 5
DIP_SWITCH-4
1 2 3 4
R1_AEM2 R2_AEM1 B2_AEM0 R0_AEAW2
EM_A00 EM_BA0 EM_BA1 EM_A04
6,16,17,30 6,16,17,30 6,16,17,30 6,16,17,30

4 3 2
TMS320DM6437 Evaluation Module Boot DIP Switches DWG NO 509102-0001 Wednesday, December 06, 2006
1
Revision: A Sheet 10 o f 34
A-11
C81
+ C84
C82 0.1uF 10uF 0.1uF R46 33
C83
0.1uF
VCC_3V3 C78 C79 NO-POP NO-POP Y2 VCC_3V3 VCC_3V3 27MHz C85 U7 U6 0.1uF 13 13 13 13 PLL_CSEL PLL_FS1 PLL_FS2 PLL_SR R48 2.2K R49 100K TP59 TP-30 10uF VCC_3V3 0.1uF
+ C367
A-12
4 3 2 1
VCC_3V3
VCC_3V3 0.1uF U5
C77
VID_CLK
74LVC1G125DCKRG4 R47 0
1 2 3 4 X1 NC VIN GND 10 11
R350 C370 10pF R60 33 R59 NO-POP 33 PI6CX100-27W
X2 NC VDD CLKOUT XT1 XT2

R50 33
8 7 6 5
AGND VCC VDD1 VDD2 VDD3
R52 Q1 2N3904 0.1uF C88 C87
22.1K 1%
MCKO1 MCKO2 SCKO0 DGND1 SCKO1 DGND2 SCKO2 DGND3 SCKO3 PLL1705DBQ
R53 R55 R56 R57

C80
C
C86 0.1uF U8
TP69 TP-60
12 5 6 7 CSEL FS1 FS2 SR
9 8 1 13 20
5,30
PWM1
R54
33 74LVC1G125DCKRG4 R58 0
AUDIO_CLK 26,31
R51
NO-POP
4 16 17
14 15 19 18 2 3
NO-POP NO-POP 33 NO-POP
100pF VCC_3V3
B
5,6,30 CLK_OUT
R437 30 PLL_PCLK
0 C89 0.1uF U9
TP70 TP-60
VCC 2
VCC_3V3
5 A 1 B OE GND 4 3
SN74CBTLV1G125 R324 NO-POP R62 33 TINP0L 5,31
31 VIC_TINP0L_ENABLEn
R189 10K Title: Page Contents: Size:B Date:

4 3 2
SPECTRUM DIGITAL INCORPORATED TMS320DM6437 Evaluation Module VIC DWG NO 509102-0001 Wednesday, December 06, 2006
1
VCC_3V3
JP1 3 PIN JUMPER
VCC_3V3
C90 .1uF R17 RPACK8-10K 1K SW7 GS01MSAKE R7
1 2 3 4 5 6 7 8
U10
8 7 6 5
1 2 3 4

16 15 14 13 12 11 10 9
4
RN37
SILKSCREEN: NTSC by pin 1 PAL by pin 3
5,13,17,26,28,31 I2C_DATA 5,13,17,26,28,31 I2C_CLK
1K
VCC_3V3
C187 .1uF R74 10K SW4 PADDLE DIP-4
5 4 2 1 20 19 17 16 18 13 VDD A0 SDA A1 SCL A2 INT P0 P7 P1 P6 P2 P5 P3 P4 GND NC.4 NC.1 NC.3 NC.2 PCF8574APWRG4
6 7 9 10 11 12 14 15 3 8
RN38
5 6 7 8
4 3 2 1
RPACK4-1K
5
SILKSCREEN: USER SWITCHES
I2C_INT
2 1
U66 SN74AHC1G14DCKRG4
VCC_3V3 VCC_3V3 VCC_3V3
USER CONTROLLED LEDS

R64 330 VCC_3V3 R65 330 R66 330 R67 330
C91 .1uF
RN20 RPACK4-10K
U11
DS1 LED_GRN
DS2 LED_GRN
DS3 LED_GRN
DS4
LED_RED
31 USER_I2C_IO.A0P7 31 USER_I2C_IO.A0P6
5 4 2 1 20 19 17 16 18 13
VDD SDA SCL INT P7 P6 P5 P4 NC.4 NC.3
A0 A1 A2 P0 P1 P2 P3 GND NC.1 NC.2

PCF8574APWRG4
6 7 9 10 11 12 14 15 3 8
25,32 VLYNQ_RESET

4 3 2
TMS320DM6437 Evaluation Module I2C Expanders DWG NO 509102-0001 Wednesday, December 06, 2006
1
Revision: C Sheet 12 o f 34
A-13
1 2 3 4
A-14
4 3 2 1
VCC_3V3
R252 NO-POP
D
SW3 R161
2
1K MEM_EMD7-0_SELECT 15 DIP_SWITCH-2
4 3
1
1 2
VCC_3V3 VCC_3V3 VCC_3V3 U73 C205 0.1uF
5,12,17,26,28,31 I2C_DATA 5,12,17,26,28,31 I2C_CLK
8 7 6 5
U13
R185 10K
11 11 11 11
PLL_CSEL PLL_FS1 PLL_FS2 PLL_SR
1 2 3 4
5 4 2 1 20 19 17 16 18 13
USER_I2C_IO.A1P0 USER_I2C_IO.A1P1 USER_I2C_IO.A1P2 USER_I2C_IO.A1P3 VCC_3V3 C170 0.1uF 31 31 31 31
6 7 9 10 11 12 14 15 3 8
5
VDD A0 SDA A1 SCL A2 INT P0 P7 P1 P6 P2 P5 P3 P4 GND NC.4 NC.1 NC.3 NC.2 PCF8574APWRG4 4 2 1
3
VCC_3V3
RPACK4-10K RN22
8 7 6 5
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
5 4 2 1 20 19 17 16 18 13 VDD SDA SCL INT P7 P6 P5 P4 NC.4 NC.3

PCF8574APWRG4
A0 A1 A2 P0 P1 P2 P3 GND NC.1 NC.2
6 7 9 10 11 12 14 15 3 8
SPDIF_ONn 26 I2C.IOP3

31 AIC33_ENABLEn
1 4 2
SN74LVC1G32 McBSP_ONn 26
C
C92 0.1uF VCC_3V3
RN34 RPACK4-10K
U42 SN74AHC1G14DCKRG4
VCC_3V3 VCC_3V3
VCC_3V3 RN15 RPACK8-10k
C185 0.1uF U64
VCC_3V3
C206 0.1uF U74
5,12,17,26,28,31 I2C_DATA 5,12,17,26,28,31 I2C_CLK
1 4 2
SN74LVC1G32 McASP_ONn 26
SPECTRUM DIGITAL INCORPORATED I2C.IOP4 I2C.IOP5 I2C.IOP6 CORE_VDD_SELECT 33 Title: Page Contents: Size:B Date: TMS320DM6437 Evaluation Module I2C Expanders DWG NO 509102-0001 Wednesday, December 06, 2006
3 2 1

4
7 DDR_A[0:12] U16 VCC_1V8 U17 VCC_1V8

C94 22uF 0.1uF 0.1uF 0.1uF 0.1uF C98 0.1uF C99 0.1uF C100 0.1uF C95 C96 C97
+ C102 +
DDR_A12 DDR_A11 DDR_A10 DDR_A9 DDR_A8 DDR_A7 DDR_A6 DDR_A5
V2 U7 R2 U3 U8 U2 T7 T3 A12 A11 A10 A9 A8 A7 A6 A5

C104 0.1uF VREF_STL C112 0.1uF DDR_BS02 DDR_BS01 DDR_BS00 0.1uF 0.1uF 0.1uF DDR_A4 DDR_A3 DDR_A2 DDR_A1 DDR_A0 C105 C93 C106 C107 0.1uF C108 0.1uF C109 0.1uF
DDR_A12 DDR_A11 DDR_A10 DDR_A9 DDR_A8 DDR_A7 DDR_A6 DDR_A5
V2 U7 R2 U3 U8 U2 T7 T3 A12 A11 A10 A9 A8 A7 A6 A5 VDD.1 VDD.2 VDD.3 VDD.4 VDD.5 VDDQ.1 VDDQ.2 VDDQ.3 VDDQ.4 VDDQ.5 VDDQ.6 VDDQ.7 VDDQ.8 VDDQ.9 VDDQ.10
VREF_STL C113 0.1uF
C101 0.1uF
C103 22uF
DDR_A4 DDR_A3 DDR_A2 DDR_A1 DDR_A0
VDD.1 VDD.2 VDD.3 VDD.4 VDD.5 VDDQ.1 VDDQ.2 VDDQ.3 VDDQ.4 VDDQ.5 VDDQ.6 VDDQ.7 VDDQ.8 VDDQ.9 VDDQ.10 VDDL VREF
BDDR_D[0:15] BDDR_D15 BDDR_D14 BDDR_D13 BDDR_D12
M9 H1 R9 D1 V1 F3 F7 K1 K3 K7 K9 D9 F1 F9 H9 M1 VDDL VREF E9 E1 G9 G1 G3 G7 F2 F8 DQ11 DQ10 DQ9 DQ8 M2

BDDR_D31 BDDR_D30 BDDR_D29 BDDR_D28 BDDR_D27 BDDR_D26 BDDR_D25 BDDR_D24
M9 H1 R9 D1 V1 F3 F7 K1 K3 K7 K9 D9 F1 F9 H9 M1
BDDR_D[16:31] RN24 BDDR_D26 BDDR_D29 BDDR_D24 BDDR_D31
C110 0.1uF
7 DDR_BS02 7 DDR_BS01 7 DDR_BS00
DDR_BS02 DDR_BS01 DDR_BS00
T8 T2 R7 R3 R8 P1 P3 P2 A4 A3 A2 A1 A0 BA2 BA1 BA0 M2 E9 E1 G9 G1 DQ15 DQ14 DQ13 DQ12 G3 G7 F2 F8

BDDR_D11 BDDR_D10 BDDR_D9 BDDR_D8 VREF_STL
T8 T2 R7 R3 R8 P1 P3 P2 A4 A3 A2 A1 A0 BA2 BA1 BA0
VREF_STL 7
RPACK4-22
4 3 2 1
RN26 BDDR_D28 4 BDDR_D30 3 BDDR_D25 2 BDDR_D27 1
5 6 7 8
D DR_D26 D DR_D29 D DR_D24 D DR_D31 RPACK4-22 5 D DR_D28 6 D DR_D30 7 D DR_D25 8 D DR_D27

C
AA9 AA8 AA2 AA1 D2 V8 A9 A8 A2 A1 H2 NC.1 NC.2 NC.3 NC.4 NC.5 NC.6 NC.7 NC.8 NC.9 NC.10 NC.11 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8
RN23 BDDR_D13 1 BDDR_D15 2 BDDR_D8 3 BDDR_D10 4 RN25 BDDR_D5 4 BDDR_D7 3 BDDR_D2 2 BDDR_D0 1 RPACK4-22 8D DR_D13 7D DR_D15 6DDR _D8 5D DR_D10 RPACK4-22 5DDR _D5 6DDR _D7 7DDR _D2 8DDR _D0
AA9 AA8 AA2 AA1 D2 V8 A9 A8 A2 A1 H2 NC.1 NC.2 NC.3 NC.4 NC.5 NC.6 NC.7 NC.8 NC.9 NC.10 NC.11
R78
22
V3 V7 N9 RFU.1 RFU.2 ODT

R79 22
DQ7 DQ6 DQ5 DQ4 V3 V7 N9 DQ3 DQ2 DQ1 DQ0

DDR_ CS DDR_CAS DDR_RAS DDR_WE DDR_CKE DDR_CLK DDR_CLK_N
J9 J1 L9 L1 L3 L7 K2 K8
BDDR_D3 BDDR_D2 BDDR_D1 BDDR_D0
BDDR_D7 BDDR_D6 BDDR_D5 BDDR_D4
RFU.1 RFU.2 ODT
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
J9 J1 L9 L1 L3 L7 K2 K8
BDDR_D23 BDDR_D22 BDDR_D21 BDDR_D20 BDDR_D19 BDDR_D18 BDDR_D17 BDDR_D16
RN28 BDDR_D23 BDDR_D16 BDDR_D18 BDDR_D21 RN30 BDDR_D19 BDDR_D17 BDDR_D22 BDDR_D20
7 DDR_CS 7 DDR_CAS 7 DDR_RAS 7 DDR_WE 7 DDR_CKE
DDR_CS DDR_CAS DDR_RAS DDR_WE DDR_CKE
P8 P7 N7 N3 N2 CS# CAS# RAS# WE# CKE CK CK# M8 N8
BDDR_D12 4 BDDR_D14 3 BDDR_D11 2 BDDR_D9 1 RN27 BDDR_D4 1 BDDR_D6 2 BDDR_D3 3 BDDR_D1 4 RN29
5D DR_D12 6D DR_D14 7D DR_D11 8DDR _D9 RPACK4-22 8DDR _D4 7DDR _D6 6DDR _D3 5DDR _D1 RPACK4-22 P8 P7 N7 N3 N2 M8 N8 CS# CAS# RAS# WE# CKE
1 2 3 4 4 3 2 1
RPACK4-22 8 D DR_D23 7 D DR_D16 6 D DR_D18 5 D DR_D21 RPACK4-22 5 D DR_D19 6 D DR_D17 7 D DR_D22 8 D DR_D20
7 DDR_CLK 7 DDR_CLK_N
DDR_CLK DDR_CLK_N
CK CK#
7 DDR_DQS1 7 DDR_DQS2 7 DDR_DQM3 7 DDR_DQM2 DDR_DQS2 22
DDR_DQS1 R80 7 DDR_DQS3
22 BDDR_DQS1
DDR_DQS3 22
R81 R83 DDR_DQM3 DDR_DQM2
BDDR_DQS3 BDDR_DQS2
7 DDR_DQS0
DDR_DQS0 R82
22 BDDR_DQS0
D8 E7 H8 J7 E3 J3
D8 E7 H8 J7 E3 J3
7 DDR_DQM1 7 DDR_DQM0
DDR_DQM1 DDR_DQM0
VSS.1 VSS.2 VSS.3 VSS.4 VSS.5 VSSQ.1 VSSQ.2 UDQS#/NU VSSQ.3 UDQS VSSQ.4 LDQS#/NU VSSQ.5 LDQS VSSQ.6 VSSQ.7 VSSQ.8 UDM VSSQ.9 LDM VSSQ.10 VSSDL 92-ball DDR Package
U9 T1 H3 D3 M3 G8 J8 D7 J2 E2 L8 L2 E8 H7 G2 M7
VSS.1 VSS.2 VSS.3 VSS.4 VSS.5 VSSQ.1 VSSQ.2 UDQS#/NU VSSQ.3 UDQS VSSQ.4 LDQS#/NU VSSQ.5 LDQS VSSQ.6 VSSQ.7 VSSQ.8 UDM VSSQ.9 LDM VSSQ.10 VSSDL 92-ball DDR Package
U9 T1 H3 D3 M3 G8 J8 D7 J2 E2 L8 L2 E8 H7 G2 M7
64 MEGABYTES
64 MEGABYTES
7 DDR_D[0:31] SPECTRUM DIGITAL INCORPORATED

A
Layout schematic is shown for the 92-ball DDR Package but is compatible with 84-ball DDR2 Devices.
Title: Page Contents: Size:B Date:
TMS320DM6437 Evaluation Module DDR2 Memories DWG NO 509102-0001 Wednesday, December 06, 2006 Sheet 14 o f Revision: A 34
A-15
A-16
VCC_3V3 C114 0.1uF VCC_3V3 U18 6,30 C_FIELD U19
VCC VCC 4 7 9 12
MEM.EM_D7 MEM.EM_D6 MEM.EM_D1 MEM.EM_D0
24 16
MEM.EM_D[7:0] 16,17
C115 0.1uF
D
VCC_3V3 22,30 22,30 22,30 22,30 VCC_3V3 B.CI7 B.CI6 B.CI5 B.CI4 B.CI7 B.CI6 B.CI5 B.CI4 B.C I0 B.C I1 B.C I6 B.C I7
MEM.EM_A21 MEM.EM_A13 MEM.EM_A14 MEM.EM_A15 MEM.EM_A16
2 5 11 14 1B1 2B1 3B1 4B1 1A 2A 3A 4A
R88 NO-POP 22,30 22,30 22,30 22,30 R90 NO-POP 6,30 6,30 6,30 6,30 COUT7 COUT6 COUT1 COUT0 B.CI3 B.CI2 B.CI1 B.CI0 B.CI3 B.CI2 B.CI1 B.CI0 MEM.EM_A17 MEM.EM_A18 MEM.EM_A19 MEM.EM_A20 COUT7 COUT6 COUT1 COUT0
30 CI_EMA_ENABLEn
3 4 7 8 11 14 17 18 21 22 1A1 1A2 1A3 1A4 1A5 2A1 2A2 2A3 2A4 2A5 3 6 10 13 1B2 2B2 3B2 4B2 1OE 2OE GND
BMEM_EMD7-0_SELECT
1B1 1B2 1B3 1B4 1B5 2B1 2B2 2B3 2B4 2B5 12
30 MEM_EMD7-0_ENABLEn
2 5 6 9 10 15 16 19 20 23 15 1 OE S GND 8
74CBTLV3257PWR
1 13
SN74CBTLV3384PW R248 10K
R247 10K
R89 MEM.EM_A21 17 MEM.EM_A[20:13] 16,17
C195 .1uF

47K MEM.EM_A21 VCC_3V3 VCC_3V3 U20 VCC_3V3 C116 0.1uF
C
VCC_3V3
C196 0.1uF RPACK8-47K R91 10K U71 B.CI2 B.CI3 B.CI4 B.CI5
16 15 14 13 12 11 10 9 RN31 2 5 11 14 1B1 2B1 3B1 4B1 VCC 16
1 2 3 4 5 6 7 8
MEM.EM_A20 MEM.EM_A19 MEM.EM_A18 MEM.EM_A17 MEM.EM_A13 MEM.EM_A14 MEM.EM_A15 MEM.EM_A16
1 4 2
SN74LVC1G32 6,30 6,30 6,30 6,30 COUT5 COUT4 COUT3 COUT2 COUT5 COUT4 COUT3 COUT2
2 1
1A 2A 3A 4A 3 6 10 13 15 1 1B2 2B2 3B2 4B2
4 7 9 12
MEM.EM_D5 MEM.EM_D4 MEM.EM_D3 MEM.EM_D2
SN74AHC1G14DCKRG4
U69
OE S
GND
8
74CBTLV3257PWR
13 MEM_EMD7-0_SELECT
R451
BMEM_EMD7-0_SELECT
JP2 6 EM_CS2
1 3 5 7
FLASH_CEn 17 SRAM_CEn 16 NAND_CEn 16 DC_EM_CS2n 30 CONN 4x2
2 4 6 8
EM_CS2 SELECT PIN 1 TO 2 FLASH PIN 3 TO 4 NAND FLASH PIN 5 TO 6 SRAM PIN 7 TO 8 DAUGHTERCARD
4 3 2
SPECTRUM DIGITAL INCORPORATED TMS320DM6437 Evaluation Module EMIF Muxing DWG NO 509102-0001 Wednesday, December 06, 2006
1
VCC_3V3
C118 0.1uF 6,10,17,30 EM_BA0 0 R75 NO-POP MEM.EM_A18 MEM.EM_A17 MEM.EM_A16 MEM.EM_A15 MEM.EM_A14 MEM.EM_A13 VCC_3V3 17,22,30 17,22,30 17,22,30 17,22,30 17,22,30 17,22,30 17,22,30 17,22,30 VCC_3V3 R107 10K 6,10,17,30 EM_A04 6,17,30 EM_A03 6,17,30 EM_A02_CLE 6,17,30 EM_A01_ALE 6,10,17,30 EM_A00 6,10,17,30 EM_BA1 B.EM_A12 B.EM_A11 B.EM_A10 B.EM_A09 B.EM_A08 B.EM_A07 B.EM_A06 B.EM_A05 0.1uF
C119
VDD.1 VDD.2
D1 E6
GND.1 GND.2
NC.A1 NC.A2 NC.B1
NC.A9 NC.A10 NC.B9 NC.B10
NC.L1 NC.L2 NC.M1 NC.M2
NC.L9 NC.L10 NC.M9 NC.M10
A1 A2 B1
L1 L2 M1 M2
A9 A10 B9 B10
L9 L10 M9 M10

D6 E1
U22
D
15,17 MEM.EM_A[18:13]
R94
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
B6 C5 C6 D5 E5 F5 F6 G6
MEM.EM_D0 MEM.EM_D1 MEM.EM_D2 MEM.EM_D3 MEM.EM_D4 MEM.EM_D5 MEM.EM_D6 MEM.EM_D7
MEM.EM_D[7:0] 15,17
R93 10K
H6 G2 H1 D3 E4 F4 F3 G4 G3 H5 H4 H3 H2 D4 C4 C3 B4 B3 A5 A4 A3 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 NC.2 NC.3 NC.7 NC.8 NC.9 NC.10 NC.4 NC.5 A1 B2 E3
R70 NO-POP R69 0
B1 C1 C2 D2 E2 F2 F1 G1
15 SRAM_CEn 6,17,30 WRITE_WE 6,17,30 READ_OE
B5 A6 CE CE2 NC.11 WE OE G5 A2
NC.1 NC.6
IS62WV102416BLL-10MLI
VCC_3V3
R95 0
VCC_3V3 U23 R96 10K R98 6,30 WAIT_BSYn 6,17,30 READ_OE 15 NAND_CEn VCC_3V3 VCC_3V3 R100 10K 6,17,30 EM_A02_CLE 6,17,30 EM_A01_ALE 6,17,30 WRITE_WE C122 .1uF 0 R97 10K
VCC_3V3
MEM.EM_D7 MEM.EM_D6 MEM.EM_D5 MEM.EM_D4 VCC_3V3 C123 .1uF
R101 NO-POP
D3 D6 D7 D8 E3 C5 C8 D4 C6 E4 E5 H8 K3 E6 E7 D5 C4 C7 C3 E8 F3 F4 F5 F6 NC.D3 NC.D6 NC.D7 NC.D8 NC.E3 GND1 R/#B #RE #CE NC.E4 NC.E5 VCC1 GND2 NC.E6 NC.E7 CLE ALE #WE #WP NC.E8 NC.F3 NC.F4 NC.F5 NC.F6
NAND512W3A2BZA6E NC.J5 J5 NC.J3 J3 NC.H7 H7 NC.H6 H6 I/O7 J8 I/O6 K7 I/O5 J7 I/O4 K6 NC.H5 H5 NC.H3 H3 NC.G7 G7 VCC2 J6 GND3 K8 NC.G6 G6 NC.G5 G5 NC.G4 G4 I/O3 K5 I/O2 K4 I/O1 J4 I/O0 H4 PRE G8
R99
MEM.EM_D3 MEM.EM_D2 MEM.EM_D1 MEM.EM_D0 NO-POP
NC.G3 NC.F8 NC.F7
G3 F8 F7
SPECTRUM DIGITAL INCORPORATED
A
CE DON'T CARE DEVICE
TMS320DM6437 Evaluation Module NAND-Flash/SRAM DWG NO 509102-0001 Wednesday, December 06, 2006 Sheet 16 o f Revision: B 34
A-17
A-18
U24 MEM.EM_D0 MEM.EM_D1 MEM.EM_D2 MEM.EM_D3 MEM.EM_D4 MEM.EM_D5 MEM.EM_D6 MEM.EM_D7
D
MEM.EM_D[7:0] 15,16
VCC_3V3
15,16 MEM.EM_A[20:13] 0 EM_BA0 6,10,16,30 VCC_3V3
6,10,16,30 EM_BA1 6,10,16,30 EM_A00 6,16,30 EM_A01_ALE 6,16,30 EM_A02_CLE 6,16,30 EM_A03 6,10,16,30 EM_A04 16,22,30 B.EM_A05 16,22,30 B.EM_A06 16,22,30 B.EM_A07 16,22,30 B.EM_A08 16,22,30 B.EM_A09 16,22,30 B.EM_A10 16,22,30 B.EM_A11 16,22,30 B.EM_A12 R102 10K
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15/A-1 RY/BY VCC
VCC_3V3
E3 H3 E4 H4 H5 E5 H6 E6 F3 G3 F4 G4 F5 G6 F6 G7 A4 G5 F1 D8
C124 0.1uF VCC_3V3
MEM.EM_A13 MEM.EM_A14 MEM.EM_A15 MEM.EM_A16 MEM.EM_A17 MEM.EM_A18 MEM.EM_A19 MEM.EM_A20 NO-POP 0
R103 10K 15 MEM.EM_A21 6,10,16,30 EM_BA0 R153 R154
R105 NO-POP
E2 D2 C2 A2 B2 D3 C3 A3 B6 A6 C6 D6 B7 A7 C7 D7 E7 B3 C4 D5 D4 C5 B8 C8 F8 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 NC/A24 VIO.1 VIO.2 BYTE CE OE WE
C183 0.1uF C125 0.1uF
F7 F2 G2 A5 B5 RESET WP/ACC B4
VCC_3V3
VSS.1 VSS.2 VSS.3
H2 H7 E8

6,16,30 READ_OE 6,16,30 WRITE_WE R71 10K 3,19,26,28,30,33 SYS_RESETn
15 FLASH_CEn
NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10
A1 B1 C1 D1 E1 G1 H1 A8 G8 H8
R104 10K
S29GL256N11FFI010
R106 NO-POP
VCC_3V3 C126 0.1uF U25
8 VCC SDA SCL

CAT24C256 5,12,13,26,28,31 I2C_DATA 5,12,13,26,28,31 I2C_CLK
5 6
A0 A1 A2 WP VSS
1 2 3 7 4
Internal pull-downs
VCC_3V3 C366 R309 10K U65 VCC_3V3 5,31 FSX0 5,26,31 DR0 10K R310 SPECTRUM DIGITAL INCORPORATED
A
0.1uF
1 2 3 4
CS SO WP GND
VCC HOLD SCK SI
8 7 6 5
SOCKETED_SPI_EEPROM
CLKX0 DX0
5,26,31 5,26,31
TMS320DM6437 Evaluation Module NOR-Flash/EEPROM DWG NO 509102-0001 Wednesday, December 06, 2006
3 2 1

4
VCC_3V3 C128 0.1uF U27
VCC
24
R358 1K
8 7 6 5
VCC_3V3
1 2 3 4
8 7 6 5
1 2 3 4

VCC_3V3
D
C175 0.1uF U14
23,31 B.TXD2 23,31 B.TXD3 23,31 B.RXCLK 23,31 B.COL 23,31 B.CRS 23,31 B.RXD2 23,31 B.RXD3 23,31 B.MDC 23,31 B.MDIO
3 4 7 8 11 14 17 18 21 22 1A1 1A2 1A3 1A4 1A5 2A1 2A2 2A3 2A4 2A5 1OE 2OE GND 12 1B1 1B2 1B3 1B4 1B5 2B1 2B2 2B3 2B4 2B5
EPHY.TXD2 19 EPHY.TXD3 19 EPHY.RX_CLK 19 EPHY.COL 19 EPHY.CRS 19 EPHY.RXD2 19 EPHY.RXD3 19 EPHY.MDC 19 EPHY.MDIO 19
2 5 6 9 10 15 16 19 20 23
1 4 2
SN74CBTLV3384PW SN74LVC1G32
1 13
VCC_3V3 C127 0.1uF
RN35 RPACK4-100K U26 23,31 23,31 23,31 23,31 B.TXCLK B.TXD0 B.TXD1 B.TXEN
2 5 11 14 1B1 2B1 3B1 4B1 1B2 2B2 3B2 4B2 1A 2A 3A 4A 4 7 9 12 VCC 3 6 10 13
16
EPHY.TXCLK 19 EPHY.TXD0 19 EPHY.TXD1 19 EPHY.TX_EN 19
R326 NO-POP
31 ENET_ENABLEn
15 1
OE S
GND
8
74CBTLV3257PWR
R246 10K
VCC_3V3
RN36 RPACK4-100K
U28 23,31 23,31 23,31 23,31 B.RXD0 B.RXD1 B.RXDV B.RXER
C129 0.1uF
2 5 11 14
1B1 2B1 3B1 4B1
VCC
16
1A 2A 3A 4A 3 6 10 13 15 1 1B2 2B2 3B2 4B2
4 7 9 12
EPHY.RXD0 19 EPHY.RXD1 19 EPHY.RX_DV 19 EPHY.RX_ER 19 Title: Page Contents:
SPECTRUM DIGITAL INCORPORATED TMS320DM6437 Evaluation Module ENET Muxing
OE S
GND
8
74CBTLV3257PWR
Size: B Date:
4 3 2
DWG NO
509102-0001 Wednesday, December 06, 2006

1
A-19
13
7 24
U30
31 38
47
VDDRX VDDRCV
VDDPLL
R111
22
VDDIO1 VDDIO2
VDDC1
TXC142
40
RXD+ RXD-CT RXD-
18 18 18 18 18
EPHY.TXCLK EPHY.TXD0 EPHY.TXD1 EPHY.TXD2 EPHY.TXD3
15 17 18 19 20 TX+ TX_CLK/REF_CLK TXD0 TXD1 TXD2 TXD3 TX_EN TX_ER

1000pF 2kV
18 EPHY.TX_EN
16 14 RX+ RXFXSD/FXEN
R114 R123 R126 NO-POP NO-POP R120 NO-POP R115 49.9 R117 49.9
33 32
GND_E_ENET
GND_E_ENET
GND1 GND2 GND3 GND4 GND5 GND6 GND7
8 12 23 35 36 39 44

4 3 2 1
R112 NO-POP
R113 NO-POP
R119
NO-POP
R116
VCC_3V3 NO-POP
34
C
R121
NO-POP
R118
NO-POP
VDD_3V3A
NC1 NC2
NO_POP R124 R127 330 EPHY.LED0 6.65K
42 43 37 26 27 28 29
VCC_3V3 R131 10K R128 330 EPHY.LED2 R130 NO-POP
REXT
RN32
C143 0.1uF R129 NO-POP
18 EPHY.COL 18 EPHY.CRS 18 EPHY.RXD0 18 EPHY.RXD1 18 EPHY.RXD2 18 EPHY.RXD3 18 EPHY.RX_DV 18 EPHY.RX_ER VCC_3V3 18 EPHY.RX_CLK R132 10
1 2 3 4 5 6 7 8 21 22 6 5 4 3 9 11 10 RX_CLK XI
18 EPHY.MDC VCC_3V3
RPACK8-10 16 15 14 13 12 11 10 9
LED0/TEST COL/RMII CRS/RMII_BTB LED1/SPD100 RXD0/PHYAD4 RXD1/PHYAD3 LED2/DUPLEX RXD2/PHYAD2 RXD3/PHYAD1 LED3/NWAYEN RX_DV/CRSDV/PCS_LPBK RX_ER/ISO 46
L55 BLM21PG221SN1D L56 BLM21PG221SN1D .1uF

B
2 MDC MDIO INT#/PHYAD0 1 48 RESET# 2 PD# GND OUT 25MHz 30 EN VCC 4 3 R249
U72
R133
1
1.5K TP12 TP-30
XO
45
C199
18 EPHY.MDIO
25
3,17,26,28,30,33 SYS_RESETn
22 R134 R137 NO-POP L8 BLM21PG221SN1D NO-POP VCC_3V3 VDD_3V3A
R135 NO-POP KS8001L
R136 NO-POP
VCC_3V3
R192 10K
13 14
S1 S0
A-20
PHY_1V8 VDD_1V8RX VDD_3V3A VCC_3V3 C130 0.1uF 4.7uF VDD_3V3A C134 P3 C138 0.1uF VDD_1V8PLL C136 0.1uF R109 49.9 R110 49.9 EPHY.LED2 C137 4.7uF C139 4.7uF 0.1uF EPHY.LED0 RJ45 HALO HFJ11-2450E-L21
D
SILKSCREEN: ETHERNET
+ C133
C131 0.1uF
C132 4.7uF
12 11 10 9 LED2LED2+ LED1LED1+ NC1 GND TXD+ TXD-CT TXD7 8 1 4 2
C140 0.1uF
C141 4.7uF
41
3 5 6
GND_E_ENET
SPECTRUM DIGITAL INCORPORATED PHY_1V8 VDD_1V8PLL L9 BLM21PG221SN1D VDD_1V8RX Size: B L11 BLM21PG221SN1D Date:
4 3 2
Title: Page Contents:
TMS320DM6437 Evaluation Module ENET DWG NO 509102-0001 Wednesday, December 06, 2006
1
R328 NO-POP R362 VCC_5V R361 R363 C150 C146 0.1uF 0.1uF R188 10K NO-POP R360 0 NO-POP 0 VCC_3V3
1OE 2OE 3OE 4OE GND 7 SN74CBTLV3125PWRG4

VCC_3V3 R342 SN65HVD235DRG4
0 C149 100pF_NO-POP D2 PGB0010603_NO-POP R140 0 R141 120
TP14 TP-60
31 CAN_ENABLEn
GND_E_CAN C151 4700pF_NO-POP

B

4 3 2 1 D
VCC_3V3 VCC_3V3 R138 10K
C147 0.1uF R139 C148 100pF_NO-POP 10K GND_E_CAN DB9-FEMALE D1 PGB0010603_NO-POP TP13 TP-60
C
U32
5,21,31 TOUT1L
VCC
U31 CAN_D
14 3 4 1
T1
R343
5,21,31 TINP1L
2 5 9 12 1A 2A 3A 4A 2 1B 2B 3B 4B
CAN_R R256 33
B_CANH B_CANL
VCC_3V3
3 6 8 11 D GND VCC R NC.2 CANH CANL NC.1
1 2 3 4
8 7 6 5
1 4 10 13
ACT45B-510-2P_NO-POP
5 9 4 8 3 7 2 6 1
P7
Texas Instruments Title: Page Contents: Size: B Date:

4 3 2
TMS320DM6437 Evaluation Module CAN DWG NO 509102-0001 Wednesday, December 06, 2006
1
A-21
A-22
4 3 2 1 D
VCC_3V3 C153 1uF U34

+
VCC_3V3 C154 47uF R142 10K R143 10K
VCC_3V3
VCC_3V3
C152 .1uF
15 VCC FORCEON VCC

L12 1uH UART_TXD UART_RXD
FORCEOFF 12
16
GND_E_RS232 DB9-MALE
U33 5,31 5,31 UTXD0 URXD0
16 11 T_IN
C155 10pF R257 33 C156 10pF GND_E_RS232 L13 1uH
31 RS232_ENABLEn
15 1 OE S GND
R145 GND_E_RS232 0
8 EN INVALID
10
C157 10pF
C158 10pF GND_E_RS232
74CBTLV3257PWR VCC_3V3 GND_E_RS232
R187 10K
R146 NO-POP
2 C1+
C160 1uF
C2+
C159 1uF
4
R147 10K
C1V+ 3 7
C161 1uF
C2-
14 GND
MAX3221CPWRG4
V-
C162 1uF
B
L57 BLM21PG221SN1D L58 BLM21PG221SN1D
GND_E_RS232

VCC_3V3 5,20,31 TOUT1L 5,20,31 TINP1L
2 5 11 14 1B1 2B1 3B1 4B1 1A 2A 3A 4A 9 R_OUT R_IN 8

GND_E_RS232
4 7 9 12 T_OUT
13
R144 NO-POP
3 6 10 13 1B2 2B2 3B2 4B2
5 9 4 8 3 7 2 6 1
P8
GND_E_CAN

4 3 2
TMS320DM6437 Evaluation Module RS232 DWG NO 509102-0001 Wednesday, December 06, 2006
1
23 C184 0.1uF 23,24 PCI_P_AD[31:0] 0.1uF U52 C186
PCI4.1V
17
VCC.1
17
VCC.1
GND.4 GND.3 GND.2 GND.1
R337
R338 NO-POP
49 38 19 8
49 38 19 8
S OE
GND
SN74CBT3257PW
15,30
B.CI2

U51 23 PCI_DETECTn
D
24 PCI_P_CLK 24 PCI_P_GNTn 24 PCI_P_REQn
S
R158 PCI_P_AD16 PCI_P_AD17 PCI_P_AD18 PCI_P_AD19 PCI_P_AD20 PCI_P_AD21 PCI_P_AD22 PCI_P_AD23 24 PCI_P_IDSEL
1
24 PCI_P_IRDYn 24 PCI_P_FRAMEn 24 PCI_P_C/BEn2
PCI_DETECTn
PCI_DETECTn
23,24 PCI_P_AD[31:0] PCI_P_AD31 PCI_P_AD30 PCI_P_AD29 PCI_P_AD28 PCI_P_AD27 PCI_P_AD26 PCI_P_AD25 PCI_P_AD24
24 PCI_P_C/BEn3 22 R333
54 52 50 47 45 43 41 39 36 34 32 30 1B1 2B1 3B1 4B1 5B1 6B1 7B1 8B1 9B1 10B1 11B1 12B1 1A 2A 3A 4A 5A 6A 7A 8A 9A 10A 11A 12A
PCICLK CI4 CI1 CI3 AD30 CI5 AD28 CI6 AD26 CI7 EM_A11 EM_A12 6 6 6 6 6 6 6 6 6 6 6 6
2 4 6 9 11 13 15 18 21 23 25 27
0 PCI_S_CLKOUT0 PCI_S_GNTn PCI_S_REQn0 PCI_S_AD31 PCI_S_AD30 PCI_S_AD29 PCI_S_AD28 PCI_S_AD27 PCI_S_AD26 PCI_S_AD25 PCI_S_AD24 PCI_S_C/BEn3
54 52 50 47 45 43 41 39 36 34 32 30 1B1 2B1 3B1 4B1 5B1 6B1 7B1 8B1 9B1 10B1 11B1 12B1
1A 2A 3A 4A 5A 6A 7A 8A 9A 10A 11A 12A
2 4 6 9 11 13 15 18 21 23 25 27
PCI_S_AD16 PCI_S_AD17 PCI_S_AD18 PCI_S_AD19 PCI_S_AD20 PCI_S_AD21 PCI_S_AD22 PCI_S_AD23
PIDRDYn 6 PFRAMEn 6 PCBE2n 6 AD16 6 AD17 6 AD18 6 EM_A05 6 EM_A06 6 EM_A08 6 EM_A07 6 EM_A10 6 EM_A09 6
25,32 VLYNQ_CLOCK
22 0 0 0 0 0 RN3A RN3B RN3C RN3D RN3E RN3F
15,30 B.CI4 15,30 B.CI1 15,30 B.CI3 15,30 B.CI5 15,30 B.CI6 15,30 B.CI7 16,17,30 B.EM_A11 16,17,30 B.EM_A12
1 2 3 4 5 6 7 8 1 2 3 4 5 6 A A A A A A B B B B B B 16 15 14 13 12 11
RN5 RPACK8-33 R339 NO-POP SN74CBT16292DGGR
16 15 14 13 12 11 10 9
53 51 48 46 44 42 40 37 35 33 31 29 1B2 2B2 3B2 4B2 5B2 6B2 7B2 8B2 9B2 10B2 11B2 12B2 NC.1 NC.2 NC.3 NC.4 NC.5 NC.6 NC.7 NC.8 NC.9 NC.10 NC.11 NC.12 NC.13 NC.14
3 5 7 10 12 14 16 20 22 24 26 28 55 56
25,32 VLYNQ_TXD0 25,32 VLYNQ_RXD3 25,32 VLYNQ_RXD2 25,32 VLYNQ_RXD0 25,32 VLYNQ_RXD1 25,32 VLYNQ_SCRUN 16,17,30 B.EM_A05 16,17,30 B.EM_A06 16,17,30 B.EM_A08 16,17,30 B.EM_A07 16,17,30 B.EM_A10 16,17,30 B.EM_A09
R307 R308 R329 R347 R331 R332 RPACK8-22 RPACK8-22 RPACK8-22 RPACK8-22 RPACK8-22 RPACK8-22
53 51 48 46 44 42 40 37 35 33 31 29
1B2 2B2 3B2 4B2 5B2 6B2 7B2 8B2 9B2 10B2 11B2 12B2
NC.1 NC.2 NC.3 NC.4 NC.5 NC.6 NC.7 NC.8 NC.9 NC.10 NC.11 NC.12 NC.13 NC.14
3 5 7 10 12 14 16 20 22 24 26 28 55 56
SN74CBT16292DGGR RN3G
C361 5.6pF C364 5.6pF 24 PCI_P_PINTAn 15,30 B.CI0 R171 0 PCI_P_PINTAn
C362 NO-POP
C363 RN3H NO-POP
7 8
A B A B
10 RPACK8-22 9 RPACK8-22
R181 23 PCI4.1V VCC_3V3 C178 0.1uF C144 U12 U40 0.1uF VCC_3V3
PCI4.1V
VCC 1A 2A 3A 4A
16 4 7 9
VCC_3V3 VCC_3V3 PCI_S_PINTAn PCI_S_RSTn CI0 CI2 6 6
24 PCI_P_RSTn
1 4
SN74LVC1G08
NO-POP
3,31 RESET_OUTn
2 3 5 6 11 10 14 13 1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2 1 15

PCI_DETECTn
12
C120
R170 10K
0.1uF
SPECTRUM DIGITAL INCORPORATED R177 NO-POP Title: TMS320DM6437 Evaluation Module
2 1
RESETn 3,4,30 U36 SN74LVC1G07

NO-POP
Page Contents: Size:B Date:
PCI-Switches DWG NO 509102-0001 Wednesday, December 06, 2006 Sheet 22 o f Revision: B 34
R172
A-23
17
17
VCC.1
VCC.1
A-24
4 3 2 1
22,24 PCI_P_AD[31:0] VCC_5V R68 1.5K PCI4.1V 22 LM4040DCIM3-4.1 D5 0.1uF C176 U53 0.1uF U54 22 PCI_DETECTn PCI_DETECTn PCI4.1V
D
PCI4.1V C174
PCI4.1V
S
PCI_P_AD11 PCI_P_AD12 PCI_P_AD13 PCI_P_AD14 PCI_P_AD15
1 S
PCI_P_AD10 PCI_P_AD9 PCI_P_AD8 PCI_P_AD7 PCI_P_AD6 PCI_P_AD5 PCI_P_AD4 PCI_P_AD3 PCI_P_AD2 PCI_P_AD1 PCI_P_AD0 24 PCI_P_C/BEn0
49 38 19 8
C365 5.6pF SN74CBT16292DGGR
49 38 19 8

54 52 50 47 45 43 41 39 36 34 32 30 1B1 2B1 3B1 4B1 5B1 6B1 7B1 8B1 9B1 10B1 11B1 12B1 54 52 50 47 45 43 41 39 36 34 32 30 1B1 2B1 3B1 4B1 5B1 6B1 7B1 8B1 9B1 10B1 11B1 12B1 1A 2A 3A 4A 5A 6A 7A 8A 9A 10A 11A 12A 2 4 6 9 11 13 15 18 21 23 25 27
PCI_S_AD10 PCI_S_AD9 PCI_S_AD8 PCI_S_C/BEn0 PCI_S_AD7 PCI_S_AD6 PCI_S_AD5 PCI_S_AD4 PCI_S_AD3 PCI_S_AD2 PCI_S_AD1 PCI_S_AD0
24 PCI_P_C/BEn1 24 PCI_P_PAR 24 PCI_P_SERRn 24 PCI_P_STOPn 24 PCI_P_PERRn 24 PCI_P_DEVSELn 24 PCI_P_TRDYn
1A 2A 3A 4A 5A 6A 7A 8A 9A 10A 11A 12A
2 4 6 9 11 13 15 18 21 23 25 27
TXEN TXCLK RXDV TXD1 TXD0 TXD3 TXD2 CRS COL PPERn PDEVSELn PTRDYn 6 6 6 6 6 6 6 6 6 6 6 6
PCI_S_AD11 PCI_S_AD12 PCI_S_AD13 PCI_S_AD14 PCI_S_AD15 PCI_S_C/BEn1 PCI_S_PAR PCI_S_SERRn PCI_S_STOPn
PCI_DETECTn RXER RXD0 RXCLK RXD2 RXD1 RXD3 MDC GIO003 MDIO GIO002 GIO001 GIO000 6 6 6 6 6 6 6 5 6 5 5 5
C
18,31 B.TXEN 18,31 B.TXCLK 18,31 B.RXDV 18,31 B.TXD1 18,31 B.TXD0 18,31 B.TXD3 18,31 B.TXD2 18,31 B.CRS 18,31 B.COL 25,32 VLYNQ_TXD3 25,32 VLYNQ_TXD2 25,32 VLYNQ_TXD1 0 0 22 R334 R335 R336
53 51 48 46 44 42 40 37 35 33 31 29 1B2 2B2 3B2 4B2 5B2 6B2 7B2 8B2 9B2 10B2 11B2 12B2
18,31 B.RXER 18,31 B.RXD0 18,31 B.RXCLK 18,31 B.RXD2 18,31 B.RXD1 18,31 B.RXD3 18,31 B.MDC 31 B.GP[03] 18,31 B.MDIO 31 B.GP[02] 31 B.GP[01] 31 B.GP[00]
NC.1 NC.2 NC.3 NC.4 NC.5 NC.6 NC.7 NC.8 NC.9 NC.10 NC.11 NC.12 NC.13 NC.14 53 51 48 46 44 42 40 37 35 33 31 29 1B2 2B2 3B2 4B2 5B2 6B2 7B2 8B2 9B2 10B2 11B2 12B2
3 5 7 10 12 14 16 20 22 24 26 28 55 56
NC.1 NC.2 NC.3 NC.4 NC.5 NC.6 NC.7 NC.8 NC.9 NC.10 NC.11 NC.12 NC.13 NC.14
3 5 7 10 12 14 16 20 22 24 26 28 55 56
SN74CBT16292DGGR
R315 PCI_DETECTn PCI_DETECTn 22 0 VCC_3V3 C121 0.1uF
24 PCI_PLUGn U39 SN74AHC1G14DCKRG4
2 1
PCIEN 3
SPECTRUM DIGITAL INCORPORATED Title: Page Contents: Size: B Date: TMS320DM6437 Evaluation Module PCI-Muxing DWG NO 509102-0001 Wednesday, December 06, 2006
3 2 1

4
VCC_3V3 PCI_PLUGn 23 NO-POP
R163
10K
R164
PCI_P_AD[31:0] 22,23 R178 PCIVCC_3V3 PCI_VIO VCC_5V P4 PCI_VIO 0

D

PCI_P_PINTAn 22
VCC_5V
PCIVCC_3V3
R179
R180
PCI_VIO
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11

PCI_VIO
Length to Cap no greater that 0.25 inches
22 PCI_P_CLK PCI_P_GNTn 22 PCI_P_AD30 PCI_P_AD28 PCI_P_AD26 PCI_P_AD24 PCI_P_IDSEL 22 PCI_P_AD22 PCI_P_AD20

A21,A27,A33,A39,A45,A53 B25,B31,B36,B41,B43,B54 PCIVCC_3V3 A10,A16,B19 A59,B59
PCI_P_RSTn 22
A10,A16,A59 B19,B59
C172 0.1uF
C179 0.1uF
Trace size to cap 20 mil Any number of pin shares as long as does not exceed length
C
22 PCI_P_REQn
PCI_P_AD31 PCI_P_AD29
PCI_P_AD27 PCI_P_AD25 PCIVCC_3V3
22 PCI_P_C/BEn3
PCI_P_AD23
PCI_P_AD21 PCI_P_AD19 PCI_P_AD18 PCI_P_AD16 PCI_P_FRAMEn 22 PCI_P_TRDYn 23 PCI_P_STOPn 23 PCI_P_PAR 23 PCI_P_AD15
Length to Cap no greater that 0.25 inches
PCI_P_AD17
22 PCI_P_C/BEn2
A21,A27,B25,B31
C180 0.1uF
A33,A39,B41,B43
C181 0.1uF
A53,B54
C182 0.1uF
22 PCI_P_IRDYn
23 PCI_P_DEVSELn
23 PCI_P_PERRn 23 PCI_P_SERRn
23 PCI_P_C/BEn1 PCI_P_AD13 PCI_P_AD11 PCI_P_AD9
PCI_P_AD14
VCC_5V
Length to Cap no greater that 0.25 inches +
PCI_P_AD12 PCI_P_AD10
B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49
33uF C204 C203 0.1uF
A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49
PCI_P_AD8 PCI_P_AD7 PCI_P_C/BEn0 23 PCI_P_AD6 PCI_P_AD4 PCI_P_AD2 PCI_P_AD0
PCI_P_AD5 PCI_P_AD3
PCI_P_AD1
B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62
-12V TCK GND TDO +5V +5V INTB INTD PRSNT1 Rsvd.2 PRSNT2 Key.5 Key.6 Rsvd.3 GND CLK GND REQ +V I/O AD31 AD29 GND AD27 AD25 +3.3V C/BE3 AD23 GND AD21 AD19 +3.3V AD17 C/BE2 GND IRDY +3.3V DEVSEL GND LOCK PERR +3.3V SERR +3.3V C/BE1 AD14 GND AD12 AD10 M66EN Key.7 Key.8 AD8 AD7 +3.3V AD5 AD3 GND AD1 +V I/O ACK64 +5V +5V A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62
TRST +12V TMS TDI +5V INTA INTC +5V Rsvd.0 +V I/O Rsvd.1 Key.1 Key.2 3.3Vaux RST +V I/O GNT GND PME AD30 +3.3V AD28 AD26 GND AD24 IDSEL +3.3V AD22 AD20 GND AD18 AD16 +3.3V FRAME GND TRDY GND STOP +3.3V SDONE SBO GND PAR AD15 +3.3V AD13 AD11 GND AD9 Key.3 Key.4 C/BE0 +3.3V AD6 AD4 GND AD2 AD0 +V I/O REQ64 +5V +5V
SPECTRUM DIGITAL INCORPORATED PCI Connector Title: Page Contents: Size: B Date:
4 3 2
TMS320DM6437 Evaluation Module PCI-Connector DWG NO 509102-0001 Wednesday, December 06, 2006
1
A-25
Power Supplies
Debug Signals (Do not connect in the host)
17 39 123 To_Host_VLYNQ_SDIO_VIO OSC32_768KHz 4

U67 SN74LVC1G06DBVRG4
WLAN CTLs
BTH BTH BTH PCM UART CTLs
VLYNQ SDIO
VLYNQ2

VCC_5V VCC_3V3 C405 470pF C376 C377 VCC_1V8
D
DBG_JTAG_WLAN_3V DBG_GPIO_3V DBG_RS232_3V 7 2 1

R419 1K WLAN_RSTn R394 NO-POP
A-26
C371 0.33uF C378 22uF C380 470pF C394 470pF 0 .33uF C386 0 .33uF 470pF 0.33uF 4.7uF C381 C382 C383 C384 22uF 470pF 0.33uF 22uF C372 C373 C374 C375
J20
mPCI_Host_WLAN_CONNECTOR
D1_5V
470pF 0.33uF C392 0.33uF C385 0.33uF
2 97 103
C379 470pF C393 470pF
122 120 118 117 5V_97 5V_103 VBAT 1
WLAN_UART_RXD WLAN_UART_TXD WLAN_RS232_RXD WLAN_RS232_TXD
13 12 10 11 8 D3_3V_19 D3_3V_28 D3_3V_31 D3_3V_40 D3_3V_63 D3_3V_70 D3_3V_88 D3_3V_89 D1_8V

VCC_3V3 VCC_1V8 C171 0.1uF VCC_3V3
JTAG_WLAN_TCK JTAG_WLAN_TMS JTAG_WLAN_TRSTN JTAG_WLAN_TDI JTAG_WLAN_TDO 19 28 31 40 63 70 88 89 111 115 18
107 106 108 105
DBG_I2C_SCL DBG_I2C_SDA DBG_I2C_SA2 DBG_EE_WP
15 55 57 VIOXIO_3V
RESERVED_15 RESERVED_55 RESERVED_57
VLYNQ_RESET 12,32
SLP_CLK_EN PM_EN WLAN_/RESET WLAN_ELP_REQ WLAN_/INTR 1.8V_BTH_/SHUTDWN 1.8V_BTH_ELP_WKUP 1.8V_BTH_/INTR 1.8V_BTH_UART_RTS 1.8V_BTH_UART_CTS 1.8V_BTH_UART_TXD 1.8V_BTH_UART_RXD 1.8V_BTH_PCM_CLK 1.8V_BTH_PCM_FS 1.8V_BTH_PCM_TXD 1.8V_BTH_PCM_RXD 16 24
VLYNQ_CLOCK 22,32 VLYNQ_SCRUN 22,32 VLYNQ_RXD0 22,32 VLYNQ_RXD1 22,32
3 5 26 4 6 29 38 30 113 116 104 109 71 73 75 77
WLAN_VLYNQ_CLK/SDIO_CLK WLAN_VLYNQ_SCRUN/SDIO_D0 WLAN_VLYNQ_TD0/SDIO_CMD WLAN_VLYNQ_TD1/SDIO_D3 WLAN_VLYNQ_RD0/SDIO_D2 WLAN_VLYNQ_RD1/SDIO_D1 WLAN_VLYNQ2_CLK WLAN_VLYNQ2_SCRUN WLAN_VLYNQ2_TXD0 WLAN_VLYNQ2_TXD1 WLAN_VLYNQ2_RXD0 WLAN_VLYNQ2_RXD1 BT_RF_SD BT_FREQ BT_PRI_DATA BT_PA_ON_OR_RX 47 49 51 53 112 121 98 100 93 124 36 43
VLYNQ_TXD0 22,32 VLYNQ_TXD1 23,32
21 22
9 14 20 23 25 27 32 33 34 35 37 41 45 42 44 46 48 50 52 54 56 58 60 62 64 66 68 69 72 74 76 78 79 81 83 85 87 90 91 92 94 95 96 99 101 102 110 114 119

VLYNQ_RXD2 VLYNQ_RXD3 VLYNQ_TXD2 VLYNQ_TXD3 22,32 22,32 23,32 23,32 Title: Page Contents: Size: B Date:
4 3 2
GND_9 GND_14 GND_20 GND_23 GND_25 GND_27 GND_32 GND_33 GND_34 GND_35 GND_37 GND_41 GND_45 GND_42 GND_44 GND_46 GND_48 GND_50 GND_52 GND_54 GND_56 GND_58 GND_60 GND_62 GND_64 GND_66 GND_68 GND_69 GND_72 GND_74 GND_76 GND_78 GND_79 GND_81 GND_83 GND_85 GND_87 GND_90 GND_91 GND_92 GND_94 GND_95 GND_96 GND_99 GND_101 GND_102 GND_110 GND_114 GND_119
SPECTRUM DIGITAL INCORPORATED TMS320DM6437 Evaluation Module BTH_WLAN_CONNECTOR DWG NO 509102-0001 Wednesday, December 06, 2006
1
125 126 127 128
HOLE1 HOLE2 GND_PAD1 GND_PAD2
Check your Layout Lib
WLAN_VLYNQ_TD2 WLAN_VLYNQ_TD3 WLAN_VLYNQ_RD2 WLAN_VLYNQ_RD3 WLAN_VLYNQ2_TD2 WLAN_VLYNQ2_TD3 WLAN_VLYNQ2_RD2 WLAN_VLYNQ2_RD3
59 61 65 67 80 82 84 86
mPCI_HOST_WLAN_CONNECTOR
SILKSCREEN: MINI PCI Check the layout library regarding pins 125-128.
VCC_3V3 L18 BLM21PG221SN1D R193
P10
3
5.6K 0.1uF R194 5.6K C226 VCC_1V8 0.1uF C232 0.1uF 0.1uF GND_AIC C233 0.1uF 0.1uF 10uF C225 0.1uF GND_AIC R195 GND_AIC C227 C228 C224 220pF
+
C219 0.1uF 10uF 0.1uF 0.1uF
C220
C221
C222
C223 L19 BLM21PG221SN1D C230 C229 0.1uF
VCC_3V3
220pF C241 C242 0.1uF GND_AIC 0.1uF GND_AIC GND_AIC R201 10K R202 330 0.1uF C244
0.1uF
A4 B5 B4 A3 LINE2L+ LINE2LLINE2R+ LINE2RHPLOUT HPLCOM DRVSS.1 DRVSS.2 HPRCOM HPROUT MONO_LO+ MONO_LOJ2 J3 D1 E1 E2 F2 F1 G1
C240
GND_AIC
C243
1B 2B 3B 4B GND 7
13 SPDIF_ONn

4 2 1
C231 0.1uF
D
Line In
P11
3
5.6K L20 U43 0.1uF BLM21PG221SN1D GND_AIC GND_AIC C236 0.1uF C237 0 C238 0 R200 0.1uF R199 R197 47K R198 330 R196 5.6K C234 220pF C235
4 2 1 H9 C9 D9 DVDD IOVDD DVSS
Mic In
A6 A5 B7 B6 LINE1L+ LINE1LLINE1R+ LINE1R-
DRVDD.1 DRVDD.2 AVDD_ADC AVSS_ADC.1 AVSS_ADC.2 AVDD_DAC AVSS_DAC.1 AVSS_DAC.2
C1 H1 B1 C2 D2 J1 G2 H2
GND_AIC GND_AIC GND_AIC BLM21PG221SN1D 33uF,6.3V 33uF,6.3V L21 BLM21PG221SN1D L22
C239
P12
1 2 4 3
Headphone Out R203 20K R204 20K
A2 A1 B3 B2 MICBIAS MIC3R MIC3L MICDET
3,17,19,28,30,33 SYS_RESETn
H8 RESET
VCC_3V3 C246 0.1uF TP15 TP-30 TP16 TP-30 10 no-pop VCC_3V3 R205 R206 R207 R208 10K NO-POP NO-POP 10K
DR0 DX0 CLKX0 CLKX1 FSR1 DX1
<--> <--> <--> <--> <--> <-->
AFSR0 AXR0[1] ACLKR0 ACLKX0 AXR0[0] AFSX0
B8 B9 A8 A9 MFP0 MFP1 MPF2 MFP3 MCLK G8
LEFT_LO+ LEFT_LORIGHT_LO+ RIGHT_LO-
J4 J5 J6 J7
GND_AIC GND_AIC
U75
VCC
24
11,31 AUDIO_CLK ALT_AIC33_CLK
R209 R182
GND_AIC
P13
GPIO1 GPIO2 SCL SDA
J9 J8 C8 D8
C245 10UF,6.3V C247 10UF,6.3V TVL320AIC33IZQE L24 L23
BLM21PG221SN1D BLM21PG221SN1D
1 2 4 BCLK WCLK DIN DOUT SELECT 3

Line Out TP17 TP-30
5,31 5,31 5,31 5,31 5,31
CLKX1 CLKR1 FSX1 DX1 DR1
B_CLKX1_ACLKX0 B_CLKR1_ACLKR0 B_FSX1_AFSX0 B_DX1_AXR0[0] B_DR1_AXR0[1]
R213 R214 R215 R218 R219
10 10 10 10 10
G9 F9 E9 F8 E8
5,17,31 CLKX0 B_FSR1_AFSR0 R216 10 R221 10K
5,17,31 DR0 5,17,31 DX0
3 4 7 8 11 14 17 18 21 22 1B1 1B2 1B3 1B4 1B5 2B1 2B2 2B3 2B4 2B5
R222 10K
1A1 1A2 1A3 1A4 1A5 2A1 2A2 2A3 2A4 2A5 GND 12
2 5 6 9 10 15 16 19 20 23
R210 20K TP18 TP-30 R212 20K
R211 20K
13 McBSP_ONn 13 McASP_ONn
1 13
1OE 2OE
GND_AIC GND_AIC R217 20K
SN74CBTLV3384PW VCC_3V3 VCC_3V3 C207
I2C_CLK 5,12,13,17,28,31 I2C_DATA 5,12,13,17,28,31 R20 10K VCC_3V3
U76
5,31
FSR1
2 5 9 12 VCC 3 6 8 11
1A 2A 3A 4A
14
0.1uF
C191 0.1uF U62
Isolate analog and digital GNDs at single location in the ground plane
SPECTRUM DIGITAL INCORPORATED Title: TMS320DM6437 Evaluation Module
13 McBSP_ONn 13 McASP_ONn 13 SPDIF_ONn
1 4 2
SN74LVC1G32 BLM41P750SPT GND_AIC
4 3 2
1 4 10 13
1OE 2OE 3OE 4OE
R356
33
SPDIF_OUT 27
L16
Page Contents: Size:B Date:
AIC33 DWG NO 509102-0001 Wednesday, December 06, 2006

1
SN74CBTLV3125PWRG4
A-27
MP1
VCC 2 A
PCLK 6
MP2
28 TVP5146_PCLK
B 3
TOTX141P R228 0
1 OE GND
SN74CBTLV1G125 R348 DC3_PCLK 30 0
30 TVP5146_ENABLEn
R186 10K

4 3 2 1 D
TVP5146YIN0 TVP5146YIN1 TVP5146YIN2 TVP5146YIN3 TVP5146YIN4 TVP5146YIN5 TVP5146YIN6 TVP5146YIN7 C250 R224 220
0.1uF 74LVC1G125DCKRG4 R226 0
R225 100
28 TVP5146_HS 28 TVP5146_VS
3 4 7 8 11 14 17 18 21 22 2 4 1A1 1A2 1A3 1A4 1A5 2A1 2A2 2A3 2A4 2A5
YI0 YI1 YI2 YI3 YI4 YI5 YI6 YI7 HD VD 6,30 6,30 6,30 6,30 6,30 6,30 6,30 6,30 6,30 6,30
1B1 1B2 1B3 1B4 1B5 2B1 2B2 2B3 2B4 2B5
2 5 6 9 10 15 16 19 20 23
A-28
VCC_3V3 C248 0.1uF VCC_3V3 U45 C249
VCC
0.1uF U46
24
28 TVP5146YIN[7:0]
SILKSCREEN: SPDIF OUT
J10 RCA JACK
1 13 1OE 2OE GND 12 SN74CBTLV3384
VCC_3V3 VCC_3V3
VCC_3V3
SILKSCREEN: SPDIF OUT
C253 C252 C251 0.1uF U49 0.1uF 0.1uF
P14
2 1
VCC GND
U48
5 4
26 SPDIF_OUT
2
74LVC1G125DCKRG4
IN

4 3 2
TMS320DM6437 Evaluation Module SPDIF/TVP5146-Switch DWG NO 509102-0001 Wednesday, December 06, 2006
1
VCC_3V3 L26
L25
3V3D_DEC
VCC_1V8
1V8A_DEC
C275 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
C276
C277
C278
C279
C280
C281
C282
C283
AGND CH1_A18GND CH2_A18GND CH3_A18GND CH4_A18GND CH1_A33GND CH2_A33GND CH3_A33GND CH4_A33GND A18GND_REF PLL_A18GND
TVP5146M2 GND_DENC
THERMAL_LAND
0.1uF
0.1uF
0.1uF
Isolate digital and analog GNDs and connect at a single location in the ground plane.
GND_DENC 1V8D_DEC
L15 BLM41P750SPT SPECTRUM DIGITAL INCORPORATED

A
3V3A_DEC
C284 0.1uF 0.1uF 0.1uF 0.1uF
C285
C286
C287
C288
C289
C290
C291
GND_DENC Title: Page Contents: Size: B Date:

4 3 2
81

BLM41P750SPT
D
BLM41P750SPT
VCC_3V3 L28 U50 BLM41P750SPT 3V3A_DEC 3V3D_DEC
L27
3V3A_DEC
VCC_1V8
1V8D_DEC
BLM41P750SPT
1V8A_DEC
IOVDD IOVDD IOVDD DVDD DVDD DVDD DVDD

1V8D_DEC
38 48 61 31 41 55 67
S-VIDEO IN
P2 L29 2.7uH L30 2.7uH C254 0.1uF 680pF GND_DENC GND_DENC GND_DENC GND_DENC GND_DENC C258 0.1uF C259 0.1uF 330pF C257 R229 75 C255
749181-1
4 5 20 21 78 11 14 25 76 12 CH1_A33VDD CH2_A33VDD CH3_A33VDD CH4_A33VDD CH1_A18VDD CH2_A18VDD CH3_A18VDD CH4_A18VDD PLL_A18VDD A18VDD_REF
TVP5146YIN[7:0] 27
3
C256
1
GND_DENC
330pF
80 1 2 VI_1_A VI_1_B VI_1_C
Y_0 Y_1 Y_2 Y_3 Y_4 Y_5 Y_6 Y_7 Y_8 Y_9 8 7 6 5 4 3 2 1
54 53 52 51 50 47 46 45 44 43
RPACK8-33 RN33
9 10 11 12 13 14 15 16
TVP5146YIN0 TVP5146YIN1 TVP5146YIN2 TVP5146YIN3 TVP5146YIN4 TVP5146YIN5 TVP5146YIN6 TVP5146YIN7 3V3D_DEC
3V3D_DEC
C
R230 2.2K
GND_DENC
7 8 9 VI_2_A VI_2_B VI_2_C

C260 0.1uF C263 330pF C270 0.1uF GND_DENC GND_DENC GND_DENC GND_DENC GND_DENC C264 0.1uF C265 0.1uF C266 0.1uF C267 0.1uF C268 0.1uF R233 75
R231 4.7K
R232 NO-POP
L31 2.7uH
L32 2.7uH
C_0/GPIO C_1/GPIO C_2/GPIO C_3/GPIO C_4/GPIO C_5/GPIO C_6/GPIO C_7/GPIO C_8/GPIO C_9/GPIO HS/CS/GPIO VS/VBLK/GPIO DATACLK
70 69 66 65 64 63 60 59 58 57 72 73 40
C261
C262
16 17 18 23 VI_3_A VI_3_B VI_3_C VI_4_A
R234 R235 R236
33 33 33
TVP5146_HS 27 TVP5146_VS 27 TVP5146_PCLK 27 R237 NO-POP 3V3D_DEC
330pF GND_DENC GND_DENC
680pF
GND_DENC
GND_DENC
74
L34 2.7uH Y4 14.31818MHz C272 680pF 33pF C274 GND_DENC GND_DENC GND_DENC 330pF C273 R239 75 R241 0 33pF C269 R238 100K
XTAL1
TP58 TP-30
J5 RCA JACK 1
L33 2.7uH
VIDEO IN
C271
75
XTAL2
TP19 TP-30 SYS_RESETn 3,17,19,26,30,33 I2C_CLK 5,12,13,17,26,31 I2C_DATA 5,12,13,17,26,31 R242 2.2K
R240 2.2K
330pF
GLCO/I2CA FSS/GPIO PWDN AVID/GPIO FID/GPIO RESETB SCL SDA INTREQ
37 35 33 36 71 34 28 29 30
GND_DENC GND_DENC
TP20 TP-30
3V3D_DEC
1V8A_DEC
26 79 10 15 24 3 6 19 22 13 77
DGND DGND DGND DGND DGND IOGND IOGND IOGND
27 32 42 56 68 62 49 39
TMS320DM6437 Evaluation Module TVP5146 DWG NO 509102-0001 Wednesday, December 06, 2006
1
0.1uF
0.1uF
0.1uF
0.1uF
GND_DENC
A-29
A-30
4 3 2 1
VCC_3V3 DAC_3V3
3V3A_VOUT
+
L35 L37 C292 0.1uF DAC_3V3 10pF GND_DAC DAC_3V3 U103 GND_DAC GND_DAC GND_DAC 10pF
D
BLM41P750SPT 1uH C297 C294 10uF C293 0.01uF C296 R243 75
J1 NO-POP
DAC A OUTPUT
5 ENABLE
GND_DAC
V+ OUT
R245 75 C300 10pF GND_DAC GND_DAC GND_DAC GND_DAC 10pF C301
6 4 2
L40 1uH
C401 0.1uF
8 DAC_IOUT_A
1 IN+ RSET GND OPA361AIDCKT

R444 NO-POP
J2 RCA JACK
DAC B OUTPUT
8 DAC_RBIAS R445 0
GND_DAC L41 R250 DAC_3V3 U104 C303 C304 10pF GND_DAC 75 1uH

DAC_3V3
J3 RCA JACK
DAC C OUTPUT
C
5 ENABLE
GND_DAC
V+ OUT GND
749181-1 GND_DAC P1
6 4 2
GND_DAC
C402 0.1uF 10pF
8 DAC_IOUT_B
1 IN+ RSET
OPA361AIDCKT R441 NO-POP R446 0
GND_DAC
8 DAC_RBIAS
S-VIDEO OUT
GND_DAC DAC_3V3
U105 DAC_3V3
5 V+
GND_DAC
5 ENABLE IN+ 2
R255 GND_DAC 75
6 4
C403 0.1uF GND_DAC

B
8 DAC_IOUT_C
1 OUT
R442 NO-POP
8 DAC_RBIAS
3 RSET GND OPA361AIDCKT

R443 0 DAC_3V3
L46 C307 10pF GND_DAC
1uH C308 10pF GND_DAC GND_DAC
J4 RCA JACK
DAC D OUTPUT
GND_DAC DAC_3V3 U106
5 ENABLE
GND_DAC
V+ OUT 2 4
C404 0.1uF
8 DAC_IOUT_D
1 IN+ RSET GND OPA361AIDCKT

GND_DAC R447 NO-POP
ISOLATE GROUNDS AND CONNECT AT SINGLE LOCATION IN THE GROUND PLANE
8 DAC_RBIAS R448 0
L14 BLM41P750SPT GND_DAC Size: B Title: Page Contents:
SPECTRUM DIGITAL INCORPORATED TMS320DM6437 Evaluation Module Video Out DWG NO Date: 509102-0001 Wednesday, December 06, 2006
3 2 1
GND_DAC

4
11 PLL_PCLK DC_P1

NO-POP R265
D
27 DC3_PCLK 27 TVP5146_ENABLEn 6,27 YI3 6,27 YI2 6,27 YI1 6,27 YI0 YI4_(CCD4)_GP[40] YI5_(CCD5)_GP[41] YI6_(CCD6)_GP[42] YI7_(CCD7)_GP[43] YI4 YI5 YI6 YI7 C_FIELD HD B.CI4 B.CI5 B.CI6 B.CI7 VSYNC HSYNC 6 6 YOUT4_FASTBOOT 6,10 YOUT5 6,10 YOUT6 6,10 YOUT7 6 6,15 6,27 15,22 15,22 15,22 15,22 6,27 6,27 6,27 6,27 C_FIELD_EM_A[21]_GP[34] HD_GP[52] CI4_(CCD12)_EM_A[16]_EM_D[3]_GP[48] CI5_(CCD13)_EM_A[15]_EM_D[2]_GP[49] CI6_(CCD14)_EM_A[14]_EM_D[1]_GP[50] CI7_(CCD15)_EM_A[13]_EM_D[0]_GP[51] VSYNC_EM_CS4n_GP[32] HSYN C_EM_CS5n_GP[33] YOUT4_GP[26]_FASTBOOT YOUT5_GP[27] YOUT6_GP[28] YOUT7_GP[29] COUT4_EM_D[4]_GP[18] COUT5_EM_D[5]_GP[19] COUT6_EM_D[6]_GP[20] COUT7_EM_D[7]_GP[21] R0_EM_A[4]_GP[10]_(AEAW2) B1_EMA[2]_(CLE)_GP[8]_(AEAW0) R1_EM_A[0]_GP[7]_(AEM2) G0_EM_CS2n_GP[12] LCD_OE_EM_CS3n_GP[13] EM_A[9]_GP[92] EM_A[10]_GP[91] EM_A11_GP[90] EM_A[12]_GP[89] EM_OEn CLK_OUT_PWM2_GP[84] GP[4]_PWM1 I2C_INT_ENABLEn VCC_1V8 6 C_W EN 6,27 VD 15,22 B.CI3 15,22 B.CI2 15,22 B.CI1 15,22 B.CI0 6 6 YOUT3_GP[25]_BOOTMODE3 YOUT2_GP[24]_BOOTMODE2 YOUT1_GP[23]_BOOTMODE1 YOUT0_GP[22]_BOOTMODE0 COUT3_EM_D[3]_GP[17] COUT2_EM_D[2]_GP[16] COUT1_EM_D[1]_GP[15] COUT0_EM_D[0]_GP[14[ B0_LCD_FIELD_EM_A[3]_GP[11] G1_EM_A[1]_(ALE)_GP[9]_(AEAW1) R2_EM_BA[0]_GP[6]_(AEM1) B2_EM_BA[1]_GP[6]_(AEM0) EM_WAIT_(RDY/BSYn) EM_A[5]_GP[96] EM_A[6]_GP[95] EM_A[7]_GP[94] EM_A[8]_GP[93] EM_WEn MEM_EMD7-0_ENABLEn CI_EMA_ENABLEn RESETn SYS_RESETn VCC_1V8 VCC_3V3 VPBECLK VPBECLK_GP[30] VCLK VCLK_GP[31] C_WE_RNW_GP[35] VD_GP[53] CI3_(CCD11)_EM_A[17]_EM_D[04]_GP[47] CI2_(CCD10)_EM_A[18]_EM_D[05]_GP[46] CI1_(CCD9)_EM_A[19]_EM_D[06]_GP[45] CI0_(CCD8)_EM_A[20]_EM_D[07]_GP[44]
PCLK_GP[54] TVP5146_ENABLEn YI3_(CCD3)_GP[39] YI2_(CCD2)_GP[38] YI1_(CCD1)_GP[37] YI0_(CCD0)_GP[36]
RESERVED
6,10 6,10 6,10 6,10 6,15 6,15 6,15 6,15 COUT3 COUT2 COUT1 COUT0
YOUT3_BOOTMODE3 YOUT2_BOOTMODE2 YOUT1_BOOTMODE1 YOUT0_BOOTMODE0
COUT4 COUT5 COUT6 COUT7
6,15 6,15 6,15 6,15 EM_A04 6,10,16,17 EM_A02_CLE 6,16,17 EM_A00 6,10,16,17 DC_EM_CS2n 15 LCD_OE 6 B.EM_A09 B.EM_A10 B.EM_A11 B.EM_A12 READ_OE 16,17,22 16,17,22 16,17,22 16,17,22 6,16,17 CLK_OUT 5,6,11 PWM1 5,11 I2C_INT_ENABLEn 5
B
6,16,17 EM_A03 6,16,17 EM_A01_ALE 6,10,16,17 EM_BA0 6,10,16,17 EM_BA1 6,16 WAIT_BSYn
16,17,22 B.EM_A05 16,17,22 B.EM_A06 16,17,22 B.EM_A07 16,17,22 B.EM_A08 6,16,17 WRITE_WE
15 MEM_EMD7-0_ENABLEn 15 CI_EMA_ENABLEn 3,4,22 RESETn 3,17,19,26,28,33 SYS_RESETn
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99
VCC_3V3 CONNECTOR 50 X 2
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100
VCC_5V VCC_5V

4 3 2
TMS320DM6437 Evaluation Module VIDEO DC Conn. DWG NO 509102-0001 Wednesday, December 06, 2006
1
A-31
A-32
4 3 2 1
CONNECTOR 45 X 2
D
13 USER_I2C_IO.A1P1 13 USER_I2C_IO.A1P3 USER_I2C_IO.A0P7 USER_I2C_IO.A0P6 12 18,23 B.TXCLK 18 ENET_ENABLEn 18,23 B.TXD0 18,23 B.TXD2 18,23 B.MDIO 18,23 B.RXCLK 18,23 B.COL 18,23 B.RXD2 18,23 B.RXD0 18,23 B.RXER HINTn_RXD3_GP[82] HDS1n_RXD1_GP[79] B.RXD3 B.RXD1 RESET_OUTn 3,22 18,23 18,23 RESET_OUTn HD09_COL_GP[67] HRDYn_RXD2_GP[80] HDS2n_RXD0_GP[78] HCNTL0_MRXER_GP[76] HRNW_RXCLK_GP[77] B.CRS B.RXDV 18,23 18,23 HD1 0_CRS_GP[68] HHWIL_RXDV_GP[74] HASn_MDIO_GP[83] B.MDC 18,23 HCSn_MDC_GP[81] ENET_ENABLEn HD14_TXD0_GP[72] HD12_TXD2_GP[70] B.TXEN B.TXD1 B.TXD3 18,23 18,23 18,23 HCNTL1_TXEN_GP[75] HD13_TXD1_GP[71] HD11_TXD3_GP[69] HD15_TXCLK_GP[73] USER_I2C_IO.A0P6
USER_I2C_IO.A1P1 USER_I2C_IO.A1P3 USER_I2C_IO.A1P0 13 USER_I2C_IO.A1P2 13
USER_I2C_IO.A1P0 USER_I2C_IO.A1P2

5,26 5,26 5,26 I2C_DATA ACLKR0_CLKX0_GP[99] AXR0[1]_DX0_GP[104] AXR0[2]_FSX0_GP[103] CLKR0 DR0 FSR0 AUDIO_CLK 11,26 TINP1L 5,20,21 5 5,17,26 5 CAN_ENABLEn HECC_TX_TOUT1L_UTXD1_GP[55] UCTS0_GP[87] URTS0_PWM0_GP[88] B.GP[03] B.GP[01] CLKS0_TOUT0L_GP[97] AHCLKR0_CLKR0_GP[101] AFSR0_DR0_GP[100] AXR0[3]_FSR0_GP[102] AUDIO_CLK NO-POP R270 AUDIO_CLK HECC_RX_TINP1L_URXD1_GP[56] DX1 CLKR1 FSX1 AFSX0_DX1_GP[107] AHCLKX0_CLKR1_GP[108] AMUTEIN0_FSX1_GP[109] CLKX1 5,26 DR1 5,26 FSR1 5,26 AIC33_ENABLEn 13 I2C_CLK 5,12,13,17,26,28 ACLKX0_CLKX1_GP[106] AMUTE0_DR1_GP[110] AXR0_FSR1_GP[106] AIC33_ENABLEn I2C_CLK
C
12 USER_I2C_IO.A0P7
5,12,13,17,26,28 I2C_DATA 5,17,26 CLKX0 5,17,26 DX0 5,17 FSX0 20 CAN_ENABLEn 5,20,21 TOUT1L 5 5 23 B.GP[03] 23 B.GP[01] 5 TOUT0L UCTS0 URTS0 UTXD0_GP[86] URXD0_GP[85] RS232_ENABLEn B.GP[02] B.GP[00] CLKS1_TINP0L_GP[98] VIC_TINP0L_ENABLEn UTXD0 5,21 URXD0 5,21 RS232_ENABLEn 21 B.GP[02] 23 B.GP[00] 23 TINP0L 5,11 VIC_TINP0L_ENABLEn 11
90 88 86 84 82 80 78 76 74 72 70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 90 88 86 84 82 80 78 76 74 72 70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
DC_P2 VCC_3V3
89 87 85 83 81 79 77 75 73 71 69 67 65 63 61 59 57 55 53 51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
89 87 85 83 81 79 77 75 73 71 69 67 65 63 61 59 57 55 53 51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
VCC_3V3
VCC_5V
VCC_5V
SPECTRUM DIGITAL INCORPORATED Title: Page Contents: Size:B TMS320DM6437 Evaluation Module EMAC/MCBSP DC Conn. DWG NO 509102-0001 Date: Wednesday, December 06, 2006
4 3 2 1

4 3 2 1 D
VCC_3V3 DC_P3 22,25 VLYNQ_SCRUN 22,25 VLYNQ_RXD0 22,25 VLYNQ_RXD1 22,25 VLYNQ_RXD2 22,25 VLYNQ_RXD3 HD03_VLYNQ_RXD2_GP[61] HD04_VLYNQ_RXD3_GP[62] HD07_VLYNQ_TXD2_GP[65] HD08_VLYNQ_TXD3_GP[66] HD01_VLYNQ_RXD0_GP[59] HD02_VLYNQ_RXD1_GP[60] HD05_VLYNQ_TXD0_GP[63] HD06_VLYNQ_TXD1_GP[64] HD00_VLYNQ_SCRUN_GP[58] VLYNQ_ CLOCK_GP[57] VLYNQ_CLOCK 22,25 VLYNQ_TXD0 22,25 VLYNQ_TXD1 23,25 VLYNQ_TXD2 23,25 VLYNQ_TXD3 23,25
1 3 5 7 9 11 13 15 17 19
HEADER 10X2
2 4 6 8 10 12 14 16 18 20
VCC_5V
VCC_5V
VCC_3V3
VCC_3V3
VCC_1V8
C177 0.1uF
R266 1K
R267 NO-POP
12,25 VLYNQ_RESET U15 SN74LVC1G06DBVRG4
2 1

4 3 2
TMS320DM6437 Evaluation Module VLYNQ/EMIF DC Conn. DWG NO 509102-0001 Wednesday, December 06, 2006
1
A-33
A-34
4 3 2 1
0 CORE_VDD_SELECT 13
G
R272
34 1V8_PWR_OK BSS123
S D
Q4 R273 56.0K 1% NO-POP R274 56.0K 1% C312
34 3V3_PWR_OK
CORE_VDD_SELECT function: 0: 1.05V 1: 1.2V The FET and resistor in series with it can be removed if voltage scaling is not desired.
R344 NO-POP AGND VCC_5V 3300pF C317 10K 0.1% R279 10K CORE_PWR_OK 34 DSP_CORE_VDD 0.047uF 0.025 L50 2.7 uH
+
R349 0 R275 C314 71.5K 1% 0.1uF 107 1% R277 R278 0.039uF U55 TP21 TP-30 C316 560pF C315
3.3 sq in AGND, min thermal pad
Connect at pin 1
R276 1.65K 1%
C313 0.01uF
VCC_5V L49 C318 C319 NO-POP

+
21 20 19 18 17 1 2 3 4 5
R280 C325 100 uF 100uF 4V TP22 TP-60 TP23 TP-60 1000pF C323 C324
BLM41P750SPT C320 0.1uF

+
C321 C322 0.1uF
16 15 14 13 12 11
TPS54310PWP 101338-0001

10uF LESR
POWERPAD RT AGND SYNC VSENSE SS/ENA COMP VBIAS PWRGD BOOT VIN3 VIN2 VIN1 PH1 PH2 PGND3 PH3 PGND2 PH4 PGND1 PH5 6 7 8 9 10
VCC_3V3 VCC_1V8 U56 R282 9.09K 1% C326 R281 1K
VCC_3V3
5 SENSE1 CT MR
TPS3808G09DBVRG4
Reset Threhold 0.84 Volts
VDD RESET GND 2 1
0.1uF
R283 10K 1%
4
C327
SYS_RESETn 3,17,19,26,28,30
NO-POP
D10
3
VCC_3V3 C328
1
VCC_3V3
R314
EMU_SYS_RESETn
VCC_3V3 U57 R285 20K 1%
BAS16-7-F
JP4
5 SENSE1 CT MR
TPS3808G09DBVRG4
VDD RESET GND 2 1
0.1uF
R284 10K
TP25 TP-60
TP26 TP-60
TP27 TP-60
TP28 TP-60
TP29 TP-60
TP30 TP-60
1 2 4
C329
R287 10K 1%
NO-POP
Reset Threhold 0.84 Volts GND Test Points
HEADER 2 NO-POP VCC_3V3 VCC_3V3 DSP_CORE_VDD 0 R289 U58 C330 0.1uF R288 10K VCC_3V3
nPOR
SW5 R346
R345 10K
A AA
R290 10K 1% C368 1uF NO-POP C331
B BB
33
5 4 3
SENSE1 CT MR
VDD RESET GND
6 1
PUSHBUTTON SW
SPECTRUM DIGITAL INCORPORATED
2
TPS3808G09DBVRG4
Reset Threhold 0.84 Volts
TMS320DM6437 Evaluation Module RESET SUPERVISOR DWG NO 509102-0001 Wednesday, December 06, 2006
3 2 1
Revision: B Sheet 33 o f 34

4
1V8_PWR_OK
Sets Voltage Connect at pin 1
33 CORE_PWR_OK AGND
0.1uF
13 12 11 PGND3 PGND2 PGND1

TPS54310PWP 101338-0001
PH1 PH2 PH3 PH4 PH5
6 7 8 9 10
100uF 4V
1000pF

R291 3.74K 1%
R292 C333 NO-POP NO-POP 0.1uF C336 10K 1% C337 R297 3300pF R296 107 1% 0.039uF VCC_5V L51 0.047uF L52 3.3 uH
+
R393 C334 71.5K 1% U59 C335 470pF
R294
R293 2K 1%
C332 8200pF
VCC_5V TP32 TP-30 R295 10K 3V3_PWR_OK VCC_3V3 0.025 R298 NO-POP C343
+
TP31 TP-30
SILKSCREEN: 5V IN
J16
21 20 19 18 17 POWERPAD RT SYNC SS/ENA VBIAS AGND VSENSE COMP PWRGD BOOT 1 2 3 4 5
C338
CENTER SHUNT SLEEVE

R299 220 C344 1000pF 100uF 4V 100 uF 4V TP33 TP-60 C345 10uF LESR 0.1uF
+
2.5 MM JACK RASM712
C340 47uF

+
C342 C339
16 15 14 VIN3 VIN2 VIN1
13 12 11 PGND3 PGND2 PGND1
PH1 PH2 PH3 PH4 PH5
6 7 8 9 10
C346 TP34 TP-60

3.3V @1.5Amp Max
100 uF
DS5 GREEN
TPS54310PWP 101338-0001
3V3_PWR_OK 33
3V3_PWR_OK
Sets Voltage Connect at pin 1
33 CORE_PWR_OK AGND
R300 10.2K 1%
1V8_PWR_OK 33
R438 C348 71.5K 1% NO-POP 0.1uF 0.039uF 0 U60 C350 470pF C349
R439
R301
R302 2K 1%
C347 8200pF
VCC_5V TP36 TP-30 C351 3300pF R305 R303 10K 1% 1V8_PWR_OK 107 1% R304 10K
B
VCC_5V L53
21 20 19 18 17 POWERPAD RT SYNC SS/ENA VBIAS AGND VSENSE COMP PWRGD BOOT

0.047uF
1 2 3 4 5
C352 VCC_1V8 0.025 L54 2.7 uH C357 C358 R306 NO-POP C353

+
C355 10uF LESR
C356
16 15 14 VIN3 VIN2 VIN1
TP37 TP-60
TP38 TP-60
C359 100 uF

4 3 2
TMS320DM6437 Evaluation Module POWER DWG NO 509102-0001 Wednesday, December 06, 2006
1
Revision: B Sheet 34 o f 34
A-35
A-36
Appendix B Mechanical Information
This appendix contains the mechanical information about the DM6437 EVM produced by Spectrum Digital.
B-1
B-2
THIS DRAWING IS NOT TO SCALE
Printed in U.S.A., December 2006 509105-0001 Rev C

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TMS320DM6437 Evaluation Module

DSP Development Systems

Downloaded from Elcodis.com electronic components distributor

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TMS320DM6437 Evaluation Module Technical Reference

509105-0001 Rev. C December 2006

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Copyright 2006 Spectrum Digital, Inc.

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Table 1: Manual History Revision A B Alpha Release Beta Release History

Table 2: Board History Revision A B Alpha Release Beta Release History

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Chapter 1 Introduction to the DM6437 EVM

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Spectrum Digital, Inc

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Spectrum Digital, Inc

DIP LEDs NAND Flash

DAC B DAC C DAC D

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DM6437 Video Port PCI

VLNQ Mini PCI

1.2V Core Supply S/PDIF 3.3V I/O Supply

Spectrum Digital, Inc

DM6437 EVM Technical Reference

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Spectrum Digital, Inc

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Spectrum Digital, Inc

DM6437 EVM Technical Reference

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Chapter 2 Board Components

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DM6437 EVM Technical Reference

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Spectrum Digital, Inc

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Spectrum Digital, Inc

AIC33 Codec I2C

Figure 2-2, DM6437 EVM CODEC INTERFACE

DM6437 EVM Technical Reference

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Spectrum Digital, Inc

PLL1705 DM6437 XT1

SCK03 SCK02 SCK01 SCK00 MCK02 MCK01

STCLK VCXO Circuit Using PICX100-27

Figure 2-3, Audio PLL/VCXO Circuit/PLL1705 Clock Generator

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Spectrum Digital, Inc

DM6437 EVM Technical Reference

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Spectrum Digital, Inc

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* only one should be enabled at a time

DM6437 EVM Technical Reference

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Spectrum Digital, Inc