Compact Highly Integrated X-Band Power Amplifier Using Commercially Available Discrete GaN FETs

Charles F. Campbell and Matthew Poulton

TriQuint Semiconductor, Defense and Aerospace Business Unit 500 West Renner Road, Richardson, TX 75080, United States ccampbell@tqs.com
Abstract This paper describes the design and characterization of a highly integrated X-band power amplifier that utilizes commercially available discrete GaN transistors. The compact design integrates all of the RF matching and bias circuitry on to er=36 circuit boards, one for the input and one for the output. This includes the DC blocks, RF bypasses and RF chokes. Dimensions for the complete single stage power amplifier are 9.8 x 8.6 mm2. Measured results for the GaN power amplifier under pulsed bias conditions demonstrate up to 66W output power with associated gain and power added efficiency of 8.3dB and 45% respectively. Index Terms power amplifier, Gallium Nitride, X-band, discrete FET.

structures are integrated on to the input and output r=36 circuit boards. The circuit was designed and anlayzed using a in-situ probe based method that allows individual FET cell loading to be determined for the actual mode of operation [5]. This technique reveals the impact of input and output matching network asymmetry on the loading of the transistor cells and provides a means to minimize these effects. The first part of this paper describes the design of the circuit and measured results are presented in the second section. II. CIRCUIT DESIGN The motivation for this work was to develop a demonstration circuit for the TriQuint Semiconductor TGF2023-10 discrete GaN transistor. The circuit design goals were to combine two TGF2023-10 die to achieve greater than 50W of saturated output power and minimum 40% peak power added efficiency at X-band frequencies. The device datasheet states that under efficiency tuned conditions a single transistor is capable of producing 35W of saturated output power and 49% peak PAE at 10GHz. A linear circuit model is provided on-line in the form of a 16 port s-parameter file which includes the input bond pads and output drain bus as shown in Figure 1. The efficiency tuned load target at 10GHz is Rp=7.2 and Cp=4.1pF.

I. INTRODUCTION Microwave power amplifier design using discrete GaN transistors is a viable alternative to monolithic implementation given the present cost and availability of this technology. Some advantages of this approach include reduced cost by minimizing GaN area, potential reduced network loss, more flexible tuning of fabricated circuits and the availability of discrete GaN transistors from a number of different vendors. The are however a number of notable disadvantages. For frequencies above C-band there is a lack of suitable high power components that can be used for matching, DC blocks, bias chokes, etc. and distributed architectures tend to be far less compact. Recently some of these issues have been addressed with the use of high dielectric constant substrate materials [1-3]. A C-band single stage power amplifier with 100W CW output power and 68% PAE is reported in [2]. A notable X-band benchmark is described in [1], under pulsed conditions the output power and efficiency of this amplifier are reported to be 101W and 53%. The performance of a Ku-band amplifier that uses a combination of high dielectric and alumina substrates for the matching networks is reported to be 62W and 45% power added efficiency under pulsed conditions [3]. None of these circuits however are complete amplifiers, the reported results are for the active device and input/output matching networks only. In the other words the biasing circuitry is not included in the measurement. Inclusion of the DC blocks, gate bias and drain bias networks in the measurement would have surely reduced the performance of these circuits. This paper describes the design and characterization of a single stage, highly integrated X-band power amplifier utilizing TriQuint Semiconductor TGF2023-10 discrete GaN FETs [4]. All bias, matching, stability and DC blocking

Fig. 1.

TGF2023-10 GaN FET and on-line s-parameter model.

A simplified schematic for the circuit is shown in Figure 2. To achieve a compact design and a high degree of integration, 10mil thick r=36 board material was used to realize the circuit. The board surface preparation is as fired and the gold metallization is 3m thick.
VG TGF2023-10 VD

up a TGF2023-10 device [5]. Initial circuit simulations for the transistors contacted with minimum length bondwires predicted that the unit cell output ports would be not be uniformly loaded. The distribution of output load impedances for the eight connection points is shown in Figure 4. Note that Cp has been absorbed in the output network. The output bondwire configuration can be altered to compensate for this effect. Placing the bondwires at increasing angles as shown in Figure 5 significantly improves the load imbalance. The simulated loading for the angled bondwire configuration is plotted in Figure 6. The load impedances are much more uniform and better centered on the real axis.

TGF2023-10 VG VD

Fig. 2.

Simplified schematic for the amplifier.

A photograph of the final amplifier is shown in Figure 3. 2 The circuit dimensions are 9.6 x 8.6 mm and the boards were built by ATP (Applied Thin-Film Products). The various components are soldered to a 40mil thick CuMo carrier plate. The assembled carrier plate is mounted to an aluminum test fixture and the RF ports contacted with connectorized launchers. The white blocks attached to the board surface are alumina tuning chips that were used to optimize circuit performance. The matching networks were EM simulated TM with Sonnet featuring individual ports for each bondwire connection. The entire amplifier circuit was analyzed with TM AWR Microwave Office utilizing the quasi-EM based multiple bondwire model (BWIRES2) resident in the simulation tool [6].

Fig. 4.

Output loading for minimum length bondwires.

Fig. 5.

Angled output bondwires to improve load imbalance.

Fig. 3.

Photograph of the assembled amplifier. Fig. 6. Output loading with bondwire compensation.

The circuit was simulated and optimized with a probe based technique which the allows a determination of the load and output power for each of the 8 unit FET cells that make

A significant advantage of the r=36 board material is that the matching, biasing, bypassing, DC block and stability circuitry can be integrated on to a single circuit board. The DC blocking capacitors are realized as the interdigitated structure shown in Figure 7. The high dielectric constant board material increases the amount of capacitance that can obtained in a reasonable amount of area. The capacitor shown in Figure 7 is approximately 1pF. Thin film resistors are also available and the stability resistors shown in Figure 2 are also integrated on to the circuit boards. The RF bypass capacitors for the gate and drain bias circuits are realized as open microstrip stubs as shown in Figure 3. Again, using the high dielectric constant substrate greatly improves the bandwidth for which the open stubs provide an effective power supply bypass. A small signal simulation of the amplifier is shown in Figure 8 for 100 monte carlo trials with a 100% uniform variation applied to the bondwire inductance connected to the pads labeled VG and VD in Figure 3. Note that the open stubs bypass the circuit well from 8GHz to about 12GHz.

III. MEASURED RESULTS Measured in-fixture s-parameters for the power amplifier are shown in Figure 9. The data was collected under DC bias conditions at room temperature for a 30V drain bias and ~1A of quiescent current. The small signal gain is 8dB to 10dB over a 8.9-9.9GHz band and the input and output return losses are better than -6dB and -10dB respectively. In comparison to the simulated results shown in Figure 8, the passband has shifted down about 500MHz and the small signal gain is reduced by about 2dB. The TGF2023-10 linear model is based on data collected from an isolated 1.25mm unit FET cell. A very different thermal environment will exist for two 10mm devices placed in close proximity to one another as shown in Figure 3. Therefore under DC (not pulsed) bias conditions one would expect a somewhat lower small signal gain and the simulated gain level plotted in Figure 8 would be more representative of the amplifier under pulsed bias conditions.
12 6 0 -6 -12 -18 8 8.5 9 9.5 10 Frequency (GHz) 10.5 11

Linear Gain and Return Loss (dB)

IRL ORL Gain

Fig. 9. Fig. 7. Integrated interdigitated blocking capacitor.

S-parameters, Vd = 30V, Iq = 1.0A, room temperature.

Fig. 8.

Integrated interdigitated blocking capacitor.

Measured power data under pulsed conditions is shown in Figures 10 and 11. The applied RF input signal is CW and the gate bias voltage is fixed for a Iq=1A, however the drain bias voltage is pulsed from 0V to 30V for a duration of 100s at a 10% duty cycle. For a 40dBm CW input signal the measured output power typically exceeds 50W from 8.99.8GHz and is greater than 66W from 9.0-9.4GHz. The power added efficiency is greater than 40% from 8.7-9.6GHz with a peak value of 45% at 9GHz. The compression characteristics of the amplifier at 9.4GHz are shown in Figure 11. Note that the linear gain is 11.5dB which agrees much better with the simulated results shown in Figure 8. The amplifier is well behaved as it is driven into saturation and demonstrates more than 9dB of gain at peak power added efficiency. The linear decrease in gain before the onset of compression is believed to be caused by device heating because the amplifier power dissipation, hence channel temperature, also increases linearly as a function of input power in dB.

50
Output Power (dBm)

50
% Power Added Efficiency

IV. CONCLUSION The design and characterization of a highly integrated Xband power amplifier utilizing commercially available discrete GaN transistors has been presented. The design integrates all of the RF matching and biasing circuitry on to r=36 input and output matching network circuit boards. Dimensions for the complete single stage power amplifier are 9.8 x 8.6 mm2. Measured results for the GaN power amplifier under pulsed conditions demonstrate up to 66W output power with associated gain and power added efficiency of 8.3dB and 45% respectively.

49 48 47 46 45 8.6 8.9 9.2 9.5 Frequency (GHz) 9.8 Power PAE

40 30 20 10 0 10.1

Fig. 10. 40dBm input, pulsed 100s, 10% duty, Vd =30V, 25C.
50
Output Power (dBm) and %PAE

REFERENCES
[1] H. Shigematsu, et al., C-band 340-W and X-band 100-W GaN Power Amplifiers with Over 50-% PAE, IEEE Intl. Microwave Symp., 2011, pp. 12651268. [2] T. Yamasaki, et al., A 68% Efficiency, C-Band 100W GaN Power Amplifier for Space Applications, IEEE Intl. Microwave Symp., 2010, pp. 1384-1387. [3] K. Yamauchi, et al., A 45% Power Added Efficiency, Kuband 60W GaN Power Amplifier, IEEE Intl. Microwave Symp., 2011. [4] TriQuint Semiconductor Datasheet, TGF2023-10, www.tqs.com. [5] C. F. Campbell, A Probe Based Simulation Technique for Modeling Saturated Power Amplifiers, Accepted for publication, EuMW., 2011. [6] Bond Wire Modeling Standard. EIA/JEDEC Standard EIA/JESD59: Electronics Industries Association, June 1997.

18 16 Power PAE Gain 14 12 10 8 18 22 26 30 34 Input Power (dBm) 38 42

40 30 20 10 0

Fig. 11. 9.4GHz, pulsed 100s, 10% duty, Vd =30V, 25C.

Gain (dB)