BASICS OF PERIPHERAL DEVICES AND WORKING

Introduction
Microprocessor based system design involves interfacing of the processor with one or more peripheral devices for the purpose of communication with various input and output devices connected to it. During the early days of the microprocessor revolution, these techniques required complex hardware consisting of Medium scale integration devices making the design highly complex and time consuming. So, the manufacturers ( !"#$% have developed a large number of general and special purpose peripheral devices most of them being single chip circuits. "hey are also programmable devices. &ence these peripheral devices are found to be of tremendous use to a system designer. 'eripheral devices, can broadly be classified into two categories. (a% (eneral purpose peripherals and (b% Special purpose peripherals (Dedicated function peripherals% (eneral purpose peripherals are devices that perform a task but may be used for interfacing a variety of )* devices to microprocessor. "he general purpose devices are given below+ Simple )* 'rogrammable peripheral nterface ('' % 'rogrammable nterrupt 1ontroller 'rogrammable DM3 1ontroller 'rogrammable 1ommunication nterface 'rogrammable nterval "imer ,, (!on,programmable% (./00% (./02% (./45)./05% (./06% (./04)./07%

Special function peripherals are devices that may be used for interfacing a microprocessor to a specific type of )* device. "hese peripherals are more complex and therefore, relatively more expensive than general purpose peripherals. "he special function peripherals (Dedicated function peripherals% are 'rogrammable 18" 1ontroller 'rogrammable 9loppy Disc 1ontroller 'rogrammable &ard Disc 1ontroller 'rogrammable :eyboard and display interface.

"he functioning of these devices varies depending on the type of )* device they are controlling.

PROGRAMMABLE PERIPHERAL INTERPHASE - 8 !!A Introduction !"#$ introduced this programmable peripheral interface ('' % chip ./003 for interfacing peripheral devices to the .;.0 system. "his versatile chip ./003 is used as a general purpose peripheral device for parallel data transfer between microprocessor and a peripheral device by interfacing the device to the system data bus. "he '' has three programmable )* ports vi<., 'ort 3, 'ort = and 'ort 1 each of . bit width. 'ort 1 can be treated as two ports 'ort 1 upper ('15,7% and 'ort lower ('14 - ;% and these two can be independently programmed as !'>" or *>"'>" ports also.

S"#i$nt F$"tur$%
i. t is a general purpose programmable )* device which is compatible with all !"#$ processors and also most other processors. ii. t provides /7 )* pins which may be individually programmed in two groups. iii. "his chip is also completely ""$ compatible. iv. t is available in 7; pin D '.. v. t has three . bit ports. 'ort 3, 'ort = and 'ort 1. 'ort 1 is treated as two 7 bit ports also. vi. "his ./00 is mainly programmed in two modes (a% the )* mode and (b% "he bit set)reset mode (=S8% mode. "he )* mode is further divided into three modes+ Mode ;, Mode 6, and Mode /. vii. 3n . bit control resister is used to configure the modes of ./00. "here is also another . bit port called control port, which decides the configuration of ./00 ports. "his port is written by the microprocessor only.

Pin D$%cri&tion
"he ./003 is a 7; pin D ' chip which works at single ? 0@ D1. "he pin diagram of ./003 chip is shown in 9ig. "he pin details of the chip are given below.

'34 '3/ '36 '3; 1S (!D 36 3; '15 '1A '10 '17 '1; '16 '1/ '14 '=; '=6 '=/

6 / 4 7 0 A 5 . 2 6; 66 6/ 64 67 60 6A 65 6. 62 /;

7; 42 4. 45 4A 40 47 44 4/ 46 4; /2 /. /5 /A /0 /7 /4 // /6

'37 '30 '3A '35 8eset D; D6 D/ D4 D7 D0 DA D5 @cc '=5 '=A '=0 '=7 '=4

8 !!A

Pin Con'i(ur"tion o' 8 !! )To& *i$+ , DIP P"c-"($.

Pin d$%cri&tion o' 8 !!A

4

S$#$ction o' 8 !!A Port% "nd t/$ir 'unction

B#oc- Di"(r"0 o' t/$ 8 !!A

"he functional diagram of ./003 is shown in 9ig. #ach functional unit is explained below.

Function"# B#oc- Di"(r"0 o' 8 !!A Pro(r"00"1#$ P$ri&/$r"# Int$r'"c$ )PPI. D"t" Bu% 1u''$r "his tri,state bidirectional . bit buffer is used to interface the data bus of ./003 to the system data bus. Data is transmitted or received by the buffer when the 1'> executes input or output instructions control words and status information is also transferred through the data bus buffer. R$"d2Writ$ "nd Contro# Lo(ic "he function of this block is to manage all the internal and external transfers of both data and control or status words. t accepts inputs from the 1'> and inturn issues commands to both of the control groups. Grou& A "nd Grou& B Contro#% #ach of the group 3 and group = control blocks receives control words from the 1'> and issues suitable commands to the ports associated to it. "he group 3 control block controls port 3 and port 1 >pper ('15 , '17% where are group = control block, controls port = and port 1 lower ('14 , '1;% Port A t has one . bit data output latch)buffer and one . bit input latch buffer. "his port 3 can be configured in all the three modes+ mode;, mode 6, mode /. Port B "his has an . bit data input)output latch) buffer which can be programmed both in mode ; and mode 6. Port C t has one . bit unlatched input buffer and an . bit output latch)buffer. "his port can be divided into two 7 bit ports under the mode control. "hese two ports can be used as control signals for ports 3 and = in the handshake mode.

O&$r"tion"# Mod$% o' 8 !!

./00 can be mainly configured in two modes. i% nput)*utput mode ( )* mode% ii% =it Set,8eset mode (=S8 mode% In&ut2Out&ut 0od$ n )* mode, the ports of ./00 acts as programmable ports, while in =S8 mode only port 1 ('1; , '15% can be used to set or reset its individual port bits. "he ./00 can programmed to operate in any one of the following modes.
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i% Mode ; (simple mode%

ii% Mode 6 (strobed mode%

iii% Mode / (bi,directional bus mode% Mod$ 34 Si0&#$ I2O Mod$ "his is a simple )* or basic mode in which no hand shake signals are used. 'ort 3 and 'ort = are used as two simple . bit )* ports and port 1 as two 7 bit ports it is used with those )* devices whose timing characteristics are clearly known. 9or example, if an )* device sends a byte for every 6; ms, to the >', we can execute the ! instruction for every 6; ms to receive the data. A## t/$ 5 &ort% c"n 1$ &ro(r"00$d in Mod$ 36 Mod$ 74 Stor1$d Mod$ "his is a handshake )* mode (strobed mode% in which the data transfer is controlled by handshake signals. 9or example, when the microprocessor wish to transfer the data to a relatively slow device like printer, for proper transfer of data handshake signals are used to inform the processor whether the printer is ready to receive the data or not. "he data transfer by handshake use both port 3 and port = as . bit input)output ports. 'ort 3 uses the upper three signals '14, '17 and '10 where as port = uses the lower signals '1 /, '16 and '1; for handshaking signals. "he remaining two lines of port 1 are used in Mode ;. "he unique feature of this mode is that the data transfer can take place without direct 1'> intervention. Bhen port 3 or port = are configured as input ports the three control signals used are =9 ( nput =uffer 9ull%, (strobe% and !"8 ( nterrupt request%. Similarly when port 3 or port = are programmed as mode 6 output ports, the three control signals used are (*utput =uffer 9ull%, (3cknowledge% and !"8 ( nterrupt 8equest%. 3 very important point to be remembered is that only port 3 and port = can be configured in mode 6. Mod$ 4 Bidir$ction"# I2O )or. Stro1$d Bidir$ction"# I2O n this mode port 3 alone can be configured to both, transmit and receive data. 'lace over a single . bit data bus using handshaking signals. "his mode of operation is useful when transferring data between two computers. 3s it is bidirectional )*, it needs more number of handshake signals i.e., 0 lines of port 1, '14 , '15. "he remaining lines of port 1 can be used by port = in Mode 6. So, when port 3 is programmed to operate in mode /, port = can operate in mode; or mode6. f programmed for mode ;, '1; , '1/ can be programmed as mode ; inputs or outputs. f port = is programmed for mode 6, '1; , '1/ become handshake signals for this port. n conclusion, we can understand that, Port A c"n 1$ in Mod$ 38 Mod$ 7 or Mod$ 6 Port B c"n 1$ in Mod$ 3 or Mod$ 7 Port C c"n on#9 1$ in Mod$ 36 !ote+ 3 high on reset line of ./00, resets all the ports 3, = and 1 to work as input ports in mode ;. "he reset pin of ./00 is generally connected to 8eset *ut pin of .;.0.
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BSR )Bit S$t2R$%$t. Mod$ "he =S8 mode is related to only with the . bits of port 1, which can be set or reset by writing an appropriate control word in the control register. 3 control word with bit D 5 C ; is treated as a =S8 control word. t does not change any previously transmitted control word with bit D5C6.So, the )* operations of port 3 and port = are not changed by a =S8 control word. n =S8 mode, individual bits of port 1 can be used for applications such as an *!)*99 switch.

Contro# Word
"he ./003 has an . bit control register. "he contents of this register called, the control word, decides the )* function for each port. "his register is allowed to write a control word when 3; and 36 lines are at logic 6. "his register is not accessible for a read operation.

n the control word register, the bits D; through D/ correspond to the group = control block as shown in 9ig.7.4. =it D; configures the lower four lines of port 1 for input ) output operation.

Contro# Word For0"t o' 8 !! "nd Contro# Bit D$%cri&tion

Bhen

D; C ;, port 1 $ower , output port D; C 6, port 1 $ower , input port.

"he bit D6 configures port = as an . bit wide input or output Bhen D6 C ;, port = is output port. D6 C 6, port = is input port. "he bit D/ is the mode select bit for port = and the lower 7 bits of port 1. D/ C ;, selects Mode ; D/ C 6, selects Mode 6. "he bits D4 through DA in the control register correspond to the group 3 control. =its D4 and D7 of the control register are used to configure the operation of the upper half of port 1 and complete port 3. Bhen D4 C ;, port 1 upper is output port. or D4 C 6, port 1 upper is input port. or D7 C 6, port 3 is input port. "he bits D0 and DA are used to select among the three modes of operation names mode ;, mode 6 and mode /. DA D0 C ;; selects mode ; C ;6 selects mode 6 C 6x selects mode /. "he last control register bit D5 is the mode set flag, which is shown in 9ig.4. D5 D5 C 6 selects )* mode and C ; selects =S8 mode. Similarly when D7 C ;, port 3 is output port.

BSR Mod$ Contro# Word R$(i%t$r For0"t

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"he bit set)reset function is not really a control word. nstead, it allows individual bits of port 1 to be set or reset. =ut only one bit can be set or reset at a time. *ne of the advantages of this mode is that individual bits of port 1 can be changed without changing any of the others. "his is needed when port 1 is used to control the *!)*99 status of several external devices. 9or example, the device connected to '17 can be turned *! without affecting the status of any devices connected to the other seven outputs. "he bit set)reset function is used in mode 6 and / to enable interrupt outputs available in these modes.

Pro(r"00"1#$ Int$r*"# Ti0$r - 8 !52!:

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Introduction t is always possible to generate accurate time delays using the microprocessor system by using software loop programs. =ut that will waste the precious time of 1'>. &ence !"#$ introduced the chips ./04)./07 which is a hardware solution for the problem of generating accurate time delays. "hese chips can be used for applications such as a real,time clock, event counter, a digit alone shot, a square wave generator and also as a complex wave form generator. S"#i$nt F$"tur$% ./07 is an upgraded version of ./04 and they are pin,compatible. "he features of these chips are almost same except that, ./07 can operate with higher clock frequency ranging from D1 to . M&< and 6; M&<, whereas the ./04 can operate with clock frequency from D1 to / M&<.

./07 includes a status read,back command that can latch the count and the status of the counters. "his command is not available in ./04. ./04 uses !,M*S technology where as ./07 uses &,M*S technology. "he chips are packaged in /7 pin D ' and requires a single ?0@ D1 power supply. "hree identical 6A bit counters that can operate independently in any of the six modes are available. "he counters are down counters. "hese chips are compatible with all !"#$ and most of the other microprocessors. "o operate a counter, a 6A bit count is loaded in its register and on command beings to decrement the count until it reaches ;. 3t the end of the count, it generates a pulse that can be used to interrupt the microprocessor. "he counters can be programmed for either binary or =1D count. "he read,back command of ./07 allows the user to check the count value and current status of the counter.

Pin D$%cri&tion "he chips ./04)07 is packaged in a /7 pin D ' and require a single ?0@ power supply. "he pin diagram is shown in 9ig. "he description of each pin is given below.

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Pin Di"(r"0 o' 8 !52!:)To& *i$+ Di&.

B#oc- Di"(r"0 o' 8 !: "he block diagram of the 'rogrammable nterval "imer is shown in 9ig. "he block diagram includes three counters , 1ounter ;, 1ounter 6 and 1ounter /, a data bus buffer,
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read)write control logic and a control word register. #ach counter has two input signals 1$*1: and (3"# and one *>"'>" signal,out.

Function"# B#oc- Di"(r"0 o' 8 !528 !: D"t" Bu% Bu''$r "his tri,state bidirectional . bit buffer is used to interface the ./04 to the system bus. Data is transmitted or received by the buffer upon execution of !'>" or *>"'>" 1'> instructions. "he data bus buffer has three basic functions. "hey are i. 'rogramming the M*D#S of the ./04. ii. $oading the count registers and iii. 8eading the count values. R$"d2Writ$ Lo(ic "he read)write logic accepts inputs from the system bus and in turn generates control signals for overall device operation. t is enabled or disabled by so that no operation can occur to change the function unless the device is selected by the system logic. RD 4 3 low on this pin informs the ./04 that the 1'> is inputting data in the form of counters value.

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WR 4 t is an active low pin. 3 low on this pin informs the ./04 that the 1'> is outputting data in the form of mode information or loading counters. A38A74 "hese two lines are address lines used to select one of the three counters and the control word register as shown in the table for mode selection. CS(C/i& S$#$ct.4 t is an active low pin. 3 low on this input enables ./04. !o read or write will occur unless the device is selected. "he input has no effect on the actual operation of the counters.

S$#$ction "nd 'unction o' 8 !52!: Count$r% Contro# Word R$(i%t$r "his register is selected when 3;, 36 are at logic 6. t then accepts the information from the data bus buffer and stores it in a register. "he information stored in this register controls the operation M*D# of each counter, selection of binary or =1D counting and the loading of each count register. "he control word register can only be written to into, but no read operation is possible. Count$r 38 Count$r 78 Count$r "hese three functional blocks are identical in operation. #ach counter consists of a single 6A bit, pre,settable D*B! counter. "he counter can operate in either binary or =1D and its input, gate and output are configured by the selection of modes stored in the control word register. "he counters are totally independent. "he counter can be read by a simple 8#3D operation for event count applications. O&$r"tion"# D$%cri&tion "he complete functional operation of ./04 is programmed by the system software. 3 set of control words must be sent out by the 1'> to initiali<e each counter of ./04)./07 with the
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desired M*D#. *nce programmed, the ./04 is ready to perform whatever timing tasks it is assigned to perform. "he actual counting operation of each counter is totally independent and additional logic is provided on,chip so that the usual problems associated with efficient monitoring and management of external, asynchronous events or rates to the micro computer system have been eliminated. Pro(r"00in( 8 !52!: #ach counter of ./04)07 is individually programmed by writing a control word into control word register. "he control word register is shown in 9ig.below. "he different bits of this . bit register are either set or reset for the operation of the counters. "he various options are given below.

Contro# Word For0"t 1ounter selection is done by the DA, D5 bits.

"he bits D7, D0 decides the counter 8#3D)$*3D operations as shown below.

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"he bits D6, D/ and D4 decides the mode operation ./04)07 can be configured in six modes. "his mode selection is done by these bits as shown below.

"he D; bit decides whether the counter is a 6A bit binary counter or a =1D counter. Bhen D; C ; it acts as a 6A bit binary counter. D; C 6 it acts as a binary coded decimal counter (=1D% Bhile using ./04)07 we must write the control word to initiali<e the counter to be used. 9or every counter we use, the control word must be written and select the counter and set it up. ./04)07 can operate in six different modes. "he modes of operation are explained below. Mod$ 3 )Int$rru&t on T$r0in"# Count. "he output of the counter will be initially low after the mode set operation. 3fter the count is loaded into the selected counter register the output will remain low and the counter will count. Bhen terminal count is reached, the output will go high and remain high until the selected count register is reloaded with the mode or a new count is loaded. Mod$ 7 )Pro(r"00"1#$ on$ %/ot. n this mode, the out signal is initially high. Bhen the (3"# is triggered, the *>" goes low, and when count reaches ;, the *>" goes high again. "hus a one shot signal is generated due to the signal on the (3"#. Mod$ )R"t$ G$n$r"tor. t is a divide by ! counter. n this mode, a pulse is generated that is equal to the clock period at a given interval controlled by the count that is loaded. Bhen the count is loaded, the *>" signal stays high until the count reaches 6, at this point the *>" signal goes low for one clock period. 3fterwards, the count is reloaded automatically and the cycle repeats, generating a continuous string of pulses. Mod$ 5 )S;u"r$-+"*$ G$n$r"tor. n this mode, when the count is loaded, the *>" signal is high. "he count is then determined by two with each clock cycle. Bhen the count reach ; the *>" signal goes low and the count is reloaded automatically. 3s this is repeated continuously a square wave is generated on the *>" signal. "he period of the square wave is controlled by the count value.
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Mod$ : )So't+"r$ Tri(($r$d Stro1$. n this mode, the *>" signal is initially high and goes low for one clock period when the count reaches ;. So, one strobe pulse (low% is generated for each count. "he count must be reloaded for more strobe signals. Mod$ ! )H"rd+"r$ - Tri(($r$d Stro1$. "his mode is similar to mode 7, except the strobe is hardware triggered with a signal on the (3"# signal. "he *>" signal is initially high. Bhen the (3"# signal goes from low to high, the count starts and when it reaches ;, the *>" signal goes low for one clock period. R$"d-B"c- Co00"nd "he read,back command in the ./07 allows the user to read the count and the status of the counters ("his command is not available in ./04%. Bhen the read,back command is selected in the control word (S16 S1; , 66% each of the counters specified is latched and then the count and) or the status may be read for each counter latched. "he command is written in the control register and the count of the specified counter(s% can be latched if 1*>!" (bit D0% is ;. 3 counter or a combination of counters is specified by making the respective 1!" bits (D6, D/ and D4% high. "he read,back command format is shown below.

D; C ; (8eserved for future expansion% 1!";, 1!"6, 1!"/ are counter select bits. R$"d 1"c- co00"nd 'or0"t "he S"3">S of the counters can be read if D 7 bit (S"3">S% of 8ead,back command is ;. "he 8ead,back command eliminates the need of writing separate counter latch commands for different counters.

Pro(r"00"1#$ Int$rru&t Contro##$r - 8 !<

Introduction "here is an absolute need of this 'rogrammable nterrupt 1ontroller for nterfacing )* devices to the microprocessor "he .;.0 processor has 0 interrupt lines namely, "rap, 8S" 5.0, 8S" A.0, 8S" 0.0 and !"8. So, we can interface five )* devices, which can perform the interrupt driven data transfer safely. =ut, suppose we wish to connect more than five )* devices, to the microprocessor, then we may have to connect more than one )* device to the interrupt lines. "his will affect the interrupt driven data transfer and the microprocessor has to perform polling. i.e, it has to check each device, which is in need of interrupt service. "his polling has the dis,advantage of long time and slow interrupt response. &ence to overcome all
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these problems, !"#$ introduced the /. pin D ' chip ,./02. "his device accepts interrupt requests from as many as . devices independently and as many as A7 )* devices by cascading method. S"#i$nt F$"tur$% !"#$ ./02 is a single chip programmable interrupt controller which is compatible with .;.0, .;.A and .;.. processors. t is a /. pin D ' 1 with !,Mos technology and requires a single ?0 D1 supply. t handles up to eight vectored priority interrupts for the 1'> and cascadable for up to A7 vectored priority interrupts without the need of any additional circuitry. when two ./02s are cascaded through cascade lines the first ./02 will act as master and the second ./02 will act as a slave.

Pin D$%cri&tion "he pin diagram of ./02 is shown below . "he pin details are given below

Pin Di"(r"0 o' 8 !<

B#oc- Di"(r"0 "he block diagram of programmable interrupt controller is shown in 9ig. below. "he block diagram consists of eight sub units. "hey are 1ontrol logic, 8ead)write logic, Data bus

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buffer. "hree register ( 88, S8 and M8%, 0 priority resolver and cascade buffer. "he functions of each unit are explained below.

Priorit9 R$%o#*$r "his logic unit determines the priorities of the bits set in the 88. "he highest priority is selected and strobed in to the corresponding bit of the S8 during pulse. Int$rru&t M"%- R$(i%t$r )IMR. "he M8 stores the bits which mask the interrupt lines. "he M8 operates on the 88. Masking of a higher priority input will not affect the interrupt request lines of lower priority.
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Contro# Lo(ic "his unit has two pins. !" ( nterrupt% as an output pin and (interrupt acknowledge% as an input pin. "he !" is connected to the interrupt pin of the microprocessor unit. Bhenever an interrupt is noticed by the 1'>, it generates signal. Wor-in( o' 8 !< "he ./02 accepts interrupt requests from any one of the . )* lines ( 8; , 85%. "hen it ascertains the priority of the interrupt lines. "hen it ascertains the priority of the interrupt lines. Suppose, the received interrupt has higher priority than currently serviced, it interrupts the microprocessor and after receiving the interrupt acknowledgement from microprocessor. t provides a 4 byte 13$$ instruction. "he sequence of steps that occur when an interrupt request line of ./02 goes high is as follows. "he ./02 accepts the requests on 8 ; , 85 in 88. "hen it checks the contents of M8 whether that request is masked or not. "he ./02, then checks S8 to know the interrupt levels that are being currently serviced. 3fter this ./02 sends a high !" to .;.0 processor. !ormally, it is the Dob of the priority resolver to check the contents of 88, M8 and S8 and decide whether to activate !" output of ./02 or not. !ow .;.0 processor responds by suspending the program flow at the end of the current instruction and makes low. *n receiving, ./02 sends code for 13$$ to the microprocessor on D5,; bus.

"his code for 13$$ in 8 register of ./02 causes the .;.0 to issue two more signals. Bhen goes low the second time, ./02 places $S= of SS address on the data bus. Bhen goes low the third time, ./02 places the MS= of SS address ont he data bus. !ow, the microprocessor branches to the SS after saving the contents of program counter on the stack top. 3fter finishing the SS, the control returns to the main program by popping the top of stack to '1.

Pro(r"00in( 8 !< "he ./02 requires two types of command words namely, nitiali<ation 1ommand Bords ( 1B% and *perational 1ommand Bords (*1B%. "he ./02 can be initiali<ed with four 1Bs, the first two are essential and the other two are optional based on the modes being used. "hese words must be issued in a sequence. *nce the ./02 is initiali<ed, the ./02 can operate in various modes by using three different *1Bs.

Dir$ct M$0or9 Acc$%% )DMA.

Bhen large amount of data is to be transferred between microprocessor and )* device it is a very time consuming operation and the 1'>s time is wasted. f the )* port can directly access memory for data transfer, without 1'> intervention, that will be more efficient. So, in any microprocessor system, if the data transfer occurs without the intervention of the 1'>, that

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method is known as Direct Memory "ransfer technique (DM3%."his is explained in the figure below.

3s an example , the data transfer between a floppy disk and a 8)B memory in a computer system is based on DM3. "o perform the DM3 transfer in .;.0 based systems two pins &*$D and &$D3 (&old 3cknowledge% are used. 3n )* device which wishes to transfer data using DM3 scheme, sends the &*$D signal to the 1'>. *n receiving the &*$D signal from an )* device, the 1'> sends a hold acknowledge signal (&$D3% to the )* device to indicate that it has received the &*$D request and it will give,up the buses in the next machine cycle. "he )* device takes over the control of buses and directly transfer data to the memory or reads data from the memory. "his data transfer can be shown by the 9ig.7.67. "here are two types of DM3 schemes. "hey are a% =urst mode DM3 b% 1ycle stealing DM3 Bur%t Mod$ DMA "his method is used when a large data block is to be transferred between a )* device and main memory. n each DM3 cycle one byte will be transferred and the DM3 controller givesup control of system buses only after all the data has been transferred. "he DM3 controller interrupts the microprocessor and &*$D request is withdrawn. "his technique was widely used by magnetic disk drives. n case of magnetic disks data transfer can not be stopped or slowed down without loss of data. &ence burst mode data transfer scheme is useful. C9c#$ St$"#in( DMA "his method is used when the )* device is relatively slow. 3fter a DM3 cycle which results in a byte of data transfer, the )* device withdraws the DM3 request. So, the DM3 controller withdraws the &old request by making it low. So, the 1'> comes out of &*$D mode and continues to execute the main program. 3fter some time when the )* device is again ready, it once again activates the data request )' of DM3 controller. So, DM3 again activates the &*$D pin and waits for &$D3. !ow the data transfer is performed again. n this way the

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complete data is transferred. 3s the data transfer occurs during certain cycles of 1'>, it is called cycle stealing DM3.

DMA Contro##$r - Int$# 8 5=28 !=

n Direct Memory 3ccess technique, the data transfer takes place without the intervention of 1'>, so there must be a controller circuit which is programmable and which can perform the data transfer effectively. 9or this purpose ntel introduced the controller chip ./05 which is known as DM3 controller. 3 DM3 controller temporarily borrows the address bus, data bus and control bus from the microprocessor and transfers the data bytes directly from the port to memory devices. 3s the transfer is handled totally by hardware, it is much faster than software program instructions. 3 DM3 controller can also transfer data from memory to a port. S"#i$nt F$"tur$% ntel ./05 is a programmable, 7,channel direct memory access controller i.e., four peripheral devices can request data transfer at any instant. "he request priorities are decided internally. #ach channel has two signals, D8E (DM3 8equest% and (DM3 acknowledge%. #ach channel has two 6A bit registers. *ne for the memory address where the data transfer should being and the second for a 67,bit count. "here are also two .,bit registers one is the mode set register and the other is status register. t can operate both in slave and master mode. t is a totally ""$ compatible chip. 'in Diagram+ ./05 is a 7; pin 1 package which requires a single ?0@ supply for its operation. "he pin details are as follows. "he pin diagram is shown in 9ig below.

Pin Di"(r"0 o' 8 !=

B#oc- Di"(r"0 "he functional block diagram is shown below. t consists of
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 Data bus buffer 8ead)Brite logic DM3 channels 1ontrol logic Mode set 8egister Status 8egister D"t" Bu% Bu''$r "hree state bidirectional, . bit buffer interfaces the ./05 to the system data bus. Bhen the ./05 is being programmed by the 1'>, eight bits of data for DM3 address register, a terminal count register or the mode set register are received on the data bus. Bhen the 1'> reads the DM3 address register, a terminal count register or status register, the data is sent to the 1'> over the data bus. Bhen ./05 is operating as Master, during a DM3 cycle, it gains control over the system buses. n this mode, the ./05 sends out the . MS=s of the DM3 address register of the channel being serviced on the D;,D5 pins at the starting of each DM3 cycle to the ./6/ latch. 3fter this, the bus is released to handle the memory data transfer during the remaining DM3 cycle. R$"d2Writ$ Lo(ic

Pin "nd B#oc- Di"(r"0 o' 8 !=

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n the slave mode, when the 1'> reads data from or writes data to the ./05, the read)write logic accepts the )*8 (or% )*B signals and decodes the least significant 7 address bits (3; , 34%. During DM3 cycles, when ./05 is the master, the read)write logic generates the )* read and memory write or )* write and memory read signals which controls the data link with the peripheral that has been granted DM3 cycle. "he different signals are )I2O R$"d. t is active low bidirectional three,state line. n the slave mode, it is an input, which allows the .,bit status register or upper)lower byte of a 6A bit DM3 address register of terminal count register to be read. n the master mode, is a control output, which is used to access data from a peripheral during the DM3 write cycle. )I2O Writ$. t is an active low bi,directional tri,state line. n slave mode, it is an input, which allows microprocessor to write. n the master mode, is a control output, which allows data to be ouput in the peripheral during DM3 read cycle. CLK )C#oc- In&ut. "his is the clock output of the microprocessor. RESET t is an asynchronous input from the microprocessor which disables all DM3 channels by clearing the mode register and tri,states all control lines. A3 - A5 )Addr$%% Lin$%. "hese least significant four address lines are bidirectional. n the slave mode they are inputs, which select one of the registers to be read or programmed. n the master mode, they are outputs, which constitute the most significant 7 bits of the 6A bit memory address generated by the ./05. )C/i& S$#$ct. t is an active low input which enables the )* read or )* write input when the ./05 is being read or programmed in the slave mode. n the master mode, is automatically disabled to prevent the chip from selecting while performing the DM3 function. Contro# Lo(ic B#oc"his block controls the sequence operations during all DM3 cycles by generating the appropriate control signals and 6A bit address that specifies the memory relations to be accessed. A: - A= )Addr$%% Lin$%. "hese four address lines are tri,stated outputs which contains 7 to 5 of the 6A bit memory address generated by the ./05 during all DM3 cycles. READ> "his is an asynchronous input used to insert wait states during DM3 read or write machine cycles. Bait states are included between S4 and S7 states of the duty transfer.
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HR? )Ho#d R$;u$%t. "his output line requests the control of the system bus. "his is connected to the &*$D input of .;.0. DMA C/"nn$#% "he ./05 has four separate DM3 channels each channel with two 6A bit registers (6% a DM3 address register (/% 1ounter register. =oth these registers must be initiali<ed before a channel is enabled. "he DM3 address register is loaded with the address of the first memory location to be accessed. "he value loaded into the low order 67 bits of the terminal count register specifies the number of DM3 cycles minus one before the terminal count output is activated. DR?3 - DR?5 )DMA R$;u$%t. "hese are active low signals one for each of the four DM3 channels. "he output acts as a chip select for the peripheral device requesting service. "he D31: line becomes ; and then 6 for each byte of DM3 data transfer. Mod$ S$t R$(i%t$r "his register is used to set the mode of operation of ./05. t is normally programmed by the 1'> after the DM3 address register and terminal count registers are initiali<ed. "his register is cleared by 8#S#" input, by disabling all options. "he mode set register is shown in 9ig. =y setting the 7th bit we can opt for rotating priority. !ormally D8E ; has highest priority and D8E4 has lowest priority. =ut in the rotating priority mode the priority of the channels has a circular sequence and after each DM3 cycle, the priority of each channel changes. f the rotating priority bit is reset, (is a <ero% each DM3 channel has a fixed priority in the fixed priority mode. i.e., channel ; has highest priority and channel,4 has lowest priority. "he terminal count ("1% bits (bits ; , 7% for the four channels are set when the "erminal 1ount output goes high for a channel. "he "1 bits in the status word are cleared when the status word is read or when the ./05 receives a 8eset input. "he update flag is cleared when (i% ./05 is reset or (ii% the auto load option is set in the mode set register or (iii% when the update cycle is completed. "he update flag is not affected by a status read operation. DMA Wor-in( n .;.0 microprocessor two lines dedicated for DM3 operation. "hey are &*$D and &$D3. f any device is in need of DM3 service it activates a D8E line. !ow the ./05 in turn sends out &*$D request (&8E% to microprocessor on &*$D line. "he microprocessor then completes the current machine cycle and then goes to &*$D state, where the address bus, data bus and the related control bus signals are tri,stated. !ow the &$D3 signal is activated. "he DM3 controller which is a slave to the microprocessor so far will now become the master. "he DM3 controller resolves the priorities of the requesting )* devices and accordingly sends a signal to the suitable )* device. Bhen the microprocessor is the master, D5,; is used by the ./05 for communication with microprocessor and 34,; are i)p lines to ./05 to select register for communication with microprocessor. =ut in the &*$D state the ./05 sends out most significant byte of memory address 360,. on D5,;, sends out address information on 34,; and also on 35,7. !ow become
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output lines of ./05. So, the ./05, after sending out a signal to the requesting )* device, generates and signals if it is a DM3 read operation. ./05 generates and signals for DM3 write operation. "hen a byte of data is transferred between )* device and memory directly in 7 clock cycles. "his is known as a DM3 machine cycle, at the end of which, the number of bytes to be transferred is decremented by 6 in the count register and address register is incremented by 6 to point to the next memory address for data transfer.

@SART-8 !7)@ni*$r%"# S9nc/ronou% A%9nc/ronou% R$c$i*$r Tr"n%0itt$r.

"he ./06 is a >S38" (>niversal Synchronous 3synchronous 8eceiver "ransmitter% for serial data communication. n a microprocessor system the 1'> has to perform the data conversion like serial to parallel or parallel to serial and transmit the data to peripheral devices. "his process will wastes the precious time of the 1'>. n order to release the 1'> from this burden and continue its processing work , !"#$ introduced a /.,pin D ' chip called the programmable communication interface. "his chip will take care of all the communication activities and lessens the burden of the Microprocessor ."his chip is compatible with all the !"#$ processors. "his ./06 receives parallel data from the 1'> and transmits serial data after conversion. Similarly it also receives serial data from conversion. "he ./06 is a /. pin D ' chip which works at 0 volts D1. "he 'in diagram of ./06 is shown below. outside devices and transmits parallel data into the 1'> after

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"he =lock diagram of ./06 is shown below

s"he >S38" chip consists of four important

sections ."hey are 1'> nterface F 1ontrol $ogic section "ransmitter Section 8eceiver Section Modem 1ontrol Section
.

CP@ Int$r'"c$ A Contro# Lo(ic %$ction 4 "he 1'> interface and control logic accepts signals from 8D, B8, 1$:, 1)D, 1S , D 5,; and 8#S#" pins of the system and generates the necessary signals for controlling the device operation. t consists of three registers ,.,bit data buffer register ,one 6A,bit control word register and one .,bit status word register. "he active low signals 8D, B8, 1S and 1)D ($ow% are used for read)write operations with these three registers. Bhen 1)D bar is high, the control register is selected for writing control word or reading status word. Bhen 1)D bar is low, the data buffer is selected for read)write operation. Bhen the reset is high, it forces ./063 into the idle mode. "he clock input is necessary for ./063 for communication with 1'> and this clock does not control either the serial transmission or the reception rate.

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Tr"n%0itt$r %$ction4 "he

transmitter section accepts parallel data from 1'> and converts

them into serial data. "his section is double buffered, i.e., it has a buffer register to hold an .,bit parallel data and another register called output register to convert the parallel data into serial bits. Bhen output register is empty, the data is transferred from buffer to output register. !ow the processor can again load another data in buffer register. f buffer register is empty, then "x8DG is goes to high. f output register is empty then "x#M'"G goes to high. "he clock signal, "x1 (low% controls the rate at which the bits are transmitted by the >S38". "he clock frequency can be 6, 6A or A7 times the baud rate. R$c$i*$r S$ction4 "he receiver section accepts serial data and convert them into parallel data "his receiver section is also double buffered with two registers. i.e., it has an input register to receive serial data and convert to parallel, and a buffer register to hold the parallel data.Bhen the 8xD line goes low, the control logic assumes it as a S"38" bit, waits for half a bit time and samples the line again. f the line is still low, then the input register accepts the following bits, forms a character and loads it into the buffer register. "he 1'> reads the parallel data from the buffer register. Bhen the input register loads a parallel data to buffer register, the 8x8DG line
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goes high. "he clock signal 8x1 (low% controls the rate at which bits are received by the >S38". During asynchronous mode, the signal SG!D#")=8:D#" will indicate the break in the data transmission. During synchronous mode, the signal SG!D#")=8:D#" will indicate the reception of synchronous character. MODEM Contro# S$ction4 "he M*D#M control unit allows to interface a M*D#M to ./063 and to establish data communication through M*D#M over telephone lines. "his unit takes care of handshake signals for M*D#M interface. "he Modem control signals are general purpose in nature and can be used for functions other than the Modem control if necessary."he Modem sends certain hand shake signals for proper communication between two devices. "he D"8 and 8"S are the are the hand shake signals sent out by the ./06 to Modem and they are activated by using command instruction register. "he DS8 and 1"S are the hand shake signals sent by the Modem to ./06.

BB
DSR (Data Set 8eady%+ "his signal is general purpose in nature. "his signal is used to normally test the Modem condition. "he 1'> reads its condition by Status read operation.

BBB
DTR (Data "erminal ready% +"his is an output signal which is also a general purpose. "he D"8 signal is used to control the modem operation such as Data terminal ready or rate select. t can be set low by programming the appropriate bit in the command instruction word.

BBB
RTS )R$;u$%t to S$nd.4"his output signal is normally used to control the Modem operations such as 8equest to send. "his pin can be set low by programming the appropriate bit in the command instruction word. BBB CTS (1lear to Send% +3 low on this pin enables the ./06 to transmit the serial data ,if the "x #! bit in the command byte is set to one. "his Modem control section will decrease the burden of the 1'> by converting the ; s and 6s into unique audio frequencies and transmit on the telephone network.

Pro(r"00"1#$ K$91o"rd2Di%&#"9 Int$r'"c$ - 8 =<

ntel ./52 is the programmable keyboard)display controller, used to interface the keyboard and the display unit to the Microprocessors. "he advantage of ./52 is that it is able to drive the

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signals for both the keyboard and display and hence it is possible for the microprocessor to concentrate on its processing tasks without wasting time. "he ./52 has two maDor sections. *ne is the :eyboard section and the other is the Display section. "he ./52 chip provides four scan lines and eight return lines for interfacing keyboards and a set of eight output lines for interfacing a display. "he ./52 scans a keyboard regularly and detects a key depression ,de,bounces the signal from the pressed key and stores the code for the pressed key in an internal 83M of si<e .x.."he microprocessor reads this 83M on first in first out basis. Similarly the ./52 refreshes the multiplexed display consisting of5,segment $#D digits. "he 5,segment codes for the data to be displayed are stored in a display 83M of si<e 6Ax. with in the ./52."he ./52 automatically sends the code for each data to be displayed one after the other until all digits have been displayed. "he ./52 is available as a 7; pin D ' chip and it is compatible with all the !"#$ basic processors. t works at ?0 volts D1. "he pin diagram of ./52 is shown below.

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"he keyboard section can interface to regular type,writer style keyboards or random toggle or thumb switches. "he display section drives alphanumeric displays or a bank of indicator lights. So, the 1'> is relieved from scanning the keyboard or refreshing the display continuously. "he keyboard portion can provide a scanned interface to a A7,contact key matrix. "he keyboard portion interfaces an array of sensors or a strobed interface keyboard. :eyboard depressions can be /,key lockout or !,key rollover. :eyboard entries are de,bounced and strobed in an ., charcter 9 9*. f more than . characters are entered, over,run status is set. :ey entries set the interrupt output line to the 1'>. "he display section provides a scanned display interface for any display device. =oth numeric and alphanumeric segment displays may be used as well as simple indicators. "he ./52 has 6AH. displays 83M which can be organi<ed into dual 6AH7. "he 83M can be loaded or interrogated by the 1'>. =oth right entry, calculator and left entry typewriter display formats are possible. =oth read and write of the display 83M can be done with auto,increment of the display 83M address.

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Since the ./52 is directly connected to the microprocessor, the microprocessor can program all operating modes of ./52. "he various input modes of the ./52 are scanned keyboard, scanned sensor matrix and strobed input. BLOCK DIAGRAM + "he block diagram of the ./52 is shown below and each block is explained.

n scanned keyboard mode, a key depression generates a A,bit encoding of the key position. 'osition and shift control status are stored in the 9 9*. :eys are automatically de,bounced with /,key lockout or !,key rollover. n the scanned sensor matrix, key status is stored in 83M addressable by the microprocessor. Data on return lines during control line strobe is transferred to 9 9* in strobed input. n one output mode, . or 6A character multiplexed displays are organi<ed as dual 7,bit or single .,bit and another output mode deals with right entry or left entry display formats. "he keyboard interface part of ./52 continuously scans the keyboard to check if any key has been pressed. f it finds that a particular key has been pressed it sends the code of the corresponding key to the microprocessor. "he microprocessor uses ./52 to send the result to the display device. n other words, we can say that ./52 controller transmits the data received from the 1'> to the display device. "he maDor advantage of using ./52 is that both of these activities are done without the intervention of the microprocessor. "he keyboard can be interfaced to the
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microprocessor either in the polled mode or in the interrupt mode. n the polled mode the microprocessor reads an internal flag of ./52 to check if any key has been pressed. n the interrupt mode, the processor is requested service only if a key is pressed otherwise the microprocessor can proceed with its routine activities. ./52 permits a maximum of A7 keys to be present in the keyboard. "his -$91o"rd2di%&#"9 contro##$r maintains an .,byte 9irst in 9irst out 8andom 3ccess Memory (9 9* 83M%. f the 9 9* contains a valid key entry, the 1'> is interrupted (in interrupt mode% or the 1'> checks the status (in polling mode% to read the entry. *nce the 1'> reads the key, the corresponding entry is deleted from the queue to generate space for the future keys that may be pressed. "he ./52 normally provides a maximum of sixteen 5 segment display interface with 1'>. t contains a 6A,byte display 83M that can be used either as an integrated block of 6AH. bits or two 6AH7 bit blocks of 83M. "he data entry to 83M block is controlled by 1'> using the command words of the ./52. "he I2O contro# %$ction controls the flow of data to)from the ./52. "he data buffers interface the external bus of the system with internal bus of ./52. "he )* section is enabled only if 8D (3ctive $ow% is low. "he pins 3;, 8D (3ctive $ow%, B8 (3ctive $ow% select the command, status or data read)write operations carried out by the microprocessor with ./52. Ti0in( contro# r$(i%t$r% store the keyboard and display modes and other operating conditions programmed by the processor. "he registers are written with 3;C6 and B8 (3ctive $ow% C ;. "he timing and control unit controls the basic timings for the operation of the circuit. Scan counter divide down the operating frequency of ./52 to derive scan keyboard and scan display frequencies. "he scan counter has two modes to scan the key matrix and refresh the display. n the encoded mode, the counter provides a binary count that is to be externally decoded to provide the scan lines for keyboard and display. n the decoded scan mode, the counter internally decodes the least significant / bits and provides a decoded 6 out of 7 scan on S$;,S$4. "he keyboard and the display both are in the same mode at a time. 3nother set of functional components is return buffers and keyboard debounce and control. "hese components scan for a key closure row wise. f it is detected, the keyboard debounce unit debounces the key entry (i.e. wait for 6; ms%. 3fter the debounce period, if the key continues to be detected the code of the key is directly transferred to the sensor 83M along with S& 9" and 1*!"8*$ key status. 3nother block present in ./52 is the FIFO %$n%or RAM and Status $ogic. 9 9* is used to handle the quick pressings of the key. #ach key code of the pressed key is entered in the order of the key, and in the meantime, read by the 1'>, till the 83M becomes empty. "he status logic generates an interrupt request after each 9 9* read operation till the 9 9* is empty. n scanned sensor matrix mode, this unit acts as the sensor 83M. #ach row of the sensor 83M is loaded with the status of the corresponding row of sensors in the matrix. f a sensor changes its state, the 8E line goes high to interrupt the 1'>.

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"he display address registers hold the address of the word currently being written or read by the 1'> to or from the display 83M. "he contents of the registers are automatically updated by ./52 to accept the next data entry by 1'>. "he 6A,byte display 83M contains the 6A,bytes of data to be displayed on the sixteen 5,segment displays in the encoded scan mode.

,,,,,,,,,,xxxxxxxxxxxxxxxx,,,,,,,, ACKNOWLEDGEMENTS 4 "hanks are due to 'rof.:.>daya :umar ,'rincipal ,=!M 1ollege, =angalore , a good friend and wellwisher who inspired me in microprocessor teaching during early 2;s.

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