Computer Organization And Architecture(MCA2050)

1. The ___________ model refers to both the style and method of problem description. a) Problem description c) Procedural style b) Utilized parallelism d) Data-driven

2. n a ___________ ! the al"orithm for solvin" the problem is stated. a) Problem description c) Procedural style b) Utilized parallelism d) Data-driven

#. ___________ e$ecution is characterized by the rule that an operation is activated as soon as all the needed input data is available. a) Problem description c) Procedural style b) Utilized parallelism d) Data dri!en

%. _________ &as the first mechanical device! invented by 'laise Pascal. a) Procedural style b) Data-driven c) Pascaline d) () machine

*. ___________ &as a ne& version of the +D,(-! &hich &as built by von .eumann. a) Procedural style b) Data-driven c) Pascaline d) "A# machine

/. The fourth "eneration of computers &as mar0ed by use of nte"rated -ircuits 1 -s) in place of transistors. a) True b) $alse c) -ant determined

2. Personal -omputers 1P-s)! also called as 3icrocomputers. a) %rue b) 4alse c) -ant determined

5. (ll threads of a process share its virtual address space and system resources. a) %rue b) 4alse c) -ant determined

6. 7hen the scheduler selects a process for e$ecution! its state is chan"ed from ready-to-run to the &ait state. a) True b) $alse c) -ant determined

18. -oncurrent e$ecution is the temporal behavior of the _______ 3odel. a)& client ' ser!er b)1-client .-server c) .-client .-server d).-client 3-server

11. Durin" selection! the ran0s of all competin" clients are computed and the client &ith the hi"hest ran0 is scheduled for service. a) %rue b) 4alse c) -ant determined

12. n ___________ all processin" units e$ecute the same instruction at any "iven cloc0 cycle. a) #ingle "nstruction Multiple Data b) 3ultiple nstruction )in"le Data

c) 3ultiple nstruction 3ultiple Data

d) .one of the above

1#. n &hich system a sin"le data stream is fed into multiple processin" units9 a) )in"le nstruction 3ultiple Data c) 3ultiple nstruction 3ultiple Data b) Multiple "nstruction #ingle Data d) .one of the above

1%. ___________ is the most common type of parallel computer. a) #ingle "nstruction Multiple Data c) 3ultiple nstruction 3ultiple Data b) 3ultiple nstruction )in"le Data d) .one of the above

1*. Parallel computers offer the potential to concentrate computational resources on important computational problems a) %rue b) 4alse c) -ant determined

1/. (dvances in instruction-level parallelism dominated computer architecture from the mid-1668s until the mid2888s . a) True b) $alse c) -ant determined

12. Parallelism occurrin" durin" e$ecution is called :::::::::::::. a) Problem description c) Procedural style b) (tilized parallelism d) Data-driven

15. Parallelism at the instruction level is also called middle-"rained parallelism. a) True b) $alse c) -ant determined

16. Data parallelism is re"ular! &hereas functional parallelism! &ith the e$ecution of loop-level parallelism! is usually irre"ular. 1True; a) %rue b) 4alse c) -ant determined

28. The computational model consists of the subse<uent three abstractions= 1. The basic items of computations 2. The problem description model #. The e$ecution model a) >nly 1 b) >nly 2 c) >nly1!2 d) All')2)*

21. The Turin" machine architecture operates by manipulatin" symbols on a tape. a) .eumann 22. 3atch the follo&in" 1. 3essa"es 2. (r"uments #. +lements a)1- !2-ii!#-iii i) applicative model ii) predicate-lo"ic-based model iii) ob?ects-based model d)1-ii!2- !#-iii b) %uring c) 'oth d) .one

b)1-iii!2-ii!#-

c)' iii)2 ")* ii

2#. +very ________presents the resources re<uired to e$ecute a pro"ram.

a) Process

b) Threads

c) 'oth

d) .one

2%. ( _________is the entity &ithin a process that can be scheduled for e$ecution. a) Process b) %hreads c) 'oth d) .one

2*. ( _______contains all the information relevant to the &hole life cycle of a process. a) Process 2/. +D)(a) ,lectronic Delay #torage Automatic Calculator b) +lectronic Discrete )tora"e (utomatic -omputer c) +lectric Discrete )tora"e (utomatic -omputer d) +lectric Discrete )tora"e (utomatic -alculator b) Thread c) PC+ d) .one of the above

22. The ____________ had the ability to inte"rate the functions of a computer@s -entral Processin" Unit 1-PU) on a sin"le-inte"rated circuit. a) Processor b) Microprocessor c) )upercomputerd) 3ainframe

25. _______________ computers used to support typical applications li0e business data support and lar"e-scale scientific computin". a) Processor b) 3icroprocessor c) #upercomputer d) 3ainframe

26. The performance re<uirement in an embedded application is real-time e$ecution. 1%rue;4alse) #8. ________________ is the chief ob?ective of embedded computers. a) 3a$imum -ost b) Minimum cost c) 3inimum Aesource d) 'oth b!c

#1. The &orld@s first desi"ner &as __________________. a) 4.7 Bordan b) Charles +abbage c) .euron d) .one

#2. ___________________ acts as the boundary bet&een soft&are and hard&are. a) "#A b) - )c) A )d) 'oth b!c

##. )( has ___________________ "eneral-purpose re"isters. a)5 b)'c)#2 d)/%

#%. - )- stands for ___________________. a) Comple. instruction set computer c) -omplicate instruction set computer b) -omplete instruction set computer d) -omple$ instruction set control

#*. The desi"ner should never plan for the technolo"y chan"es that &ould lead to the success of the computer. 1True;$alse)

#/. _______________ are electronic circuits manufactured by formin" interconnections bet&een semiconductor devices. a) nte"rated circuits b) microchips c) +oth d) .one

#2. Performance of the computer is improved by ____________________. a) Adopting parallelism b) microchips c) 'oth d) .one

#5. The ability of the servers to e$pand its processors and dis0s is 0no&n as _________________. a) (doptin" parallelism b) #calability c) Pipelinin" d) Temporal Cocality

#6. The main ob?ective of ____________________ is to e$tend beyond the instruction implementation to cut the total time ta0en to complete the instruction series. a) (doptin" parallelism b) )calability c) Pipelining d) Temporal Cocality

%8. ____________________ declares that the item referred in the recent times has potential to be accessed in the near future. a) (doptin" parallelism b) )calability c) Pipelinin" d) %emporal /ocality

%1. ____________________ states that the items nearby the location of the recently used items may also be referred close to"ether in time. a) )calability b) Pipelinin" c) Temporal Cocality d) #patial /ocality

%2. ____________________ can normally be dealt for performance or cost benefits. a) -ost +fficiency b) Po0er ,11iciency c) 'oth d) .one

%#. ____________________ is the product of the transistor s&itchin" and the s&itchin" rate. a) )patial Cocality b) Temporal Cocality c) Po&erd) Dynamic Po0er

%%. The number of s&itchin" transistor rate is proportional to ___________ and the performance is proportional to ______________. a)Di"h issue ratesb) sustained performance c) +oth %*. 3atch the follo&in" 1. Dependability 2. )calability #. Aeal-time performance %. )oft real-time a)1- !2-ii!#-iii!%-iv b)1- i!2-i!#-iii!%-iv i) the standard time for a particular ?ob is constrained and the number of occurrences &hen the ma$imum time is e$ceeded ii) )peed! thou"h in varyin" de"rees! is an important factor in all architectures iii) )ervers are hi"hly scalable in terms of the increasin" demand or re<uirements iv) 'rea0do&n of this type of a server is e$tremely more disastrous than the brea0do&n of a sin"le independent system c)' "!)2 iii)* ii)2 i d)1- !2-iii!#-ii!%-iv d) .one

%/. 1A )-) a) 3educed instruction set computer c) Aeduced instruction set controller b) Aelated instruction set computer d) Aeduced instruction subset computer

%2. _____ uses a capacitor to store each bit of data! and the level of char"e on each capacitor determines &hether that bit is a lo"ical 1 or 8. a) )A(3 b) )emi conductor DA(3 c) D3AM d) )emiconductor )A(3

%5. The bits of the instruction are divided into "roups called ___________. a) $ields b) Aecords c) ,alue d) (ll of the above

%6. ______________ uses an implied accumulator 1(-) re"ister for all data manipulation. a)T&o-address instructions c) Three-address instructions b)One address instructions d)4our-address instructions

*8. )election of operands durin" pro"ram e$ecution does not depend on the addressin" mode of the instruction. 1True; $alse) *1. Dard&are-accessible units of memory lar"er than one cell are called &ords. 1 %rue; 4alse) *2. ______________ instructions are implied mode instructions. a)T&o-address instructions c) Three-address instructions b)>ne-address instructions d)4ero address instructions

*#. Aelative (ddress 3ode is applied often &ith ___________ instruction. a) Bump 3ode b) Ae"ister 3ode c) +ranch Mode d) ndirect 3ode

*%. The _______________ is a special -PU re"ister that contains an inde$ value. a) 'ranch Ae"ister b) Direct Ae"ister c) "nde. 3egister c) .one

**. n an improved instruction e$ecution cycle! &e can introduce a third cycle 0no&n as the _____. a) 'ranch -ycle */. 3(A a) 3emory area Ae"ister b) 3inimized area Ae"ister c) Memory Address 3egister *2. 3'A a) Memory +u11er 3egister c) 3emory 'rea0 Ae"ister b) 3inimized 'uffer Ae"ister d) 3a$imized 'uffer Ae"ister d) 3inimized (ddress Ae"ister b) "nterrupt Cycle c) 'oth d) .one

*5. 7hen processed in the -PU! the instructions are fetched from ______________ locations and implemented. a) Consecuti!e Memory b) )e<uenced 3emory c) 'oth d) .one

*6. The ______________ and ______________ are identical in their use but sometimes they are used to denote different addressin" modes. a) 'ranch b) ?ump c) +oth d) .one

/8. >ne of the 0ey features of the 3 P) architecture is the ____________. a) rre"ular re"ister set b) 3egular register set c) 'oth d) .one

/1. T&o separate #2-bit re"isters called ____________ and ___________ are provided for the inte"er multiplication and division instructions. a)5") /O b) P-! A c)D !Pd) A!C>

/2. The instruction format is "enerally represented in a _______ bo$ denotin" the bits of the instruction as they appear in memory &ords or in a control re"ister. a) Diamond b) )<uare c) 3ectangular d) .one

The bits of the instruction are separated into "roups called fields. /#. 3atch the follo&in" 1. >peration -ode i) )pecifies the &ay the operand or the effective address is determined. 2. (ddress 4ield ii) desi"nates a memory address or a processor re"ister #. 3ode 4ield iii) )pecifies the operation to be performed. a) 1- !2-ii!#-iii b)1-ii!2-iii!#c) ' iii)2 ii)* " d)1-iii!2- !#-ii /%. C 4> implies that the last item placed on the stac0 is the first item to be ta0en out of the stac0.1 %3(,;4(C)+) /*. The operands in this mode are specified implicitly in the e$planation of the instruction. () Data 3ode b) "mplied Mode c) Ae"ister 3ode d) .one

//. The principal features of the 3 P) architecture are as follo&s= i) t has a five-sta"e e$ecution pipeline= fetch! decode! e$ecute! memory-access! &rite-result. ii) t has a re"ular instruction set &here all instructions are #2-bit. iii) There are three-operand arithmetical and lo"ical instructions. iv) t consists of 1/ "eneral-purpose re"isters of #2-bits each. a) (ll true b) (ll 4alse c) Only ")ii)iii d) >nly iv

/2. 3atch the follo&in" 1 3 P)2. 3 P)#. 3 P)% 3 P)- , a)' ")2 i) This is the ori"inal #2-bit instruction setE and is still common ii) t is an improved instruction set &ith dozens of ne& instructions iii) t has a /%-bit instruction set used by the A%888 series iv) t is an up"rade of the 3 P) ii)* iii)2 i! b)1-ii!2-iii!#- !%-iv c) 1-iii!2-ii!#- !%-iv

d)1-iii!2- !#-ii!%-iv

/5. (n implementation techni<ue by &hich the e$ecution of multiple instructions can be overlapped is called _________.

a) Pipelining

b) ,irtual parallelism

c) Coad 3emory Data

d) .one

/6. Pipelinin" is also called _______________. a) Pipelinin" b) 6irtual parallelism c) Coad 3emory Data d) .one

28. C3D is the short for ___________________. a) Cead 3emory Data b) Coad 3er"e Data c) /oad Memory Data d) .one

21. The instruction fetch se"ment can be implemented by means of a _____________. a) +ncoder b) 3ultiple$er c ) Decoder d) $"$O +u11er

22. ____________ pipelines perform only one pre-defined fi$ed functions at specific times in a for&ard direction from one sta"e to ne$t sta"e. a)/inear b) .on Cinear c) )calard) .one

2#. ________________ pipelines can perform more than one operation at a time as they have the provision to be reconfi"ured to e$ecute variable functions at different times. a)Cinear b) &on /inear c) )calard) .one

2%. .on-Cinear pipelines are also called ____________________ . a) Dynamic pipelines b) )tatic Pipelines c) 'oth d) .one

2*. _______________ are the situations that stop the ne$t instruction in the instruction stream from bein" e$ecuted durin" its desi"nated cloc0 cycle. a))caled b)5azards c) Dynamic d) .one

2/. )tructural Dazards are also called ________________ . a)Dazards b) 3esource con1licts c) Data dependency d) 'ranch difficulties

22. Data Dazards are also called ____________________ . a)Dazards b) Aesource conflicts c) Data dependency d) 'ranch difficulties

25. -ontrol Dazards are also called _______________. a)Dazards b) Aesource conflicts c) Data dependency d) +ranch di11iculties

26. Pipelinin" has a ma?or effect on chan"in" the relative timin" of instructions by overlappin" their e$ecution. 1%rue;4alse). 58. The re"ister read of F>A instruction occurs in cloc0 cycle ________________ . a)1 b)% c)d)18

51. __________ cause a "reater performance failure for a pipeline than ______________. a)Control 5azards) data hazards b) data hazards! -ontrol Dazards d) .one

52. f the P- is chan"ed by the branch to its tar"et address! then it is 0no&n as ______________ branchE else it is 0no&n as ___________.

a)Ta0en! not ta0en

b)Ta0en!unta0en c) +oth

d) .one

5#. The problem posed due to data hazards can be solved &ith a simple hard&are techni<ue called ___________________ . a) $or0arding b) 'ac0spacin" c) 'ooth d) .one

5%. 4or&ardin" is also called _________. a) 'ypassin" b) short-circuitin" c) +oth d) .one

5*. ______________ is the method of holdin" or deletin" any instructions after the branch until the branch destination is 0no&n. a) 4reeze the pipeline b) flush the pipeline c) +oth d) .one

5/. (ssume each branch as __________________ techni<ue simply allo&s the hard&are to continue as if the branch &ere not e$ecuted. a) Ta0en b) not ta7en c) 'oth d) .one

52. _____________ states the number of cycles lost to load-use stalls. a) /oad stall count b) Cead )tall count c) 'oth d) .one

55. _____________ instruction ta0es a source label and stores its address into the destination re"ister. a) /D b) DD c) )D d) .one

56. ____________ stores the source re"ister@s value plus an immediate value offset and stores it in the destination re"ister. a) /D3 b) DDA c) )DA d) .one

68. ( ___________ hazard causes the pipeline performance to de"rade the ideal performance. a) -ontrol b) Data c) #tall d) (ll

61. -P is the abbreviation for _____________. a) Cycles per "nstruction c) -omple$ity per nstruction

c) -overed per nstruction d) created per nstruction 62. The full form of 3 P) is ___________________. a) 3icroprocessor &ith nterloc0ed Pipeline )ta"es b) Microprocessor 0ithout "nterloc7ed Pipeline #tages c) 3icroprocessor &ithout nter Pipeline )ta"es d) 3icroprocessor &ithout ntel Pipeline )ta"es 6#. n recent processors dependencies are resolved ______________! by e$tra hard&are. a) Dynamically b) Directc) )tatic d) .one

6%. n ________________ the result into the re"ister file is &ritten or stored into the memory.

a) Aead 'ac0 >perand c) A;&@ 'ac0 >perand

b) 7rite 'ec0 >perand d) 8rite +ac7 Operand

6*. n Decode nstruction;Ae"ister 4etch operation! the _______________ and the __________ are determined and the re"ister file is accessed to read the re"isters. a)Opcode) operand speci1iers b) operand specifiers! >pcode

6/. 7hile processin" operates instructions! A )- pipelines have to cope only &ith ________. a) 3emory >perands c) 'oth b) 3egister Operands d) .one

62. n A )- architecture! instructions are of a uniform len"th 1%rue; 4alse). 65. 3icroprocessors &hich follo& the - )- philosophy. a) ntel 58$5/ b) 3otorola /5G series c) +oth d) .one

66. ______________ adds t&o numbers and produces an arithmetic sum. a) Carry propagation adder a) Dalf (dder b) 4ull (dder d) .one

188. n traditional pipeline implementations! load and store instructions are processed by the ______. a) )lave b) Master Pipeline c) Pipeline d) .one

181. The consistency of instruction completion &ith that of se<uential instruction e$ecution is specified b _______________. a) Processed consistency b) Processor consistency d) .one 182. Aeorderin" of memory accesses is not allo&ed by the processor &hich endorses &ea0 memory consistency does not allo& 1True;$alse). 18#. _____________ is not needed in sin"le <ueue method. a) Pipelinin" b) 3enaming c) 'oth d) .one

18%. n reservation stations! the instruction issue does not follo& the 4 4> order. 1 %rue; 4alse). 18*. The number of pipeline sta"es used to perform a "iven tas0 are=! 1. )pecification of the subtas0s to be performed in each of the pipeline sta"es! 2. Cayout of the sta"e se<uence! that is! &hether the sta"es are used in a strict se<uential manner or some sta"es are recycled! #. Use of bypassin" %. Timin" of the pipeline operations! that is! &hether pipeline operations are controlled synchronously or asynchronously. a)%%%% b)4444 c)TT44 d)44TT

18/. ntel processor 1i5/8) &hich has

a),C 7

b)scalar

c) +oth

d) .one

182. The desi"n space of pipelines can be sub divided into a) basic layout of a pipeline b)dependency resolution c) +oth d) .one

185.___________________ adds three input numbers and produces one sum output. a)-P( b)C#A c)C3D d) A )-

186. The methodolo"y! &hich involves separation of dependent instructions! minimizes data;structural hazards and conse<uential stalls is termed as__________________. () #tatic scheduling ') Dynamic schedulin" c) 3emory schedulin" d) none

118. To commence &ith the e$ecution of the )U'D! &e need to separatethe issue method into 2 parts= firstly ___________ and secondly___________. a) -hec0 the system hazards! &ait for the system absence of a data hazards b) Chec7 the structural hazards) 0ait 1or the absence o1 a data hazards c) -hec0 the structural D cable! &ait for the instruction of a system d) .one of these 111. _______________ sta"e precedes the issue phase9 a) (n of system b) (n instruction of system admin c) An instruction 1etch

112. The ________________ sta"e follo&s the read operands sta"e similarto the DCF pipeline. a) ,: b) PF -) +F D) FT

11#. 7hen the pipeline e$ecutes ____________________ before (DDD! it violates the interdependence bet&een instructions leadin" to &ron" e$ecution. a) 3UCT'! D , b) )U3-! D ,c) #(+D) ADDD d) (DD'! (DD-

11%. The ob?ective of scoreboard is achieved &ith ______________ or______________________ functional units or both. a) 4la"! instruction b) Pipelined) multiple c) pipelined! sin"le

11*. The source operand for (DDD is ____________! and is similar to destination re"ister of )U'D. a) 4/ ') 41 -) 46 d) $;

11/. The 4U status ____________________ sho&s &hether it is busy or idle. a) +usy b) 4ree c) 7ait d) none of these

112.Tumasulo scheme &as invented by ______________. a) Darbor Tomasulo b) 3obert %omasulo c) Tarboro Tomasulo

115. The ________________ could hold # operations for the 4P adder and 2 for the 4Pmultiplier.

a) '3 #%8;52/

') '3 #2%;52

c) "+M *-0<='

d) '3 21#;68

116. The ____________ and ______________ are used to store the data;addresses that come from or "o to memory. a) /oad bu11ers) store bu11ers c) Coad operatin" system! load buffers b) Coad instruction! store buffer d) none of these

128. The branch-prediction buffer is accessed durin" the ______ sta"e. a) "D b) + D c) + D d) none of these

121. The ______ field helps chec0 the addresses of the 0no&n branch instructions a) Data b) system c) /oo7up d) none

122. 'ufferin" the actual Tar"et- nstructions allo& ____________. a)+ranch $olding b) soft&are 4oldin" c) data 4oldin" d) none of these

12#. ____________ ma0es use of dynamic data dependences to select &hen to carry out instructions. a) )oft&are-based speculation c) D based speculation b) 5ard0are based speculation d) none of these

12%. Dard&are-based speculation is more beneficial &henever the hard&are-based branch prediction is hi"her-up to soft&are___________________ performed at time of compilation a) #o1t0are based branch prediction c) 4la"-based branch prediction b) Dard&are-based branch prediction d) none of these

12*. Dard&are-based speculation helps to maintain an entirely accurate e$ception model for ____________. a) User instruction d) none of these b) #peculated instructions c) administrator instruction

12/. Dard&are-based speculation demands neither ______________ nor____________. a) -omputation! coo0ies code c) .one of these b) Compensation) boo77eeping code

122. 'ranch instruction li0e Pentium is also 0no&n as............................. a) 7ait instruction b) >ump instruction c) access instruction d) none of these

125. t is possible to have Ae-locatable code in case of absolute addresses 1True;4alse). a) True b) $alse

126. ________ is a flo& alterin" instruction that is re<uired to be handled in a special manner in pipelined processors a) nstruction b) 4la" c) +ranch d) none of these 1#8. 7asteful &or0 done by pipeline for a considerable time is called the_______________.

a) 'ranch services d) 'ranch system

b) 'ranch information

c) +ranch penalty

1#1. ( number of processors such as _________ and __________ ma0e use of delayed e$ecution for procedure calls as &ell as branchin". a) )PA(-! 3T P b) #PA3C) M"P# c) )TAP! T 3P) d) ),A-! 3T P)

1#2. f any valuable instruction cannot be moved into delay slot! ___________ is placed. a) &O operation (&OP) b) D> operations c) nformation d) none of these

1##. 'ranch processin" has t&o aspects ________ and ________. a) Cayout! micro-system b) Cayout! micro-architectural implementation c) Cayout! mini- architectural implementation d) none these 1#%. .ame the ma?or sub tas0s of branch processin". a) Detectin" system d) .one of these b) Detectin" instruction c) Detecting branches

1#*. n case of 4i$ed 'ranch Prediction! the branch is presumed to be either_________ or ________________. a) &e!er ta7en) al0ays ta7en c) nstruction ta0en! al&ays ta0en b) al&ays ta0en! .ever ta0en d) none of these

1#/. )tatic strate"y ma0es use of _______________ for predictin" &hether the branch is ta0en. a) nstruction code b) "nstruction opcode c) data instruction d) none

1#2. (-/% architecture is considered as a load;store architecture havin" /%-bit ____________ as &ell as /%-bit broad ___________ . a) data address! system b) system information c) addresses) registers d) none

1#5. (-/% model is also called _______________ . a) b) c) d) ,.plicitly Parallel "nstruction Computing (,P"C) +$plicitly Permanent nstruction -omputin" 1+P -) +$plicitly Parallel nformation -omputin" 1+P -) .one of these

1#6. Trimedia processor may be the closest e$istin" processor to a ____________________________. a) H-lassicI ,CC7 Processor b) ?Classic@ 6/"8 Processor c) H-lassicI , 7 Processor c) H-lassicI CC 7 Processor 1%8. )tate t&o uses of Trimedia T3#2 -PU. a) #et top bo.es and ad!anced tele!isions c) .one of these b) cable televisions and d-T,

1%1. _______________ directly deals &ith the processor.

a) Main memory

b) secondary memory

c) primary memory

d) none

1%2. ____________ is a hi"h-speed memory &hich provides bac0up stora"e a) Au.iliary memory b) system memory c) primary memory d) none

1%#. ( ___________ memory is an intermediate memory bet&een t&o memories havin" lar"e difference bet&een their speeds of operation. a) Cache b) re"ister c) 4la" d) none of these

1%%. f the processor detects a &ord in cache! &hile referrin" that &ord in main memory is 0no&n to produce a _________________. a) 5it b) cool c) AB-%* d) none of these

1%*. 7hen both instructions and data are stored into the same cache! the desi"n is called the ______________ cache desi"n. a) (rchitecture b) uni1ied c) un-unified d) none of these

1%/. TC' stands for ____________________. a) Translation dataside 'uffer c) Translation re"ister buffer b) Translation system 'uffer d) %ranslation /oo7side +u11er

1%2. The translation of main memory address to the cache memory address is 0no&n as _________________. a) )o&in" b) mapping c) s&oopin" d) none of these

1%5. _________________ memories are e$pensive compared to A(3s. a) .on-(ssociative b) Associati!e c) (u$iliary d) none

1%6. ( desi"n &here instructions and data are stored in different caches for e$ecution conveniences is called ______________ cache desi"n. a) #plit b) (u$ c) 4la" d) none of these

1*8. --ache denotes _________________________. a) "nstruction -ache b) nformation of -ache c) nstruction of 4la" d) nstruction re"ister 1*1. ______________ affects the cloc0 cycle rate of the processor. a) nstruction time b) 5it %ime c) )ystem Time d) none of these

1*2. (vera"e memory access time J Dit time K 3iss rate $ _____________. a) 3iss data b) 3iss nformation c) Miss Penalty d) none

1*#. CP stands for _______________________. a) nstruction-Cevel Palmist c) nfraction-Cevel Parallelism b) "nstruction /e!el Parallelism d) none of these

1*%. TCP is the abbreviation for _____________________. a) %hread /e!el Parallelism c) Thread-Cevel palmist b) Thad-Cevel Parallelism d) none of these

1**. __________________ is a techni<ue aimed at enhancin" the efficiency of memory usa"es in a system a) "nterlea!ed Memory Organisation c) nstruction 3emory >r"anisation b) data 3emory or"anisation d) none of these

1*/. __________________ share common data and address buses. a) 3(As and 3AD b) -(ATs and 3A) c) MA3s and MD3s d) none

1*2. The memory band&idth is upper-bounded by ____________ and lo&er-bounded by __________________. a) m!/ b) m!# c) m!6 d) m)'

1*5. __________________ are assi"ned in the hi"h-order interleaved memory in each memory 3odule. a) )e<uential information c) )e<uential instruction b) #eAuential addresses d) none of these

1*6. ___________ model is a contract bet&een processes and a data store. a) Consistency b) system memory c) inconsistency d) none

1/8. The t&o cate"ories of consistency models are ______ and _________. a) #trong) 8ea7 b) LT !4T c) )tructure model d) none of these

1/1.____________ is able to function on one &hole vector in a sin"le instruction. a) Data processors b) 6ector processors c) 3ultiple processors

1/2. They also ta0e advanta"e of ____________ in hu"e scientific as &ell as multimedia applications. a) Data parallelism b) strip parallelism c) sin"le parallelism d) none

1/#. The memory-memory vector processors can prove to be much efficient in case the vectors are sufficiently lon". 1True;4alse). a) %rue b) 4alse

1/*. The scalar re"isters are lin0ed to the functional units &ith the help of a pair of ________. a) Crossbars b) stretchbar c) rollbar d) none of these

1//. ______________ correspond to vector load or vector store. () )imple-memory instruction c) !ector memory instructions b) 3ultiple-memory instruction d) none of these

1/2. 4unctional hazards are the conflicts in re"ister accesses 1True;4alse). a) True b) $alse

1/5. The instance of lar"er vectors is dealt &ith by a method called_______________. a) )trip memory c) #trip mining b) )trip operation d) none of these

1/6. ,ector elements are saved in the form of ______________ in memory. a) Dorizontal &ords c) #eAuential 0ords b) parallel &ords d) none of these

128. Cist t&o factors &hich enable a pro"ram to run successfully in vector mode. a) )ystem pro"ram M system capability b) User information M system capability c) #tructure o1 the program B capability o1 the compiler 121. There does not e$ist any variation in the capability of compilers to decide if a loop can be vectorised 1True;4alse). a) True b) $alse

122. ______________it can pac0 18 to 28 transistors in a sin"le chip. a) Car"e )cale inte"ration b) #mall scale integration c) none of these

12#. The various types of vector instructions for a re"ister-re"ister vector these are 1a) ,ector-scalar instructions 1c) ,ector-memory instructions 1e) 3as0in" instructions ) (!c!d!e !) All o1 these ) a!d!e!f 1b) ,ector-vector instructions 1d) Lather and scatter instructions 1f) ,ector reduction instructions ) b!c!e!f ,) none of these

12%. _______________Usin" these instructions! one or t&o vector operands are fetched from respective vector re"isters and produce results in another vector re"ister. a) ,ector-scalar instructions c) 3as0in" instruction b) Lather and scatter instructions d) !ector !ector instructions

12*.( problem is bro0en into a discrete series of ______________ . a) "nstructions b) nformation c) 4la" d) re"ister

12/. _______________ provides facilities for simultaneous processin" of various set of data or simultaneous e$ecution of multiple instructions. a) 3icro -omputer b) 3ini -omputer c) Parallel Computer d) none of these

122. Parallel processin" in uni-processor computer is said to_____________ parallel processin". a) 3anual or systematic b) simulated or !irtual c) none of these

125. ) 3D stands for ________________. a) #ingle "nstruction) Multiple Data c) )in"le- nstruction! 3anual data b) si"nal- information! 3anual data d) none of these

126. 4lynn classified computin" architectures into ) )D! 3 )D! ) 3D and _______________________ . a) A3 + ') -AT c) M"MD d) AD +

158. ) 3D is 0no&n as ____________ because its basic unit of or"anisation is the vector. a) Data processin" b) !ector processing c) vector-vector processin"

151. )uperscalar ) )D machines use one property of the instruction stream by the name of ___________. a) instruction le!el parallelism c) system-level parallelism 152. 3PP is the acronym for ____________. a) Massi!ely Parallel Processor c) 3assively Parallel Pro"ram b) 3aster Parallel Processor d) 3aster parallel process b) Aesister-level parallelism d) none of these

15#. (ll hi"hly parallel computers have problems concerned &ith______________________. a) nput data b) output of data c) "nput and output o1 data d) none of these

15%. The t&o parallel computers manufacturers of coarse-"rained architecture are ____________________. a) .rube and Thin0in" 3achines nc c) .tube and Thin0in" 3achines nc b) ncube and %hin7ing Machines "nc d) none of these

15*. )P3D is the acronym for ____________________. a) #ingle program multiple data c) serial pro"ram multiple data b) si"nal process multiple data d) server process multiple data

15/. _____________________ is the first of the -A(N family. a) -32 b) -3/ c) CM' d) -35

152. The latest system in the -A(N family is _________________. a) CM5 b) -3# c) -32 d) -36

155.The first vector machine &as _____________. a) -D- )tar 288 b) CDC #tar '00 c) -D- )tar %88 d) -D- )tar 1*8

156.________ >perations "et the scalar inputs present in scalar re"isters.

a) )ystem

b) A D

c) 6ector

d) none of these

168._____________ specifies the count of instructions completed per unit time. a) "nstruction throughput c) >perator throu"hput b) Data throu"hput d) none of these

161. Pipelinin" is also called ________________ as it provides an essence of parallelism only at the instruction level. a) 6irtual Parallelism c) nstruction Parallelism b) ,ector Parallelism d) none of these

162. Cinear pipelines perform only one pre-defined fi$ed functions at specific times in a for&ard direction. 1True;4alse) a)True b) $alse

16#.(ll multiprocessin" computers are ______________ computers. a) 3 D b) 3 3+ c) + D+ d) M"MD 16%. n U3( machines! each memory &ord cannot be read as <uic0ly as other memory &ord. 1True; 4alse). a) True 16*. b) $alse

.U3( stands for _____________________. a) &on (ni1orm Memory Access c) .on Uric 3emory (ccess b) .o Uniform 3emory (ccess d) .on Uniform machine (ccess

16/. _______________ &as a 0ey problem in the data-parallel architectures since they aimed at massively parallel systems a) 3emote loads b) soft&are loads c) data load d) none of these e$ecutin" different

162. CCCCCCCCCCCCCCC)ystems &ith multiple -PUs! &hich are capable of independently tas0s in parallel. a) Processor b) microprocessor c) Multiprocessor d) none

165._________________is associated &ith each se"ment in the pipeline to provide isolation se"ment. a) 4la" b) 3egister c) 3emory d) none of these

bet&een each

166. The main desi"n issues in scalable parallel computers are as follo&s a) Processor desi"n c) 3emory system desi"n ) (!c!d only b) nterconnection net&or0 desi"n d) ;> system desi"n ) b!c!d only ) a!b!c only "6) all o1 these

288. ____________ si"nifies those systems attributes &hich are visible to a developer. a) )ystem (rchitecture b) soft&are (rchitecture c) Computer architecture

281. _______________ si"nifies operational units in addition to the connection bet&een them that reco"nize the specification of architecture. a) -omputer system c) Computer organization b) -omputer application d) none of these

282. A(3 stands for ________________. a) Aandom (ccess machine c) 3andom Access memory b) Aesources access machine d) none of these

28#. Physical components on &hich data is stored are called __________. a) Ae"ister b) dis0 c) #torage Media d) none of these

28%. AP3 is the acronym for ______________. a) Aevolutions per machine c) Aeservation per minute b) Aeservation per machine d) 3e!olutions per minute

28*. To read data from ______________ ! a laser beam is directed on the surface of a spinnin" dis0. a) -D-A(3 b) D,D-A>3 c) CD 3OM d) D,D-A(3

28/. __________ is used in computers for bac0up stora"e. a) 3a"netic devices b) 3a"ic dis0 c) 3a"ic devices d) Magnetic tape

282. __________ from the processor is attached to all peripheral interfaces. a) ;> re"ister b) ;> instruction c) ;> data d) "<O bus

285. (____________ is issued to test various status conditions in the interface and the peripheral. a) )ustained -ommand b) system -ommand c) #tatus command d) none

286. ______________ refers to consistent reportin" &hen information is lost because of failure. a) )oft&are inte"rity b) Data integrity c) system inte"rity d) none of these

218. _____________ is an innovation that improves both availability and performance of stora"e systems a) Dis7 array b) Data array c) system array d) none of these

211. A( D is the acronym for _____________. a) 3edundant array o1 ine.pensi!e dis7s c) Aedundant array of ine$pensive data b) Aeduces array of ine$pensive dis0s d) Aedundant array of inde$ data

212. ______________ uses t&ice as many dis0s. a) Mirroring or shado0ing b) )hado&in" or monitorin" 21#. _________ is also 0no&n as band&idth. a) Throu"hout b) Thorou"hpin b) 3irrorin" or monitorin" d) none of these c) %hroughput d) none of these

21%. __________________ is sometimes called latency. a) Ae<uest time b) 3esponse %ime c) Aedundant Time d ) none of these 21*. 3ultithreadin" is the capability of a processor to do multiple thin"s at one time. 1T!4) 21/. ( thread has the follo&in" features a) ( state of thread e$ecution b) The saved thread conte$t &hen not runnin" c) ( stac0 tracin" the e$ecution path d) )ome space for local variables e) (ll the above 212. Traditional operatin systems such as D>) and U. F support the concept of sin"le Threadin". 1T!4) 215. ( Bava ,irtual 3achine 1B,3) is also an e$ample of multithreadin" system. 1T!4) 216. The multithreadin" system has a concept of priorities and therefore! is also called ___________ or ___________. 228. t ta0es much more time to create a ne& thread in an e$istin" process than to create a brand-ne& process 1True;4alse). 221. The number of s&itches is proportional to the number of remote reads 1True; 4alse). 222. ________ typically refers to a thread of a fe& to tens of instructions. 22#. _________parallelism is the OconventionalO parallelism &hile _________ parallelism is the means by &hich threads can correspond &ith other threads e$istin" in other processors. 22%. The number of instructions in a thread is 0no&n as ________ 22*. ________usually is a thread of a fe& to tens of instructions. t is basically for instructionlevel multithreadin". a) 4ine-"rain threadin" b) 3edium-"rain threadin" c) -oarse-"rain threadin" 22/. ________ is considered as a looplevel or function-level threadin"! and it consists of hundreds of instructions. a) 4ine-"rain threadin" b) 3edium-"rain threadin" c) -oarse-"rain threadin" 222. ________is treated as a tas0-level threadin"! &here each thread consists of thousands of instructions 4ine-"rain threadin" b) 3edium-"rain threadin" c) -oarse-"rain threadin" 228. ( computer architecture that is desi"ned to e$ecute more than one Processor is called a ________. a) scalable architecture b) Scaling up c) Scaling out 226. _________is achieved by addin" e$tra resources to a sin"le machine to allo& an (pplication to service more re<uests. The most common &ays to do this are by addin" memory 1A(3) or to use a faster -PU. a) scalable architecture b) )calin" up c) )calin" out 2#8. _________is achieved by addin" servers to a server "roup to ma0e applications scale by scatterin" the processin" amon" multiple computers. a) scalable architecture b) )calin" up c) )calin" out 2#1. (lmost all business applications are __________________. 2#2. 7hen an application is run! each of the processes contains at least one _________ . 2##. There are basically three types of computational models as follo&s a) ,on .eumann model b) Dataflo& model c) Dybrid multithreaded model d) all 2#%. The combination of lan"ua"es and the computer architecture in a common foundation or paradi"m is called ____________. 2#*. -omputational model uses mathematical lan"ua"e to describe a

system 1True; 4alse) 2#/. -loc0 rates of todayOs processors are in the ran"e of 2 to #.% LDz and they allo& up to /88 million basic operations 1T!4) 2#5. The instruction set to"ether &ith the resources needed for their e$ecution is called the ________. 2#6. The memory is a collection of stora"e cells! each of &hich can be in one of t&o different states 1True;4alse). 2%8. There are four possible &ays of e$ecutin" instructions 1T!4) 2%1. n this mechanism! an instruction is e$ecuted &hen the previous one in a defined )e<uence has been e$ecuted. This is the traditional &ay. a) -ontrol-flo& 3ethod b) Demand-driven 3ethod c) Pattern-driven 3ethod d) Dataflo& 3ethod 2%2. n this mechanism! an instruction is e$ecuted &hen the results of the instruction are Ae<uired by other instruction a) -ontrol-flo& 3ethod b) Demand-driven 3ethod c) Pattern-driven 3ethod d) Dataflo& 3ethod 2%#. n this mechanism! an instruction is e$ecuted &hen particular data patterns appear. a) -ontrol-flo& 3ethod b) Demand-driven 3ethod c) Pattern-driven 3ethod d) Dataflo& 3ethod 2%%. n dataflo& method! an instruction is e$ecuted &hen the operands re<uired become (vailable a) -ontrol-flo& 3ethod b) Demand-driven 3ethod c) Pattern-driven 3ethod d) Dataflo& 3ethod 2%*. The heart of the ,on .eumann computer architecture is the -entral Processin" Unit 1-PU)! consistin" of the control unit and the (CU 1(rithmetic and Co"ic Unit). 1T!4) 2%/. Dataflo& architecture does not have a pro"ram counter and the e$ecution of instructions is solely determined based on the availability of input ar"uments to the instructions 1T!4) 2%2. ___________ combined dataflo& ideas &ith se<uential thread e$ecution to define a hybrid computation model 2%5. P-A )- e$plores the possibility of constructin" a multithreaded architecture around a - )- processor 1True; 4alse). (ns&ers 1 * 6 1# 12 21 2* 26 ## #2 %1 %* %6 *# *2 /1 /* /6 2# 22 51 5* 56 6# 62 ( D ' ' ' ' T ' ( D ' D ( ( ' ' ' ( ( ( T 2 / 18 1% 15 22 2/ #8 #% #5 %2 %/ *8 *% *5 /2 // 28 2% 25 52 5/ 68 6% 65 ' ( ( ' ( ' ( ' ' ( 4 ( ( D ' D # 2 11 1* 16 2# 22 #1 #* #6 %# %2 *1 ** *6 /# /2 21 2* 26 5# 52 61 6* 66 D ( ( ( ( ( ' ' 4 D T ( D ' T ( ( ( ( % 5 12 1/ 28 2% 25 #2 #/ %8 %% %5 *2 */ /8 /% /5 22 2/ 58 5% 55 62 6/ 188 ( ( ' D ' ( D ( D ' ' T ( ( ' ( ' ' '

181 18* 186 11# 112 121 12* 126 1## 1#2 1%1 1%* 1%6 1*# 1*2 1/1 1/* 1/6 12# 122 151 15* 156 16# 162 281 28* 286 21# 212 221 22* 226 2## 2#2 2%1 2%*

' ( ( ' ' ' ( ' ( ' D ' + ' ( ( D ' + 4 TDA+(D LA(.(UC TN ( Thread T ( T

182 18/ 118 11% 115 122 12/ 1#8 1#% 1#5 1%2 1%/ 1*8 1*% 1*5 1/2 1// 128 12% 125 152 15/ 168 16% 165 282 28/ 218 21% 215 222 22/ 2#8 2#% 2#5 2%2 2%/

4 ' ' ( ' D ( ( D ( ' ' D ' D ( ( ( ' ' D ( ' T T ( ' D 1 )() ' T

18# 182 111 11* 116 12# 122 1#1 1#* 1#6 1%# 1%2 1*1 1** 1*6 1/# 1/2 121 12* 126 15# 152 161 16* 166 28# 282 211 21* 216 22# 222 2#1 2#* 2#6 2%# 2%2

' D ( ' ' ' ( ' ( ' ' ( ( ( ' ' ( ( ( ( D D ( T 4 .+ LA( . TDA+(D .L ' -omputational 3odel T annucci

18% 185 112 11/ 128 12% 125 1#2 1#/ 1%8 1%% 1%5 1*2 1*/ 1/8 1/% 1/5 122 12/ 158 15% 155 162 16/ 288 28% 285 212 21/ 228 22% 225 2#2 2#/ 2%8 2%% 2%5

T ' ( ( ( ( ' ( ' ( ( ' ( ( ' ' ' ' ' ( D ( T 'ac0"round processin"! pre-emptive multitas0in" ->3PUT(T >. (.D ->33U. -(T >. )calable T T D 4