FINFET TECHNOLOGY BY: KIRTI KUMAR KASAT FINAL YEAR B.

TECH (ECE)

INTRODUCTION TO VLSI TECHNOLOGY MOORES LAW AND ITS LIMITATIONS SHORT CHANNEL EFFECTS IN MOSFET INTRODUCTION TO FINFET HOW FINFET OVERCOME SHORT CHANNEL EFFECTS APPLICATIONS OF FINFET ADVANTAGES AND DISADVANTAGES FUTURE SCOPE AND CONCLUSION

April 26, 2014

INTRODUCTION TO VLSI
Very-large-scale integration (VLSI) is the process of creating integrated circuits by combining thousands of transistors into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed.
April 26, 2014 3

The Metal Oxide Semiconductor Field-Effect Transistor (MOSFET)

MOSFET TECHNOLOGY
The growth of digital technologies like the microprocessor has provided the motivation to advance MOSFET technology faster than any other type of silicon-based transistor.

A big advantage of MOSFETs for digital switching is that the oxide layer between the gate and the channel prevents DC current from flowing through the gate, further reducing power consumption and giving a very large input impedance

April 26, 2014

April 26, 2014

LIMITATIONS ON MOORES LAW

On 13 April 2005, Gordon Moore stated in an interview that the law cannot be sustained indefinitely: "It can't continue forever. The nature of exponentials is that you push them out and eventually disaster happens". He also noted that transistors would eventually reach the limits of miniaturization at atomic levels. In terms of size [of transistors] you can see that we're approaching the size of atoms which is a fundamental barrier, but it'll be two or three generations before we get that farbut that's as far out as we've ever been able to see. We have another 10 to 20 years before we reach a fundamental limit. By then they'll be able to make bigger chips and have transistor budgets in the billions
April 26, 2014 7

LIMITATIONS ON MOSFET TECHNOLOGY

Silicon-only planar transistors are fast approaching their scaling limit. Short channel effects limiting scaling into sub nanometer regime. Oxide thickness cannot be scaled down further, problems of tunneling. Need to keep Silicon technology as the base technology while innovating future devices; cost is an important factor. Performance and power dissipation need to be improved.

Planar MOSFET Scaling (Short-Channel Effect)

Lg = 0.35 m, Tox = 8 nm

Lg = 0.18 m, Tox = 4.5 nm

Short-Channel Effect

Short-Channel Effect

Lg = 0.10 m, Tox = 2.5 nm

9

Lg = 0.07 m, Tox = 1.9 nm

The extension of Moores Law into the sub nano meter range.
April 26, 2014 10

FinFET
The term FinFET was coined by University of California, Berkeley researchers (Profs. Chenming Hu, Tsu-Jae KingLiu and Jeffrey Bokor) to describe a nonplanar, doublegate transistor built on an SOI substrate.

The distinguishing characteristic of the FinFET is that the conducting channel is wrapped by a thin silicon "fin", which forms the body of the device.

The thickness of the fin (measured in the direction from source to drain) determines the effective channel length of the device.

The Wrap-around gate structure provides a better electrical control over the channel and thus helps in reducing the leakage current and overcoming other short channel effects.
April 26, 2014 11

What does FinFet look like

Gate

Source

Drain

3D view of FinFET

April 26, 2014

3D view of multi-fin FinFET

13

Why FinFETs ?

Higher current drive better performance Prophesized to show higher tolerance to scaling. Better integration feasibility, raised source-drain structure, ease in integration. Larger number of parameters to tailor device performance
14

Why FinFETs?
Double-gate FET (DGFET) can reduce Short Channel Effects (SCEs)
Reduce Drain-Induced-Barrier-Lowering Improve Sub-threshold Swing S

April 26, 2014

Medici-predicted DIBL and subthreshold swing versus effective channel length for DG and bulk-silicon nFETs

15

UC Berkeley Results FinFET/ Double Gate (2000-04)

Gate Length = 30nm, Oxide thickness =2.1nm

Gate Length = 30nm, Fin Width =20nm Gate Length = 20nm

16

IBMs FinFET / Double-Gate SOI (Nanoscale Device Research Group)

17 26, 2014 April

Courtesy: IBM T.J. Watson Research Center, Yorktown Heights, NY

From FD/SOI to FinFET

Bend up the gate and narrow the gate. Fin width = 2* film thickness The effect body thickness is reduced by 2. Xd can be regarded as Fin width /2. To obtain good control of SCE, Leff > 1.5*Wfin ( Fin width). Finfet can operate at two mode, single gate and double gate.

April 26, 2014

18

Fabrication - Process Flow

(a) SiN is deposited as a hard mask, SiO2 cap is used to relieve the stress. (b) Si fin is patterned (c) A thin sacrificial SiO2 is grown

(d) The sacrificial oxide is stripped

completely to remove etch damage (e) Gate oxide is grown

10 nm gate length, 12 nm fin width

April 26, 2014

(f) Poly-Si gate is formed

19

FinFet characteristics

Lg = 15nm Some values:

Threshold Voltage = 0.196 V Subthreshold Slope = 72 mV/decade Off Current = 70 A/m

Lg = 30nm
April 26, 2014

DIBL = 64.67 mV/V

20

FinFet: big advantages

Having excellent control of short channel effects in submicron regime and making transistors still scalable. Due to this reason, the small- length transistor can have a larger intrinsic gain compared to the bulk counterpart. Much Lower off-state current compared to bulk counterpart. Promising matching behavior.

April 26, 2014

21

FinFet: Challenges or Opportunities

Carrier mobility: Lightly doped or undoped fin body increases carrier mobility.

Short channel length enables velocity overshoot, which increases mobility.

Low Vth decreases the vertical electric field ,which increases carrier mobility.

April 26, 2014

22

FinFet: Challenges or Opportunities

Tunneling effects:Gate to channel tunneling,Band to band tunneling at PN junction

April 26, 2014 23

FinFet: Challenges or Opportunities

Parasitic resistance: a raised source/drain structure can be used to reduce the parasitic resistance. However, the overlap capacitance is increased. Parasitic resistance is the main adverse factor which prevents finfets application, which leads to lower speed and high noise. r r C
g

Gate

gd

Drain

Cgs ri

+ vgs gm*vgs

Cds rds

rs

April 26, 2014

Source

24

Applications
Low power design in digital circuit, such as RAM, because of its low off-state current.

Power amplifier or other application in analog area which requires good linearity.

April 26, 2014

25

Conclusion
Easy in concept----Tough to build

Double-gate FET can reduce Short Channel Effects and FinFET is the leading DGFET. Optimization design includes geometry, S-D fin-extension doping, dielectric thickness scaling, threshold voltage control. Fabrication of FinFET is compatible with CMOS process 10 nm gate length, 12 nm fin width device has been fabricated and shows good performance
April 26, 2014 26

Special thanks to Prof. Pooja Verma Mam (Guide) And Prof. April Pradeep Kumar 26, 2014 Sharma Sir

27

SEMINAR REPORT ON

FinFET Technology
SUBMITTED BY

KIRTI KUMAR KASAT

UNDER THE GUIDANCE OF PROF. POOJA VERMA (ASSOCIATE PROFESSOR ECE) IN PARTIAL FULFILLMENT FOR THE AWARD OF BACHELORS DEGREE IN ELECTRONICS AND COMMUNICATION ENGINEERING FROM RAJASTHAN TECHNICAL UNIVERSITY DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING JODHPUR INSTITUTE OF ENGINEERING AND TECHNOLOGY,

MOGRA, N.H. 65, PALI ROAD, JODHPUR-342802 April 2014 Batch 2010-14

JODHPUR INSTITUTE OF ENGINEERING AND TECHNOLGY

DEPARTMENT OF ELECTRONICS & COMMUNICATION

CERTIFICATE
This is to certify that Mr. Kirti Kumar Kasat Have successfully completed the Seminar Titled "FinFET Technology towards the partial fulfillment of degree of Bachelor of Technology in Electronics and Communications Engineering of Rajasthan Technical University during the academic year 2013 - 2014.

. Guide Prof. Pooja Verma (Associate Professor ECE Dept.)

. Lab In charge Prof. Pradeep Kumar Sharma (Asst. Professor, ECE Dept.)

..

Prof. Sanjay Bhandari (Head of the Department)

INTERNAL EXAMINER

EXTERNAL EXAMINER

ii

ACKNOWLEDGEMENT
With engineering, I view this year's failure as next year's opportunity to try it again. Failures are not something to be avoided. You want to have them happen as quickly as you can so you can make progress rapidly.-Gordon Moore

I take this opportunity to acknowledge the support of Prof. O.P. Vyas (Dean Engg.) for providing me this opportunity.

I also wish to thank my guide Prof. Pooja Verma for her guidance in preparation of this seminar.

I also extend my heartiest thank to Prof. K.K. Arora (HOD,M.Tech) and Prof. Sanjay Bhandari(HOD B.Tech) for their motivation.

I hereby also acknowledge the efforts of Prof. Pradeep Kumar Sharma for his tireless efforts in the seminar lab and helping me in making a better seminar presentation.

I would also like to acknowledge the support of all the faculty and staff of Electronics and Communication Engineering Department and the JIET Library staff for providing research papers related to my topic. I wish to acknowledge the support of my classmates and fellow students in preparing this report to the seminar.

KIRTI KUMAR KASAT 10EJIEC052 Batch:- C3

iii

ABSTRACT
The introduction of FinFET Technology has opened new chapters in Nano-technology. Simulations show that FinFET structure should be scalable down to 10 nm. Formation of ultrathin fin enables suppressed short channel effects. Chapter 1 deals with some multigate FETs, one of them being FinFET. It is an attractive successor to the single gate MOSFET by virtue of its superior electrostatic properties and comparative ease of manufacturability, as described in Chapter 2. Since the fabrication of MOSFET, the minimum channel length has been shrinking continuously. The motivation behind this decrease has been an increasing interest in high speed devices and in very large scale integrated circuits, as elaborated in Chapter 3. The sustained scaling of conventional bulk device requires innovations to circumvent the barriers of fundamental physics constraining the conventional MOSFET device structure. The limits most often cited are control of the density and location of dopants providing high Ion /Ioff ratio and finite sub-threshold slope and quantum-mechanical tunneling of carriers through thin gate from drain to source and from drain to body, as discussed through the characteristics in Chapter 4. The channel depletion width must scale with the channel length to contain the off-state leakage Ioff. This leads to high doping concentration, which degrade the carrier mobility and causes junction edge leakage due to tunneling. Furthermore, the dopant profile control, in terms of depth and steepness, becomes much more difficult. The gate oxide thickness tox must also scale with the channel length to maintain gate control, proper threshold voltage V T and performance. The thinning of the gate dielectric results in gate tunneling leakage, degrading the circuit performance, power and noise margin, as discussed in Chapter 5 & 6 Keywords: FinFET, MOSFET, nanotechnology, short channel effects, quantum tunneling, DIBL

iv

Table Of Contents
Cover Page....i Certificate.ii Acknowledgement..iii Abstract...iv Table of Contents.v List of Figures.vi INTRODUCTION TO FINFET TECHNOLOGY ........................................... 1 LITERATURE SURVEY ................................................................................ 2 Chapter 1-FinFET : A MULTI GATE FET...................................................... 8 Chapter 2-FinFETs ........................................................................................ 12 Chapter 3-FinFET Fabrication ....................................................................... 16 Chapter 4-FinFET Characteristics .................................................................. 18 Chapter 5-APPLICATIONS OF FINFET ...................................................... 23 Chapter 6 -ADVANTAGES and DISADVANTAGES of FinFET ................. 27 CONCLUSION ............................................................................................. 31 REFERENCES .............................................................................................. 33 APPENDIX ................................................................................................... 35

List Of Figures:
Figure 1 Thin Body MOSFETs are the origin of today's FinFETs ..................................................... 11 Figure 2 From Planar DG FET to FinFET .......................................................................................... 11 Figure 3 FinFET Structure .................................................................................................................. 12 Figure 4 FinFET structure with multiple fins ..................................................................................... 13 Figure 5 FinFET structures (a) SG and (b) IG .................................................................................... 13 Figure 6 Oriented FinFETs with nFinFETs along < 100 > sidewalls and pFinFETs along < 110 > sidewalls.............................................................................................................................................. 14 Figure 7 Comparison of fin density in spacer and optical lithography ............................................... 17 Figure 8 Ids vs Vds characteristics for different orientation ............................................................... 20 Figure 9 Transfer Characteristics of 32nm FinFET ............................................................................ 21 Figure 10 : Different kinds of FinFET NAND gate designs ............................................................... 23 Figure 11 SRAM cell structure ........................................................................................................... 25 Figure 12 conventional Tri Gate FinFET (cross sectional view) ........................................................ 29

vi

INTRODUCTION TO FinFET TECHNOLOGY

The scaling of conventional planar MOSFETs has been facing problems such as subthreshold swing degradation, significant DIBL, fluctuation of device characteristics, and leakage. To solve the problems, 3-D device structures could be a solution and have been studied. FinFETs (built on bulk silicon or SOI wafers) among 3-D devices are very promising candidate for future Nano-scale CMOS technology and high-density memory application. For the bulk FinFETs which is going to be applied to mass production, we discuss about fundamental properties, modeling, and application of the bulk FinFETs. Moore, who was later co-founder of Intel, said in a paper that the number of transistors on integrated circuits had doubled every year since the integrated circuit, or microchip, was invented in 1958. Moore predicted that the trend would continue "for at least 10 years." In 1975, he recalculated the period of doubling to every two years. Since then, the pace has slowed a bit, and now data density has continued to double about every 18 months. FinFETs and tri-gate FETs have extended Moore's law down to a gate length of 20-15nm. At these dimensions, quantum confinement and effects should be understood for proper development of functional CMOS circuits and robust design methodology. From Moores Law, we can infer that FinFETs represent the most radical shift in semiconductor technology in over 40 years. When Gordon Moore came up with his law back in 1965, he had in mind a design of about 50 components. Todays chips consist of billions of transistors and design teams strive for better, sooner, cheaper products with every new process node. However, as feature sizes have become finer, the perils of high leakage current due to short-channel effects and varying dopant levels have threatened to derail the industrys progress to smaller geometries. The FinFET transistor structure promises to rejuvenate the chip industry by rescuing it from the short-channel effects that limit device scalability faced by current planar transistor structures.

LITERATURE SURVEY
[1] Chenming Hu, Tsu-Jae King, Vivek Subramaniam et al, FINFET TRANSISTOR DOUBLE STRUCTURES CHANNEL OTHER PUBLICATIONS HAVING FROM A A

GATE

EXTENDING

VERTICALLY

SUBSTRATE AND METHODS OF MANUFACTURE, US Patent No. 6413802 B1, awarded July 2 2002 The paper describes the invention of FinFET. It describes the structure of basic FinFET and discusses various methods of manufacturing the device. FinFET structures came into existence to reduce the short channel effects of conventional MOSFETs when scaled to sub nanometer size. It is an outcome of Silicon-OnInsulator technique, with the device extending from the insulator as a fin, thus giving it the name FinFET. In one embodiment, a CMOS transistor pair can be fabricated with a common Gate. This technology provides multiple channels from source to drain, increasing current capacity. [2] Vivek Subramaniam, et al, Sub 50 nm P-Channel FinFET, IEEE Transactions on Electron Devices, Vol. 48, No. 5, May 2001. The paper discusses the fabrication of a sub-50 nm double gate MOSFET (FinFET) which can be scaled down to 10 nm (as per simulation data). A self-aligned doublegate MOSFET structure (FinFET) is used to suppress the short-channel effects. The key finding of the paper is that the thickness of the fin is critical in suppressing the Short Channel Effect of PMOSFET. The paper concludes that FinFET play a key role in scaling MOSFETs beyond 50 nm, paving the path for nanotechnology in semiconductor devices.

[3] Chenming Hu, Tsu-Jae King, Erik Anderson, Charles Kuo, Bokor et al, FinFETA Self-Aligned Double-Gate MOSFET Scalable to 20 nm, IEEE Transactions on Electronic Devices, Vol. 47No. 12, December 2000. The paper highlights the feasibility of a double gate MOSFET scalable to 17 nm. The result of the research is a quasi-planar device which can be easily fabricated using

conventional MOSFET fabrication techniques. The self-aligned double gate technique suppresses short channel effects. The paper concludes that the FinFET can easily be the next generation transistor technology for the Ultra Large Scale Integration. [4] Dragica Vasileska et al, Quantum Transport Simulation of Experimentally Fabricated nano FinFET, IEEE Transactions on Electron Devices, Vol. 54, No. 4, April 2007. The paper discusses experimental analysis of FinFET using simulation by Contact Block reduction method. The paper also discusses various results of simulation based on varying length fin FETs. The sub threshold degradation at high temperatures is also analyzed. This paper compares theoretical and simulation results. The variation of transfer characteristics with fin length is also studied. [5] Xiaoxia Wu, Feng Wang, Yuan Xie, Analysis of Sub threshold FinFET circuits for ultra-low power design, CSE Department, Pennsylvania State University, 2007. The paper discusses the power requirements of a sub threshold FinFET. It tries to find an optimal power supply point for minimum energy consumption. It leads to the result that FinFET technology is more power efficient than bulk CMOS technology, reducing energy by order of magnitude 4 and Finfet has better soft error immunity in sub threshold region. [6] F. Djeffal , Z. Ghoggali, Z. Dibi, N. Lakhdar ,Analytical analysis of nanoscale multiple gate MOSFETs including effects of hot-carrier induced interface charges, Institute of Microeletronics, LEA, Department of Electronics, University of Batna, Batna 05000, Algeria, 29 November 2008 The paper discusses a nanoscale multiple gate MOSFETs. As the channel length rapidly shrinks down to the nanoscale regime, the multiple gate MOSFETs structures have been considered as potential candidates for a CMOS device scaling due to its good short-channel-effects (SCEs) immunity. Therefore, in this work we investigate the scaling capability of Double Gate (DG) and Gate All Around (GAA) MOSFETs using an analytical analysis of the two dimensional Poisson equation in which the hot-

carrier induced interface charge effects have been considered. Basing on this analysis, we have found that the degradation becomes more important when the channel length gets shorter, and the minimum surface potential position is affected by the hot-carrier induced localized interface charge density. The presented analysis is based on an analytical compact model of the surface potential developed in this work in the presence and absence of hot carrier degradation effect in nanoscale multigate MOSFETs. All parameters of devices physics, such as the surface potential, threshold voltage and DIBL effect have been included in the analytical approach development. The models have been used to predict and compare the performances of downscaled DG and GAA MOSFETs, where the comparison of device architectures shows that the GAA MOSFET exhibits a superior performance with respect to the DG MOSFET both in terms of threshold voltage and DIBL effect in nanoscale domain for both cases (damaged and fresh devices). The obtained results may provide a theoretical basis and physical insights for multiple gate MOSFETs design including the hot-carrier degradation effects.

[7] Daewon Ha, H Takeuchi, Y K Choi, T-J King, W P Bai, A Agarwal et al, Molybdenum Gate HfO2 CMOS FinFET Technology, IEDM 04 IEEE, 2004 The paper reports the advantages of using HfO2 gates in place of SiO2 gates in CMOS Finfet technology. The gate leakage current density had reduced manifolds. CMOS FinFETs with MO gate on HfDz are demonstrated for the first time. Low gate leakage current density was achieved for a thin inversion EOT (down to 1.72 nm), with carrier mobilities comparable to previously reported works (limited by soft phonon scattering). VT adjustment is shown to be feasible by tuning the effective MO work function via nitrogen implantation. Further process optimization is needed to prevent nitrogen diffusion into the HD2, to make Mo-gate HfD2 FinFET technology suitable for future nanoscale CMOS technology. [8] Tai-su Parka, Euijoon Yoona, Jong-Ho Leeb, A 40 nm body-tied FinFET (OMEGA MOSFET)using bulk Si wafer, Physics E 19 (Elsevier), 2003. A new body-tied FinFET is proposed and fabricated on bulk Si wafer instead of SOI wafer. Three-dimensional device simulations show the characteristics of the proposed

device and show that it can be implemented without deteriorating short channel effect. An active fin width of 2540 nm and a gate length of 40 nm were realized by using sidewall spacer technology. Body-tied double-gate MOSFETs at nanometer scale have been demonstrated for the first time. Three-dimensional device simulation was performed to check the feasibility by comparing SOI double-gate device with the same structure and doping. By using bulk Si wafer instead of SOI wafer, we could reduce wafer cost, wafer defect density, and relieve any possible floating body effect while keeping nearly the same short channel effect as in the SOI double-gate device. Body-tied double-gate devices were fabricated and characterized. The body-tied double-gate MOSFET is a very promising candidate for future devices.

[9] Dong-Soo Woo, Jong-Ho Lee, Woo Young Choi, Byung-Yong Choi, YoungJin Choi, Jong Duk Lee, and Byung-Gook Park, Electrical Characteristics of FinFET With Vertically Nonuniform Source/Drain Doping Profile, IEEE Transactions on Nanotechnology Vol. 1, No. 4, Dec 2002 The paper discusses effects of non-uniform Source Drain profile on FinFET using 3 dimensional simulation. The simulation results have shown that larger SOI thickness can suppress short channel effects. The AC characteristics of the device are studied to determine the optimum SOI thickness of FinFET. The devices with greater SOI thickness are favourable for driving large capacitive load such as interconnects. The drive current compensates for the increased device capacitance and hence the gate delay does not increase. [10] Chris A. Mack, Fifty years of Moores Law, IEEE Transactions on Semiconductor manufacturing, Vol 24, No. 2, May 2011 The paper presents an historical perspective of semiconductor integrated circuits manufacturing right from the first Integrated Circuit to the introduction of Moores Law and the challenges the industry faces for sustainability of the law, fifty years since its inception by Gordon Moore in 1961. Moores Law predicts that the no. of transistors on a single semiconductor chip would double every 18 months. But eventually through these 50 years there have been some stiff challenges to this law leading to new technologies in semiconductor manufacturing. The author describes

these 50 years as remarkable for the industry but is least hopeful of the possibility of the relevance of Moores Law in near future.

[11] Animesh Dutta, Ashish Goel, Riza Tamer cakici, Kaushik Roy, Dheepa Lekshmanan, Hamid Mehmood, Modelling and circuit synthesis for independlty controlled double gate MOSFET, IEEE transaction on CAD of Integrated Circuits and Systems, Vol. 26, No. 11, November 2007 The paper proposes semi analytical models for different FinFET logic gates to predict their performance. The authors propose several low power circuit options using these models which were difficult to implement using the bulk CMOS technology. The study of these models show 18% power savings and 8.5% area reduction from conventional FinFET technology. Independent control of front and back gate in double gate (DG) devices can be used to merge parallel transistors in noncritical paths. This reduces the effective switching capacitance and, hence, the dynamic power dissipation of a circuit. 4-T FinFET technology, with independent gatecontrolled FinFET devices, has good potential for area efficient low-power circuit design The paper demonstrates that the IG FinFET-based design provides substantial power and area savings over the conventional 3-T FinFET-based design for a set of ISCAS85 benchmark circuits. Power and area savings are achieved even with a conservative worst corner-based circuit synthesis approach. [12] Xu Shao, Zinping Yu, Nanoscale FinFET simulation A quasi 3D quantum mechanical model using NEGF, Elsevier Solid State Electronics 49 (2005) 14351445, www.sciencedirect.com 29 June 2005. In this paper, a numerical simulation of FinFET is carried out. This computational model is also applicable to nanowires. The non-equilibrium Greens function (NEGF) is used to handle the quantum transport along the channel, and 2-D Schrodinger equation is solved at the channel cross-section to obtain the electron density profile. With the 3-D Poissons equation solved self-consistently, the model provides insights into the performance of FinFETs with ultra-small channel cross-dimension. In this paper, the authors have developed a quasi-3D numerical model for FinFET structure with ultra-thin channel and gate oxide, the ballistic transport along the channel is also

accounted for by the application of NEGF. This model considers the quantum mechanical effects in all three dimensions. Compared to the quasi-2D simulation of double-gate MOSFETs using NANOMOS, it is clear that channel electrons are further confined to center region of the fin together with the rise of the energy of sub bands. The model can also be applied to simulate nanowires with clear physical conception. With this model, several FinFET structures have been simulated and the device design insight has been acquired. The results show that the nano scale FinFET devices can work well even when the gate length is below 5 nm. [13] Lombardo, Gerardi et al., Advantage of FinFET architecture in SONOS and nanocrystals memory devices, IEEE-IEDM (1-4244-0439-X/07), 2007. Double-gate and tri-gate FinFET type memories with nitride (SONOS-like) or Si nanocrystals storage with minimum feature sizes of 10 nm were realized. Strong performance advantages in program / erase characteristics and reliability deeply linked to the FinFET architecture are demonstrated. For the first time that in addition to the advantages of suppression of SCEs, the FINFLASH architecture allows to dramatically improve the VT window -0.045 (up to 8 V with lE5 cycles) and the erase saturation problem, allowing thicker tunnel oxides with associated excellent retention, demonstrated up to 250 'C.

Chapter 1-FinFET : A MULTI GATE FET

1.1 Multigate Devices: A multigate device or multiple gate field-effect transistor (MuGFET) refers to a MOSFET (metaloxidesemiconductor field-effect transistor) which incorporates more than one gate into a single device. The multiple gates may be controlled by a single gate electrode, wherein the multiple gate surfaces act electrically as a single gate, or by independent gate electrodes. A multigate device employing independent gate electrodes is sometimes called a Multiple Independent Gate Field Effect Transistor(MIGFET). Multigate transistors are one of several to strategies being developed ever-

by CMOS semiconductor manufacturers

create

smaller microprocessors and memory cells, colloquially referred to as extending Moore's Law. Development efforts into multigate transistors have been reported

by AMD, Hitachi, IBM, Infineon

Technologies, Intel

Corporation, TSMC, Freescale

Semiconductor, University of California, Berkeley and others and the ITRS predicts that such devices will be the cornerstone of sub-32 nm technologies. The primary roadblock to widespread implementation is manufacturability, as both planar and non-planar designs present significant challenges, especially with respect to lithography and patterning. Other complementary strategies for device scaling include channel strain

engineering, silicon-on-insulator-based technologies, and high-k/metal gate materials. Dual gate MOSFETs are commonly used in VHF mixers and in sensitive VHF front end amplifiers. They are available from manufacturers such as Motorola, NXP, and Hitachi. 1.2 Types of Multigate transistor devices 1.2.1 Planar double-gate transistor Planar double-gate transistors employ conventional planar (layer by layer) manufacturing processes to create double-gate devices, avoiding more stringent lithography requirements associated with non-planar, vertical transistor structures. In planar doublegate transistors the drain-source channel is sandwiched between two independently fabricated gate/gate oxide stacks. The primary challenge in fabricating such structures is achieving satisfactory self-alignment between the upper and lower gates.

1.2.2 Flexfet Flexfet is a planar, independently-double-gated transistor with a damascene metal top gate MOSFET and an implanted JFET bottom gate that are self-aligned in a gate trench. This device is highly scalable due to its sub-lithographic channel length; non-implanted ultra-shallow source and drain extensions; non-epi raised source and drain regions; and gate-last flow. Flexfet is a true double-gate transistor in that both the top and bottom gates provide transistor operation, and the operation of the gates is coupled such that the top gate operation affects the bottom gate operation and vice versa Flexfet was developed, and is manufactured, by American Semiconductor, Inc.

1.2.3 FinFET The term FinFET was coined by University of California, Berkeley researchers (Profs. Chenming Hu, Tsu-Jae King-Liu and Jeffrey Bokor) to describe a nonplanar, double-gate transistor built on an SOI substrate, based on the earlier DELTA (single-gate) transistor design. The distinguishing characteristic of the FinFET is that the conducting channel is wrapped by a thin silicon "fin", which forms the body of the device. The thickness of the fin (measured in the direction from source to drain) determines the effective channel length of the device. The Wrap-around gate structure provides a better electrical control over the channel and thus helps in reducing the leakage current and overcoming other short channel effects. In current usage the term FinFET has a less precise definition. Among microprocessor manufacturers, AMD, IBM, and Freescale describe their double-gate development efforts as FinFET development whereas Intel avoids using the term to describe their closely related tri-gate architecture. In the technical literature, FinFET is used somewhat generically to describe any fin-based, multigate transistor architecture regardless of number of gates. A 25-nm transistor operating on just 0.7 volt was demonstrated in December 2002 by Taiwan Semiconductor Manufacturing Company. The "Omega FinFET" design is named after the similarity between the Greek letter omega () and the shape in which the gate wraps around the source/drain structure. It has a gate delay of just 0.39 picosecond (ps) for the N-type transistor and 0.88 ps for the P-type.

FinFET can also have two electrically independent gates, which gives circuit designers more flexibility to design with efficient, low-power gates. In 2012, Intel started using FinFETs for its future commercial devices. Recent leaks suggest that Intel's FinFET shape has an unusual shape of a triangle rather than rectangle and it is speculated that this might be either because a triangle has a higher structural strength and can be more reliably manufactured or because a triangular prism has a higher area to volume ratio than a rectangular prism thus increasing switching performance. In September 2012, GlobalFoundries announced plans to offer a 14-nanometer process technology featuring FinFET three-dimensional transistors in 2014. The next month, the rival company TSMC, announced start early or "risk" production of 16 nm FinFETS in November 2013. In March 2014, TSMC announced it is finishing of preparing and start of implementing of following variances of 16 nm FinFETs die-on wafers manufacturing process : 16nm FinFET ( Q4 2014) 16nm FinFET+ (cca Q4 2014) 16nm FinFET "Turbo" ( estimated in 2015-2016) 1.3 FinFET: A technology primer FinFETs have their technology roots in the 1990s, when DARPA looked to fund research into possible successors to the planar transistor. A UC Berkeley team led by Dr. Chenming Hu proposed a new structure for the transistor that would reduce leakage current.

The Berkeley team suggested that a thin-body MOSFET structure would control shortchannel effects and suppress leakage by keeping the gate capacitance in closer proximity to the whole of the channel. They proposed two possible structures

10

Figure 1 Thin Body MOSFETs are the origin of today's FinFETs

Rotating the DG structure, which has the potential to provide the lowest gate leakage current, enables easier manufacturing using standard lithography techniques as the gate electrodes become self-aligned and the layout is similar to that of a planar FET.

Figure 2 From Planar DG FET to FinFET

Modern FinFETs are 3D structures that rise above the planar substrate, giving them more volume than a planar gate for the same planar area. Given the excellent control of the conducting channel by the gate, which wraps around the channel, very little current is allowed to leak through the body when the device is in the off state. This allows the use of lower threshold voltages, which results in optimal switching speeds and power.

11

Chapter 2-FinFETs

2.1 Definition : FinFETs are quasiplanar field-effect transistors. The device physics governing the functionality of FinFETs is exactly the same as that of planar MOSFETs. Fig. 1.4 shows the structure of a FinFET. A silicon film of thickness TSI is patterned on an SOI wafer. The gate wraps around both sides of the fin. The channel is formed perpendicular to the plane of the wafer. Its length is shown as LG. This is the reason that the device is termed quasiplanar. The effective width of a FinFET is 2nHFin, where n is the number of fins and HFin is the fin height. Thus, wider transistors with higher on-currents are made possible by using multiple fins. Fig. 1.5 shows the structure of a FinFET employing two fins. It should be noted that FinFET width is quantized, in terms of the number of fins. This leads to important design considerations such as functionality, performance and power, which are sensitive to the ratio [6].

2.2 Structure of FinFET: Beyond the technology-driven benefits offered by FinFETs, circuits can also benefit from the double-gate structure of FinFETs to further optimize power and performance. Etching out the top part of the FinFET leads to some interesting designs that exploit its independent-gate structure. Various innovative circuit structures have been suggested in the literature based on independent-gate (IG) FinFETs.

Figure 3 FinFET Structure

12

Figure 4 FinFET structure with multiple fins

Figure 5 FinFET structures (a) SG and (b) IG

The FinFETs in which the two gates are shorted are referred to as shorted-gate (SG). Figs. 5(a) and 5(b) show the structure of an SG- and IG-FinFET, respectively.

2.2.1 Independent Gate FinFETs: In IG-FinFETs, the Vth of the front gate can be controlled by applying a bias to the back gate. Since Vth controls the subthreshold leakage and delay its controllability can be a powerful tool for circuit optimization. Another important characteristic of

13

FinFETs is that they can be fabricated along the < 110 > channel orientation easily by rotating the fins by 45o from the < 100 > plane. Electron mobility is highest along the < 100 > plane while the hole mobility is maximum along the < 110 > plane orientation due to carrier mobility anisotropy in crystalline silicon [9]. Hence, logic gates with pFinFETs along the < 110 > channel orientation and nFinFETs along the < 100 > channel orientation are the fastest. Fig. 1.7 shows the nFinFETs and pFinFETs in a < 100 > wafer, where the nFinFETs sidewalls are oriented in the < 100 > direction while the pFinFETs sidewalls are oriented in the < 110 > direction [3]. Such a device orientation leads to non-Manhattan layouts, which might pose an yield issue for sub-wavelength lithography.

2.3 Process variations in FinFETs: Though FinFETs are supposed to mitigate the effects of process variations, they still suffer from their effects. FinFETs are generally patterned using direct or spacer lithography. Owing to the small dimensions involved and various factors, such as line edge roughness, both techniques can result in variations in the values of the chip parameters. Also, the variations can be environmental in nature. Such variations are generally temporal in nature and can occur at a frequency of nanoseconds to years [10]. For example, effects, such as negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI), lead to variations in Vth over the circuit lifetime.

Figure 6 Oriented FinFETs with nFinFETs along < 100 > sidewalls and pFinFETs along < 110 > sidewalls

On the other hand, varying computing workload leads to temporal variations in the chip temperature. Since FinFETs are manufactured on an SOI wafer, heat dissipation issues become
14

an important concern for FinFETs. Process variations can be classified into different categories:

2.3.1 Systematic vs. random: systematic variations can be modeled using various mathematical functions. On the other hand, random variations are unpredictable. They cannot be modeled mathematically. Variations, such as lithography proximity effects, come under the realm of systematic variations. Dopant fluctuations in the channel are random in nature.

2.3.2 Inter-die vs. intra-die: variations can be classified as inter-die or intra-die depending on the spatial scale of the variation. Inter-die variations correspond to variation of a parameter value across nominally identically die. Such variations may be die-to-die, wafer-to-wafer or even lotto-lot. Intra-die variations, on the other hand, correspond to spatially distributed parameter variation inside a die. Intra-die variations are generally spatially correlated, i.e., devices in close proximity get affected similarly.

2.3.3 Process vs. environmental: variations, which occur at runtime, are classified as environmental. On the other hand, variations, which occur during the manufacturing of FinFETs, are termed process variations.

15

Chapter 3-FinFET Fabrication

In this section, we detail the various methods used to fabricate FinFETs and discuss their pros and cons. FinFETs can either be manufactured using optical lithography or spacer lithography. 1.1 Optical Lithography: With optical lithography, FinFETs are fabricated on bonded SOI wafers with a modified planar CMOS process. The optical lithography technique is used to pattern a thin silicon film followed by deposition of a thin oxide on the top of the fin. Thereafter, a pattern reduction technique is used to deposit the metal electrode. The metal electrode is doped using ion implantation to achieve a specified work function. Nitride oxide is used as the gate insulator [5]. However, this technique can result in non-uniform fin thickness in a single device. 1.2 Spacer Lithography: Spacer technology is attractive for overcoming such limitations. Further, spacer lithography provides for doubling of fin density, which doubles the drive current at a given lithography pitch. Fig.7 shows the comparison of fin density achieved using optical lithography and spacer lithography. A spacer lithography process technology uses a sacrificial layer and a chemical vapor deposition (CVD) technique to achieve uniform silicon fins. The minimum-sized features are not decided by photolithography, but by the CVD film thickness [5].

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Figure 7 Comparison of fin density in spacer and optical lithography

For FinFETs, short-channel effects can be controlled easily when the fin thickness is approximately half of channel length [10]. This becomes impossible by standard lithographic techniques when gate length reaches the limit of lithographic dimension. Further, standard lithographic techniques produce silicon fins, which are highly nonuniform. Uniformity of silicon fin thickness is very critical for FinFETs because line width roughness in silicon fins leads to large threshold variations [10]. Also, the gate length-to-silicon fin thickness ratio should be less than 1.5 to keep short-channel effects under control in FinFETs [9]. All the above requirements can be met using the spacer lithography technique. Further, since the spacer lithography technique doubles the drive current in a given area because of the doubled fin density, it has emerged as the technique of choice for fabrication of FinFET chips.

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Chapter 4-FinFET Characteristics

4.1 FinFET Device Simulation: In this section, the FinFET device is described and thereafter the effect of channel orientation on FinFETs is discussed. The parameters, which have a significant effect on the on-current and off-current in a FinFET, are identified and matched with the ITRS-predicted on-current and off-current. The performance benefits of a channel-oriented FinFET are explored. The performance and power characteristics of independent-gate (IG) FinFETs are evaluated. The impact of back-gate reverse bias in a FinFET is studied in the context of both subthreshold current and performance. In addition, the optimal reverse bias for IG FinFETs is evaluated through a series of BSIM simulations. 4.2.1 FinFET device parameters : The FinFET device consists of a thin silicon body, whose thickness is denoted TSI , wrapped around by gate electrodes. The effective gate width of a FinFET is 2nHFin, where n is the number of fins and HFin is the fin height. The fin-pitch (p) is the minimum pitch between adjacent fins allowed by lithography at a particular technology node. Table 1 shows symmetric-gate FinFET device parameters used in our simulations for the 32nm FinFET technology. The parameters, which have a drastic effect on the leakage power of FinFETs, are gate-oxide thickness (TOX ), TSI and the effective channel length (Lch). The lateral doping profile in the source/drain region defines Lch. We experimented with a number of values for the above three parameters to obtain those matching the ITRS 32nm logic technology node on- and off-current specifications. These values are shown in Table 1. The supply voltage (Vdd) was chosen to be 1V . The body was intrinsically doped with NBODY = 1015cm 3. Lphys is the physical length of the channel.
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Table 1 Finfet Device parameters

Parameter
L phys L ch T OX T SI N H

BODY

p
Fin

Value 32nm 18nm 1.0nm 10nm 15 3 10 cm 16nm 40nm

4.2.2

Channel orientation effects :FinFETs can be easily fabricated

outside the conventional <100> plane. When non-<100> orientations are used, the electron and hole mobilities are modified due to the asymmetry of the carrier effective masses in the silicon crystal lattice [9]. This property can be exploited to design faster logic gates with differently-oriented transistors in the pull-up and pull-down networks. To quantify the delay of the variously oriented transistors, we performed simulations using BSIM. Fig. shows the variation in pFinFET (nFinFET) drain-to-source current (Ids) with drain-tosource voltage (Vds) for different channel orientations. When the orientation changes from <100> to <110>, the saturation current for pFinFETs increases by around 18%, whereas for nFinFETs, when the orientation changes from <110> to <100>, it increases by 12%. There is a larger increase in the pFinFET current drive when the channel orientation changes because of the smaller dependence of the hole mobility on velocity saturation. The change in carrier mobility due to transistor orientation is diminished by the velocity saturation effect [9].

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Figure 8 Ids vs. Vds characteristics for different orientation

4.2.3

Optimal reverse bias : We next discuss how the best back-gate

reverse bias can be derived. Fig. 4.2 shows the BSIM-simulated DC transfer characteristics for a 32nm nFinFET implemented in the <100> plane. The drain voltage is set to 1V . The front gate-to-source voltage (Vgfs) is varied from 0V to 1V . The transfer characteristics are shown for various back-gate biases (Vgbs). The top curve corresponds to the OSG mode and the bottom four curves correspond to the OLP modes of operation, as indicated. There is a noticeable difference in the Ion and Ioff currents for the different modes. Ion for the OSG mode is about 73% greater than the Ion for the OLP mode (Vgbs = 0:2V ). However, the subthreshold current decreases by an order of magnitude in the OLP mode as compared to the OSG mode. It can be seen
20

that in the OLP mode, the leakage current decreases exponentially with an increase in reverse bias. The percent decrease in Ion with an increase in

Figure 9 Transfer Characteristics of 32nm FinFET

reverse bias is marginal. Beyond a certain point, a further increase in reverse bias results in a very marginal decrease in leakage current. The above discussion indicates that it is important to quantify the variation of leakage current with transistor delay. Fig. 9 shows the delay and leakage current for an OLP-mode inverter at various backgate reverse bias magnitudes, ranging from 0 to 0.4V . It can be seen that the leakage current is strongly dependent on the back gate bias. On the other hand, the degradation in delay is gradual. However, there is a knee point beyond which the leakage current graph flattens out. Thus, if the reverse bias is increased further, the reduction in leakage current is minimal whereas the degradation in delay is
21

noticeable. Therefore, for our experiments, we chose the reverse bias at the knee point: 0.2V for nFinFETs and 1.18V for pFinFETs. The back gate bias was adjusted for pFinFETs to balance the rising and falling delays.

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Chapter 5-APPLICATIONS OF FINFET

5.1 FinFET Logic Synthesis :

Various researchers have explored logic synthesis with FinFETs. The property that has been exploited the most is the use of a back-gate bias in IG-mode FinFETs to modulate the Vth of the front gate. Various innovative standard cell designs have been proposed using different combinations of SG- and IG-mode FinFETs. In [6], different logic gate styles are presented and thereafter a linear programming based sizing algorithm is used to optimize the circuit for power.

Figure 10 : Different kinds of FinFET NAND gate designs

Fig. 8 depicts the SG-, LP-(low power), IG- and IG/LP-mode NAND gates [6]. SGNAND gates have the lowest delay among the different logic styles since fast SG-FinFETs are employed both in the pull-up and pull-down network of the NAND gates. LP-NAND gates have more than double the delay of SG-NAND gates. However, the leakage power of LP-NAND gates, averaged over all the input vectors, is reduced by over 90% when compared to SG-NAND gates. This is because LP-NAND gates employ IG-mode transistors with reverse bias on the back gates. The reverse bias increases the Vth of the front gate, thereby reducing the leakage but increasing the delay of the LP-NAND gates. In IG-NAND gates, only one transistor is used in the pull-up network. To achieve equal rise and fall delays, the size of the pull-up network needs to be scaled up. IG-NAND gates can achieve equal delay as that of the SG-NAND gates. However, the gates occupy more area as compared to that of SG-NAND gates. The fourth design, IG/LP-NAND gate, is a hybrid of

23

the IG- and LP-NAND gates. The leakage/delay characteristics of the IG/LP-NAND gate lie in between those of LP-NAND and IG-NAND gates. It should be noted that sizing of NAND gates for equal rise and fall delay is a challenge because of the fin width quantization. The design rules for sizing the NAND gates are also specified in [6]. Several low-power logic gate options using independent gates are presented. An efficient circuit synthesis methodology based on the proposed low-power logic options has been developed. In [8], a genetic algorithm based power optimization framework for FinFET based circuits is proposed. The authors exploit IG-mode FinFETs along with other lowpower techniques, such as multi-VDD and gate sizing, for power optimization. A novel lookup table based approach for design of FinFET circuits is proposed. It is shown to be accurate by comparisons against mixed-mode device simulations. FinFET physical synthesis is still a nascent area of research. There is still a lack of FinFET physical synthesis tools. However, researchers have looked into the layouts of various standard cells employing SG- and IG-mode transistors. The layout structure of the FinFET depends upon the type of process used. The increased fin density made possible by spacer lithography [5, 13] can be translated to increased layout densities. Another process knob that can be used to improve layout density is fin height. An increase in fin height can translate to increased current in the same area [3]. It is shown that SG-mode standard cells occupy the same area as the standard bulk transistor cells at the same technology node. However, the IG-mode standard cells occupy almost double the area of SG-mode standard cells.

5.2 SRAM using FinFET

A typical CMOS SRAM cell is a six-transistor (6T) structure consisting of two crosscoupled inverters, as shown in Fig. 9. Access to the SRAM cell is enabled by the word line, which controls the two access transistors M5 and M6. These two transistors control whether the cell should be connected to the bit lines or not. They are used to transfer data for both read and write operations. The major SRAM design metrics are read margin, write margin and cell stability. Researchers aim to improve the above SRAM metrics while not

24

sacrificing performance/leakage of the SRAM cells.

Figure 11 SRAM cell structure

FinFET SRAM is a heavily researched area. However, in this section, we only review the most seminal works in the area of FinFET SRAM. In [29], SRAM is investigated and compared to an implementation in the 90nm node planar partially-depleted silicon-oninsulator (PDSOI) technology. It is shown that FinFET SRAM exhibits reduced delays and lower standby leakage current when compared to its PDSOI counterpart. The effect of width quantization on FinFET SRAM is also explored and demonstrated to be acceptable. In [30], both a forward bias to reduce Vth, while performing Read/Write operations in an SRAM, and a reverse bias to reduce the leakage power in the standby mode are used. In [31], the static noise margin (SNM) of FinFET SRAM cells operating in the sub threshold region is investigated. The 6T FinFET SRAM cell is also shown to be fully functional in the subthreshold regime. Further, a stability analysis is performed for various novel IG-mode

25

SRAMs. A device optimization technique for robust and low-power FinFET SRAM is presented in [32]. In this work, the gate sidewall spacer thickness is optimized to simultaneously minimize leakage current and drain capacitance to on-current ratio. Further, it is shown that the optimization reduces the sensitivity of the device Vth to fluctuations in gate length and fin thick-ness. In [33], a joint exploration of VDD-fin height-Vth design space is done for a 65nm FinFET SRAM. It is shown that taller fins can accommodate lower VDD as well as a higher Vth to deliver iso-performance at reduced leakage. An optimization study to improve cell stability in the design space of silicon fin thickness and fin ratio is done in [4]. An alternative to sizing for stability in FinFET memory cells is studied in [5]. It is shown how multiple work functions can be used to control the Vth of the six transistors to improve stability at lower leakage power consumption. An analysis of the impact of channel orientation on stability, performance and power of 6T and 8T FinFET SRAMs is done in [6].

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Chapter 6 -ADVANTAGES and DISADVANTAGES of FinFET

6.1 Benefits of Finfet To exploit different benefits of FinFET, it is fabricated into two types: (1) Dual-gate FinFET, which trims the excess silicon by fabricating the channel using an ultra-thin layer of silicon that sits on top of an insulator, therefore the electric field from the gate to the fin on the top is drastically reduced. (2) Tri-gate FinFET, in which the FET gate wraps around three sides of the transistor's elevated channel, or "fin". Since fins are made vertical in nature, high packing density can be achieved, by packing transistors closer together. Further, to get even more performance and energy-efficiency gains, designers also have the ability to continue growing the height of the fins. One important feature of FinFET is the fin thickness, which needs to be smaller than or equal to the gate length. Their scaling does not depend on oxide thickness, which is a big advantage because its the process lithography that defines the FET characteristics at each new process node. Furthermore, only one extra mask is required to create the silicon fin. Designers also have a choice of extending the width in third dimension in tri gate FinFET without affecting layout area; as a result the effective channel width can be significantly enhanced relative to a planar transistor. The advantage is greater for SRAM layouts, given their dense nature. It exhibits little or no body effect because FinFET channels are fully depleted. A 4-input FinFET NAND is equivalent to a 3-input planar NAND in terms of delay. Given the excellent control of the conducting channel by the gate, very little current is allowed to leak through the body when the device is in the off state. The FinFET can also be run at a lower operating voltage for a given leakage current, halving its dynamic power consumption (which is proportional to CV2f) for a 0.7 scaling in VDD. Some of these advantages become more significant as the operating voltage is reduced. At 1V, the FinFET is 18% faster than the equivalent planar device, but at 0.7V, the advantage is 37%. This is attributed to the FinFETs sub-threshold swing (the amount that the threshold voltage has to

27

be changed to halve its leakage) which is lower than in a planar device. This enables the device to be operated at lower threshold voltages for the same leakage. The difference between the gate and threshold voltage at very low operating voltages is much greater, thus exaggerating the performance advantage of very low-voltage FinFETs. On account of its lower threshold-voltage variability, the channel is well controlled and hence does not need heavy doping, which in turn makes it less susceptible to random dopant fluctuations. Triple gate FinFET has reduced the doping concentration required in the channel to the extent of 1015/cm3.Also, Fabrication of FinFET is compatible with that of conventional CMOS, thus making possible very rapid deployment to manufacturing. 6.2 Drawbacks and Challenges Despite the promise of higher performance and better power efficiency, the move to FinFETs comes with quite a few new challenges, For example, the entire tool chain is impacted, including transistor-level process modeling and simulation, mask synthesis, physical extraction, and physical verification, in turn requiring careful re-characterization and validation of models and libraries for higher levels of abstraction and design. One of the goals for the introduction of this fundamental change in process technology is to maintain as much compatibility with previous design flows as possible to enable quick and transparent adoption. 6.2.1 Corner Effects Though designers have flexibility in variation of height and width of tri-gate, this variation poses different challenges. Although decreasing the fin-width reduces the short channel effects, at the same time the performance of the FinFET may be degraded due to increase in parasitic drain/source resistance which leads to reduction of drive current and trans-conductance of the device. Moreover, with smaller fin width, heat cannot flow through easily and device temperature increases. The effect is more pronounced in case of SOI technology, where buried insulating layer causes severe self-heating effects due to low thermal conductivity of oxide layer.

28

Cross-sectional view of a conventional Tri-gate FinFET is shown in Figure 12[10]. Because of the proximity of gates, the charge sharing occurs in the corner region of the two adjacent gates. This gives rise to premature inversion at the corners. The gate-to-channel electric field is concentrated at the fin corners. As a result, as the gate to-source input voltage increases toward the device threshold, there will be a higher concentration of sub threshold leakage current at the corners of the fin, which is known as corner effect. This premature inversion at the corners of the triple gate FinFET degrades the sub threshold characteristics of the FinFET which results in higher off state leakage current.

Figure 12 conventional Tri Gate FinFET (cross sectional view)

6.2.2 Quantum Effects: The FinFET thickness is a key manufacturing parameter. If the FinFET is too thick, the electrostatic influence of the gate on the sides and top of the fin will be weaker, and the fin body will behave more like a (planar device) bulk substrate, losing the benefits of the FinFET topology. On the other hand, if the FinFET is very thin, then density of available electron (or hole) states is reduced. Under normal circumstances, free electrons/holes have sufficient energy to reside at the conduction/valence energy band edges of the semiconductor material, and therefore conduct current in the transistor channel. The electron/hole energy and band levels in the semiconducting silicon are strong functions of the applied voltages
29

and temperature, which are the basis for the FET model. Normally, there is no shortage of available free states for energetic electrons/holes at the band edges. However, for very thin fins, the quantum effect reduces the density of available states at the band edge. As a result, electrons/holes would need more energy to occupy available states higher than the band edge, and be free to conduct device current. 6.2.3 Performance and Variability Existing FinFETs struggle from a performance and variability perspective: (1) Fin profile shape. A slanted profile is desired to makes it easy to fill the dielectric between the fins, but this creates a design that drags down performance and introduces variability. (2) Too few fins can also cause variability. (3) Non-uniform fin doping is another problem which adds to variability. 6.2.4 Extraction of FinFET Parasitic The 3D nature of FinFETs and the multiple fins pose following challenges :( 1) Establish and extend FinFET RC parasitic models to be closer to those extracted using a field solver (2.5D versus 3D). (2) Compact RCs around FinFET not to explode design TATs. (3) Convergence between pre-layout and post layout by generating good-estimation parasitic RC models of FinFET.

30

CONCLUSION
FinFETs stand poised to enable the next big leap for computer, communications, and consumer devices of all types. FinFETs have attractive qualities, such an excellent control of short channel effects, the ability to tune their performance for energy efficiency or performance, which means they can be used as the basis of flexible SoC processes. However, FinFET technology has created new challenges in terms of fabrication processes, corner effects, quantum effects, width quantization, etc. It requires a new generation of design experience, expertise, and tools to get the most from the technology. These challenges can be addressed by extensive R&D and deep collaboration through a Common Platform. Technology scaling has provided us with increased circuit performance over the past two decades. The industry has scaled the conventional transistors for the past six years using several innovative techniques such as high-k dielectrics and strained silicon. However, scaling of conventional transistors beyond the 22nm node is very difficult due to shortchannel effects, such as drain-induced barrier lowering (DIBL), subthreshold slope and subthreshold leakage current. DGFETs have emerged as a possible solution to continue technology scaling. Such FETs have two gates to control the concentration of the electrons in the channel and thus have superior electrostatic integrity. The two gates mitigate the effect of the drain-source electric field in the channel and thus provide superior channel control. Among DGFETs, FinFETs have emerged as the most viable solution due to their ease of fabrication. The fabrication process of FinFETs is quite similar to the fabrication process of conventional transistors. The tri-gate version of FinFETs was recently announced by Intel as its choice of transistor for fabricating processors at the 22nm technology node. FinFETs have been shown to have superior on-current and off-current when compared to a conventional transistor at the same technology node. Their dual-gate structure can be exploited for innovative circuit design. E.g., if a reverse bias is applied to the back gate of IG-mode FinFETs, the threshold voltage Vth of the front gate can be modulated. Since Vth impacts both the subthreshold current and delay of a transistor, it can be used as a knob to

31

make delay-leakage trade-offs. Novel standard cells have been proposed in the literature that exploits the above fact. It has been shown that FinFETs can be easily fabricated along the < 110 > channel orientation by rotating the pFinFET by 45o relative to the nFinFET. The electron mobility is highest along the < 100 > channel orientation while the hole mobility is highest along the < 110 > channel orientation. Thus, using < 110 > transistors in the pullup network of the logic gate and < 100 > transistors in its pull-down network can lead to better delay.

FinFETs still suffer from the effects of process variations due to factors such as line edge rough-ness and temperature variations. However, they do not suffer from the random dopant fluctuation effect encountered in bulk transistors, since their body is undoped. Lithographic variations can lead to deviation in FinFET parameters, such as LG, TSI , TOX . Further, these variations can be intra-die or inter-die in nature.
G

is heavily dependent on the processing

temperature and, hence, temperature variations during processing can lead to deviations in the value of
G.

Since both leakage and delay heavily depend on the above process

parameters, it is extremely important to characterize variations in FinFET delay/leakage with variations in these parameters.

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REFERENCES
[1] Chenming Hu, Tsu-Jae King, Vivek Subramaniam et al, FINFET

TRANSISTOR STRUCTURES OTHER PUBLICATIONS HAVING A DOUBLE GATE CHANNEL EXTENDING VERTICALLY FROM A SUBSTRATE AND METHODS OF MANUFACTURE, US Patent No. 6413802 B1, awarded July 2 2002 [2] Vivek Subramaniam, et al, Sub 50 nm P-Channel FinFET, IEEE Transactions on Electron Devices, Vol. 48, No. 5, May 2001. [3] Chenming Hu, Tsu-Jae King, Erik Anderson, Charles Kuo, Bokor et al, FinFETA Self-Aligned Double-Gate MOSFET Scalable to 20 nm, IEEE Transactions on Electronic Devices, Vol. 47No. 12, December 2000. [4] Dragica Vasileska et al, Quantum Transport Simulation of Experimentally Fabricated nano FinFET, IEEE Transactions on Electron Devices, Vol. 54, No. 4, April 2007. [5] Xiaoxia Wu, Feng Wang, Yuan Xie, Analysis of Sub threshold FinFET circuits for ultra-low power design, CSE Department, Pennsylvania State University, 2007. [6] F. Djeffal , Z. Ghoggali, Z. Dibi, N. Lakhdar ,Analytical analysis of nanoscale multiple gate MOSFETs including effects of hot-carrier induced interface charges, Institute of Microeletronics, LEA, Department of Electronics, University of Batna, Batna 05000, Algeria, 29 November 2008 [7] Daewon Ha, H Takeuchi, Y K Choi, T-J King, W P Bai, A Agarwal et al, Molybdenum Gate HfO2 CMOS FinFET Technology, IEDM 04 IEEE, 2004 [8] Tai-su Parka, Euijoon Yoona, Jong-Ho Leeb, A 40 nm body-tied FinFET (OMEGA MOSFET)using bulk Si wafer, Physics E 19 (Elsevier), 2003. [9] Dong-Soo Woo, Jong-Ho Lee, Woo Young Choi, Byung-Yong Choi, Young-Jin Choi, Jong Duk Lee, and Byung-Gook Park, Electrical Characteristics of FinFET

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With Vertically Nonuniform Source/Drain Doping Profile, IEEE Transactions on Nanotechnology Vol. 1, No. 4, Dec 2002 [10] Chris A. Mack, Fifty years of Moores Law, IEEE Transactions on Semiconductor manufacturing, Vol 24, No. 2, May 2011 [11] Animesh Dutta, Ashish Goel, Riza Tamer cakici, Kaushik Roy, Dheepa Lekshmanan, Hamid Mehmood, Modelling and circuit synthesis for independlty controlled double gate MOSFET, IEEE transaction on CAD of Integrated Circuits and Systems, Vol. 26, No. 11, November 2007 [12] Xu Shao, Zinping Yu, Nanoscale FinFET simulation A quasi 3D quantum mechanical model using NEGF, Elsevier Solid State Electronics 49 (2005) 14351445, www.sciencedirect.com 29 June 2005. [13] Lombardo, Gerardi et al., Advantage of FinFET architecture in SONOS and nanocrystals memory devices, IEEE-IEDM (1-4244-0439-X/07), 2007. [14] FinFET Design challenges,, www.synopsys.com [15] FinFET Circuit Design, P Mishra, Princeton University.

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APPENDIX

1. SOI- Silicon On Insulator

2. CMOS- Complementary Metal oxide Semiconductor. 3. FET- Field Effect Transistor. 4. DIBL: Drain Induced Barrier Lowering. 5. NEGF- Non Equilibrium greens Function. 6. SG FinFET- Shorted Gate FinFET. 7. IG FinFET- Independent Gate FinFET. 8. SoC- System on Chip.

35