Experiment #5

ASYNCHRONOUS SERIAL I/O AND INTERRUPTS

5.1 OBJECTIVE
The purpose of this experiment is getting familiar with SCI module in 68HC11E9. This will be
accomplished by implementing a driver with interrupt and polling based send and receive subroutines
for the SCI module which complies with RS232 standard. Hardware setup of the serial communication
will also be studied.

Note:
You should use BUFFALO in the simulation. You can see outputs and enter inputs using Axide
terminal.

5.2 PRELIMINARY WORK
1. Read through Section 5.3.1 (Communication Configuration) to obtain background information
on SCI module.
2. Write a subroutine to initialize the SCI module, your subroutine must configure the SCI
module as the following:
1 start bit,
8 data bits,
1 stop bit,
interrupts disabled,
No wake up,
Break generator off,
BUAD rate of 9615,
Transmitter enabled.
3. Read through Section 5.3.2 (SCI transmitter) to obtain background information
on SCI transmitter.
4. Write a subroutine SendChar to send the contents of Accumulator A to the virtual terminal.
5. Write SendStr subroutine that uses SendChar to send a string to the terminal; the function
stops sending characters when it reads the first $ character.
6. Read through Section 5.3.3 (SCI receiver) to obtain background information on SCI receiver.
7. Change the initialization subroutine from (2) above to enable the receiver. Then write
RecvChar subroutine to read the user input from the keyboard and return it in Accumulator A.
8. Write RecvStr subroutine that will read the user input string from keyboard and save the
received in memory when the user presses the Enter key. Do not forget to append the $
character to the string saved in memory.
9. Write an EchoChar subroutine that uses the RecvChar and SendChar to echo (display) the
user input on the screen.
10. Write an EchoStr subroutine by modifying the RecvStr subroutine to take advantage of the
EchoChar subroutine from (9).
11. Write a welcome subroutine, using polling approach, that uses RecvStr and SendStr to ask
for the user name and then displays a welcoming message. For example:
> What is your name ? (program output)
Name (user input)
Welcome Name (program output)
12. Simulate the code you wrote in (11).
13. Read through section 5.3.4, 5 to obtain background about Interrupts and get familiar with the
BUFFALO management of Interrupt vectors.
14. Write an initializing subroutine Inten that enables the interrupt vectors.
15. Write an Interrupt Service Routine (ISR) IsrRec to handle the reception of a character. Write
another Interrupt Service Routine IsrTr that handles the completion of transmitting a
character.
16. Using on the above ISRs in (15) rewrite the welcome subroutine from (11) using interrupts,
instead of relying on polling technique.
17. Simulate the code you wrote in (16).

5.3 ASYNCHRONOUS SERIAL INTERFACE
5.3.1 Communication Configuration
Serial communication is the process of sending one bit at a time over a communication channel.
Compared to parallel communication where several bits are sent at once, serials communication
saves wiring costs especially for long distances. The Universal Asynchronous Receiver/Transmitter
(UART) is the hardware port that implements the serial data transmission. This is called the
Asynchronous Communications Interface Adapter (ACIA) or Serial Communication Interface (SCI) on
68HC11 MCU. The module is implements a receiver and a sender that complies with the RS232
protocol.

RS232 is a standard that defines a simple asynchronous communication protocol. It specifies:
Electrical signal characteristics such as voltage levels, signaling rate, timing and slew-rate
of signals, voltage withstand level, short-circuit behavior, and maximum load capacitance;
Interface mechanical characteristics, pluggable connectors and pin identification,
Functions of each circuit module in the interface connector,
Standard sub-modules of interface circuits for selected telecommunication applications.

To comply with specific physical channel and receiving equipment properties, the digital signal has to
be transported by an amplitude and time discrete signal that is optimally tuned. The waveform pattern
of voltage or current used to represent the 1s and 0s of a digital signal on a transmission link is called
line coding.
RS232 applies voltages in the range -15 to +15 V to represent the high and low logic and the special
sequence control bits. These different voltage levels require interface circuits that convert them to
normal voltage levels. MAX232 chip can be used for this purpose. This is already placed on the EVBU
and the PC boards, communicating using a serial link. Figure 5.1 shows the connection configuration
defined between the EVBU and the PC. It is called full duplex as it allows the two parts to receive and
send data at the same time.

Figure 5.1. Full duplex serial channel
Eventhough RS232 standard has many pins and uses the DB25 (25 pin) interface as the default,
DB9/EIA-574 (9 pin) interface is used widely for its smaller size (lower cost) since it is sufficient when
operating in asynchronous serial mode. Figure 5.2 shows the EIA-574 interface used in the lab and
describes the function of the nine pins.

Figure 5.2. DB9/EIA-574 male interface (used in the lab)
As the communication is asynchronous one, extra bits must be sent to group the data bits and to
define the end and start of the communication. Having more than one configuration for the way that
the data can be sent and received, the transmitter and receiver must agree on the format of the data
that is being exchanged before the communication starts. A frame packs a group of bits to be
transmitted together. Each frame contains special bits to define the start and end, and other optional
bits to help receivers detect any errors in transmitted data due to noise and other factors. Figure 5.3
depicts the data frame contents, the ninth (T8) bit and the Parity bit are optional. Start and Stop bits
identify the start and the end of the data frame as their names imply.
Stop Parity T8 7 6 5 4 3 2 1 0 Start
1 0
Figure 5.3. Data Frame
The speed of data transmission must be defined before the communication starts. Mismatches in the
receiver and transmitter clocks will result in loss of data in the receiver buffer. The speed of
communication is measured in Baud Rate. The programmer must be sure that both end points are
configured to apply the same options.
68HC11 offers a number of control registers to configure SCI settings. The critical registers are
described below.

Figure 5.4. Control Register 1 (SCCR1)
R8 - Receive Data Bit 8: If M bit is set, R8 stores the ninth bit in the receive data character.
T8 - Transmit Data Bit 8: If M bit is set, T8 stores the ninth bit in the transmit data
character.
Bit 5 - Unimplemented: Always reads 0
M - Mode Bit (select character format):
0 = Start bit, 8 data bits, 1 stop bit
1 = Start bit, 9 data bits, 1 stop bit
WAKE - Wakeup by Address Mark/Idle Bit
0 = Wakeup by IDLE line recognition
1 = Wakeup by address mark (most significant data bit set)
Bits [2:0] Unimplemented: Always read 0


Figure 5.5. Control Register 2 (SCCR2)

TIE - Transmit Interrupt Enable Bit
0 = TDRE interrupts disabled
1 = SCI interrupt requested when TDRE status flag is set
TCIE - Transmit Complete Interrupt Enable Bit
0 = TC interrupts disabled
1 = SCI interrupt requested when TC status flag is set
RIE - Receiver Interrupt Enable Bit
0 = RDRF and OR interrupts disabled
1 = SCI interrupt requested when RDRF flag or the OR status flag is set
ILIE - Idle-Line Interrupt Enable Bit
0 = IDLE interrupts disabled
1 = SCI interrupt requested when IDLE status flag is set
TE - Transmitter Enable Bit: When TE goes from 0 to 1, one unit of idle character time
(logic 1) is queued as a preamble.
0 = Transmitter disabled
1 = Transmitter enabled
RE - Receiver Enable Bit
0 = Receiver disabled
1 = Receiver enabled
RWU - Receiver Wakeup Control Bit
0 = Normal SCI receiver
1 = Wakeup enabled and receiver interrupts inhibited
SBK - Send Break: At least one character time of break is queued and sent each time SBK
is written to 1. As long as the SBK bit is set, break characters are queued and sent. More
than one break may be sent if the transmitter is idle at the time the SBK bit is toggled on
and off, as the baud rate clock edge could occur between writing the 1 and writing the 0 to
SBK.
0 = Break generator off
1 = Break codes generated


Figure 5.6. BAUD register
TCLR - Clear Baud Rate Counter Bit (Test)
SCP[2:0] - SCI Baud Rate Prescaler Select Bits
ACKB - SCI Baud Rate Clock Check Bit (Test)

5.3.2 SCI Transmitter
Figure 5.7 depicts the schematic diagram of the SCI transmitter implementation. Notice the distribution
of the SCCR1, SCCR2 and BAUD register bits in the figure.
The transmission cycle starts by waiting for the transmitter module to be freed. The status of the
transmitter can be checked by reading the TC flag in the Status Register (SCSR). Once the TC flag
goes high, this means that any previous transmission operation is finished and the transmitter is free
to send another frame of data. The process of waiting for the transmitter to be freed by checking its
status bits continuously is called polling.
Then we write the data to be sent on the Data Register (SCDR), with address $102F, which
represents a buffer for the hidden shift register. Once the data is written to the shift register, the bits
start to be transmitted, starting by the LSB bit, to the pin buffer using a clock speed controlled by the
BAUD register. While the transmitter shifts and sends out the bits, the TC flag in the Status Register
(SCSR) stays 0 to indicate that the transmitter is busy. SCSR details are shown in Figure 5.8.


Figure 5.7. SCI transmitter schematic diagram

Figure 5.8. Status Register (SCSR)
TDRE - Transmit Data Register Empty Flag: This flag is set when SCDR is empty. Clear
the TDRE flag by reading SCSR with TDRE set and then writing to SCDR.
0 = SCDR busy
1 = SCDR empty
TC - Transmit Complete Flag: This flag is set when the transmitter is idle (no data,
preamble, or break transmission in progress). Clear the TC flag by reading SCSR with TC
set and then writing to SCDR.
0 = Transmitter busy
1 = Transmitter idle
RDRF - Receive Data Register Full Flag: This flag is set if a received character is ready to
be read from SCDR. Clear the RDRF flag by reading SCSR with RDRF set and then
reading SCDR.
0 = SCDR empty
1 = SCDR full

To achieve maximum transmission throughput you can write the next data frame directly to the SCDR
after it is empty by checking the TDRE flag.
5.3.3 SCI Receiver
Figure 5.9 shows the schematic diagram of the SCI receiver implementation. The reception cycle
starts by waiting for the receiver module to be filled by a full frame of data. The status of the receiver
can be checked by reading the RDRF flag in the SCSR. Once the RDRF flag goes high, this means
that a complete data frame has been received and the SCDR is full. Again we can use the polling
technique to know if we received any new data, by checking the receiver status bits continuously.
Once we have the data, any load operation is sufficient to read the SCDR contents and to clear the
RDRF flag.
5.3.4 Interrupts
Up to this point the polling technique has been used to send and receive data using the SCI. The
polling technique requires continuous checking of the status, and therefore wastes cycles. In addition,
it adds challenges to software design especially when the application response latency is an important
factor or when there are mission critical applications with real time requirements.
Interrupt is a hardware based mechanism that forces the processor to execute a piece of code located
at special address, if a device status meets specific conditions. This piece of code is called Interrupt
Service Routine (ISR). In 68HC11 architecture, once an interrupt occurs, it loads an address of one of
the ISRs available to the PC register, depending on the type of the device that requested the interrupt.
The addresses of the different ISRs are saved in special table, called interrupt vector table, which is
located at the last part of the 64 KB memory map. You are familiar with the first interrupt vector, the
Reset Vector, which has the highest priority and is located at $FFFE-$FFFF. The priority of different
interrupts, when more than one interrupt request occurr at the same time, is decided by hardware. The
decision is made based on their order in memory except for the software interrupts, which have the
lowest priority.
Figure 5.9. SCI receiver schematic diagram
68HC11 architecture allows the programmer to control all the interrupts by using SEI and CLI
instructions. This makes it possible to define pieces of code that are not interruptible (preemptive).
Those pieces of code are called critical sections.
The SCI module has one interrupt vector located at $FFD6-$FFD7. The contents of this vector will be
loaded to PC register if any of these events happen:
Receive data register full, RDRF = 1
Transmit data register empty, TDRE = 1
Transmit complete, TC = 1
As many requests share the same interrupt vector, the ISR executed on an SCI interrupt must check
those flags to determine the status of the SCI module. In case there are more than one cause for the
interrupt, the ISR should decide which one has higher priority than the others.
To initialize the SCI module to take advantage of the interrupts, return to the SCCR2 and take a look
at the different bits that control the receiver and transmitter interrupt capabilities. RIE arms
1
the SCI
receiver, so it can interrupt once data is received. TCIE is another bit that arms the SCI transmitter to
interrupt once the data has been sent. This interrupt is very useful in case we want to send a group of
data frames. Bear in mind that you have to disarm the SCI transmitter once you finished sending the
data frames. Otherwise the last sent frame will request an interrupt and there is no extra data to be
written to clear the TC flag, which causes it to request interrupts indefinitely.
The structure of your code can follow many paradigms to work with interrupts; below is an example:
-----------------------------------------------------------------------------------
ORG $FFD6
FDB SCI_ISR
ORG $FFFE
FDB main
ORG code
****************************************************************************
main: initialize the stack pointer ;BUFFALO takes care
initialize the SCI module
1- Enable transmitter and receiver
2- Define the communication settings as BAUD, data frame characteristics
3- Arm the transmitter and the receiver.
CLI ;Enable the interrupts in the processor
Do any other tasks asked by the user
****************************************************************************
SCI_ISR:
SEI ;Disable the general interrupts flag, which does not allow nested ISRs
to be executed.

If a data frame is receved then
serve the receiver by calling recv
else
if a data frame has been sent then
serve the transmitter by calling send
CLI ;Enable the general interrupts flag
RTI ;RTI is different from RTS, in ISR you should use RTI.
****************************************************************************
recv:
PUSH the registers you will use in this subroutine (to preserve them)
Clear the flag that requested the interrupt
Serve the interrupt
PULL the registers you pushed in this subroutine
RTS
****************************************************************************
send:
PUSH the registers you will use in this subroutine (to preserve them)
Clear the flag that requested the interrupt
Serve the interrupt
PULL the registers you pushed in this subroutine
RTS
---------------------------------------------------------------------------------

1
arm and disarm are used to mean granting the device ability to request interrupts and taking away that ability.
5.3.5 BUFFALO Interrupt Management
Since the interrupt vector table is implemented in PROM, it is not possible to change the values of
those vectors in the EVBU. However, BUFFALO points these vectors to another table that resides in
RAM memory space. For example, SCI interrupt vector is filled with the address $00C4. Addresses
$00C4-$00C6 are reserved to be filled by a jump instruction that points to the user ISR. In this way,
BUFFALO allows the user to place the ISR code to anywhere in the user accessible memory without
changing the contents of the interrupt vector table.
5.4 EXPERIMENTAL WORK
1 Run your program welcome subroutine from (12) of Section 5.2, which uses the polling
mechanism and demonstrate your results to the lab instructor.
2 Run your program welcome subroutine that uses the interrupt mechanism, from (17) of
Section 5.2 and demonstrate your results to the lab instructor.
5.5 References
1 M68HC11E Family Data Sheet
2 Embedded Microcomputer Systems, Real Time interfacing. Second edition. Jonathan W.
Valvano.