MHZ Convertor PDF

Thesis for the degree of Doctor of Technology
Sundsvall, 2013

High Frequency (MHz) Resonant Converters
using GaN HEMTs and Novel Planar
Transformer Technology

Hari Babu Kotte

Supervisors
Associate Professor Kent Bertilsson
Professor Bengt Oelmann

Department of Electronics Design
Mid Sweden University, SE-851 70 Sundsvall, Sweden

ISSN 1652-893X
Mid Sweden University Doctoral Thesis 158

ISBN 978-91-87557-01-9

Akademisk avhandling som med tillstnd av Mittuniversitetet i Sundsvall
framlggs till offentlig granskning fr avlggande av teknologie
doktorsexamen i elektronik torsdag den 26
th
september 2013, klockan 10:15
i sal L111, Mittuniversitetet Sundsvall. Seminariet kommer att hllas p
engelska.

High Frequency (MHz) Resonant Converters using GaN
HEMTs and Novel Planar Transformer Technology

Hari Babu Kotte

Hari Babu Kotte, 2013

Department of Electronics Design,
Mid Sweden University, SE-851 70 Sundsvall
Sweden

Telephone: +46 (0)60 148982

Printed by Kopieringen Mittuniversitetet, Sundsvall, Sweden, 2013
iii

Dedicated at the divine lotus feet of
Bhagawan Sree Satya Sai Baba,
Sree Swami Sivananda &
Ammagaru

Truth, righteousness, peace and love these are the four
pillars on which mansion of happiness is built

iv
ABSTRACT
The increased power consumption and power density demands of modern
technologies have increased the technical requirements of DC/DC and AC/DC power
supplies. In this regard, the primary objective of the power supply researcher/engineer
is to build energy efficient, high power density converters by reducing the losses and
increasing the switching frequency of converters respectively. Operating the converter
circuits at higher switching frequencies reduces the size of the passive components
such as transformers, inductors, and capacitors, which results in a compact size,
weight, and increased power density of the converter. Therefore, the thesis work is
focussed on the design, analysis and evaluation of isolated converters operating in the
1 - 5MHz frequency region with the assistance of the latest semi conductor devices,
both coreless and core based planar power transformers designed in Mid Sweden
University and which are suitable for consumer applications of varying power levels
ranging from 1 60W.

In high frequency converter circuits, since the MOSFET gate driver plays a prominent
role, different commercially available MOSFET gate drivers were evaluated in the
frequency range of 1 - 5MHz in terms of gate drive power consumption, rise/fall times
and electromagnetic interference (EMI) and a suitable driver was proposed.

Initially, the research was focused on the design and evaluation of a quasi resonant
flyback converter using a multilayered coreless PCB step down transformer in the
frequency range of 2.7 4MHz up to the power level of 10W. The energy efficiency of
this converter is found to be 72 - 84% under zero voltage switching conditions (ZVS).
In order to further improve the energy efficiency of the converter in the MHz
frequency region, the new material device GaN HEMT was considered. The
comparisons were made on a quasi resonant flyback DC-DC converter using both the
Si and GaN technology and it was found that an energy efficiency improvement of 8
10% was obtained with the GaN device in the frequency range of 3.2 5MHz. In order
to minimize the gate drive power consumption, switching losses and to increase the
frequency of the converter in some applications such as laptop adapters, set top box
(STB) etc., a cascode flyback converter using a low voltage GaN HEMT and a high
voltage Si MOSFET was designed and evaluated using a multi-layered coreless PCB
transformer in the MHz frequency region. Both the simulation and experimental
results have shown that, with the assistance of the cascode flyback converter, the
switching speeds of the converter can be increased with the benefit of obtaining a
significant improvement in the energy efficiency as compared to that for the single
switch flyback converter.

In order to further maximize the utilization of the transformer, to reduce the voltage
stress on MOSFETs and to obtain the maximum power density from the converter
circuit, double ended topologies were considered. Due to the lack of high voltage high
side gate drivers in the MHz frequency region, a gate drive circuitry utilizing the
multi-layered coreless PCB signal transformer was designed and evaluated in both a
half-bridge and series resonant converter (SRC). It was found that the gate drive power
consumption using this transformer was around 0.66W for the frequency range of 1.5 -
v
3.75 MHz. In addition, by using this gate drive circuitry, the maximum energy
efficiency of the SRC using multilayered coreless PCB power transformer was found to
be 86.5% with an output power of 36.5W in the switching frequency range of 2
3MHz.

In order to further enhance the energy efficiency of the converter to more than 90%,
investigations were carried out by using the multiresonant converter topology (LCC
and LLC), novel hybrid core high frequency planar power transformer and the GaN
HEMTs. The simulated and experimental results of the designed LCC resonant
converter show that it is feasible to obtain higher energy efficiency isolated DC/DC
converters in the MHz frequency region. The peak energy efficiency of the LCC
converter at 3.5MHz is reported to be 92% using synchronous rectification. Different
modulation techniques were implemented to regulate the converter for both line and
load variations using a digital controller.

In order to realize an AC/DC converter suitable for a laptop adapter application,
consideration was given to the low line of the universal input voltage range due to the
GaN switch limitation. The energy efficiency of the regulated converter operating in
the frequency range of 2.8 3.5MHz is reported to be more than 90% with a load
power of 45W and an output voltage of 22Vdc. In order to determine an efficient power
processing method on the secondary side of the converter, a comparison was made
between diode rectification and synchronous rectification and optimal rectification was
proposed for the converters operating in the MHz frequency range for a given power
transfer application. In order to maintain high energy efficiency for a wide load range
and to maintain the narrow switching frequency range for the given input voltage
specifications, the LLC resonant converter has been designed and evaluated for the
adapter application. From the observed results, the energy efficiency of the LLC
resonant converter is maintained at a high level for a wide load range as compared to
that for the LCC resonant converter.

Investigations were also carried out on isolated class E resonant DC-DC converter with
the assistance of GaN HEMT and a high performance planar power transformer at the
switching frequency of 5MHz. The simulated energy efficiency of the converter for the
output power level of 16W is obtained as 88.5% which makes it feasible to utilize the
designed isolated converter for various applications that require light weight and low
profile converters.

In conclusion, the research in this dissertation has addressed various issues related to
high frequency isolated converters and has proposed solution by designing highly
energy efficient converters to meet the current industrial trends by using coreless and
core based planar transformer technologies along with the assistance of GaN HEMTs.
With the provided solution, in the near future, it is feasible to realize low profile, high
power density DC/DC and AC/DC converters operating in MHz frequency region
suitable for various applications.
vi
SAMMANDRAG
kade krav p energifrbrukningen och effekttthet i modern teknik har kat de
tekniska kraven i DC/DC och AC/DC omvandlare. I detta avseende r det primra
mlet fr konstruktren att bygga energieffektiva omvandlare med hg
effekttthet genom att minska frlusterna. Genom att ka switchfrekvensen kan
man reducera storleken p passiva komponenter ssom transformatorer,
induktanser och kondensatorer, som resulterar i en kompakt storlek, reducerad
vikt, och hg effekttthet hos omvandlaren. Denna avhandling inriktat p design,
analys och utvrdering av isolerade omvandlare verksamma i frekvensomrdet 1 -
5 MHz med hjlp av de senaste halvledarkomponenterna, planara transformatorer
(bde med och utan krna) lmpliga fr effektniver mellan 1 - 60W.
Drivkretsar fr MOSFET transistorer r mycket viktiga fr prestandan hos
hgfrekventa omvandlare och drfr har olika kretsar utvrderat med hnsyn till
energieffektivitet och stig-/falltider. Inledningsvis var forskningen inriktad p
design och utvrdering av en kvasi resonant flyback-omvandlare med en
flerlagers krnfria kretskortstransformator arbetande inom frekvensomrdet 2,7 -
4 MHz upp till 10W. Energieffektiviteten hos denna omvandlare ligger inom
intervallet 72 - 84% och utnyttjar noll-genomgng switchning (ZVS). Fr att
ytterligare frbttra energieffektiviteten hos omvandlaren i MHz omrdet, har nya
transistorer i Gallium-Nitrid (GaN) utvrderats. Prestandan hos omvandlare med
olika transistorer har jmfrts i frekvensomrdet 3.5-5MHz och genom att utnyttja
GaN komponenter s steg verkningsgraden ca 8-10%. Fr att utnyttja GaN
transistorns lgre gate laddning i applikationer som krver hgre spnningar har
en kaskod flyback omvandlare med en 200V GaN och 600V Si transistor
konstruerats och utvrderats. Bde i simulering och mtningar har det visat sig
mjligt att ka prestandan jmfrt med enbart en kiseltransistor.
Fr att maximera nyttjandegraden av transformatorn, minska stressen p
transistorn och ka effektttheten s har ven bryggkopplade topologier
utvrderats. D det saknas isolerade flytande gatedrivare som bde klarar krav p
spnning och frekvens s har en sdan konstruerats med en isolerad med en
krnfri kretskorts transformator och har utvrderats i en serieresonat omvandlare.
Energifrbrukningen fr gate drivaren visade sig vara 0.66W och relativt konstant
inom frekvensomrdet 1.5-3.75MHz. I en omvandlare byggd kring denna gate-
drivare s uppnddes en verkningsgrad av 86.5% upp till 36.5W i 2-3MHz.
Fr att n verkningsgrader ver 90% s har multiresonanta topologier (LCC och
LLC) utvrderats med krnbaserade transformatorer och GaN transistorer. Det
har verifierats att det gr att ka verkningsgraden och maximalt s har 92%
uppmtts i en LCC omvandlare med synkron likriktning. Fr att reglera
utspnningen s har olika moduleringstekniker utvrderats i en mikrokontroller.
Eftersom befintliga GaN komponenter varit begrnsade till 200V s har bara varit
vii
mjligt att konstruera fr den lgre inspnningen hos en AC/DC omvandlare. I
den reglerade omvandlaren s har verkningsgraden sjunkit ngot men ligger
fortfarande hg p ver 90% upp till 45W last arbetande i frekvensomrdet 2.8-
3.5MHz. Likriktningen av sekundrsidan r en kritisk del fr prestandan och en
synkron- resp diod-likriktare har jmfrts med varandra. En LLC omvandlare har
ocks konstruerats fr att kunna reglera omvandlaren inom ett litet
frekvensomrde men med stora variationer p inspnning och last. ven en klass
E omvandlare har utvrderats genom kretssimulering i en omvandlare arbetande
vid 5MHz och visar p att det br vara mjligt att n 88.5% verkningsgrad upp till
16W.
Sammanfattningsvis har forskningen i denna avhandling behandlat olika frgor
som rr hgfrekventa isolerade omvandlare och har freslagit lsning genom att
utforma mycket energieffektiv omvandlare fr att mta de kommersiella
trenderna med hjlp av planartransformator med och utan krna tillsammans
med nya GaN HEMT transistorer. Arbetet har visat p att det inom en snar
framtid gr att implementera omvandlare med lg bygghjd och hg effekttthet
bde fr DC/DC och AC/DC applikationer.

viii
ACKNOWLEDGMENT
First of all, I would like to express my sincere gratitude to my
supervisor, Associate professor Kent Bertilsson, for his support and guidance
throughout the course of this work. His innovative thinking and rigorous
research attitude have guided me throughout my research work and made
this task possible. Special thanks also go to my co-supervisor Prof. Bengt
Oelmann for his kind help and support during my PhD studies.

I would like to thank my colleagues Abdul Majid, Jawad Saleem, Stefan
Haller and Farhan Alam of the power electronics group in Mid Sweden
University.

My heartfelt thanks go to my colleague and friend Muhammad Anzar
Alam for his support in hard times during my PhD studies.

I am grateful to Fanny Burman, Carolina Blomberg and Lotta Frisk for
their kind administrative support, the wonderful members of the Mid Sweden
University staff who were always willing to help me out. I wish to also
express my gratitude towards my other colleagues of the electronics design
division who have directly or indirectly supported me throughout my studies
at Mid Sweden University. My special thanks go to Krister Alden, Najeem
Lawal, Henrik Andersson, David Krapohl, Mikael Bylund, Magnus Engholm,
Gran Thungstrm and Prerna Kumar for always being so kind and helpful.
My colleagues Kannan Thiagarajan and Cheng Peng are also greatly
acknowledged for having good discussions during my studies. I would also
convey my special thanks to Anne hlin and Christina Olsson for their timely
support.

The financial support of Mid Sweden University, Vinnova, European
Union and The Swedish Energy Agency, County Administrative Board in
Vsternorrlands is greatly acknowledged.

My family has been very important to my studies throughout my life.
Their dedication and encouragement has allowed me to continue my
education to the doctoral level. My heartfelt pranams go to my parents Sri.
Kotte Krishna Murthy, Smt. Suseela Devi and Grandmother Seshamma Sadhu
(bujji gadu) especially, as their unwavering support all the way through my
life has meant more than I can put into words in this thesis. My great
appreciation also goes to my brother in law Mr. Soma Sekhar, sister
Vijayalakshmi and nephew Anurag Soma Sekhar for their kind support and
ix
encouragement. I would like to take this opportunity to convey my gratitude
towards my brother in law Mr. Ambatipudi Nagendra Prasad (Sekhar).

With the deepest love, I would like to thank my wife and colleague,
Radhika Ambatipudi, for all her support and encouragement through all the
good and the bad times (both professionally and personally). With her
support and friendship, my years at Mid Sweden University, Sundsvall, and
Sweden have been full of joy.

The kind help and support offered both spiritually and professionally
by Prof. Sri. S. Kamakshaiah during the early stage of my career is greatly
acknowledged. I would like to thank my master and friend Venkateshwar Rao
garu and my close friends Kiran Kumar Kosaraju and Murali Krishna Talari
for being the driving force in my life.

My sincere thanks also go to Sri Krishnendra Santani (Morbror), Sri. C.
Rommel uncle, Sundsvall SAI community who are responsible for the
enhancement of my spiritual life here in Sundsvall, Sweden.

Sundsvall, September 2013
Kotte Hari Babu

x
TABLE OF CONTENTS
ABSTRACT ...................................................................................................................... IV
SAMMANDRAG ............................................................................................................ VI
ACKNOWLEDGMENT .............................................................................................. VIII
TABLE OF CONTENTS ................................................................................................... X
ABBREVIATIONS AND ACRONYMS ..................................................................... XV
LIST OF FIGURES ...................................................................................................... XVII
LIST OF TABLES .......................................................................................................... XXI
LIST OF PAPERS ........................................................................................................ XXII
1 INTRODUCTION ..................................................................................................... 1
1.1 IMPORTANCE OF INCREASING SWITCHING FREQUENCY ............................. 1
1.2 CHALLENGES DUE TO HIGHER SWITCHING FREQUENCIES ......................... 3
1.3 THESIS BACKGROUND AND MOTIVATION ................................................... 3
1.4 THESIS OBJECTIVE AND METHOD ................................................................ 5
1.5 THESIS OUTLINE .......................................................................................... 6
2 MOSFET GATE DRIVERS FOR HIGH SPEED SMPS .................................... 10
2.1 SWITCHING MODEL OF POWER MOSFET .................................................... 10
2.2 SWITCHING BEHAVIOUR OF POWER MOSFET ............................................ 11
2.2.1 Turn-on and Turn-off procedure in power MOSFET .................... 11
2.3 GATE DRIVE POWER CONSUMPTION ......................................................... 14
2.4 COMPARISON OF DIFFERENT DRIVERS FOR HIGH SPEED SMPS .................. 15
3 QUASI RESONANT FLYBACK CONVERTER USING CORELESS
PCB STEP-DOWN TRANSFORMER .................................................................. 19
3.1 FLYBACK DC-DC CONVERTER ................................................................. 20
3.1.1 Design guidelines of flyback transformer in DCM ........................ 22
3.1.2 Design guidelines of flyback transformer in CCM ........................ 23
3.1.3 Design Example .................................................................................. 24
3.2 DESIGN AND PERFORMANCE OF MLCLPCB STEP-DOWN POWER
TRANSFORMER ........................................................................................................ 25
3.2.1 Geometrical parameters of MLCLPCB 2:1 power transformer .... 25
3.2.2 Electrical Parameters of MLCLPCB step-down 2:1 power
transformer ....................................................................................................... 26
3.3 HARD SWITCHED CONVERTER .................................................................. 27
3.3.1 Problems associated with hard switched converter ...................... 27
3.3.2 Measures to minimize losses in hard switched converter ............ 28
xi
3.4 SOFT SWITCHED FLYBACK CONVERTER ................................................... 29
3.4.1 Zero Current Switching (ZCS) .......................................................... 29
3.4.2 Zero Voltage Switching (ZVS) .......................................................... 30
3.5 SWITCHING TRAJECTORY OF MOSFET ..................................................... 30
3.6 ZVS QUASI RESONANT FLYBACK CONVERTER ........................................... 31
3.6.1 Modes of operation of quasi resonant flyback converter .............. 31
3.6.2 Condition required for ZVS in quasi resonant flyback converter 33
3.6.3 Expression for (fsw) in quasi resonant flyback converter ............... 33
3.7 SIMULATION AND EXPERIMENTAL RESULTS OF HARD AND SOFT
SWITCHED CONVERTER .......................................................................................... 34
3.7.1 Simulation results of ZVS flyback converter .................................. 35
3.7.2 Experimental results of ZVS flyback converter .............................. 38
3.7.3 Regulation of ZVS flyback converter ............................................... 38
3.7.4 Thermal profile of ZVS flyback converter ....................................... 40
4 GALLIUM NITRIDE HIGH ELECTRON MOBILITY TRANSISTOR
FOR HIGH SPEED SMPS ...................................................................................... 42
4.1 ADVANCEMENTS IN SEMI CONDUCTOR MATERIALS ................................ 42
4.1.1 Properties of semiconductor materials ............................................ 43
4.1.2 Advantages of GaN material compared to other materials .......... 43
4.2 EVALUATION OF GAN AND SI DEVICES IN ZVS FLYBACK CONVERTER
USING MLCLPCB STEP DOWN TRANSFORMER ......................................................... 45
4.2.1 Comparison of GaN HEMT and Si MOSFET parameters ............. 45
4.2.2 Experimental results of ZVS flyback converter using GaN and Si
devices 46
5 CASCODE FLYBACK CONVERTER .................................................................. 51
5.1 OPERATING PRINCIPLE OF CASCODE FLYBACK CONVERTER .................... 52
5.2 MULTILAYERED CORELESS PCB STEP DOWN 8:1 TRANSFORMER ............... 54
5.3 SIMULATION AND EXPERIMENTAL RESULTS OF CASCODE AND SINGLE
SWITCH FLYBACK CONVERTER ............................................................................... 55
5.4 LOSS ESTIMATION OF CASCODE CONVERTER ............................................ 58
6 GATE DRIVE CIRCUITRY FOR HIGH SPEED DOUBLE ENDED
CONVERTER TOPOLOGIES ............................................................................... 62
6.1 GATE DRIVE CIRCUIT DESIGN USING MULTILAYERED CORELESS PCB
TRANSFORMER ........................................................................................................ 62
6.2 SIMULATION RESULTS OF GATE DRIVE CIRCUITRY .................................... 63
6.3 EXPERIMENTAL RESULTS OF GATE DRIVE CIRCUIT .................................... 65
6.4 GATE DRIVE POWER CONSUMPTION ......................................................... 65
7 DESIGN AND ANALYSIS OF HIGH FREQUENCY SRC USING
MLCLPCB SIGNAL AND POWER TRANSFORMERS ................................... 68
xii
7.1 SERIES RESONANT CONVERTER ................................................................. 68
7.2 MULTILAYERED CORELESS PCB HALF BRIDGE POWER TRANSFORMER ...... 69
7.3 SIMULATION AND EXPERIMENTAL RESULTS OF SERIES RESONANT
CONVERTER ............................................................................................................ 70
7.3.1 DC gain characteristics of SRC ......................................................... 71
7.3.2 Simulation results of SRC .................................................................. 72
7.3.3 Prototype of SRC ................................................................................ 73
7.3.4 Experimental evaluation of SRC ...................................................... 73
7.3.5 Loss estimation and thermal profile of SRC ................................... 74
8 HIGH FREQUENCY MULTIRESONANT CONVERTER USING
PLANAR TRANSFORMER ................................................................................... 76
8.1 CORE BASED PLANAR POWER TRANSFORMER........................................... 76
8.1.1 Structure of transformer .................................................................... 76
8.1.2 Selected core material and shape ..................................................... 77
8.1.3 Electrical parameters of novel hybrid core transformer ............... 77
8.1.4 Energy efficiency of transformer ...................................................... 77
8.2 MULTIRESONANT ZVS HALF BRIDGE CONVERTER .................................... 78
8.3 SIMULATION RESULTS OF MRC ................................................................ 80
8.3.1 Gate drive circuitry ............................................................................ 80
8.3.2 Synchronous rectification .................................................................. 81
8.3.3 Simulation waveforms of MRC ........................................................ 81
8.4 PROTOTYPE OF MRC ................................................................................. 82
8.4.1 Experimental results of MRC Unregulated converter ................ 82
8.4.2 Efficiency of regulated DC-DC converter: case (i) ......................... 85
8.4.3 Efficiency of AC/DC converter: case (ii) Laptop adapter ........... 86
9 HIGH FREQUENCY LLC RESONANT CONVERTER USING
PLANAR POWER TRANSFORMER ................................................................... 95
9.1 LLC RESONANT CONVERTER .................................................................... 96
9.2 DESIGN OF HIGH FREQUENCY LLC RESONANT CONVERTER ..................... 97
9.2.1 Converter specifications .................................................................... 97
9.2.2 DC gain characteristics of LLC resonant converter ....................... 97
9.2.3 Simulation results of LLC resonant converter ................................ 99
9.2.4 Experimental results of LLC resonant converter ......................... 101
10 HIGH FREQUENCY CLASS E ISOLATED DC-DC CONVERTER
USING HIGH PERFORMANCE PLANAR POWER TRANSFORMER ..... 103
10.1 DESIGN CONSIDERATIONS OF ISOLATED CLASS E DC-DC CONVERTER ... 104
10.2 SIMULATION RESULTS OF CLASS E ISOLATED DC-DC CONVERTER ......... 106
11 PAPERS SUMMARY AND AUTHORS CONTRIBUTION .......................... 109
xiii
11.1 PAPERS SUMMARY ................................................................................... 109
PAPER I ................................................................................................................. 109
PAPER II ................................................................................................................ 109
PAPER III .............................................................................................................. 109
PAPER IV .............................................................................................................. 110
PAPER V ................................................................................................................ 110
PAPER VI .............................................................................................................. 111
PAPER VII ............................................................................................................. 111
PAPER VIII ............................................................................................................ 111
PAPER IX............................................................................................................... 112
11.2 AUTHORS CONTRIBUTIONS..................................................................... 113
12 THESIS SUMMARY, CONCLUSIONS AND FUTURE WORK .................. 115
12.1 THESIS SUMMARY .................................................................................... 115
12.2 CONCLUSIONS ......................................................................................... 117
12.3 FUTURE WORK ......................................................................................... 118
13 REFERENCES ......................................................................................................... 119
PAPER I ............................................................................................................................ 131
PAPER II .......................................................................................................................... 141
PAPER III ......................................................................................................................... 147
PAPER IV ......................................................................................................................... 157
PAPER V .......................................................................................................................... 165
PAPER VI ......................................................................................................................... 180
PAPER VII ....................................................................................................................... 190
PAPER VIII ...................................................................................................................... 202
PAPER IX ......................................................................................................................... 212

xv
ABBREVIATIONS AND ACRONYMS
AC Alternating Current
AlAs Aluminium Arsenide
AlN Aluminium Nitride
AM Amplitude Modulation
BJT Bipolar Junction Transistor
CAD Computer Aided Design
CCM Continuous Conduction Mode
DC Direct Current
DSP Digital Signal Processing
DR Diode Rectification
DCM Discontinuous Conduction Mode
DVD Digital Versatile Disc
EMC Electro Magnetic Compatibility
EMI Electro Magnetic Interference
FEA Finite Element Analysis
FOM Figure of Merit
FM Frequency Modulation
FR4 Flame Retardant 4
GaAs Gallium Arsenide
GaN Gallium Nitride
HEMT High Electron Mobility Transistor
IC Integrated Circuit
ISM Industrial, Scientific and Medical radio bands
LGA Land Grid Array
LCD Liquid Crystal Display
LED Light Emitting Diode
MEEF Maximum Energy Efficiency Frequency
MHz Mega Hertz
MIF Maximum Impedance Frequency
MLCLPCB Multi Layered Core Less Printed Circuit Board
MOSFET Metal Oxide Semi conductor Field Effect Transistor
MRC Multi-Resonant Converter
PCB Printed Circuit Board
PoE Power over Ethernet
PRC Parallel Resonant Converter
PWM Pulse Width Modulation
PSM Pulse Skip Modulation
RF Radio Frequency
Si Silicon
SiC Silicon Carbide
xvi
SMPS Switch Mode Power Supplies
SOIC Small Outline Integrated Circuit
SOT Small Outline Transistor
SPICE
Simulation Program with Integrated Circuit
Emphasis
SPRC Series Parallel Resonant Converter
SR Synchronous Rectification
SRC Series Resonant Converter
WLAN Wireless Local Area Network
WQFN Very Very Thin Quad Flat No-lead Package
ZCS Zero Current Switching
ZVS Zero Voltage Switching

xvii
LIST OF FIGURES
Figure 1. Typical examples of high power density converter applications 2
Figure 2. Power density of converter as a function of frequency [11] 2
Figure 3. PhD thesis structure and its content 8
Figure 4. Switching Model of power MOSFET with the gate driver IC [37] 10
Figure 5. Circuit & switching waveforms during turn (a) on and (b) off
processes 12
Figure 6. Different MOSFET gate driver boards 15
Figure 7. Test circuit of MOSFET gate drivers 16
Figure 8. Measured gate drive power for Vin of (a) 5V and (b) 10V 16
Figure 9. Measured gate drive pulses of different MOSFET drivers 17
Figure 10. Calculated & measured drive power for Vin of 10V & CL of 150pF 18
Figure 11.Measured drive power for Vin of 10V & different load conditions 18
Figure 12. Schematic diagram of flyback DC-DC converter 20
Figure 13. Primary/secondary inductances in (a) DCM & (b) CCM 24
Figure 14. Structure of Coreless PCB step-down transformer 25
Figure 15. High frequency model of MLCLPCB transformer 26
Figure 16. Switching Losses of Hard Switched Converter [67] 27
Figure 17. Switching trajectory of power MOSFET [75] 31
Figure 18. Basic circuit of quasi resonant flyback converter 32
Figure 19. Waveforms of ZVS quasi resonant flyback converter [76] 32
Figure 20. Quasi resonant flyback converter using MLCLPCB transformer 34
Figure 21. Output characteristics of MOSFET (a) datasheet (b) simulations 36
Figure 22. Transfer characteristics of MOSFET (a) datasheet (b) simulations 36
Figure 23. Switching Waveforms of ZVS flyback converter 37
Figure 24. Primary/secondary voltages and currents of Coreless 37
Figure 25. Measured efficiency of hard & soft switched flyback converter 38
Figure 26. Calculated and measured voltage stress on MOSFET 38
Figure 27. (a) Energy efficiency (b) frequency of ZVS flyback converter 39
Figure 28. Energy efficiency as a function of load current 39
Figure 29. Waveforms of flyback converter a) RL=15 & b) RL=50 40
Figure 30. Thermal profile of (a) transformer & (b) flyback converter 40
Figure 31. Theoretical limits of Rds_on versus breakdown voltage [91] 44
Figure 32. Packaging of 200V Si (DPAK) left and GaN (LGA) right, 45
Figure 33. Energy efficiency of unregulated converter with GaN and Si
devices 47
Figure 34. Efficiency of regulated converter for a) line and b) load variations 48
Figure 35. Measured waveforms of converter with RL=60 at 5MHz 48
Figure 36.Bar graph representation of losses due to GaN and Si devices 50
Figure 37. Schematic diagram of cascode flyback DC-DC converter 52
Figure 38. Gate and drain voltages of the switches in cascode converter 53
xviii
Figure 39. (a) 3D view and (b) prototype of 8:1 coreless PCB transformer of
(37x37x1.48)mm 54
Figure 40. Simulated waveforms of cascode converter, case (i) 56
Figure 41. Measured waveforms of cascode converter with RL=10 56
Figure 42. Simulated (Solid) and Measured (Symbol) efficiency of 57
Figure 43. Loss estimation of cascode converter Case (i) 60
Figure 44. Thermal profile of cascode converterCase (i) 60
Figure 45. High side gate drive circuitry using MLCLPCB transformer 63
Figure 46. Drive signals of high side MOSFET for (a) 20% & (b) 45% of duty
cycle at 2MHz 64
Figure 47. Drive signals of high side MOSFET for (a) 20% & (b) 45% duty cycle
at 4MHz 64
Figure 48. (a) Simulated and (b) measured drive signals of low side and high
side MOSFETs in SRC 65
Figure 49. Block diagram for measurement of gate drive power consumption
66
Figure 50. Gate drive power consumption in Series Resonant Converter (SRC)
66
Figure 51. (a) Schematic diagram and (b) DC gain characteristics of SRC [8] 69
Figure 52. Schematic diagram of SRC with high frequency model of power
transformer 70
Figure 53. Calculated DC gain characteristics of SRC 71
Figure 54. Simulated waveforms of SRC at 2.6MHz 72
Figure 55. Prototype of SRC with MLCLPCB signal and power transformers 73
Figure 56. Measured switching waveforms of SRC at 2.6MHz 73
Figure 57. Measured energy efficiency of (a) unregulated and (b) regulated
SRC 74
Figure 58. (a) Loss estimation and (b) thermal profile of SRC at nominal input
voltage of 90V 75
Figure 59. 3D view of the planar power transformer 76
Figure 60. (a) Top and (b) bottom view of the planar power transformer 77
Figure 61. Measured transformer energy efficiency for different load
conditions [114] 78
Figure 62. Schematic diagram of multiresonant half bridge converter [119] 79
Figure 63. Schematic diagram of multiresonant half bridge converter 81
Figure 64. (a) Gate, drain signals of switching devices and (b) switching
waveforms of MRC at 120Vdc 82
Figure 65. Prototype of MRC with high frequency planar power transformer &
GaN HEMTs 83
Figure 66. (a) Measured gate signals and (b) energy efficiency of unregulated
MRC 83
Figure 67. Loss estimation of MRC at an input voltage of 120Vdc 85
xix
Figure 68. Measured efficiency of MRC as a function of (a) line & (b) load
variations 85
Figure 69. Different approaches of laptop adapter a) single stage approach and
b) two stage approach 86
Figure 70. Measured energy efficiency of regulated MRC using SR and DR 88
Figure 71. Simulation waveforms of MRC for RL=9.3 and fsw=3.19MHz at
Vin
nom
=120Vdc 89
Figure 72. Measured waveforms of MRC for RL=9.3 and fsw=3.19MHz at
Vin
nom
=120Vdc 90
Figure 73. Thermal profile of converter at load power of 40W 90
Figure 74. Measured and simulated energy efficiency of MRC 91
Figure 75. Measured output voltage of MRC for load variation of 10 100% 91
Figure 76. Required no. of pulses as a function of load resistance 93
Figure 77. Simulated waveforms of MRC for 10% load condition 93
Figure 78. Measured efficiency of MRC as a function of line variation 94
Figure 79. Schematic diagram of LLC resonant converter [128] 96
Figure 80. DC gain characteristics of LLC resonant converter 98
Figure 81. Schematic diagram of LLC resonant converter 99
Figure 82. Simulation waveforms of LLC resonant converter at 127Vdc and
RL=9.5 100
Figure 83. Comparison of designed prototype w.r.t existing laptop adapter 101
Figure 84. (a) Simulated/Measured efficiency and (b) measured waveforms of
LLC resonant converter at 127Vdc and RL=9.5 102
Figure 85. Measured efficiency of LLC converter for (a) 90Vac, 127Vdc and for
(b) line variations 102
Figure 86. Schematic diagram of Class E resonant isolated DC-DC converter
103
Figure 87. Schematic diagram of isolated class E DC-DC converter using
planar transformer 106
Figure 88. Simulated waveforms of class E DC-DC converter at 60Vdc and
RL=14.06 107
Figure 89. Simulated waveforms of class E DC-DC converter at 60Vdc and
RL=42 108
xx

xxi
LIST OF TABLES
Table 1. Comparison of different MOSFET driver parameters .......................... 15
Table 2. Comparison of different parameters in DCM and CCM at 3MHz ..... 25
Table 3. Geometrical parameters of transformer ................................................. 26
Table 4. Electrical parameters of the transformer ................................................ 27
Table 5. Required simulation SPICE parameters of MOSFET ............................ 36
Table 6. Electrical and Material properties of Si, SiC and GaN ......................... 43
Table 7. Measured values of converter with GaN/Si device at 45V .................. 49
Table 8. Parameters of devices in cascode & traditional flyback converter ..... 55
Table 9. Electrical parameters of transformer at 1MHz ...................................... 70
Table 10. Electrical parameters of transformer at 3MHz .................................... 77
Table 11. Electrical parameters of transformer at 5MHz .................................. 106
Table 12. Authors Contributions ......................................................................... 113

xxii
LIST OF PAPERS
This thesis is mainly based on the following publications, herein
referred to by their Roman numerals:

Paper I

A ZVS Flyback DC-DC Converter Using Multilayered Coreless
Printed Circuit Board (PCB) Step-down Power Transformer
Hari Babu Kotte, Radhika Ambatipudi and Kent Bertilsson
Proceedings of World Academy of Science, Engineering and
Technology, Paris, France, Issue 70, October 2010, ISSN: 1307-6892,
pp. 148-155.

Paper II Comparative Results of GaN And Si MOSFET in a ZVS
Flyback Converter Using Multilayered Coreless Printed Circuit
Board Step-Down Transformer
Proceedings of 2010 3
rd
The International Conference on Power
Electronics and Intelligent Transportation system (PEITS 2010),
November 20-21, 2010, Shenzhen, China, Vol. IV, pp. 318- 321, ISBN
978-1-4244-9162-9.

Paper III High Speed Cascode Flyback Converter Using Multilayered
Coreless Printed Circuit Board (PCB) Step-Down Power
Transformer
Proceedings of 8
th
International Conference on Power Electronics, ICPE
2011 - ECCE Asia, May 30- June 3, 2011, The Shilla Hotel, and Jeju,
Korea, pp.1856-1862.

Paper IV High Frequency Half-Bridge Converter using Multilayered
Coreless Printed Circuit Board Step-Down Power Transformer
Abdul Majid, Hari Babu Kotte, Stefan Haller, Radhika
Ambatipudi, Jawad Saleem and Kent Bertilsson
Proceedings of 8
th
international Conference on Power Electronics, ICPE
2011 - ECCE Asia, The Shilla Hotel, and Jeju, Korea, May 30- June 3,
2011, pp.1177-1181.

Paper V High Speed (MHz) Series Resonant Converter (SRC) Using
Multilayered Coreless Printed Circuit Board (PCB) Step-Down
Power Transformer
Power Electronics, IEEE Transactions on, vol.28, no.3, pp.1253-1264,
xxiii
March 2013.

Paper VI A ZVS Half Bridge DC-DC Converter in MHz Frequency
Region Using Novel Hybrid Power Transformer
Hari Babu Kotte, Radhika Ambatipudi, Stefan Haller and Kent
Bertilsson
Proceedings of International Conference on Power Electronics and
Intelligent Motion (PCIM Europe 2012), Nuremberg, Germany, 08 -
10 May 2012, pp.399-406 (Winner of the YOUNG ENGINEER
AWARD sponsored by ECPE, Infineon Technologies and
Mitsubishi Electric)

Paper VII Design and Analysis of 45W Multi Resonant Half Bridge
Converter in MHz Frequency Region using GaN HEMTs
Submitted for publication in Journal of Power Electronics (JPE), Korea
(Under revision)

Paper VIII A 45W LLC Resonant Converter in MHz Frequency Region for
Laptop Adapter Application Using GaN HEMTs
Proceedings of International Conference on Power Electronics and
Intelligent Motion (PCIM Europe 2013), Nuremberg, Germany, 14-16
May 2013, pp.1029-1035.

Paper IX High Performance Planar Power Transformer with High Power
Density in MHz Frequency for Next Generation Switch Mode
Power Supplies
Radhika Ambatipudi, Hari Babu Kotte and Kent Bertilsson
Proceedings of 28
th
Annual IEEE Applied Power Electronics
Conference & Exposition, APEC 2013, Long Beach, California, USA,
March 17 21, 2013, pp.2139-2143.

Related papers not included in thesis

Paper 1 High Speed Series Resonant Converter (SRC) using
Multilayered Coreless Printed Circuit Board (PCB) Step-Down
Power Transformer
Proceedings of IEEE 33
rd
International Telecommunications Energy
Conference, Amsterdam, The Netherlands, 9-13 October 2011.

xxiv
Paper 2 Coreless Printed Circuit Board (PCB) Step-down Transformers
for DC-DC Converter Applications
Radhika Ambatipudi, Hari Babu Kotte, and Kent Bertilsson
Proceedings of World Academy of Science Engineering and Technology
(WASET), Paris, France, October 2010, Issue. 46, pp. 379-388,
ISSN 1307-6892.

Paper 3 Comparison of Two Layered and Three Layered Coreless
Printed Circuit Board (PCB) Step-down Transformers
Radhika Ambatipudi, Hari Babu Kotte, Kent Bertilsson
rd
International Conference on Power Electronics
and Intelligent Transportation System, Shenzhen, China, November
2010, Vol. IV, pp. 314 317, ISBN 978-1-4244-9162-9.

Paper 4

Paper 5

Radiated Emissions of Multilayered Coreless Printed Circuit
Board Step-Down Power Transformers in Switch Mode Power
Supplies
Proceedings of 8
th
international Conference on Power Electronics, ICPE
2011 - ECCE Asia, The Shilla Hotel, and Jeju, South Korea, May 30-
June 3, 2011, pp.960 -965.

Effect of Dielectric Material on the Performance of Planar
Power Transformers in MHz Frequency Region
Proceedings of INDUCTICA 2012 Coil Winding, Insulation and
Electrical Manufacturing International Conference and Exhibition
(CWIEME), Berlin, Germany 26 28, June 2012.

Paper 6 Effect of Air Gap on the Performance of Hybrid Planar Power
Transformer in High Frequency (MHz) Switch Mode Power
Supplies (SMPS)
Radhika Ambatipudi, Hari Babu Kotte, and Kent Bertilsson
Proceedings of INDUCTICA 2012, Coil Winding, Insulation and
Electrical Manufacturing International Conference and Exhibition
(CWIEME), Berlin, Germany 26 28, June 2012.

Paper 7 Design and Implementation of EMI Filter for High Frequency
(MHz) Power Converters
Abdul Majid, Jawad Saleem, Hari Babu Kotte, Radhika
Ambatipudi, and Kent Bertilsson
Proceedings of International Symposium on Electromagnetic
xxv
Compatibility (EMC Europe 2012), Rome, Italy, September 17 - 21,
2012.

Paper 8 Analysis of Feedback in Converter using Coreless Printed
Circuit Board Transformer
Abdul Majid, Jawad Saleem, Hari Babu Kotte, Radhika
Ambatipudi, Stefan Haller and Kent Bertilsson
Proceedings of International Aegean Conference on Electrical Machines
and Power Electronics & Electromotion Joint Conference (ACEMP),
Istanbul, Turkey, September 8 - 10, 2011, pp.601-604.

Paper 9 High Frequency Full Bridge Converter Using Multilayer
Coreless Printed Circuit Board Step Up Power Transformer
Jawad Saleem, Abdul Majid, Radhika Ambatipudi, Hari Babu
Kotte and Kent Bertilsson
th
European Conference on Circuit Theory and
Design (ECCTD), Linkping, Sweden, August 29 - 31, 2011 pp.805-
808.

Paper 10 Energy Efficient Multi Resonant Half Bridge Converter in
MHz Frequency Region Using Novel Hybrid Planar Power
Transformer and GaN HEMTs
Submitted for Publication in Journal of Electrical Engineering and
Technology, South Korea.

Paper 11 Analysis of Solid and Parallel Winding Structures in MHz
Planar Transformers Suitable for Switch Mode Power Supplies
Submitted for Publication in Journal of Electrical Engineering and
Technology, South Korea.

xxvi
1
1 INTRODUCTION
In recent years, energy efficiency and power density has become a major concern
for every power electronics researcher/engineer as the demand for compact power
supplies has grown significantly [1] - [4]. However, no single solution exists in
relation to meet both the challenges of the converter, such as high energy
efficiency, and high power density. For example, providing a solution to one task
increases the degree of complexity in other challenges and vice versa. The energy
efficiency of the converter can be maintained at a high level by retaining a lower
switching frequency, by employing soft switching techniques and novel circuit
topologies [5] with regards to the converter. However, by maintaining this lower
switching frequency for the converters, the other crucial factor of high power
density cannot be achieved. Therefore, the researchers and engineers are striving
hard to achieve an optimal solution which will meet both the technical
requirements of todays modern switch mode power supplies (SMPS).

1.1 IMPORTANCE OF INCREASING SWITCHING FREQUENCY
With the development of information technology, 1) the computing system
applications such as telecom, server and computers, 2) consumer electronics such
as flat panel TVs, laptop/note book adapters, iPad chargers 3) lighting systems
such as LED drivers etc., are gaining prominence in todays power supply
industry. In addition to this, due to the advancements in the integrated circuit (IC)
technology, according to Moores law, there is a high demand for the slim and
portable electronic appliances, which signify the low profile, low power, high
power density converters [2], [6] & [7]. Some of the applications requiring high
power density converters in todays world are illustrated in fig. 1. In order to
obtain this low profile, high power density converters, the requirement is to reduce
the size of the passive elements and the heat sink requirement as these elements
occupy the majority of the volume, approximately 80%, in relation to the power
supply [8]. By increasing the switching frequency of the converter, a huge
reduction in the size of passive elements such as magnetics (transformers,
inductors) and capacitors can be obtained as there is less requirement for the
energy storage per single switching cycle, thereby the size and cost of the converter
gets reduced [9], [10]. This enables the miniaturization of the passive components
and hence making it to realize the highly integrated converters [7]. The relation
between the output power density and the switching frequency of converter is
depicted in fig.2 [11]. From this figure, it can be observed that the power density
improvement of the converter is proportional to the switching frequency. Apart
from these advantages, by increasing the switching frequency of converters, the
fast dynamic response can be achieved to the rapid changes in line/load variations
[12]. By maintaining a high energy efficiency of the converter, the size of the heat
2
sink requirement can be reduced. However, the commercially available isolated
DC/DC and AC/DC converters are operated at or below 1MHz [11], [13] due to
several issues, which will be discussed in the coming section.

Figure 1. Typical examples of high power density converter applications

Figure 2. Power density of converter as a function of frequency [11]
Smart Phones
iPads
DVD players
LED Drivers
Applications of
High power density
converters
LED/LCD Monitors
Ultra book
3
1.2 CHALLENGES DUE TO HIGHER SWITCHING FREQUENCIES
In the previous section, the benefits of operating the converter at higher switching
frequencies have been discussed. However, by doing so, several challenges exist in
terms of magnetics, switching devices and from the electromagnetic interference
(EMI) point of view. By increasing the switching frequency of the converter, the
core and copper losses in the transformer/inductor are increased due to the skin
and proximity effects induced by the eddy currents [14] - [16], and thus the overall
energy efficiency of the converter gets degraded. Even though the core materials
are available at higher operating frequencies, up to the few MHz frequency region,
a proper winding structure of the transformer is required in order to reduce the
skin and proximity effects at higher frequencies.

From the switching devices point of view, when the frequency of the converter is
increased, the switching losses and gate drive power consumption increases
linearly, which results in the degradation of the converter efficiency [7], [10]. In
addition to this, losses associated with the reverse recovery of the secondary side
diode rectifiers do exist. Due to these losses in the devices, the reliability of the
device/converter gets degraded resulting in high demands on the thermal
management and the cooling requirement [17].

From the topological point of view, hard switched pulse width modulation (PWM)
converters suffer several drawbacks such as turn on and turn off losses, capacitive
discharge loss when the switching frequency of converter [10], [12] is increased.
Other than these issues, EMI noise caused by parasitic elements then becomes a
hurdle with regards to increasing the switching frequency of the converter. Apart
from this, restrictions in selecting the switching frequency of converter exist
because the electromagnetic noise produced by the fundamental switching
frequency and the corresponding harmonic frequencies may interfere with that of
the other electronic devices in its vicinity. For example, AM radio receivers suffer
from interference if the switching frequency of the converter falls within the range
of 530 - 1710 kHz [13], [18]. Therefore, a switching frequency of the converter,
which exceeds the upper limit of the AM radio receiver frequency range, is
beneficial so that it eliminates the interference from these signals. Due to the
restrictions on the conducted EMI, the majority of the AC/DC converters also
operate well below 150 kHz [19].

1.3 THESIS BACKGROUND AND MOTIVATION
In order to overcome the aforementioned challenges with regards to designing
high switching frequency isolated converters with a high energy efficiency and
high power density, a great deal of research is progressing in a variety of directions
and this will be discussed in this section.
4
Dealing with the magnetics, as the core losses increase due to the increased
switching frequency of the converters, in 90s, the research was focused on the
coreless type of transformers [20] - [22] in order to completely eliminate the core
losses and to avoid the high frequency limitation as in the case of core based
counterparts. Some of the earlier related research work [22], [23] shows that these
transformers can be useful for both signal and power transfer applications with the
help of the resonant technique. Apart from this, due to the availability of better
magnetic materials in the market up to few MHz (1 - 10MHz) [24], [25], the
research is also progressing on core based planar magnetics [14], [26] and [27].

In relation to the semiconductor devices, switching devices such as CoolMOS
TM
,
Schottky diode rectifiers are introduced in order to reduce the switching losses of
the devices [28]. Apart from these, new material devices such as gallium nitride
(GaN) and silicon carbide (SiC) devices have recently been introduced into the
market due to the theoretical limitations of the Si technology [29], [30].

In terms of the topological point of view, since the hard switching converters limit
the operating frequency due to high switching losses, resonant converter
topologies such as quasi resonant [31], [32] and multiresonant converters [33], [34]
are gaining importance in order to increase the switching frequency of the
converters. In these topologies, the switches are usually operated either in a zero
voltage switching (ZVS) condition or a zero current switching (ZCS) condition in
order to limit the stress on the devices and switching losses in the converter.
In addition to these improvements, due to the advanced packaging techniques
such as the integration of a capacitor into the magnetics, an output inductor into
the isolation transformer of the converter and additionally, integrating the required
leakage inductance in the resonant converters into the designed transformer [35],
the size of the converters can be drastically reduced and can provide the possibility
of increased energy efficiencies.

Based on these recent advancements, the research was focussed on two different
aspects. The first part of the thesis is to design highly energy efficient and high
frequency low power DC/DC converters using coreless PCB step-down power
transformers by employing the resonant converter topologies. In addition to this,
the research was also focussed on to evaluate the performance of latest
semiconductor device i.e., GaN HEMTs in MHz frequency region compared to its
counterpart Si device.

In the second part of the thesis, the focus of the research is to design and evaluate
high frequency DC/DC and AC/DC converters using the novel planar power
transformers and latest GaN technology in order to achieve the goal of energy
efficient, low profile, low power converters.
5

1.4 THESIS OBJECTIVE AND METHOD
The objective of this thesis is to investigate the possibility of obtaining an isolated
high frequency (1 - 5MHz) low profile converter, with high energy efficiency and
high power density by using either coreless PCB transformer technology or novel
core based planar transformers, developed in Mid Sweden University, suitable for
consumer applications in the range of 1 60W.
In this process, several aspects related to high frequency converter circuits are
considered as intermediate goals of the thesis in order to achieve the primary
objective of obtaining energy efficient isolated converters operating in the 1
5MHz frequency region.

Determination of the low gate drive power consumption MOSFET gate
drivers possessing low rise and fall times suitable for high speed switching
converters.

Evaluation of the newly arrived semi conductor switching devices such as
GaN HEMT in converter circuits and comparing its performance with that
of the existing Si MOSFETs

Evaluation of both the transformer based and optocoupler based gate
drive circuitry required for driving high side switching devices in double
ended topologies such as half bridge and series resonant converters.

Building up of various single ended and double ended quasi resonant and
multi-resonant converters for the considered power applications and
evaluating their performance in the MHz frequency region using high
frequency coreless and core based transformers.

Investigating the possibility of obtaining a high frequency, high power
density DC/DC and AC/DC converters suitable for various consumer
applications by using the state-of-the- art switching devices and planar
transformer technology

In order to achieve these goals, it is necessary to build a proper high frequency
model of the converter by considering addition to various elements of the
converter circuit, since the parasitic elements play an important role at these high
frequency levels. For modelling various high frequency converters, the simulation
software SIMetrix is considered as a primary tool prior to the construction of the
prototypes. After the successful evaluation of these converters using the simulation
tool, the prototypes were developed using PADS/CADint PCB design softwares
6
and evaluated in a high frequency region. During this process, several new design
guidelines were proposed in relation to achieving the goals of obtaining flat profile
energy efficient DC/DC and AC/DC converters.

1.5 THESIS OUTLINE
The thesis is organized in chapter wise as follows:

Chapter 1: This chapter gives a brief introduction to the importance of high speed
SMPS in modern days. In addition to this, the corresponding research background,
the motivation, method employed and the outline of the thesis along with the
thesis structure and its content are presented.

Chapter 2: In chapter 2, different commercially available MOSFET gate drivers
were evaluated and based upon their performance, a suitable high frequency gate
driver is proposed.

Chapter 3: This chapter discusses the performance of a multilayered coreless PCB
power transformer in a quasi resonant ZVS flyback converter operated in the MHz
frequency region with the necessary theory related to the transformer and
converter design.

Chapter 4: A new type of semiconductor material i.e., GaN HEMT is compared
with the traditional Si MOSFET in a ZVS quasi resonant flyback converter operated
in the MHz frequency region. The benefits of using the GaN HEMT compared to
the Si MOSFET in terms of their performance parameters are discussed in detail.

Chapter 5: This chapter focuses on the design and analysis of a high speed cascode
flyback converter using the combination of low voltage GaN HEMT and the high
voltage Si MOSFET. In addition to this, the performance of the converter is
compared to the traditional single switch flyback converter in the MHz frequency
region in terms of various factors such as gate drive power consumption, switching
frequency, energy efficiency etc.,

Chapter 6: This chapter introduces the high speed gate drive circuitry in order to
drive the high side MOSFET with the assistance of a multilayered coreless PCB
signal transformer in double ended topologies such as half bridge converter and
series resonant converter.

Chapter 7: The design, implementation and analysis of a high speed series
resonant converter using a novel multilayered coreless PCB power transformer in
MHz frequency region are presented.
7

Chapter 8: In this chapter, the design and implementation of one of the series
parallel resonant converters i.e., an LCC resonant converter in the MHz frequency
region using a novel hybrid core planar power transformer is covered.

Chapter 9: The characteristics of the LLC resonant converter and its practical
implementation in the MHz frequency region using a high frequency integrated
planar power transformer for laptop adapter application are discussed.

Chapter 10: This chapter presents the simulated results of a high frequency class E
isolated DC-DC converter using the high performance planar power transformer
designed at Mid Sweden University.

Chapter 11: Summary of publications and authors contribution.

Chapter 12: Thesis summary, conclusions and future work.

Chapter 13: References.

8
(Chapter 3)
Implementation of Quasi
resonant flyback converter
using Si MOSFET
(Chapter 1)
Introduction and Motivation
GOAL: Design of high frequency
(1 5MHz), energy efficient, low power converters
using novel planar magnetics and GaN HEMTs
(Chapter 2)
Evaluation of different MOSFET gate
drivers in 1 5 MHz frequency region
for GaN HEMTs and Si MOSFETs
Design of High frequency
converters using MIUN Core
based Technology
See Fig.3 (b)
Paper I
Paper V
Design of High Frequency
converters using MIUN
Coreless PCB Transformer
Technology
(Chapter 4)Performance
comparison of Si MOSFETs
w.r.t GaN HEMTs in MHz
frequency region
(Chapter 5)
Cascode converter using LV
GaN HEMT and Si MOSFETs
(Chapter 6&7)
Implementation of double
ended converter topologies
(Half bridge and SRC)
Paper II
Paper III
Paper IV

Figure 3(a). PhD thesis structure and its content
9
Design of High frequency
converters using MIUN Core
based Technology
Paper VII
(Chapter 8)
Implementation of LCC
resonant converter using
GaN HEMTs in MHz

(Chapter 9)
Implementation of LLC
GaN HEMTs in MHz
Frequency
(Chapter 10)
Implementation of Class E
GaN HEMT in MHz frequency
(Chapter 10)
Paper VIII
Paper VI
Paper IX

Figure 3(b). PhD thesis structure and its content (contd.)

10
2 MOSFET GATE DRIVERS FOR HIGH SPEED SMPS
A MOSFET gate driver is necessary whenever the controller circuit itself is unable
to drive the power MOSFET directly due to its low current capability [36]. A power
MOSFET gate driver is a power amplifier, which takes the signal from the
controller circuit and amplifies it in order to drive the switching power MOSFETs.
By maintaining an individual controller and driver circuits, it is possible to ensure
that the controller runs under both cooler and stable conditions even though high
peak currents flow in the driver circuit, while driving the power MOSFETs. This
feature becomes attractive as the switching frequency of the converter gets
increased. The drivers can be classified as either discretized, using bipolar devices
such as NPN and PNP emitter follower circuits, or, as a single IC driver, which
uses logic gates. However, the use of an IC gate driver has several advantages in
comparison to using one which is discretized in terms of space [37], propagation
delay, reduced noise and voltage drops across the trace between the gate and the
MOSFET gate driver, among others. The gate drive power consumption, the rise
and fall times of the gate signal plays an important role in the energy efficiency of
the converter, particularly for high speed SMPS. Therefore, in this chapter,
different commercially available MOSFET gate drivers performance in the high
frequency region have been evaluated.

2.1 SWITCHING MODEL OF POWER MOSFET
The simplified switching model of a power MOSFET including a gate driver IC is
shown in fig. 4. This figure illustrates the MOSFET model consisting of the
parasitic elements such as the gate-source, drain-source and gate-drain/miller
capacitances, which all have a significant influence on the switching behaviour in
terms of switching transients.

Figure 4. Switching Model of power MOSFET with the gate driver IC [37]
Rext
11
Here, Ld and Ls are the parasitic inductances corresponding to the MOSFETs
whereas Rg/Rext are the internal/external resistances which have a significant
impact on the switching times and the MOSFETs dv/dt immunity [37]. The
switching speed of the MOSFET is mainly determined by the Miller effect, which is
produced by the gate-drain capacitance Cgd. This capacitance is highly non-linear
in nature with respect to both the gate-source and the drain voltages.

In general, the current required to drive the MOSFET during the turn-on and turn-
off times is high due to the gate/input capacitance of the MOSFET, which includes
the gate-source Cgs and the gate-drain Cgd capacitances.

2.2 SWITCHING BEHAVIOUR OF POWER MOSFET
In high frequency SMPS, it is important to make the correct selection of the
components and gate drive circuitry as these play prominent roles. Therefore, it is
necessary to have a sound knowledge regarding the switching behaviour of the
power MOSFETs in order to select the correct MOSFET gate driver and its
components. Hence, a brief description of the turn-on and turn-off procedure of
the power MOSFETs is discussed in this section.

2.2.1 Turn-on and Turn-off procedure in power MOSFET
The idealized switching behaviour of the MOSFET under turn-on and turn-off
conditions [38] including the current flow in the circuits is illustrated in fig. 5 (a)
and fig. 5 (b) respectively. Fig. 5 (a) and (b) shows the gate-source voltage Vgs, gate
current Ig, drain-source voltage Vds and drain current Id of a power MOSFET
during turn-on and turn-off conditions. The switching behaviour can be explained
during the turn-on process in its different modes [38] as follows.

Mode 1 (0<Vgs<Vth): In this mode of operation, the input capacitance Cgs+Cgd
becomes charged from 0 to the gate threshold voltage Vth. The majority of the gate
current flows into the gate-source capacitance as compared to the gate-drain
capacitance. As the gate voltage fed to the MOSFET is increasing in nature, the
potential of the gate terminal of the MOSFET increases, which, in turn, reduces the
voltage across the gate-drain capacitance of the MOSFET. From fig. 5 (a), it can be
observed that, in this mode the drain-source voltage Vds and drain current Id
remain unchanged and this represents the fact that the switch is not turned-on.
This period is known as the turn on delay time of the MOSFET.

Mode 2 (Vth Vgs <Vgs_miller): When the gate-source voltage Vgs reaches its gate-
threshold voltage Vth, the MOSFET gets ready to carry the drain current. In this
mode, the current starts to increase in a linear proportional manner to the gate
voltage Vgs until it reaches the Miller plateau region i.e., Vgs_miller. In this mode
12
also, the gate current flows into the input capacitance (Cgs+Cgd) as in the previous
case. Unless and until all the current is transferred into the MOSFET and the
complete turnoff of the body diode, the drain-source voltage, Vds remains
constant, which can be observed from fig. 5 (a).

(a) (b)
Figure 5. Circuit & switching waveforms during turn (a) on and (b) off processes

Mode 3 (Vgs=Vgs_miller): Once the channel is fully opened, the drain current is
completely transferred into the MOSFET and the body diode gets fully turned off,
then the drain-source voltage Vds across the MOSFET starts to fall. During this
period, the gate-source voltage remains constant as it cannot increase until the
input capacitance (Cgd+Cgs) gets fully charged [39]. This is known as the Miller
plateau region of the gate voltage [40]. During this mode, in order to bring the
rapid voltage change across the drain-source terminal, the entire available gate
current gets diverted for discharging the capacitor Cgd. Providing sufficient gate
drive to traverse the Miller plateau region of power MOSFET at a faster rate is the
main characteristic of the MOSFET gate driver. In this mode, the drain current is
maintained at a constant rate, whose magnitude is mainly determined by the load
conditions.
Mode 4 (Vgs_miller < Vgs Vgsopt): In this mode of operation, the gate-source voltage,
Vgs is further increased in order to fully enhance the MOSFET.
Vgsopt=VDRV
13
Additionally, in order to maintain a low on-state resistance of the MOSFET, it is
further increased to its optimal gate-source voltage Vgsopt, thereby reducing the
conduction losses of the power MOSFET. In this mode, the gate-source and gate-
drain capacitances become charged by maintaining the constant drain current with
the decreased drain-source voltage, Vds.

Similarly, the turn-off procedure of MOSFET [38] which is a reverse process
compared to turn-on procedure can be explained in different modes of operation
with the assistance of fig. 5 (b).

Mode 1 (Vgsopt
Vgs >Vgs_miller): During this mode of operation, the input capacitance

Cgs+Cgd gets discharged from its initial value to the miller plateau value which is
also considered as turn-off delay of the MOSFET. Here, the gate current is supplied
by the input capacitance and hence flows through the capacitors Cgs and Cgd. As
the gate voltage gets decreasing in nature, the drain voltage starts to increase
slightly whereas the drain current remains constant throughout this period as
shown in fig. 5 (b).

Mode 2 (Vgs= Vgs_miller): In this miller plateau region, the gate-source voltage remains
constant as in the mode 2 operation of the turn-on procedure of the MOSFET.
However, in this case, due to the constant gate voltage, the gate current is the
charging current of the miller capacitance i.e., Cgd. Here, the drain source voltage
Vds starts to increase from its on-state voltage drop to its final blocking voltage
whereas the drain current remains constant which is determined by the load
current.

Mode 3 (Vgs_miller >Vgs
Vth): In this mode of operation, the gate source voltage starts

to decrease from its miller value to the gate threshold voltage. As the miller
capacitance is fully charged in the earlier mode of operation, the majority of the
gate current represents the current coming from the gate source capacitance, Cgs.
Since, the gate-source voltage is decreasing in nature, the drain current starts to
decrease to zero level as shown in fig. 5 (b) whereas the drain-source voltage
remains at its off state voltage.

Mode 4 (Vth>Vgs>0): In this mode of operation, the gate source voltage is further
reduced from its threshold voltage to zero value. Here, the input capacitance of the
device gets fully discharged by the majority of the current supplied from the gate
source capacitance Cgs. In this mode, the drain current and drain source voltage
remains unchanged.
From the procedure explained for the turn-on and turn-off processes, it can be
concluded that in all these different modes of operation the parasitic elements play
14
an important role. Therefore, it is necessary to determine the correct devices and
gate drive circuitry for high speed SMPS, as discussed in the beginning of this
section.

2.3 GATE DRIVE POWER CONSUMPTION
As discussed in the earlier section, whenever the MOSFET is fed with the gate
voltage Vg, the input capacitance of MOSFET gets charged during turn-on, while
it gets discharged during turn-off condition. During this process, some inevitable
losses exist in the MOSFET gate driver, which cannot be directly obtained by the
input capacitance of the MOSFET due to its non-linear behavior [41] with respect
to the gate and drain voltages. Therefore, in order to determine the gate drive
power consumption, the total gate charge specified at a particular gate voltage and
drain voltage of the MOSFET in the gate drive characteristics of power MOSFET
datasheet, is considered. The power dissipated in the gate driver due to the total
gate charge is given [42], [43] as follows.

sw g g gate
f Q V P = (1)
where,
Qg total gate charge at specified Vgs and Vds
Vg gate voltage
fsw switching frequency

Apart from the above major loss contribution in the MOSFET gate driver, other
losses exist, which are known as the quiescent power loss and transient power loss.
Quiescent power loss Pquiescent is the power dissipation in the MOSFET gate driver
due to the quiescent current consumed by the driver input stage and this power
can be obtained [43] from the following equation.

( ) ( ) D I D I V P
CCH CCL g quiescent
+ = 1 (2)
where,
ICCL supply current with low state drive output
ICCH supply current with high state drive output
D duty cycle of the driver output

The transient power loss Ptransient in the driver circuit [43] is obtained when the
driver output changes its state from the ON state to the OFF state and vice versa
and it can be calculated as follows.

( ) ( )
4
10 8 08 . 1 + =
sw gd gs g g transient
f C C V V P (3)
However, since the losses corresponding to the quiescent power Pquiescent and the
transient power Ptransient are negligible compared to the loss associated with the
15
charging and discharging of the gate capacitance i.e., Pgate and hence these losses
can be ignored.

2.4 COMPARISON OF DIFFERENT DRIVERS FOR HIGH SPEED SMPS
Based on the above analysis, four different gate drivers from different
manufactures have been tested in order to check the performance characteristics
such as the rise/fall times and the gate drive power consumption of these drivers in
high frequency switching power supplies. Even though the details of the rise/fall
times, propagation delays, gate drive power consumption do all exist in their
corresponding datasheets, it is difficult to compare different manufacturers
drivers because these details correspond to specific test conditions.
Some of the details corresponding to these MOSFET drivers available in datasheets
including the manufacturer details are listed in table 1.
Table 1. Comparison of different MOSFET driver parameters
Drivers Vin (V) Trise/Tfall(ns) Td1/Td2(ns) Manufacturer
LM5111 3.5-14 14/12@2nF 25/25@2nF Texas Instruments
EL7222 4.5-15 10/13@1nF 18/20@1nF Intersil
TC4451 4.5-18 30/32@15nF 44/44@15nF Microchip
FAN3111 4.5-18 9/8@470pF 15/15@470pF Fairchild Semiconductor
*Here, Td1/Td2 corresponds to turn-on and turn-off propagation delay times.
The drivers LM5111, EL7222 and TC4451, which are considered, are of 8-pin SOIC
package whereas the FAN3111, also being considered, is of 5-pin SOT23 as
illustrated in fig. 6.

Figure 6. Different MOSFET gate driver boards
For the typical low power DC-DC converters, the total gate charge Qg of the
MOSFET is in the range of 1.5 50nC and with the gate voltage Vg in the range of
4.5 12V. Since the MOSFET is considered as a capacitive load, a capacitor of
150pF is considered as the load capacitance and estimation is made in relation to
the gate drive power consumption of all the above listed MOSFET drivers within
the switching frequency range of 1 - 5MHz.
The circuit diagram for testing MOSFET gate drivers is illustrated in fig. 7.
LM5111
TC4451
EL7222
FAN3111
16

The measured power consumption for two different input voltages of 5V
(considering GaN HEMTs) and 10V (Si devices) are illustrated in figs.8 (a) and (b)
respectively. From these figures, it can be observed that there is a significant
difference in the gate drive power requirement among different gate drivers and
the highest gate drive power consumption is observed to be for TC4451 followed
by the FAN3111 and EL7222 drivers. The power consumed by the MOSFET driver
LM5111, in both cases, is found to be less than that of the other drivers.

1 1.5 2 2.5 3 3.5 4 4.5 5
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0.16
0.18
0.2
Frequency[MHz]
P
o
w
e
r
[
W
]

LM5111
EL7222
TC4451
FAN3111

1 1.5 2 2.5 3 3.5 4 4.5 5
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
Frequency[MHz]
P
o
w
e
r
[
W
]

LM5111
EL7222
TC4451
FAN3111

(a) (b)

Apart from determining the power consumption of the drivers, the gate drive
signals of all these drivers for a 5V input and switching frequency of
approximately 2.5MHz were captured and illustrated in fig. 9.
The rise/fall times for all the gate signals of the MOSFET drivers at approximately
2.5MHz for a load capacitance of 150pF are displayed in fig. 9. From these figures,
it can be observed that the rise and fall times of the LM5111 are small compared to
those for the other MOSFET drivers. This is one of the desirable characteristics of
the MOSFET gate drivers, which reduces the switching losses [44] of the power
MOSFET and thereby increases the energy efficiency of the converter. However,
C

Load
VOLTAGE

REGULATOR
LMP 3 3
VCC
MOSFET

driver
VCC
OUT
GND
IN
DSPIC

MICROCONTROLLER
Gnd
VDD PWM
Figure 7. Test circuit of MOSFET gate drivers

Figure 8. Measured gate drive power for Vin of (a) 5V and (b) 10V

17
due to the fast rise and fall times, a high radiated EMI exists as compared to that
for the slow turn-on and turn-off processes. This is one of the trade-offs in the
MOSFET gate drivers, which should be considered while designing gate drive
circuitry and high speed SMPS. From fig. (8) and fig. (9), it can be observed that the
MOSFET gate driver with low rise/fall times possesses low gate drive power
consumption when compared to other drivers.
Since the MOSFET gate driver LM5111 has consumed a low gate power, in
addition to possessing fast rise/fall times, it was considered as being the best of the
tested gate drivers and hence it was utilized in the high frequency converter
circuits, which will be discussed in later chapters.

The theoretical gate drive power consumption obtained by using equation (1) and
the measured gate drive power consumption of this driver for a 10V input voltage
with respect to the frequency is plotted in fig. 10. It can be observed that there is a
good agreement in the theoretical and measured values, which implies that very
little gate drive power was consumed in terms of Ptransient and Pquiescent and all the
energy is used for turning on/off of the transistor. In addition to this, the measured
gate drive power consumption as a function of switching frequency for various
load conditions using LM5111 is depicted in fig. 11.
The recent award winning LM5113 half bridge gate driver optimized for GaN
HEMTs has the capability to drive the switch up to a few MHz. It also possesses an
integrated insulated high side driver but, it cannot be utilized for the input

Figure 9. Measured gate drive pulses of different MOSFET drivers
LM5111 EL7222
TC4451 FAN3111
18
voltages exceeding 100V [45]. Another recent MOSFET gate driver LM5114 [46]
from Texas Instruments also possesses the desirable features such as, low
propagation delay times and availability in miniaturized packages (WQFN) etc., In
addition to this, its turn on/turn off propagation delay times are given as 12ns for
the load capacitance of 1000pF, which are comparable with those for the LM5111.
1 1.5 2 2.5 3 3.5 4 4.5 5
0.02
0.03
0.04
0.05
0.06
0.07
0.08
Frequency[MHz]
P
o
w
e
r
[
W
]

Measured
Calculated

1 1.5 2 2.5 3 3.5 4 4.5 5
0.05
0.1
0.15
0.2
0.25
Frequency[MHz]
P
o
w
e
r
[
W
]

C
L
=150pF
C
L
=680pF
C
L
=1200pF

However, in this thesis, the LM5111/LM5112 MOSFET gate drivers are considered
for driving the Si MOSFETs/GaN HEMTs in all the converter circuits which will be
discussed in the coming sections.

Figure 10. Calculated & measured drive
power for Vin of 10V & CL of 150pF
Figure 11.Measured drive power for Vin of
10V & different load conditions

19

3 QUASI RESONANT FLYBACK CONVERTER USING CORELESS PCB
STEP-DOWN TRANSFORMER
The latest trend towards high power density, low profile and fast transient
response of converters for various DC-DC converter applications, demands an
increased switching frequency of the converters [47] - [50] as discussed earlier.
However, as the switching frequency of a converter is increased, the magnetic
losses and the switching losses in the semiconductor devices together with the gate
drive power consumption increase thus leading to reduced energy efficiency for
the converter. In this regard, most of the commercially available isolated DC-DC
converters operate well below 500 kHz [11].

In the case of a hard switched converter, as the switching frequency of the
converter is increased, the turn on and turn off losses, which are frequency
dependent, increase proportionately. Also, the stored energy in the output
capacitance of the MOSFET during the turn OFF condition gets dissipated
internally when the switch is turned ON. Moreover, the switch turn-ON at the
higher voltage levels induces a switching noise through the Miller capacitance of
the MOSFET, which is coupled to the gate drive circuit, thus leading to significant
noise or EMI [31], [51] and instability of the driver circuit. However, this situation
worsens due to the parasitic elements effect as the switching frequency of the
converter is further increased. Therefore, at higher operating frequencies with the
assistance of soft switching techniques such as, zero voltage switching (ZVS) and
zero current switching (ZCS), the above problems in relation to the switching
device can be mitigated and hence the energy efficiency of the DC-DC converters
can be improved.

From the magnetics point of view, the core losses, consisting of hysteresis and
eddy current losses, which are frequency dependent, become elevated as the
operating frequency of the transformers is increased as discussed in chapter 1. In
this regard, lot of research is also being carried out on coreless transformer
technology for various applications [52] - [56]. However, the earlier conducted
research works on the coreless PCB transformers for power transfer application
was limited to the unity voltage transformation ratio (used as an isolation
transformer) [52], [53]. On the other hand, majority of the SMPS applications, such
as power over Ethernet (PoE), telecommunications, server applications etc.,
requires step-down/step-up conversion ratios. Therefore, the first part of the thesis
was concentrated to design the high frequency low power converters using
coreless PCB step-down transformers.
In this chapter, a DC-DC converter operated in the MHz frequency region, using
the designed 2:1 multilayered coreless PCB (MLCLPCB) transformer and
20
employing a quasi resonant flyback converter topology for a given power transfer
application, is discussed.

3.1 FLYBACK DC-DC CONVERTER
A flyback converter is an isolated version of the basic buck-boost converter [57]. It
is the most widely used SMPS topology for power transfer applications falling
below 150 W [58] since it utilizes a single magnetic element as compared to other
SMPS topologies. It can be used for several AC-DC and DC-DC applications,
including a laptop adapter, a computer monitor, telecom, PoE, WLAN access
points etc., In this case, the transformer serves the purpose of isolation and it can
be utilized for multiple outputs thus leading to better converter optimization for
very large/very small conversion ratios [59]. The basic schematic of the flyback DC-
DC converter is shown in fig. 12. Based on the output power level, input/output
voltage range, isolation requirement, efficiency and relative cost comparison, the
flyback converter topology has been selected.

Figure 12. Schematic diagram of flyback DC-DC converter
Here, in the above figure.12, transformer T1 primary winding is connected in
series with switch SW1. In this case, the flyback transformer is acting as an energy
storage device instead of acting as a true transformer. This flyback transformer can
be named as a coupled inductor or a multi winding inductor. Briefly, the operation
of the flyback converter can be explained as follows. In the steady state operation,
when the switch SW1 is ON for a period of Ton, the dot end of the winding is
positive compared to its non dot end and the energy is stored in the primary
winding of the transformer T1. During this period, the flyback diode is in reverse
biased condition and the filter capacitor C1 supplies the load current to the
resistance RL. When the switch SW1 is OFF for a period of Toff, the flyback diode
is forward biased and the stored energy in the inductor is delivered to the load.
During the OFF period, the drain source voltage of the SW1 is the sum of the
input voltage Vin and the output voltage Vo reflected back through the turns ratio
n, and the energy stored in the leakage inductance and is given by the following
equation.
21
oss
lk
peak o in sw
C
L
I nV V V + + = (4)
where,
Ipeak peak current flowing through switch SW1
Llk leakage inductance of transformer T1
Coss Output capacitance of switch SW1
The two different modes of operation of the flyback converter are

1. Discontinuous conduction mode of operation (DCM)
2. Continuous conduction mode of operation (CCM)

The factors determining the operational mode of the flyback converter are the
primary inductance and the load current. In the case of the DCM or complete
energy transfer mode [60], the energy stored in the primary winding of the
transformer during the Ton period is completely transferred to the output during
the Toff period. Otherwise, it is the case that the flyback converter would be
considered as being in an incomplete energy transfer mode or in CCM.

The DCM or CCM operation of the flyback converter will have its own advantages
and disadvantages. In the case of the DCM, the switching losses of the secondary
side flyback diode,D1 are less when compared to flyback converter in CCM mode
of operation. In addition to this, the size of the transformer gets reduced because
the primary inductance is smaller compared to that of the CCM system. Also, in
the case of the DCM, the RMS currents flowing through the windings are high
compared to those for the CCM. The conduction losses in the switching devices,
such as the MOSFET or BJT are higher and the stress on the output filter
capacitor,C1is increased.

Generally, the DCM is preferable for high voltage and low current applications,
whereas the CCM is preferred for low voltage and high current applications [60].
In the case of the CCM, the voltage conversion ratio (Vo/Vin) depends on the duty
cycle, where Vo is the output voltage of the converter and Vin is the input voltage
fed to the converter. In case of DCM, the voltage conversion ratio not only depends
on the duty cycle but, also on the load condition, RL, switching frequency, fsw and
the primary inductance, Lp. The output voltage of the flyback converter operated
in the DCM mode [61] is given as

sw p
L
in o
f L
R
D V V

=
2
(5)
The output voltage of the flyback converter operated in the CCM mode is given as

22
n D
D
V V
in o
1
1
= (6)
where D is the duty cycle of the switch,
T
T
T T
T
D
on
off on
on
=
+
=
n is the transformer turns ratio
As discussed previously, in order to design a compact SMPS, the switching
frequency fsw of the converter must be increased. Since, the switching frequency of
the converter determines the size of the passive elements such as the transformers,
inductors and capacitors, for the given power transfer application, the inductance
required for the flyback transformer as a function of frequency for both DCM and
CCM mode of operation is estimated.

3.1.1 Design guidelines of flyback transformer in DCM

In this section, the design guidelines for the flyback transformer operating in the
discontinuous conduction mode of operation (DCM) [58] are discussed briefly.

STEP 1: In core based transformers, the first step is to select the core type and size
in order to meet the given power requirements. However, in case of coreless PCB
transformer, this STEP 1 can be ignored.

STEP 2: The selection is made regarding the turns ratio, n, so as to estimate the
maximum stress across the switch (SW1) in the off state, ignoring the leakage
inductance spike. The maximum voltage stress on the switch, SW1, at Vin_max, by
considering a 1V drop across the flyback diode is given as follows.

( ) 1
max _ max _
+ + =
o in ds
V n V V (7)
STEP 3: In order to maintain the converter to be in DCM mode of operation, the
volt-sec product during the Ton period must be equal to the volt-sec product
during the reset time Tr as given in equation (8). The on-state voltage drop across
the switching device is taken as approximately 1V. The total time period T also
consists of the dead time Tdt, and is given by equation (9). The dead time is
usually considered as 20% of the total time period, T.

r o on in
nT V T V ) 1 ( ) 1 (
min _
+ = (8)
dt r on
T T T T + + = (9)
STEP 4: From equations (8) and (9), the on-period Ton can be obtained as follows.

n V V
T n V
T
o in
o
on
) 1 ( ) 1 (
) 8 . 0 ( ) 1 (
min _
+ +
+
= (10)
23
STEP 5: By considering the energy efficiency of the converter as 80%, the
inductance of the primary winding is given by equation (11), where Po is the Load
power of the converter circuit.
) 5 . 2 (
) (
2
min _
o
on in
p
P T
T V
L

= (11)
STEP 6: The primary peak current flowing through the switching device is
computed from equation (12). In the case of power MOSFETS, the peak current
rating should be 5-10 times [58] higher than the calculated value obtained from (12)
in order to achieve a lower conduction loss of the MOSFET.
p
on in
peak
L
T V
I
) (
min _

= (12)
The primary/secondary RMS currents flowing through the flyback transformer can
be computed from (13) and (14).
T
T
I
I
on
peak
rms p
=
3
_
(13)
n
T
T
I
I
r
peak
rms s
=
3
_
(14)
Since one ampere of RMS current requires 500 circular mils, the required wire size
can be computed from, Ip_rms and Is_rms as follows

rms p p I W _ 500 =
(15)
rms s s I W _ 500 =

(16)

where, Wp/Ws primary/secondary width of conductor

3.1.2 Design guidelines of flyback transformer in CCM

In the previous section, the design guidelines in relation to the flyback transformer
operating in DCM have been discussed and in this section the design guidelines
when operated in CCM [58] will be presented.
STEP 1: In this case also, the first step for the core based transformers is to select
the core type and size in order to meet the given power requirements.
STEP 2: The turns ratio is determined in the same manner as discussed in STEP 2
of section 3.1.1
STEP 3: Since no dead time exists, as in the case of DCM, the total time period T is
the summation of the Ton and Toff. The duty cycle ratio (D) in CCM is obtained as
follows
( )
( ) ( ) 1 1
1
1
min _
+ +
+
= =
o in
o on
V n V
V
T
T
D (17)
24
STEP 4: From the given output power Po, the current at the center of the ramp of
the secondary current pulse can be obtained by knowing the duty cycle and output
voltage of the converter and is given by the following equation.
( ) D V
P
I
o
o
cs
=
1
(18)
STEP 5: By assuming the energy efficiency to be 80%, the current at the center of
the ramp of the primary pulsed current can be obtained as follows
.
min _
25 . 1
in
o
cp
V D
P
I
= (19)
STEP 6: At the minimum specified value of the output power, Po_min, the primary
and secondary inductances of the transformer are given by the following
equations.
T P
T V V
L
o
on in in
p

=
) ( 5 . 2
) ( ) 1 (
min _
min _ min _
2
(20)
( )
1
2

= n L L
p s
(21)
3.1.3 Design Example
Consider a 10W, 12V flyback converter for a PoE application, with an input voltage range
of 25V-40V and with a nominal input voltage of 32.5V and turns ratio n of 2 with an
assumption of a minimum output power of the 1/10
th
nominal power.
The primary/secondary inductances of the transformer for the given power under
DCM and CCM were determined with respect to the frequency variation by using
the above mentioned design procedure, except for step 1, and are illustrated in fig.
13 (a) and (b) respectively.
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
1
2
3
4
5
6
7
8
Frequency in MHz
I
n
d
u
c
t
a
n
c
e

i
n

H

L
p
L
s

0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
20
40
60
80
100
120
Frequency in MHz
I
n
d
u
c
t
a
n
c
e

i
n

H

L
p
L
s

(a) (b)
Figure 13. Primary/secondary inductances in (a) DCM & (b) CCM
From figs.13 (a) and (b), it can be observed that the inductances of the
primary/secondary of the transformer are drastically reduced as the switching
frequency is varied from 500 kHz to 5 MHz, in both cases. In the DCM mode of
operation, the inductance value is further reduced as compared to that of the CCM
25
mode of operation. However, larger peaks exist for the primary/secondary currents
flowing through the windings of the transformer when operated under the DCM
conditions as compared to those of the CCM which can be verified from the
calculated values given in table 2 at a switching frequency of 3MHz.
Table 2. Comparison of different parameters in DCM and CCM at 3MHz
Parameters DCM CCM
Primary/Secondary Inductance, [H] 1.44/0.36 21.63/5.4
Primary/Secondary Peak current, [A] 2.4/4.8 0.96/1.92
Duty Cycle 0.416 0.52
Wp/Ws, [mm] 0.6/0.7 0.4/0.44
In order to completely eliminate the core losses at these frequencies, a high
frequency MLCLPCB step-down transformer operating at a few MHz for a power
transfer application has been designed [62]. In the next section, the characteristics
of the designed transformer will be discussed.

3.2 DESIGN AND PERFORMANCE OF MLCLPCB STEP-DOWN POWER TRANSFORMER
A coreless printed circuit board step down transformer, which can be utilized for
DC-DC converter applications, has been designed in a four layer PCB laminate.
Here, the traditional FR-4 PCB laminate, whose breakdown strength is of
approximately 50kV/mm [63], is used. In this case, in order to achieve a good
coupling coefficient K by providing exact alignment between the primary and
secondary windings, the two primaries are on either side of the secondary winding
forming a primary-secondary-primary (PSP) structure as illustrated in fig. 14. The
aforementioned procedure of section 3.1.2 has been utilized in the design of this
transformer in order to operate the converter in the CCM mode of operation based
on load power, input voltage range and output voltage. STEP 1 described in the
procedure is ignored because these transformers do not have any magnetic cores.

Figure 14. Structure of Coreless PCB step-down transformer

3.2.1 Geometrical parameters of MLCLPCB 2:1 power transformer
The inductance required to design a flyback transformer for a given power transfer
application as a function of frequency can be obtained by the following procedure
mentioned in section 3.1.2. However, due to the absence of core material, the
electrical parameters such as inductance, capacitance and resistance, in the case of
26
a coreless PCB transformer, is determined by the geometrical parameters. These
required electrical parameters can be analytically obtained from the geometrical
parameters using the Hurley and Duffy method [64]. The geometrical parameters
considered for the design of the MLCLPCB step-down 2:1 power transformer in
order to obtain the desired electrical parameters are given in table 3.
Table 3. Geometrical parameters of transformer
S.No Parameters Value
1 No. of Primary/Secondary turns 32/16
2 Width of conductor [mm] 0.6
3 Track separation [mm] 0.4
4 Height of conductor [m] 70
5 Outermost Diameter [mm] 30
6 Board Thickness [mm] 1.48

3.2.2 Electrical Parameters of MLCLPCB step-down 2:1 power transformer
After the design and manufacturing of the MLCLPCB transformer, in order to
determine its exact electrical parameters, the initial parameters were measured at
1MHz using a high precision RLC meter HP4284A. The self/leakage inductance of
the primary Lp/Llkp was obtained by open circuiting and short circuiting the
secondary winding, respectively and vice versa. Also, a four wire measuring
method was utilized [65] for measuring the leakage inductances of the flyback
transformer below 1H, which can be obtained as follows.
=
50
2
50
V
V
f
L
dut
lk
(22)
where Llk is the leakage inductance, Vdut/V50 is the voltage across the device under
test/voltage across a 50 resistor and f is the excitation frequency. The exact
parameters of the transformer were obtained by passing these initial parameters
into the high frequency model of the transformer which is illustrated in fig. 15.

Figure 15. High frequency model of MLCLPCB transformer

These parameters were fine tuned so that the modelled performance characteristics
such as transfer function H(f), input impedance Zin, impedance angle match
to those measured within the frequency range of 1 - 10MHz. By following the
above mentioned procedure, the actual parameters of the transformer [62], [66]
were obtained and are given in table 4.
27
Table 4. Electrical parameters of the transformer

3.3 HARD SWITCHED CONVERTER
In switching power converters, when the switch transition takes place from the ON
state to the OFF state and vice versa, both the voltage and current exist
simultaneously for a short period of time. In this case, the converter is said to be
operated in a hard switched condition.

3.3.1 Problems associated with hard switched converter
The above mentioned situation leads to a power loss in the switching device,
which degrades the energy efficiency of the converter. The corresponding
switching power loss across the device during switch transition times is illustrated
in fig. 16.

Figure 16. Switching Losses of Hard Switched Converter [67]

Particularly in the case of high frequency DC-DC converters, the switching losses
of the power MOSFET, which are the function of frequency and the transition
times tsw(on)/tsw(off) [68], are significantly increased as the switching frequency of
converter increases and is given by the following expression

( )
) ( ) ( off sw on sw sw sw
t t f P +
As the losses in the MOSFET increase, the temperature of the converter, the
stresses on the MOSFET and the cooling requirement are also raised, whereas the
S.No Parameters Value
1 Primary/Secondary DC resistance [] 1.1/0.55
2 Primary/Secondary self inductance [H] 17.23/4.54
3 Primary/Secondary leakage inductance [H] 0.46/0.23
4 Primary/Secondary Mutual inductance [H] 16.77/4.31
5 Inter winding capacitance [pF] 178
6 Coefficient of coupling 0.95
28
energy efficiency of the converter is reduced. In addition, the rate of change of both
the current (di/dt) and voltage (dv/dt) in the devices are high and uncontrollable,
which results in high EMI as mentioned earlier and hence the reliability of
converter is reduced. It then becomes vulnerable if any stray capacitance and
leakage inductance occurs in the layout of the chosen converter and components.
Because of these associated problems, which are involved by increasing switching
frequency, the operating frequency of the converter is forced to be at lower
frequencies in the case of the hard switched converter, which leads to an increase
in the size of the converter.

3.3.2 Measures to minimize losses in hard switched converter

In the above section, the problems associated with a hard switched converter are
discussed. It is very important to minimize these losses and their related
consequences and, therefore the required measures are discussed in this section.

a) Circuit layout

By reducing the parasitic capacitances and inductances, the circuit layout can be
improved.

b) Utilizing passive or active snubbers to control high di/dt and dv/dt

Generally snubbers are classified as passive and active or dissipative and non-
dissipative in nature. Passive snubber circuits consist of resistors, capacitors,
inductors and diodes whereas the active snubber is built by using active switches
such as transistors, with additional external drive circuitry. This reduces the
switching losses but, additionally, increases the power consumption and
complexity of the circuit in case of active snubber circuit [69], [70]. Therefore, it is
not applicable to use the active snubbers for all the applications.

In the case of dissipative snubbers, the stored energy in the snubber is dissipated in
the resistor. Here, the rate of change of the voltage/current is reduced by shaping
the switching trajectory [58]. Also by using the passive snubber, the stress and loss
of the switching devices are merely transferred to the snubber instead of the
switching element, thus resulting in more or less the same energy efficiency of the
converter. Therefore, the switching frequency of the converter is still limited to
lower frequencies by using passive snubber circuits since the switching loss is
proportional to the switching frequency.

However, if the stored energy is utilized by pumping it into the source or load, it is
called a non-dissipative snubber. In the case of non-dissipative snubbers, the
29
elements L and C are utilized to shape the current waveform during the turn-off
process. On the other hand, these are relatively complex to be implemented
compared to those for the dissipative snubbers.

c) Controlling turn-on and turn-off times to reduce di/dt and dv/dt

The rise and fall times associated with the turn-on and turn-off times can be
controlled either by adjusting the gate voltages of the switching device [71], [72] or
by placing an external gate resistance prior to the gate terminal of MOSFET.
Usually, by varying the gate resistance of the MOSFET, the rise and fall times of
the gate pulses can be adjusted. By increasing the gate resistance, the rise time and
fall times of the pulse increases and this results in a reduced dv/dt and di/dt.
However, by doing this, the reduction of EMI is possible at the cost of switching
losses in relation to the MOSFET.

d) Soft-switching techniques

The above discussed measures provide a partial solution for the problems allied to
the hard switched converter. Also, these measures do not have any impact in the
compact SMPS, which can be obtained by increasing the switching frequency of the
converter. Therefore, a method, which is useful for minimizing the problems
associated with a hard switched converter, together with a solution which involves
increasing the switching frequency, are discussed in the coming section.

3.4 SOFT SWITCHED FLYBACK CONVERTER
The aforementioned problems and limitations imposed by a hard switched
converter can be eliminated by adopting some changes in terms of converter circuit
parameters. For this purpose, soft switching circuits have been introduced. These
can be mainly classified as
Zero Current Switching (ZCS)
Zero Voltage Switching (ZVS)

3.4.1 Zero Current Switching (ZCS)
In order to operate the switching power converter at higher frequencies, the turn-
on/off loss of the switching device must be reduced as discussed in earlier sections.
In the case of the ZCS converter, the resonant elements, such as the inductor L
and capacitor C, assist in the shaping of the waveform, with regards to the
current, in a sinusoidal form rather than, for example, a square or triangular
waveform. When the circuit is turned-on and turned-off at zero current, it is
known as a zero current switching converter (ZCS) [51]. In this case, the switching
loss at the switch transient periods gets reduced.
30

3.4.2 Zero Voltage Switching (ZVS)
In order to operate the converters at higher switching frequencies from a few
hundred kHz to the MHz range, MOSFETs are generally considered as compared
to their counterparts, the BJTs [51]. During the OFF state of the MOSFET, a
considerable amount of energy is stored in its output capacitance as given by
equation (23). This energy becomes dissipated in the MOSFET once the switch is
turned-on [58]. However, since the output capacitance of the MOSFET is nonlinear
in nature due to which the drain source voltage becomes nonlinear, the values
obtained from this equation are considered to be overestimated. Hence, a new
method to obtain the exact switching loss of the power MOSFET by considering
the internal physics of the switching loss mechanism is proposed in [74].
sw oss loss
f V C P =
2
2
1
(23)
In order to circumvent the problem of discharging the energy into the MOSFET
during turn-on, a zero voltage switching (ZVS) technique is employed.
In ZVS converters, the switch is usually turned-on when the drain-source voltage
of the MOSFET reaches zero [68], [73] due to which the turn-on loss across the
MOSFET gets significantly reduced. Usually, the ZVS of the converter is achieved
by using the resonant elements Lr and Cr, which form a resonant circuit. In
section 3.3, the discussion was that parasitic elements cause more serious problems
in the case of hard switched converters. However, in the case of ZVS converters,
the undesirable parasitic elements of the circuit can prove to be useful in achieving
the ZVS condition by forming a resonant tank circuit. In this case, Lr includes the
transformer leakage inductance, the parasitic wire inductance and the external
resonant inductor. The resonant capacitor, Cr consists of the output capacitance of
the MOSFET, the winding capacitance of the transformer and other parasitic
capacitances.

3.5 SWITCHING TRAJECTORY OF MOSFET
Switching trajectory is a good measure in determining the power lost in the
MOSFET. Therefore, the switching trajectory of the MOSFET in the hard switched
converter, with and without a snubber network and together with the soft
switching converter, are presented in fig. 17. It can be observed that a significant
amount of energy is saved in the case of the soft switching converters because of
the decreased switching losses of the MOSFET.
31

Figure 17. Switching trajectory of power MOSFET [75]

3.6 ZVS QUASI RESONANT FLYBACK CONVERTER
For a high frequency isolated converter application where a large step-down ratio
is required, a quasi resonant flyback converter [76] is considered to be a good
choice. The reason for this is because it requires very few components and can thus
be highly integrated into modern electronic systems. The basic circuit of a quasi
resonant flyback converter is illustrated in fig. 18 and the corresponding theoretical
waveforms are shown in fig. 19. Here, the turns ratio of the transformer is
considered as N. As discussed previously, the passive elements LR and CR form
the resonant tank circuit. The characteristic impedance Zn, resonant frequency fr,
normalized load resistance, r and voltage conversion ratio M of the circuit are
given by the following equations.
R
R
n
C
L
Z = (24)
R R
r
C L
f
2
1
= (25)
n
L
Z
R
r = (26)
in
o
V
V
M = (27)

3.6.1 Modes of operation of quasi resonant flyback converter
The operation of a quasi resonant flyback converter [76] based on figs. 18 and 19
can be divided into several modes and these are briefly explained as follows.
32

CR
LR
RL
DSCH
S
P1 S1
TX1
CF
Ds
N:1
Vin

Figure 18. Basic circuit of quasi resonant flyback converter

Figure 19. Waveforms of ZVS quasi resonant flyback converter [76]

iS
iLR
+
-
VDS
33
Mode.1 (0<t<t0): The gate signal is applied to the MOSFET during this period and
the switch S comes into the conduction state. The input voltage Vin is applied to
the primary winding of the transformer and the flyback diode DSCH is reverse
biased because of the polarity of the transformer. In this mode, the entire primary
current or magnetizing current flows through the switch S.

Mode.2 (t0<t<t1): In this mode of operation at t0, the switch S is turned-off and the
primary current is diverted from the switch to the resonant capacitor CR. The
drain-source voltage across the switch starts to rise in a linear fashion. Hence, it is
known as the linear charging resonant capacitor, CR.

Mode.3 (t1<t<t2): As soon as the drain source voltage reaches a magnitude of
Vin+NVo, the diode DSCH comes into the action after it achieves the forward biased
condition. During this period, LR and CR resonate and the drain-source voltage
Vds reaches its maximum value given by the following equation.

n m o in ds
Z I NV V V + + =
max _

(28)
At the instant t2, the voltage across the switch S is reduced to a zero value
resulting in a ZVS condition of the converter and the diode Ds becomes forward
biased and the voltage of (Vin-NVo ) is applied to the resonant inductor, which
results in the linear increase of the inductor current iLR . When this current reaches
the value of the magnetizing current, the flyback diode DSCH becomes reverse
biased and the cycle repeats itself.

3.6.2 Condition required for ZVS in quasi resonant flyback converter
In order to achieve ZVS in a quasi resonant flyback converter, the following
equation must be satisfied.
N
M
r (29)
3.6.3 Expression for (fsw) in quasi resonant flyback converter
The expression for determining the switching frequency [76] fswof the quasi
resonant flyback converter can be determined by the following equation
( ) ( )
|
|
|
|
\
|
(
+ + +
=

cos 1
2
1
2
rN
M
M
rN
MN
f f
r sw
(30)
where,
|
\
|
+ =
M
rN
arcsin (31)

34
3.7 SIMULATION AND EXPERIMENTAL RESULTS OF HARD AND SOFT SWITCHED
CONVERTER
The designed MLCLPCB step down 2:1 transformer was initially simulated and
then tested in a quasi resonant flyback converter. The schematic of this converter
using high frequency model of the transformer is shown in fig.20.

Rg
Cr RL
Df
Lms
Vg
Vin
Cin
Q1
Rs
Llks
Rp
Lr
Lmp
Cf
Cps

Figure 20. Quasi resonant flyback converter using MLCLPCB transformer

The considered converter specifications are:
Input voltage : 25 -40V
Output voltage : 12V
Load power : 10W
Load range : 15 - 50
Switching frequency range : 2.5 4.5 MHz

The devices selected for the aforementioned converter specifications are as follows:

POWER MOSFET Q1: The power MOSFET considered is the ZXMN15A27K from
Diodes Incorporated, whose drainsource voltage is 150V with an on-state
resistance Rds_on of 0.65 at Vgs of 10V. The typical rise and fall times of the switch
Q1 are 12.7 and 13.3ns respectively. The rise and fall times of the MOSFET should
be as low as possible in order to achieve lower switching losses of the MOSFET as
discussed earlier. The typical output capacitance Coss of MOSFET from the
datasheet is 64.5pF [77].

SCHOTTKY DIODE Df: Because of a low forward voltage drop of 0.46V, a
Schottky diode STPS15L45CB, whose reverse blocking voltage capacity of 45V with
a forward current rating of 15A [78], was utilized.
High frequency model
of power transformer
35
DSPIC33FJ016GS502 Microcontroller: The PWM signals required to drive the
MOSFET were generated from the PWM channels of the micro-controller and fed
to the MOSFET driver in order to strengthen the gate signal. The micro-controller
possesses a resolution of 1.04ns for the duty cycle, dead-time, phase shift and
frequency [79], which is a highly desirable feature for high frequency converter
circuits.

MOSFET Driver: The power MOSFET Q1 is driven with the assistance of LM5111
MOSFET driver due to the characteristics as discussed in chapter 2.

As discussed previously, Lr and Cr form the resonant tank which leads to the
ZVS condition for the flyback converter. The estimated resonant capacitor of the
circuit is 168pF including the parasitic and output capacitance of the MOSFET. In
table 4, it was mentioned that the leakage inductance of the transformer is 0.46H,
which is not sufficient to meet the ZVS condition according to equation (29).
Therefore, an external inductor of 5.2H was placed in series with the primary
winding of the transformer. Since core losses dominate at these higher frequencies
in core based inductors, a PCB inductor without a core operating in this frequency
region was designed and utilized. The characteristic impedance and resonant
frequency of the circuit were obtained by using equations (24) and (25) and were
found to be 183.5 and 5.16MHz respectively.

3.7.1 Simulation results of ZVS flyback converter
The simulations of the ZVS flyback converter were performed by using SIMetrix
software.

3.7.1.1 Modelling of MOSFET

The MOSFET utilized in the converter is the ZXMN15A27K as discussed
previously. Since, no readily available SPICE model exists for this MOSFET, the
device has been modelled prior to its utilization in the converter circuit. In order to
model the MOSFET, the important parameters [80], [81] to be considered are listed
in table 5.

By considering these parameters, a spice model for the ZXMN15A27K has been
developed using SIMetrix software. The output and the transfer characteristics of
the MOSFET from the manufacturers data sheet and for the modelled MOSFET
have been illustrated in figs. 21 and 22 respectively.

From these figures, it can be observed that a best fit for the considered MOSFET is
achieved using the simulation software.
36
Table 5. Required simulation SPICE parameters of MOSFET

Drain-Source Voltage / V
100m 200m 400m 1 2 4 10 20
D
r
a
i
n

C
u
r
r
e
n
t

/

A
200m
400m
1
2
4
10
20
40
Vgs 3.5V
Vgs 4V
Vgs 4.5V
Vgs 5V
Vgs 5.5V
Vgs 6V
Vgs 8V

(a) (b)
Figure 21. Output characteristics of MOSFET (a) datasheet (b) simulations
Gate-Source Voltage/V 1V/div
2 3 4 5 6 7 8
D
r
a
i
n

C
u
r
r
e
n
t

/

A
100m
200m
400m
1
2
4
10
20
T 25 degrees
T 150 degrees
T -55 degrees
Vds 15 V

(a) (b)
Figure 22. Transfer characteristics of MOSFET (a) datasheet (b) simulations
S.No Parameters Symbol Units
1 Length of channel L m
2 Width of channel W m
3 Oxide Thickness Tox m
4 Zero bias Threshold Voltage VTO V
5 Transconductance KP A/V
2

6 Substrate doping density NSUB 1/cm
3

7 Fast surface state density NFS 1/cm
2

8 Saturation field factor KAPPA -
9 Surface mobility UO cm
2
/V.Sec
10 Source/Drain ohmic resistance RS/RD
11 Bulk p-n saturation current IS A
12 Gate drain overlap capacitance/channel width CGDO F/m
13 Gate source overlap capacitance/channel width CGSO F/m
14 Bulk drain zero bias p-n capacitance CBD F
37
This modelled MOSFET is then placed in the quasi resonant flyback converter
circuit, shown in fig. 20 and simulated. At an input voltage, Vin of 35V and a load
resistance of 15, the converter was switched at a frequency of 3.26MHz. The
simulated waveforms of the ZVS converter and the transformer in the converter
circuit, under these conditions are illustrated in figs. 23 and 24 respectively. From
top to bottom, the figure.23 illustrates the gate source voltage, Vg fed to the
MOSFET, the drain-source voltage Vds across Q1, output voltage Vo, and the
mean current flowing through the switch Imean.
From this figure, it can be observed that the converter is operating in ZVS
condition.
V
o

/

V
12.076
12.082
12.088
12.092
V
g

/

V
0
2
4
6
8
10
V
d
s

/

V
-0
20
40
60
80
100
Time/uSecs 200nSecs/div
498.2 498.4 498.6 498.8 499 499.2 499.4 499.6 499.8 500
I
m
e
a
n

/

A
-0
1
2

Figure 23. Switching Waveforms of ZVS flyback converter

V
s
e
c

/

V
-40
-20
0
V
p
r
i

/

V
-80
-40
0
40
I
p
r
i

/

A
-1
-0.6
-0.2
0.2
498.2 498.4 498.6 498.8 499 499.2 499.4 499.6 499.8 500
I
s
e
c

/

A
-2
-1
0

Figure 24. Primary/secondary voltages and currents of Coreless
PCB transformer in ZVS flyback converter
Figure. 24 illustrates the primary/secondary voltages and currents of the multi-
layered coreless PCB transformer utilized in the converter circuit. The coreless PCB
transformers behaviour in the switching circuit was initially examined by using the
38
simulation software and based upon the high frequency model and simulations,
the converter prototype was built and the experiments were carried out which will
be discussed in coming sections.

3.7.2 Experimental results of ZVS flyback converter
The flyback converter circuit was tested for both hard switched and soft switched
conditions using a multi-layered coreless PCB transformer. The energy efficiencies
of the unregulated converter, under both hard and soft switched conditions, at a
load resistance of 30 for the varied input voltage, Vin of 25 - 40V are shown in
fig. 25. In this case, the duty cycle ratio D considered is 50%. As discussed in the
previous sections and from fig. 25, it was verified that the energy efficiency of the
converter can be improved by implementing one of the soft switching techniques
i.e., ZVS. In addition, the calculated stress on the MOSFET using equation (28) and
the measured ones under the ZVS conditions are as shown in fig. 26.
25 30 35 40
55
60
65
70
75
80
85
V
in
[Volts]
C
o
n
v
e
r
t
e
r

E
f
f
i
c
i
e
n
c
y
,

[
%
]

ZVS Condition
Hard Switched Condition
25 30 35 40
90
100
110
120
130
140
150
160
V
in
[Volts]
V
d
s
[
V
o
l
t
s
]

Measured
Calculated

3.7.3 Regulation of ZVS flyback converter
The converter has been open loop regulated to the constant output voltage of 13V
for the varied input voltage range of 25 - 40V at a constant load resistance of 30.
The corresponding measured energy efficiency of converter is shown in fig. 27 (a).
For the open loop regulation of the output voltage of the quasi resonant flyback
converter, a constant off time frequency modulation technique was utilized where
the converter switching frequency is varied in order to maintain the output
voltage. The energy efficiency of the converter is maximum at the nominal input
voltage of 32.5V and, becomes reduced at lower input voltages because of the
increased conduction losses due to the increased duty cycle (61%) and, at higher
voltages because of the increased switching losses of the converter.

The calculated and measured switching frequencies of the regulated converter for
varied input voltages in order to remain a constant output voltage are depicted in
Figure 25. Measured efficiency of hard & soft
switched flyback converter
Figure 26. Calculated and measured voltage
stress on MOSFET
39
0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7
65
70
75
80
85
I
Out
[Amps]
C
o
n
v
e
r
t
e
r

E
f
f
i
c
i
e
n
c
y
,

[
%
]
fig. 27 (b). The measured switching frequencies are in good agreement with those
calculated by using equation (30).
25 30 35 40
65
70
75
80
85
V
in
[Volts]
C
o
n
v
e
r
t
e
r

E
f
f
i
c
i
e
n
c
y
,

[
%
]
25 30 35 40
1
2
3
4
5
V
in
[Volts]
F
s
w
,
[
M
H
z
]

Calculated
Measured

(a) (b)
Figure 27. (a) Energy efficiency (b) frequency of ZVS flyback converter

The measured energy efficiency of the unregulated converter at different load
conditions of 15 - 50 and at a constant input voltage of 35V is illustrated in fig. 28
at a switching frequency of 3.26MHz. Under these conditions, the output voltage of
the converter was within 10 - 14V. As in the previous case, the output voltage can
also be regulated to 13V for load variations by using the frequency modulation
technique described in the previous section.

The measured wave forms of the flyback converter at load resistances of 15 and
50 respectively are illustrated in figs. 29 (a) and (b). It can be observed that, in the
first case, the circuit was operating under the ZVS condition whereas, the circuit
loses its ZVS property under a light load condition, which can be observed from
fig. 29 (b).

Figure 28. Energy efficiency as a function of load current
40

(a) (b)
Figure 29. Waveforms of flyback converter a) RL=15 & b) RL=50

3.7.4 Thermal profile of ZVS flyback converter
For the input voltage of 40V and at a particular load resistance of 30, the
input/output powers of the converter are 12.32/10.05W respectively, resulting in an
energy efficiency of 81.5%. The remaining losses are distributed in the converter
elements and the corresponding thermal profile of the transformer and converter
are illustrated in figs. 30 (a) and (b) respectively, which provides a clear picture of
the lossy components of the converter.

(a) (b)
Figure 30. Thermal profile of (a) transformer & (b) flyback converter

From the estimated losses of the transformer by knowing the currents flowing
through primary and secondary windings and the AC resistance of transformer
[66], it was found that the transformer contributes to nearly 40% of the total loss in
relation to the total converter losses and the remaining losses were shared by the
other elements such as MOSFET and diode. Thus, by adopting a proper optimal
design of the transformer and further reducing the losses in the MOSFET and
schottky diode of the converter, it is possible to build a highly energy efficient
MOSFET
DIODE
41
compact power supply operating in the MHz frequency region using coreless PCB
transformer.
In the earlier research works [55] & [56], the peak energy efficiency of the flyback
DC-DC converter utilizing the coreless PCB transformer is reported to be 68% for
the maximum output power level of 1W. Here, the maximum switching frequency
of the converter is around 900 kHz. However, in the demonstrated quasi resonant
flyback DC-DC converter of this thesis, the energy efficiency of the converter
utilizing MLCLPCB transformer for the tested output power level of
approximately 10W is 81.5% at a switching frequency of 3.26MHz which leads to
the power density improvement of converter.

42
4 GALLIUM NITRIDE HIGH ELECTRON MOBILITY TRANSISTOR FOR
HIGH SPEED SMPS
As discussed in previous chapters, the operation of the converter circuit at higher
switching frequencies results in a size reduction of the energy storage elements,
such as the inductors, transformers, capacitors and EMI filters. At the higher
switching frequency of the operation, the power MOSFETs are considered to be the
best choice in comparison to bipolar junction transistors (BJT) according to [82] &
[83] as discussed in earlier chapter. This is because of their remarkable behaviour
such as the higher current gain, more ruggedness and, moreover, MOSFETs are the
majority carrier devices because they are considered as being faster devices as
compared to their minority carrier counterparts, i.e., BJTs. Based on these
characteristics, over the past three decades the silicon based power MOSFETs have
ruled the power management area. During this period, several developments in
Si devices such as Si super junction devices i.e., Infineon CoolMOS etc., have been
made in an attempt to bring out their best in relation to power converters for high
frequency applications. However, due to the theoretical limitations of the existing
Si MOSFET technology for high frequency applications, a great deal of research
was conducted for introducing the new semiconductor materials [84] in order to
meet the current market demands. For example, by increasing the switching
frequency of the converter to a few MHz, the losses in the traditional Si MOSFET
such as conduction, switching losses and the gate drive power consumption gets
elevated. The gate charge Qg of a Si MOSFET at its respective operating voltage is
high and this leads to the increased gate drive power consumption. Due to these
limitations in relation to the Si MOSFET, the overall energy efficiency of a
converter with a traditional Si MOSFET goes down. In this regard, this chapter
discusses the benefit of the newly arrived GaN HEMT with that of the Si MOSFET
for the given high frequency power transfer application using MLCLPCB
transformer.

4.1 ADVANCEMENTS IN SEMI CONDUCTOR MATERIALS
Due to the above mentioned theoretical limitations of the state -of -the -art Si
material devices [85], [86] other new material devices are required, which is useful
in relation to meet the current trends in the market. Therefore, in order to
overcome the limitations imposed by the traditional Si MOSFET at higher
switching frequencies, a tremendous research effort has been made in order to
introduce new materials and structures for semiconductor devices. In this process,
a great deal of research was conducted into several new semiconductor materials
such as GaAs, AlAs, SiC, GaN and AlN and their impact on power electronic
applications are reported in [87] and [88].

43
4.1.1 Properties of semiconductor materials
A few comparable material and electrical properties [82], [89] [91] of the -state -of
-the -art Si, SiC and GaN materials at room temperature, useful for power
electronic converter applications, are listed in table. 6.
Table 6. Electrical and Material properties of Si, SiC and GaN
Parameters Si SiC GaN
Band gap energy, Eg(eV) 1.12 3.2 3.4
Critical electric field strength, Ec(MV/cm) 0.3 3.5 3.3
Electron Mobility, n (cm
2
/V.s) 1500 650 2000
Thermal Conductivity, (W/cm.K) 1.3 4.9 2.3
Saturated drift velocity Vs(x10
7
cm/s) 1.0 2.0 2.5

4.1.2 Advantages of GaN material compared to other materials
From the semiconductor parameters listed in table 6, the device performance
characteristics, in terms of power conversion applications, can be interpreted in
terms of conduction efficiency, breakdown voltage, switching efficiency and the
size and cost of the devices, which will be covered in this section. However, among
the new SiC and GaN material devices, an enhancement mode GaN HEMT [85]
offers a better performance as compared to the Si and SiC equivalents because of
the following advantages [86], [88].

1. High power and high temperature applications: For these applications, it is
necessary to have a large band gap which makes it difficult to release a free
electron even at higher temperatures [51]. In this aspect, the SiC and GaN
material devices gain the upper hand when compared to their counterpart Si
material devices which makes them to be suitable for these applications.

2. On state resistance (Rds_on): Due to higher electron mobility, high conduction
electron density and wide band gap [51], [86], the on state resistance of the
GaN HEMT was significantly reduced when compared to the Si and SiC
devices.

3. Conductivity: GaN devices possesses lower Rds_on x Area, because of the high
electron mobility, which allows for a higher current in a very small device
package. The on state resistance, Rds_on for a given switching device area is an
important feature in the determination of the cost of the product. The
theoretical limits of the Rds_on for a given area can be given in terms of the
device breakdown voltages as shown in fig.31 for Si, SiC, Si Super Junction
MOSFET and GaN devices [91].

4. Higher switching speeds: Due to the lateral device structure, the
capacitances/areas are very low compared to the Si trench MOSFETs, which
44
results in very high switching speeds of the transistors. Due to low
capacitances, the device is capable of switching hundreds of voltages in a very
few nanoseconds and hence can be utilized for multi megahertz frequency
converters. This is a desirable and crucial feature which leads to compact
power supplies.

Figure 31. Theoretical limits of Rds_on versus breakdown voltage [91]

5. Zero reverse recovery: Because there are no minority carriers, no stored
charges exist and hence no reverse recovery, Qrr for these devices. This
becomes a significant advantage in these devices as compared to the- state- of -
the-art Si MOSFETs.

6. Low temperature coefficient: GaN HEMT consists of much lower temperature
coefficient as compared to those of the Si MOSFETs, which enables it to
operate at higher temperatures with low Rds_on.

7. High breakdown voltage: From table.6, it can be observed that the critical
electric field strength of the GaN is higher as compared to the Si, which enables
the GaN device to withstand higher breakdown voltages within a small die
area resulting in low device cost and compact designs.

Due to the aforementioned advantages of GaN material, these devices can be
operated in harsh and hot, high power, radiation field conditions making it to be
useful in the environments where earlier the switching devices were prohibited
due to the limitations imposed by Si devices [51].

45
4.2 EVALUATION OF GAN AND SI DEVICES IN ZVS FLYBACK CONVERTER USING
MLCLPCB STEP DOWN TRANSFORMER
Because of the above discussed exceptional features of the GaN device, it was
evaluated in a quasi resonant ZVS flyback converter operated in the MHz
frequency region by using a coreless PCB step down power transformer designed
at Mid Sweden University. These results were compared with the converter
operated using the traditional Si MOSFET and are discussed in the coming
sections. In this case, the designed coreless PCB transformer of 2:1 turns ratio
discussed in the previous chapter was utilized.

4.2.1 Comparison of GaN HEMT and Si MOSFET parameters
For evaluating the performance of the GaN and Si devices in the ZVS flyback
converter based on the input and output voltage specifications, a 200V drain-
source blocking voltage capability, GaN (EPC1012) [93] and Si (IRFR220PBF) [94]
devices were chosen. The physical dimensions of these devices are illustrated in
fig. 32 with packages of land grid array (LGA 1.7x0.9 mm) and DPAK respectively.

Figure 32. Packaging of 200V Si (DPAK) left and GaN (LGA) right,
enhancement mode HEMT

From this figure, it can be observed that for the given breakdown voltage, the size
of the GaN HEMT is very small compared to that of the Si device which results in
high power density converters while using former device. The continuous drain
current Idof the GaN/Si devices at an ambient temperature are 3/4.8A respectively.
The on-state resistances, Rds_on of these devices are 0.1/0.8 at their respective Vgs
and Id conditions. The total gate charge Qg of the GaN/Si is 1.9/14nC at Vgs of
5/10V respectively. The typical reverse recovery charge Qrr of the GaN device is
zero, as discussed previously, whereas for the Si MOSFET it is about 0.91nC. The
reverse transfer capacitance (miller capacitance) of the GaN/Si is 7.5/30pF. This low
transfer capacitance of the GaN device means that it possesses a fast voltage
switching capacity as compared to that for the Si MOSFET because of the lower
Miller effect. As discussed at an earlier stage, it is very important to choose the
correct switching device especially in relation to high frequency switching power
converters. The reason is that, a trade off exists between the on-state resistance
Rds_on and the gate charge Qg of the switching element and it is always beneficial
to determine a figure of merit (FOM) for the device before utilizing it in a converter
circuit. Two types of figure of merit exist in terms of conduction and switching of
the device [86], [92]. In both cases, the desire is to have a low FOM in order to
46
obtain a better performance for the device. The FOM corresponding to the
conduction of the device can be expressed in terms of Rds_on and Qg and is given
as follows.
( ) ( ) ( )
ds g g ds g on ds ds g
V V Q V V R V V FOM , , ,
_
= (32)
The calculated FOM corresponding to the conduction of the GaN/Si devices are
approximately 1.33/31.3. Similarly, FOM corresponding to switching of the device
in terms of Rds_on and Qgd can be given as follows.
gd on ds sw
Q R FOM =
_
(33)
This calculated FOM of the GaN/Si devices are approximately 0.09/6.32. Here, the
FOM of the GaN device is much lower than that of the Si device, which has been
calculated in relation to their corresponding optimal operating regions and which
shows that the GaN device is better as compared to the Si MOSFET in both the
cases, in terms of the product of the on-state resistance and gate charge.

4.2.2 Experimental results of ZVS flyback converter using GaN and Si devices
In order to evaluate the aforementioned devices, the quasi resonant ZVS flyback
converter illustrated in fig.20 was considered with the following specifications.

Input supply voltage (Vin): 30 - 60V, nominal voltage (Vin_nom) of 45V
Regulated output voltage (Vo): 15V1%
Load resistance range(RL): 30 - 60
Switching frequency range(fsw): 3 - 5MHz

In both cases, the resonant capacitor Cr including the drain-source capacitance
and the parasitic capacitance was found to be approximately 80pF. Since, the
leakage inductance Llk of the transformer given in table 4 is insufficient to reach
the ZVS conditions of the converter, an external resonant PCB inductor of 5.2H is
added to the leakage inductance, forming a resonant inductor Lr. In this way, the
operating frequency of the converter was maintained within the desired frequency
range by the resonant tank circuit elements Lr and Cr as discussed in the
previous chapter. The characteristic impedance Zch and the resonant frequency fr
of this circuit are calculated by using equations (24) and (25) and are obtained as
284 and 8MHz respectively.

Unregulated converter: Initially the experiments were carried out on the converter
using both the devices and the energy efficiency of the unregulated converter was
measured. The corresponding figure is depicted in fig. 33. In this case, the
measured energy efficiency of the converter also includes the gate drive power
consumption. The maximum energy efficiencies of the converter, in both cases, are
found to be 82.5/74.2% with the GaN/Si devices at the nominal input voltage
Vin_nomof 45V and load resistance of 30. It can be observed from the figure, that
47
an energy efficiency improvement of about 8% can be achieved with the assistance
of GaN device when compared to existing Si based device for the given power
transfer application.
30 35 40 45 50 55 60
60
65
70
75
80
85
90
Input Voltage (V)
E
n
e
r
g
y

E
f
f
i
c
i
e
n
c
y
,

(
%
)

GaN HEMT
Si MOSFET

Figure 33. Energy efficiency of unregulated converter with GaN and Si devices
The output power of the converter at the maximum input voltage of 60V in both
cases is approximately 12W. In this case, the duty cycle ratio of the converter was
maintained at 50%.

Line regulation: The converter was then open loop regulated for the specified
input voltage range by using the constant off time frequency modulation technique
as discussed in the previous chapter and the energy efficiency was recorded. Here,
the output voltage of the converter was regulated to 15V with 1% tolerance band
for a full load resistance of 30. The corresponding energy efficiency of the
converter is depicted in fig. 34 (a).

From fig 34 (a), it can be observed that the energy efficiency of the converter is at
the maximum at Vin_nom and it is reduced at the lower end of the input voltage range
because of the increased conduction losses. At higher input voltage, the energy
efficiency is reduced because of the increased switching losses due to the higher
switching frequencies. At a nominal input voltage of 45V, with a load resistance of
30, the converter was regulated to 15V with 1V tolerance in the both cases. At
the nominal input voltage condition, the switching frequency of the converter in
both cases was approximately 4MHz. The circuit was operated under ZVS
conditions and the energy efficiencies with the GaN HEMT and the Si MOSFET
were found to be 82.5/74.2% respectively.

Load regulation: The converter was also open loop regulated to 15V by changing
the load resistance from RLmin to RLmax at a Vin_nom of 45V. The measured energy
efficiency under these conditions is illustrated in fig. 34 (b). In this case, for the
48
converters operated with both switching devices, the ZVS conditions were
maintained up to a certain load resistance and it ceases to follow after this limit.
30 35 40 45 50 55 60
60
65
70
75
80
85
90
Input Voltage (V)
E
n
e
r
g
y

E
f
f
i
c
i
e
n
c
y
,

(
%
)

GaN HEMT
Si MOSFET
30 35 40 45 50 55 60
40
50
60
70
80
90
Load resistance R
L
()
E
n
e
r
g
y

E
f
f
i
c
i
e
n
c
y
,

(
%
)

GaN HEMT
Si MOSFET

(a) (b)
Figure 34. Efficiency of regulated converter for a) line and b) load variations

This condition was observed at the light load of 60 and the waveforms were
captured for the converter operated with the GaN device and is shown in fig. 35.
This figure shows the nominal input voltage Vin_nom fed to the converter, gate signal
Vgs, the drain source voltage Vds of the GaN HEMT and the output voltage Vo of the
converter. In this case, it can be observed that the converter has lost its ZVS
property at the switching frequency of the converter, which was approximately
5MHz.

Figure 35. Measured waveforms of converter with RL=60 at 5MHz

In all the three cases, it can be observed that the energy efficiency of the ZVS
flyback converter with the GaN HEMT is always higher than that of the converter
using Si MOSFET. This can be explained by the following factors

Gate drive power consumption
Conduction losses of device
Switching losses of device
Input voltage
Gate signal
Drain signal
Output voltage
Lost ZVS property
49
Under the nominal input voltage condition, the measured mean input/output
currents flowing in the converter and output voltage across the load along with the
input/output powers for both the cases is given in table 7.

Table 7. Measured values of converter with GaN/Si device at 45V

At the considered switching frequency of 4MHz, the calculated gate drive power
consumption using equation (1) for converter with GaN/Si devices is 38/400mW
respectively. While driving the Si MOSFET, a gate voltage of 10V was considered
in order to have a low Rds_on for the MOSFET. For the GaN HEMT, the gate voltage
Vg was considered as being 5V, since this device becomes fully enhanced at this
voltage. Under these conditions, the corresponding measured drive power in both
cases is 40.5/475mW. This shows that for the same power transfer application, the
gate drive power consumption is 11 times higher in case of converter with Si
device when compared to converter with GaN HEMT.

The average conduction loss [95] of GaN/Si switches calculated using the following
equation (34) by knowing the measured mean current Id flowing through the
switch in both the cases is 1.9/18mW respectively. This shows that the conduction
loss is increased by approximately 9 times in the converter with Si device due to
the variation in the measured mean currents as well as the on-state resistance of
the device along with slight variation in duty cycle.
D R I P
on ds d conduction
=
_
2
(34)
In both the cases, the converter is operated in ZVS condition resulting in zero turn-
on and output capacitance losses of the device. However, the turn-off loss of the
device was obtained approximately by integrating the voltage and current
waveforms in the oscilloscope for the time duration during the overlap period.
This resulted in turn-off loss of the GaN/Si devices as 176/502mW leading to
approximately 3 times higher turn-off losses in the converter with Si MOSFET. The
losses corresponding to the aforementioned conditions are represented as bar
graph and are shown in fig.36. From this figure, it can be observed that the
switching loss and the gate drive power consumption were greatly reduced with
the assistance of the GaN HEMT when compared to its Si counterpart. Hence, it
can be concluded that the newly arrived GaN switch possesses superior
performance when compared to the state-of-the-art Si device for the considered
high frequency low power application.
Measured values of converter
Vin Iin Vo Io Pin Pout Efficiency[%] Duty cycle Frequency
GaN 45 0.202 15 0.5 9.09 7.5 82.5 46% 4MHz
Si 45 0.224 15 0.5 10.09 7.5 74.32 45% 4MHz
50
GaN
Si
Drive Power
Conduction loss
Switching loss
0
100
200
300
400
500
600
GaN vs Si
P
o
w
e
r

C
o
n
s
u
m
p
t
i
o
n

[
m
W
]

Figure 36.Bar graph representation of losses due to GaN and Si devices

In relation to the cost per unit for 10,000pcs, the commercially available GaN
HEMT costs about 1.86$ whereas the Si MOSFET is 0.57$. However, all the above
desirable features, such as low switching loss, conduction loss and gate drive
power consumption can be obtained by utilizing the GaN HEMT, which enhances
the energy efficiency and power density of the converter when compared to the Si
device.

51
5 CASCODE FLYBACK CONVERTER
In most of the AC-DC and DC-DC converter applications, the most commonly
used switching device for high frequency converter applications is the power
MOSFET. Based on the output power levels, the input voltage range and topology,
the required drain source blocking voltage of these MOSFETs are in the range of
500 - 1000V. For example, in topology point of view, in the quasi resonant flyback
converter discussed in chapter 3, the calculated and measured drain source
blocking voltages are approximately 4 times the input voltage. If the high voltage
rating MOSFETs are considered, they generally consist of a higher gate charge
when compared to the low voltage rating MOSFETs. However, in order to achieve
compact and high power density SMPS, as discussed earlier, the switching
frequency of the converter must be increased. If the switching frequency is
increased, the power required to turn on the MOSFETs is also increased, which, in
turn, leads to a higher gate drive power consumption. In order to obtain the lower
conduction losses/static losses, a low on-state resistance is required for the power
MOSFET. However a trade-off exists in the commercially available MOSFETs
between the gate charge and the on-state resistance of the MOSFET according to
FOM, which was discussed in the earlier chapter. For example, if a high voltage
MOSFET, consisting of a low Qg is selected, it consists of a high Rds_on which leads
to higher conduction losses. In order to reduce the conduction losses of these
MOSFETs, either the die area should be increased or there is a requirement for the
paralleling of the MOSFETs. In either case, the switching losses of the MOSFET are
increased due to the increased gate capacitance, which, in turn, increases the gate
drive power and reduces the switching speed of the MOSFET. Therefore, it is
necessary to look for an alternative solution to build an energy efficient, high
frequency converter with low gate drive power consumption, but without
significantly increasing the conduction and switching losses. One of the possible
solutions is to implement the cascode configuration of the switch so as to avoid the
high conduction losses, switching losses and gate drive power consumption,
particularly in high frequency and low power applications [96]. In general, a
cascode switch configuration consists of a single low voltage MOSFET and a high
voltage BJT [97] for high power applications, since a high voltage MOSFET consists
of a large on-state resistance. However, to attain a high speed converter, a MOSFET
is the better option when compared to the BJT due to the stored charge effects. In
this regard, this chapter discusses the advantage of the cascode flyback converter
for a given power transfer application when compared to a single switch flyback
converter in terms of issues related to the switching devices. In the previous
chapter, the advantages of the GaN device as compared to the state-of- the-art Si
device were explored in MHz frequency region. Since the GaN possesses a good
FOM as compared to its Si counterpart, here, the low voltage device is considered
as a high speed GaN HEMT, whereas the high voltage MOSFET is considered as a
52
Si device (due to the non existence of the high voltage GaN device). The benefits
obtained by using a cascode converter, especially with a low side GaN HEMT as
compared to Si MOSFET, are discussed.

5.1 OPERATING PRINCIPLE OF CASCODE FLYBACK CONVERTER
The circuit diagram of the cascode flyback converter is illustrated in fig. 37. In the
case of the cascode configuration, a low voltage (LV) MOSFET Q1, having a low
gate charge Qg, is connected in series with the high voltage (HV) MOSFET Q2.
The capacitor C1 in the schematic limits the drain-source voltage of the LV
MOSFET Q1 within its maximum drain-source breakdown voltage Vds_max. This
also ensures that the gate- source voltage of the HV MOSFET Q2 is within its
limits. A reservoir capacitor C2 across the gate of the HV MOSFET Q2 is charged
with the external DC source.

Rg
C2
Vdc
RL
Df
Lms
Vg
Vin
Cin
Q2
Rs
Llks
Rp
Llkp
Lmp
Cf
Cps
Q1
Rsh
C1

Figure 37. Schematic diagram of cascode flyback DC-DC converter

The operating principle of the cascode flyback converter [98] in different modes
can be explained as follows. Under ideal conditions, the gate-source and drain-
source voltage of the high voltage and low voltage MOSFETs in different modes of
operation are illustrated in fig. 38.

Mode (i) (Vgs1>Vth1 & Vgs2>Vth2): When the gate -source voltage of the LV MOSFET
Q1 ie., Vgs1 is greater than the gate threshold voltage, Vth1, the LV MOSFET Q1
becomes fully enhanced and enters the ON state. As soon as the LV MOSFET Q1
turns ON, the HV MOSFET Q2 enters the conduction state due to the voltage
across the reservoir capacitor C2. During this period, the cascode converter
achieves its conduction state and hence the current starts to flow through the
primary winding of the flyback transformer and the two switches (Q1 and Q2). In
High frequency (HF)
model of transformer
Cascode configuration of Switches
53
this state, the voltage drop across both MOSFETs is equal to their on-state forward
voltage drops. Here, during this mode of operation, the flyback diode Df is in
reverse biased condition and hence, the filter capacitor Cf supplies the load
current.

Mode (ii) (Vgs1<Vth1): When the gate-source voltage Vgs1 is less than its gate
threshold voltage Vth1, MOSFET Q1 is turned OFF. Since, the gate voltage across
the MOSFET Q2 is constant, when the MOSFET Q1 is OFF, the current takes a
path through the parallel capacitor across Q1 i.e., C1 and the gate -source
capacitance of the HV MOSFET Q2. Now the drain-source voltage Vds1 across the
LV MOSFET starts to build up. During this period, the potential of the source
terminal of the HV MOSFET Q2 starts to increase.

Figure 38. Gate and drain voltages of the switches in cascode converter

Mode (iii) (Vgs2<Vth2): As the potential of the source terminal of the HV MOSFET
Q2 builds up in the previous mode, the gate-source voltage Vgs2 of the HV
MOSFET is reduced and when it reaches its gate threshold voltage Vth2, the HV
MOSFET Q2 is turned OFF. From this moment, the drain-source voltage Vds2 of
the HV MOSFET Q2 starts to build up. Under this condition, the current in both
the switches now attempts to flow in the drain-source capacitance of the HV
MOSFET Q2, the drain-source capacitance of the LV MOSFET Q1, its parallel
capacitor C1 and into the reservoir capacitor C2. To a small extent this current
also flows into its Miller capacitance.

Mode (iv) (Vgs1<Vth1 & Vgs2<Vth2): When the gate-source voltages of both switches
t
t
t
t
Gate Source
Voltage of LV
device
Drain Voltage
of LV device
Gate Source
Voltage of HV
device
Drain Voltage
of HV device
54
Q1 and Q2 are less than their corresponding gate threshold voltages, the switches
enter the complete turn OFF condition. In this case, the flyback diode Df enters the
ON state and the stored energy in the secondary winding is fed to the load
resistance, RL.

Since the LV MOSFET Q1 consists of a low gate charge, the gate drive power
consumption due to Q1 is considered to be negligible. The DC current flowing
into the gate of the HV MOSFET Q2 is also negligible because of the equalization
of the amount of charge entering and leaving the capacitor C2 [98] during the turn
ON/turn OFF process, respectively, neglecting the initial charge of the capacitor. In
this manner, the drive power required to switch the HV MOSFET is almost zero
and that of the LV MOSFET is negligible.

5.2 MULTILAYERED CORELESS PCB STEP DOWN 8:1 TRANSFORMER
In order to evaluate the cascode switch flyback converter w.r.t a traditional single
switch flyback converter in the MHz frequency region for the given power transfer
application, an approximately 8:1 turns ratio flyback transformer was designed as
per the procedure described in chapter 3. The transformer was designed on a four
layered PCB and it is of primary-secondary-secondary-primary (PSSP) structure.
The 3D view of the designed transformer together with the prototype is illustrated
in figs.39 (a) and (b) respectively.

(a) (b)
Figure 39. (a) 3D view and (b) prototype of 8:1 coreless PCB transformer of (37x37x1.48)mm
The two primaries on the top and bottom layers of the PCB are connected in series
and the two inner layers, which constitute the secondary windings, are connected
in parallel. The number of turns in each layer of the PCB is 24 where 4 no. of turns
in the secondary layer are connected in parallel resulting in 6 secondary turns. The
corresponding inner/outermost diameters of the transformer are 11.7/36.7mm.
The measured primary/secondary DC resistances Rp/Rs of the transformer using
agilent multimeter are 2.46/0.01. The electrical parameters of the transformer,
such as the self/leakage inductance of the primary and secondary are
29.38H/1.9H and 0.548H/0.038H, respectively and these are obtained as
described in section 3.2.2. The interwinding capacitance of the transformer is 125pF
and the intrawinding/self capacitances of these transformers are considered as
55
almost negligible. The achieved coupling coefficient K of the transformer [99] is
0.93. This multi-layered coreless PCB transformer was utilized in both the cascode
flyback converter and single switch flyback converter and the performance of these
converters was evaluated in the MHz switching frequency region.

5.3 SIMULATION AND EXPERIMENTAL RESULTS OF CASCODE AND SINGLE SWITCH
FLYBACK CONVERTER
With the assistance of SIMetrix software, the simulations were carried out for the
cascode and the traditional flyback converters using MLCLPCB transformer. As
discussed earlier, the soft switching techniques enables the high frequency
operation, high energy efficiency, compact and light weight converters. Therefore,
both the cascode and single switch flyback converters were maintained to be
operated under ZVS conditions. Based on the simulation results and analysis, the
prototype was designed and then tested under the following conditions:

DC input voltage to converter: 60-120V with Vnom of 90V
Full load resistance of the converter: 10
Switching frequency range : 2.6 - 3.7MHz

The simulations and experiments were conducted by considering the following
cases while evaluating the performance of the cascode converter w.r.t a single
switch flyback converter
Case (i): Cascode converter with Q1 as Si LV MOSFET: ZXMN15A27K and Q2 as
Si HV MOSFET: STP3NK60ZFP
Case (ii): Cascode converter with Q1 as GaN HEMT: EPC1013 and Q2 as Si HV
MOSFET: STP3NK60ZFP
Case (iii): Traditional flyback converter shown in fig.18 with switch as Si HV
MOSFET: STP3NK60ZFP
The important parameters for the devices utilized in the converter circuits are
listed in table.8
Table 8. Parameters of devices in cascode & traditional flyback converter
S.No Switch Vds_max (V) Id (A) Rds_on () Qg (nC) Coss (pF) Material
I ZXMN15A27K 150 2.4 0.65 6.6 64.5 Si
II EPC1013 150 3.0 0.1 1.7 85 GaN
III STP3NK60ZFP 600 2.4 3.3 11.8 43 Si

In all the cases, the secondary side diode considered is a Si Schottky SR1660, whose
reverse blocking voltage capacity is 60V and with a forward current rating of 16A.
In the case of the cascode converter, the HV MOSFET Q2is driven by a supply
voltage of 12Vdc with a charging capacitor of 10F.

The simulation waveforms of the cascode flyback converter i.e., case (i) for an
56
input voltage of 70V and full load condition of 10 are illustrated in fig.40. The
figure shows, from top to bottom, the gate-source voltage fed to LV MOSFET Q1
(Vg), drain-source voltages Vds_max of both MOSFETS Q1 & Q2 , the output voltage of
the converter (Vo), and the voltage across the shunt resistor Rsh i.e., Vsh. From the
figure, it can be observed that the HV switch is operating under the ZVS condition
where as the LV MOSFET is operating under the hard switched condition.

V
o

/

V
10.78
10.79
10.8
10.81
10.82
V
g

/

V
0
4
8
Q
2
_
D
r
a
i
n

/

V
50
100
150
200
250
Q
1
_
D
r
a
i
n

/

V
2
4
6
8
10
149.1 149.2 149.3 149.4 149.5 149.6 149.7 149.8 149.9 150
V
s
h

/

m
V
-50
50
150
250
350

Figure 40. Simulated waveforms of cascode converter, case (i)
Under the same conditions, the measured waveforms of the converter are shown in
fig.41. The same phenomena can be observed w.r.t ZVS in the measured
waveforms of the converter.

Figure 41. Measured waveforms of cascode converter with RL=10
Gate signal of LV
MOSFET
Voltage across shunt Rsh
Drain signal of LV MOSFET
Drain signal of HV MOSFET
Gate signal of LV MOSFET
Voltage across shunt Rsh
Drain signal of LV
MOSFET
Drain signal of HV
MOSFET
Output Voltage Vout
57
The simulated and measured energy efficiencies of the unregulated converter in all
three cases for the input voltage variations are illustrated in fig. 42 including the
gate drive power consumption at a duty cycle ratio of 50%. The maximum load
power attained in all three cases is 30W and all the measurements and
comparisons were made at approximately the same power levels for the
considered input voltage range [99]. This figure shows that the simulated and
measured energy efficiencies of the converters are in good agreement with each
other. From this figure, it can be observed that the converter energy efficiency is at
a maximum in the case of the cascode converter with the GaN HEMT followed by
the cascode converter with the Si MOSFET and then the traditional single switch
flyback converter. At a nominal input voltage of 90V, the energy efficiencies of the
cascode converter with the GaN HEMT/Si MOSFET are 80.4%/79.5%, respectively
and for the single switch flyback converter i.e., case (iii) it is only 76.4%.
60 70 80 90 100 110 120
70
72
74
76
78
80
82
V
in
(Volts)
E
f
f
i
c
i
e
n
c
y
,

(
%
)

Case(i)
Case(ii)
Case(iii)

Figure 42. Simulated (Solid) and Measured (Symbol) efficiency of
cascode & traditional flyback converter

Gate drive power consumption:
The measured gate drive power consumption in case (i) is 0.28W whereas in case
(ii) it is 0.05W and in case (iii) it is 0.6W. This shows that the gate drive power
consumption in the case of the cascode flyback converter using the GaN HEMT is
negligible because of the low gate charge, Qg. If the comparison is made between
case (i) and case (ii), at higher input voltages, no significant improvement exists in
terms of energy efficiency as the contribution of the gate drive power consumption
is negligible. However, at lower input voltages, the energy efficiency in case (ii) is
increased because of the large contribution of gate drive power consumption for
low powers. Due to this factor, from fig. 42, it can also be observed that the energy
efficiency of the single switch flyback converter is drastically reduced as compared
to the other two cases, particularly at lower input voltages because of the high
58
influence of the gate drive power consumption.

Conduction losses:
In the case of the cascode flyback converter, because of the two MOSFETs, the
static/conduction losses are increased due to the summation of the Rds_on of both
the devices. Therefore, the conduction losses of the devices, in all three cases, were
measured at a given power and at a nominal input voltage of 90V. By knowing the
measured mean current flowing through the switch, duty cycle and the Rds_on of
devices, the conduction losses using equation (34) are obtained as, case (i): 0.133 W,
case (ii): 0.118 W and in case (iii): it is 0.115 W. From the measured conduction
losses, it can be observed that, due to the desirable feature of having low Rds_on in
case of GaN HEMT, the conduction losses in case(ii) are comparable with that of
the case (iii). However, it is not the same case if we compare the case (i) and case
(iii).
From the measured gate drive power consumption and the conduction losses in all
three cases, it can be observed that the gate drive power consumption is the
dominant factor when compared to the conduction losses of the MOSFETs, which
influences the change in the energy efficiency of converters. Therefore, due to the
low gate drive power consumption using GaN device, cascode topology has
advantages in the high frequency SMPS particularly in low power and light load
conditions as compared to the single switch flyback converter.

Switching frequency:
The maximum switching frequency of the cascode converter at Vin of 120V with the
Si MOSFET/GaN HEMT as low voltage devices were found to be 3.45/3.65MHz,
respectively whereas in the case of the single switch flyback converter it is only
2.88MHz. It is due to the fact that, in case of cascode flyback converter, the
MOSFET gate driver is required to drive a very small capacitive load due to the LV
MOSFET. In addition to this, due to the cascode arrangement of the LV and HV
switches, the Miller capacitance of the combination gets reduced which results in
increased switching speeds of converter.

Increased blocking voltage capacity and reliability of composite switch:
Another advantage regarding the use of the cascode converter is that the
breakdown voltage capacity of the cascode switch gets increased when compared
to that of the single switch flyback converter and thereby the reliability of the
switch gets increased. In addition to this, the stress of the HV MOSFET gets
slightly shared by the LV MOSFET in case of cascode switch flyback converter [99].

5.4 LOSS ESTIMATION OF CASCODE CONVERTER
The loss estimation was made for case (i) under the following conditions. At the
59
nominal input voltage of 90V, with a load resistance of 10, the input/output
powers for the converter are 21.1/16.8W, respectively, which leaves a total loss of
about 4.3W. At this instant, the switching frequency of the converter is 3.45MHz.

a) Transformer Losses: The measured RMS currents flowing through the
primary/secondary windings of the transformer are 0.252/1.7A. The measured AC
resistance of the primary/secondary winding at 3.45MHz are 5.8/0.446 and hence
the copper losses of the transformer, given by the following equation, are obtained
as 0.36/1.28W, respectively.
( ) ) ( ) (
2 2
s R i p R i P
ac s ac p loss
+ = (35)
where,
ip/is- RMS currents through primary/secondary winding
Rac(p)/Rac(s) - Primary/secondary winding ac resistance

b) MOSFET Losses: These losses consist of both the conduction and switching
losses [59]. The measured mean current flowing through LV/HV MOSFETs is
0.232A. The corresponding calculated average conduction losses using equation
(34) are 0.020/0.113W, respectively.

Since, the converter was not fully operated under the ZVS condition, it experiences
some of the turn-on losses. In addition to this, there exists also the turn-off losses
which can be estimated [68] by the following equation (36).

( )
sw d ds off on switching
f I V t t P + = 5 . 0 (36)
where
ton turn-on switch transition time
toff turn-off switch transition time
Vds drain source voltage
Id current through MOSFET
fsw switching frequency
Under the above mentioned conditions, the estimated switching losses of the
LV/HV MOSFETs using the above equation are 0.439/0.604W.

c) MOSFET driver loss: The theoretical power consumption of the gate driver was
estimated by using equation (1). The calculated/measured MOSFET driver losses
are found to be 0.27/0.28W.

d) Diode Losses: The flyback diode conduction loss [95] obtained by using the
following equation is 0.388W.
( ) D I V P
avg D f diode
= 1
_
(37)
where,
60
Vf - Diode forward voltage drop
ID_avg - Average current flowing through the flyback diode

E) Miscellaneous losses: It consists of Coss loss of MOSFETs, switching losses of
the secondary rectifier diode and the remaining circuit losses.
All the above computed losses are illustrated as a pie diagram and shown in fig.
43. Under these conditions, the temperature profile of the cascode converter circuit
including the transformer, LV/HV MOSFETs, driver and flyback diode are
illustrated in fig.44.
6%
9%
14%
10%
23%
3% < 1%
21%
14%
Transformer Primary Loss
Transformer Secondary Loss
Q
1
Conduction Loss
Q
2
Conduction Loss
Q
1
Switching Loss
Q
2
Switching Loss
Driver Loss
D
f
Conduction Loss
D
f
Switch Loss + Q
1
&Q
2
Coss + Circuit

Figure 43. Loss estimation of cascode converter Case (i)

Figure 44. Thermal profile of cascode converterCase (i)

This figure illustrates the temperature for the area of the switch STP3NK60ZFP
(Q2) Ar1, area of the transformer Ar2, area of the switch ZXMN15A27K (Q1)
Ar3, area of the Schottky diode SR1660 Ar4, MOSFET Driver LM5111 Ar5.
The loss contributed by the multi-layered coreless PCB transformer is around 38%
of the total loss. Further, by reducing the primary/secondary resistances of
Transformer
Q
2

Q
1

MOSFET
Driver
Diode
61
transformer and, also, by maintaining the exact ZVS conditions, a highly energy
efficient and low profile cascode flyback converter can be achieved.

From the experimental analysis, it can be observed that the cascode switch
configuration has many advantages particularly with the assistance of GaN HEMT,
such as low gate drive power consumption, lower switching losses and possible
higher switching frequencies for the converter without increasing the significant
amount of conduction losses. The improved energy efficiency and high reliability
of the converter can be obtained with the help of composite switch comprising
GaN HEMT. In this regard, the current industrial trend is towards the introduction
of the high voltage composite structure of GaN HEMTs [91], [100], [101] (GaN on Si
substrate) in order to achieve energy efficient high power density converters.

62
6 GATE DRIVE CIRCUITRY FOR HIGH SPEED DOUBLE ENDED
CONVERTER TOPOLOGIES
In all chapters from 2 - 5, the discussions have involved single ended topologies
such as the single switch quasi resonant flyback and cascode flyback converters
operating in the MHz frequency region by employing soft switching techniques. In
cascode and single switch quasi resonant flyback converters, it can be observed
that the peak voltage stress on the semiconductor devices is high for the given
input/output voltage specifications under ZVS conditions. For example, in the case
of the cascode flyback converter discussed in an earlier chapter, the stress on the
HV MOSFET is about 480V for the DC input voltage of 120V with an output
voltage of approximately 17V. If this is the case, then a MOSFET rating of
approximately greater than 1kV is required for the universal input voltage range of
the 85 - 265VAC, which in turn increases the gate charge and on state resistance of
the MOSFET. On the other hand, if the double ended converter topologies such as
the half bridge converter and the derived converter topologies are chosen, the
drain source voltage is clamped to the input voltage and, additionally, the stress of
the single switch can be shared by the two MOSFETs. In addition to this, for a
given power transfer application, the size of the transformer can be reduced in
double ended converter topologies due to its full utilization as compared to that of
the transformer in single ended converter topologies [102], [103]. However, in
order to drive the high side MOSFET at higher input voltages (125V) and
frequencies greater than 1MHz, to the authors knowledge, no commercially
available isolated MOSFET gate drivers exist [104]. Therefore, it is necessary to
design individual gate drive circuitry in order to operate the converters at higher
switching frequencies as well as for high input voltages to drive the high side
MOSFET with galvanic isolation. Hence, this chapter focuses on the design of
passive gate drive circuitry using low profile MLCLPCB gate drive transformers,
suitable for operating in the MHz frequency region. Here, multilayered
transformers are considered instead of a two layered transformer in order to
reduce the winding resistance [105], transformer area and EMI emissions [106].

6.1 GATE DRIVE CIRCUIT DESIGN USING MULTILAYERED CORELESS PCB
TRANSFORMER
Floating gate drive circuitry is required in all the double ended converter
topologies such as half-bridge, full-bridge and resonant converters. For this
isolation purpose, either a gate drive transformer or an optocoupler can be utilized.
In this case, the function of using a gate drive transformer/optocoupler is to
transfer the ground referenced signals with galvanic isolation in order to drive the
high side MOSFET gate w.r.t floating ground on the other side. However, the
traditional optocouplers are very slow and the high speed digital optocouplers are
quite expensive. Therefore, an alternative solution is to use the transformer
63
isolated gate drive circuitry. In this regard, a high frequency MLCLPCB
transformer of unity turns ratio was designed and manufactured. The performance
characteristics of the designed transformer are given in [107]. The high side gate
drive circuitry together with the high frequency model of the MLCLPCB
transformer and other passive elements is illustrated in fig. 45. The dimensions of
the designed MLCLPCB transformer are 8.75x8.75x1.48mm. In addition to this, a
high frequency NiZn, 4F1 material flat ferrite plates of 10mm diameter are used on
both sides in order to achieve the desired inductance as well as to reduce the
magnetizing current, thus leading to low gate drive power consumption as
discussed in [107]. Here, the driver output is coupled to the transformer with the
assistance of a DC blocking capacitor C1 [108].

1K
R4
20
R3
Vdriver 790m
R2
169p
C3
100n
C2
100n
C1
440n
L3
1.5u
L2
1.4u
L1
450n
L4
BZX79-9V1 D1
11p
C4
780m
R1
V1
Vgate
3G
R5

Figure 45. High side gate drive circuitry using MLCLPCB transformer

The secondary side of the transformer is connected to a level shifting circuitry
using a capacitor C2 and zener diode D1. Here, this diode also acts as a transient
voltage protection device [109]. After the level shifting circuit, a series resistor R3
of 20 is used in order to reduce the EMI [109] due to fast turn-on/turn-off, the
noise of the PWM controller, clock jitter etc., Since the gate drive circuitry is
designed for a MOSFET load, which is capacitive in nature, in this case a parallel
combination of resistor R4 and capacitor C3 is considered as the load.

6.2 SIMULATION RESULTS OF GATE DRIVE CIRCUITRY
The simulated waveforms of the drive circuit shown in fig.45 for duty cycle ratios
of 20% and 45% at an operating frequency of 2MHz are depicted in figs. 46 (a) and
(b), respectively. From top to bottom, these figures illustrate the driver output
voltage Vdriver and the gate signal Vgate fed to the MOSFET load. Similarly, the
simulated drive signals for the switching frequency of 4MHz and for the
corresponding duty cycles are also depicted in figs. 47 (a) and (b). Here, the
maximum duty cycle ratio is considered to be 45%, since in double ended
converter topologies, the duty cycle is limited by the dead time between the two
High frequency model of gate drive
transformer
Level shifting circuit
MOSFET load
64
switches. From these figures, it can be observed that these transformers possess
wide frequency bandwidth, which is useful for the regulation of the converter in
terms of large input voltage and load variations.

V
d
r
iv
e
r

/

V
0
2
4
6
8
10
12
197.6 197.8 198 198.2 198.4 198.6 198.8 199 199.2 199.4 199.6 199.8
V
g
a
t
e

/

V
-0
2
4
6
8

V
d
r
iv
e
r

/

V
0
2
4
6
8
10
12
197.6 197.8 198 198.2 198.4 198.6 198.8 199 199.2 199.4 199.6 199.8
V
g
a
t
e

/

V
-0
2
4
6
8

(a) (b)
Figure 46. Drive signals of high side MOSFET for (a) 20% & (b) 45% of duty cycle at 2MHz

In addition to this, it can also be observed that for low duty cycle ratios, a ringing
exists prior to the turn on of the switch due to the high leakage inductance of the
transformer. These signals can be further improved based on an optimal design for
the gate drive transformer. However, since the ringing voltage is far below the
threshold voltage of the MOSFET, it does not lead to the mistriggering of the
switching device. Therefore, this gate drive circuitry is employed in various
converter topologies, such as half bridge converter [110] and the series resonant
converter circuit in the MHz switching frequency range and for higher input
voltages. In the following sections, the experimental result of designed gate drive
circuitry is discussed.

V
d
r
iv
e
r

/

V
0
2
4
6
8
10
12
198.6 198.8 199 199.2 199.4 199.6 199.8
V
g
a
t
e

/

V
-0
2
4
6
8

V
d
r
iv
e
r

/

V
0
2
4
6
8
10
12
198.6 198.8 199 199.2 199.4 199.6 199.8
V
g
a
t
e

/

V
-0
2
4
6
8

(a) (b)
Figure 47. Drive signals of high side MOSFET for (a) 20% & (b) 45% duty cycle at 4MHz

65
6.3 EXPERIMENTAL RESULTS OF GATE DRIVE CIRCUIT
After the simulation of the gate drive circuitry, for the testing of the circuit, the
evaluation has been conducted using double ended converter topologies; half
bridge [110] and series resonant converters (SRC) [107]. As per the converter
specifications, the low side and high side MOSFETs considered in SRC are
ZXMN15A27K ,whose typical input capacitance Ciss is of 169pF and gate charge
Qg of 6.6nC. In this regard, while simulating the circuit, the load capacitance is
considered to be 169pF. Here, in this circuit, the low side MOSFET was driven
from one of the out pins of the LM5111 gate driver, whereas the high side MOSFET
was driven by using the designed gate drive circuitry. The simulated and
measured gate drive signals of the SRC are depicted in figs. 48 (a) and (b),
respectively. Here, the switching frequency of the converter is 2.3MHz with the
switch duty cycle ratio of 40%.

V
d
r
i
v
e
r

/

V
0
2
4
6
8
10
12
197.6 197.8 198 198.2 198.4 198.6 198.8 199 199.2 199.4 199.6 199.8
V
g
a
t
e

/

V
-0
2
4
6
8
Vgate
Rise Time (10%-90%)=23.131903nSecs
Fall Time (10%-90%)=19.292258nSecs
Vdriver

(a) (b)
Figure 48. (a) Simulated and (b) measured drive signals of low side and high side MOSFETs
in SRC

From figure 48, it can be observed that the simulated/measured rise and fall times
of high side MOSFET are 23.13/17.53ns and 19.29/19.92ns, respectively.

6.4 GATE DRIVE POWER CONSUMPTION
In order to evaluate the performance of the designed gate drive circuitry in the
obtained wide operating frequency region, it is required to determine the gate
drive power consumption of the circuit. Therefore, in this section, the measured
gate drive power consumption of the designed circuitry will be discussed.

The block diagram representation of the practical gate drive circuitry from a 12V
lab power supply is represented in fig. 49.

Here, a buck regulator which steps down the voltage from 12V to 3.3V is chosen to
drive the dsPIC micro-controller dspic33fj16gs502. The input voltage required for
Gate signal of low side MOSFET
Gate signal of high side MOSFET
66
the MOSFET driver is fed directly from the lab power supply. The total power
consumption of the gate drive circuit is measured as a function of frequency and is
illustrated in fig. 50. This figure shows the power consumption of the total circuit
Ptotal, the power consumption of the switching regulator alone, Psw, the MOSFET
gate drive power (while driving both the MOSFETs) given as Pdriver, the power
consumed by the microcontroller Pctrl.

Figure 49. Block diagram for measurement of gate drive power consumption
1 1.5 2 2.5 3 3.5 4 4.5
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Frequency [MHz]
P
o
w
e
r

C
o
n
s
u
m
p
t
i
o
n

[
W
]

P
total
P
reglator
P
driver
P
ctrl

Figure 50. Gate drive power consumption in Series Resonant Converter (SRC)

12V
Lab power Supply

12 - 3.3V
Switching
regulator
Microcontroller
dsPIC
Gate
Driver
Drive
Transformer
Low side
MOSFET
High side
MOSFET
Level Shifter
67

From fig.50, it can be observed that the gate drive power consumption Pdriver is
well below 1W for the entire frequency range. It is comparatively low in the
frequency range of 1.5 3.75MHz, due to higher input impedance of transformer
and it is 0.663W at 2MHz.

However, from 1.1 - 1.5MHz frequency region, the gate drive power consumption
is increasing in nature because of the low input impedance of the gate drive
transformer and also above 3.75MHz; it is increasing since the frequency
dependent losses increase.

Since the designed gate drive circuitry provides the desirable switching signals
with low power consumption, this circuitry was practically implemented in SRC
and successfully tested in the MHz frequency region for power transfer application
and the details of it are covered in the next chapter.

68
7 DESIGN AND ANALYSIS OF HIGH FREQUENCY SRC USING
MLCLPCB SIGNAL AND POWER TRANSFORMERS
As discussed previously, the double ended converter topologies are becoming
popular for low-medium power applications due to the full utilization of
transformer. In addition to this, by employing a resonant conversion process in the
converter circuit, the switching losses and the EMI emissions [51], [111], [112] from
the converter and transformer can be greatly reduced. This enables the converter to
operate at higher switching frequencies with low MOSFET stresses without
sacrificing the energy efficiency. Resonant converter topologies, which are being
investigated intensively [2], [8], results in very low switching losses, thus enabling
the converters to operate at higher frequencies. Therefore, for obtaining the energy
efficient converters in the MHz frequency region, resonant converter topologies
such as series resonant converter (SRC), parallel resonant converter (PRC) and
series-parallel resonant converter (SPRC) or LLC resonant converters are the most
popular topologies. Since these converter topologies consist of both high side and
low side switches, the designed passive gate drive circuitry discussed in chapter 6
is applied to drive the high side MOSFET in the resonant converter topology. Also,
the designed energy efficient MLCLPCB half bridge power transformer, whose
design guidelines are proposed in [107], is employed in the SRC and evaluated for
higher switching frequencies.
Therefore, this chapter deals with the design and analysis of the SRC implemented
in MHz frequency region for the given power transfer application.

7.1 SERIES RESONANT CONVERTER
The circuit diagram and DC gain characteristics of the SRC are illustrated in figs.51
(a) and (b), respectively. In the case of the series resonant converter (SRC)
topology, the resonant elements such as Lr and Cr are connected in series with the
load [8], [28] as shown in fig.51 (a). Here, the resonant tank circuit and the load
network act as a voltage divider and hence the maximum gain attainable in the
SRC is unity and occurs at a resonant frequency as shown in fig.51 (b).

As the operating frequency of the converter changes, the impedance offered by the
resonant network varies and hence the input voltage Va is divided between the
resonant tank circuit and the load, proportionately. Since in power MOSFETs, ZVS
is preferred to the ZCS as discussed earlier, the operating frequency region of the
SRC lies on right hand side of the DC gain characteristics and is represented as a
shadow area where the DC gain characteristics possess the negative slope. Apart
from the ZVS operation of the converter, operating the converter above resonant
frequency fr, offers many advantages such as, inherent short circuit protection,
reduced harmonic components, utilization of transformer leakage inductance [113]
69
etc., The characteristic impedance Zch and resonant frequency fr, of the circuit can
be obtained from equations (24) and (25), respectively.

(a) (b)
Figure 51. (a) Schematic diagram and (b) DC gain characteristics of SRC [8]

The quality factor Q, which is a function of characteristic impedance Zch and the
load resistance RL can be obtained by the following equation.

L
ch
R
Z
Q = (38)
From the DC gain characteristics of SRC, it can be observed that for regulating the
output voltage of the converter under light load conditions, the switching
frequency of the converter has to be increased to a very high value (theoretically :
towards infinity) which was previously considered to be a severe drawback in this
converter. However, this drawback of the converter can be eliminated with the
solution provided in [113]. From the DC gain characteristics shown in fig.51 (b), it
can be observed that under lower input voltage condition, the switching frequency
of the converter is closer to the resonant frequency whereas the frequency is
increased at higher input voltages. Thus, a high circulating current [8] flowing
through the resonant tank circuit exists, which is also considered as one of the
drawbacks of the SRC. However, due to the aforementioned advantages, the SRC
is considered and evaluated using MLCLPCB signal and power transformers.

7.2 MULTILAYERED CORELESS PCB HALF BRIDGE POWER TRANSFORMER
For the given converter specifications, the multilayered coreless PCB half bridge
center tapped power transformer is designed and evaluated. The structure of the
transformer is considered as a primary-secondary-secondary-primary (PSSP) in
order to obtain the desired leakage inductance of the transformer without using
any external resonant inductor. The outermost radius/height of the PCB of the
transformer is 10mm/1.48mm, respectively [107]. The measured electrical
parameters of the transformer at 1MHz are given in table 9.
70
Table 9. Electrical parameters of transformer at 1MHz
Lp[H] Llkp[H] Ls[H] Llks[H] Cps[pF] K n
7.89 1.95 0.65 0.16 30 0.75 3.51
The transformer has been evaluated for the load power range of 0.1 50W at
maximum energy efficiency frequency (MEEF) of 2.6 MHz. The measured energy
efficiency of the transformer for sinusoidal excitation is reported to be in the range
of 87 - 96% with the achieved power density of 107W/cm
3
. Since, the transformer
possesses the desired performance characteristics; it was evaluated using SRC in
MHz frequency region which will be discussed in the coming sections.

7.3 SIMULATION AND EXPERIMENTAL RESULTS OF SERIES RESONANT CONVERTER
The converter was initially simulated and then experimental work has been carried
out by considering the following specifications.

DC input voltage range : 60 -120V with 90V as nominal voltage
Load resistance range : 10 - 30
Switching frequency : 2 - 3MHz

For the above mentioned converter specifications, the low side and high side
MOSFETs were considered as ZXMN15A27K from the Diodes Corporation, whose
breakdown voltage is 150V and whose on-state resistance and gate charge are
0.65 and 6.6nC, respectively. The secondary side rectifier diode is the SR1660,
whose reverse blocking voltage is 60V with a maximum average forward current
rating of 16A. The maximum forward voltage drop and the junction capacitance of
the diode/leg are 0.7V and 120pF, respectively. The schematic diagram of the SRC
is depicted in fig.52.

R2
R1
V2
D3
C1
L2
Q2
Cr
D2
CF
Lmp
Llkp
Cps1
Lms1 RL
Vin
Cin
Rp
Llks2
Lms2
D1
Llks1
Rs2
Rs1
Q1
L1
C2
D4
V3
U1
U2
Cps2
Cres

Figure 52. Schematic diagram of SRC with high frequency model of power transformer
HF model of power
transformer
Signal transformer
U1 & U2: MOSFET drivers
71
From the primary/secondary leakage inductances of the transformer, the resonant
inductance given by the following equation is obtained as 3.94H.
lks lkp r
L n L L
2
+ = (39)
A resonant capacitor Cr of 1.36nF is considered in series with the transformer
primary so that the calculated resonant frequency of the converter using equation
(25) is obtained as 2.17MHz. The voltage rating of the capacitor is considered as
200V with 5% capacitance tolerance. As discussed in section 7.1, the operating
frequency region of the converter lies above 2.17MHz, which falls within the
required switching frequency range of the converter without utilizing any external
resonant inductor. A resonant capacitor Cres across the secondary winding is
considered as 240pF so that the MEEF of the transformer lies in the switching
frequency region of the converter. Here, it is important to select the resonant
capacitor across the secondary winding of the transformer carefully such that it
does not vary the characteristics of the SRC. With the considered resonant
capacitor across the secondary winding and the interwinding capacitance of the
transformer, referred to primary [52], obtained by equation (40) being 33pF, which
is very small and hence can be neglected.
1
2 2
'
1
2
1
ps res res
C
n
n
C
n
C |
\
|
+ |
\
|
= (40)
7.3.1 DC gain characteristics of SRC
The DC gain characteristics of the SRC for various load conditions are illustrated in
fig.53 which calculated by using the equations (41) (44).
0.4 0.6 0.8 1 1.2 1.4
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Normalized Frequency, [F
sw
/F
r
]
G
a
i
n

10
15
20
25
30
Q=1.8
Q=5.4
Increasing Q

Figure 53. Calculated DC gain characteristics of SRC
|
|
\
|
+
=
ac
C
ac
L
gain
R
X
R
X
j
V
1
1
(41)
72
where,
r sw L
L f X . 2 = (42)
r sw
C
C f
X

=
2
1
(43)
2
2
8
L
ac
R n
R
= (44)

7.3.2 Simulation results of SRC
The converter has been initially simulated by using a high frequency model of
signal and power transformers for the above mentioned input voltage
specifications and for the load resistance of 15. The simulated waveforms of the
converter for a nominal input voltage of 90Vdc are illustrated in fig.54.

Figure 54. Simulated waveforms of SRC at 2.6MHz
From top to bottom, the figure illustrates the gate and drain signals of low side
MOSFET and high side MOSFETs, primary voltage/current, voltage across series
Gate Voltage of Q2
Drain Voltage of Q2
Gate Voltage of Q1
Drain Voltage of Q1
Primary Voltage
Primary Current
Capacitor Voltage
Secondary Voltage
Secondary Current
Input Current
Output Voltage
Load Current
73
resonant capacitor Cr, secondary voltage/current, input current of the circuit and
output voltage/current, respectively. The simulation was carried out at a switching
frequency of 2.6MHz with each switch duty cycle ratio being 41%. The output
voltage of the converter for the load resistance of 15 is 14.7V resulting in the
energy efficiency of the converter as 86.2%.

7.3.3 Prototype of SRC
Based on the simulation results, the converter prototype was built and the
measurement was carried out for the considered converter specifications. The
prototype of the designed SRC is illustrated in fig. 55. The controller and power
components are on either side of the PCB and the power transformer prototype
together with the signal transformer are connected to the converter through the
interface pins as shown in fig. 55.

Figure 55. Prototype of SRC with MLCLPCB signal and power transformers

7.3.4 Experimental evaluation of SRC
Under the same conditions of 90Vdc input, load resistance of 15 and, at a
switching frequency of 2.6MHz, the measurements were conducted on the
prototype and the corresponding switching waveforms were illustrated in fig.56.

Figure 56. Measured switching waveforms of SRC at 2.6MHz
Converter prototype
Signal transformer
Power transformer
Gate signal of Q2
Drain signal of Q2
Transformer primary voltage
Transformer primary current
Interface pins
74
From figures 54 and 56, it can be observed that the MOSFETs are operating under
the ZVS condition. Here, the dead time between the low side and high side
MOSFETs are considered as 39ns in order to prevent the short through currents.
The measured energy efficiency of the unregulated converter as a function of the
input voltage for different load conditions is illustrated in fig.57 (a). The energy
efficiency of the converter at a nominal input voltage of 90Vdc and with a load
resistance of 15 is 85.8%, with an achieved output voltage of 14.68V. From this, it
can be observed that the measured values agree well with the simulated ones. The
input/output powers of the converter under these conditions are 16.74/14.36W,
respectively. The maximum tested output power of the converter is 34.5W at
input/output voltages of 120V and 18.5V, respectively, with the achieved energy
efficiency of 85.2%. The measured peak energy efficiency of the converter is
reported to be 86.5% and can be observed from fig.57 (a) at an input voltage of
100V. The energy efficiency of the regulated SRC is depicted in fig.57 (b). Here, the
input/output voltages of the converter are 120/20V, respectively. The output
voltage is open loop regulated to 20V by considering a 2% tolerance and using a
constant OFF time frequency modulation.
60 70 80 90 100 110 120
65
70
75
80
85
90
Input Voltage,V
in
[V]
E
n
e
r
g
y

E
f
f
i
c
i
e
n
c
y
,

[
%
]

R
L
=10
R
L
=15
R
L
=20
R
L
=25
R
L
=30
15 20 25 30
65
70
75
80
85
90
Load Resistance,R
L
[]
E
n
e
r
g
y

E
f
f
i
c
i
e
n
c
y
,

[
%
]

V
in
=120V

(a) (b)
Figure 57. Measured energy efficiency of (a) unregulated and (b) regulated SRC

7.3.5 Loss estimation and thermal profile of SRC
At a nominal input voltage of 90V, the loss estimation of the converter has been
carried out. The total loss of the converter under these conditions is 2.38W, which
are distributed by various elements of the converter and is depicted as a bar graph
in fig.58 (a). The corresponding thermal profile of the converter is illustrated in
fig.58 (b). The thermal profile of the converter shows the spot temperatures of the
transformer Sp1, low side MOSFET Sp2, series resonant capacitor Sp3, high
side MOSFET Sp4 and diode rectifier Sp5. From fig.58 (a), the loss contributed
by the multilayered coreless PCB power transformer is 1W, which is 42% of the
total losses due to the fact, that for achieving the desired amount of inductance,
many turns are required in the coreless PCB transformer which in turn increases
75
the AC resistance of the transformer in MHz frequency. As a result the copper
losses in the transformer gets elevated which is considered as one of the
bottlenecks of the coreless PCB transformer. From the thermal profile of the
converter, it can be observed that the series resonant capacitor has a high spot
temperature, which can be reduced by using a C0G ceramic capacitor. Based on the
results proposed, in future, by optimizing the transformer (with advanced winding
strategies such as planar litz for further reduction of AC resistance), by using high
performance GaN HEMTs and with the assistance of C0G ceramic capacitors,
highly energy efficient, low profile converter using MLCLPCB transformers can be
realized.

Q_cond
CAP
D_cond
Q1_Sw
Q2_Sw
Psec
Ppri
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
P
o
w
e
r
L
o
s
s

[
W
]

(a) (b)
Figure 58. (a) Loss estimation and (b) thermal profile of SRC at nominal input voltage of 90V

76
8 HIGH FREQUENCY MULTIRESONANT CONVERTER USING PLANAR
TRANSFORMER
In chapters 2 - 7, the discussions have involved the single ended and double ended
converter topologies using coreless PCB transformers operated in the MHz
frequency region. The maximum energy efficiency of the SRC obtained by using
this multilayered coreless PCB transformer is 86.5% and the maximum tested
output power level of the converter is 34.5W. Here, the loss contribution of the
coreless PCB transformer is around 42% of the total losses in the converter.
However, in order to achieve energy efficiencies of the converter greater than 90%
in the MHz frequency region, a novel high frequency planar power transformer
with the existing high frequency core material is designed according to the
requirements. Hence, this chapter deals with the design and analysis of the high
frequency multi resonant converter (MRC) circuit by utilizing the core based
planar power transformer and GaN HEMTs.

8.1 CORE BASED PLANAR POWER TRANSFORMER
In order to further miniaturize the existing flat profile planar power transformers
for achieving high power density and high energy efficiency, a novel hybrid core
planar power transformer has been designed. This transformer consists of three
parts namely; 1) stand alone multilayered PCB 2) copper windings etched on the
PCB and 3) high frequency magnetic core material.

8.1.1 Structure of transformer
The transformer is designed on a six layered PCB [114] with a primary-secondary-
secondary-primary (PSSP) structure as shown in fig.59.

Figure 59. 3D view of the planar power transformer
In order to meet the isolation requirements between the primary and secondary
windings, the distance between them is considered to be 0.4mm [115]. Here, on the
secondary side of the transformer, in order to carry large amount of currents, the
windings were paralleled instead of having a single solid conductor as in the case
of the conventional planar power transformer. This is due to the fact that, at higher
Auxiliary - A
Primary - P
Secondary - S
Mid point - SV
Secondary S
Primary P
S
A
P
P'
A'
SV
S'
77
operating frequencies, the rate of rise of the eddy current phenomenon and
magnetic field intensity increases rapidly in the case of the solid winding strategy
compared to that for the parallel winding strategy [116]. Here, the number of turns
of the primary and half of the secondary winding of the transformer are 8 and 2,
respectively. The design guidelines and other geometrical parameters of the
transformer are covered in [114].

8.1.2 Selected core material and shape
The selected core material is the NiZn 1F material from Kolektor Magma, which
consists of an initial permeability of 80. This material possesses higher resistivity in
the order of 10
5
m resulting in low eddy current losses in the core material. The
shape of the core is selected as a pot core since it possesses excellent shielding
characteristics compared to other core structures. On the other side of the
transformer, a flat ferrite plate was placed so that the stringent height of the planar
transformer can be achieved. The top and bottom views of the transformer
prototype are illustrated in fig. 60 (a) and (b) respectively.

(a) (b)
Figure 60. (a) Top and (b) bottom view of the planar power transformer
8.1.3 Electrical parameters of novel hybrid core transformer
The electrical parameters of the transformer were measured using a sine phase
impedance analyzer at a frequency of 3MHz [117] and are given in table 10.
Lp[H] Llkp[H] Ls1[H] Llks1[H] Cps[pF] Rp Rs1
4.56 0.15 0.31 0.05 22.2 0.7 0.1

The turns ratio n and the coupling coefficient K obtained from the measured self
inductances of the transformer are 3.83:1 and 0.964, respectively.

8.1.4 Energy efficiency of transformer
The measured energy efficiency of the transformer as a function of frequency for
different load conditions is depicted in fig.61. Here, the measured peak energy
efficiency of the transformer is reported to be 98% for a load resistance of 10 as
shown in fig.61. From this figure, it can be observed that the operating frequency
78
region of the transformer is in the range of 3 5MHz, since it posseses an energy
efficiency greater than 90% for the measured load conditions.
1 1.5 2 2.5 3 3.5 4 4.5 5
75
80
85
90
95
100
Frequency,f [MHz]
E
n
e
r
g
y

E
f
f
i
c
i
e
n
c
y
,

[
%
]

R
L
=10
R
L
=15
R
L
=20
R
L
=25
R
L
=30

Figure 61. Measured transformer energy efficiency for different load conditions [114]
The designed transformer has been characterized upto the load power of 50W [114]
at a frequency of 3MHz and the obtained power density of the transformer under
this condition is 47W/cm
3
. Since, the transformer posseses the desirable
characteristics to meet the given converter specifications, it has been implemented
in MRC and evaluated.

8.2 MULTIRESONANT ZVS HALF BRIDGE CONVERTER
For achieving the high power density converters with high energy efficiency, the
quasi resonant (QRC) and multiresonant (MRC) half bridge converters are
considered as a good choice compared to other existing topologies [118]. However,
in the case of QRCs, the ZVS condition is achievable within a limited load and
frequency range. In addition to this, undesired parasitic oscillations exist between
the resonant inductor and the diode junction capacitances, which affect the DC
voltage conversion ratio such that the voltage gain exhibits a positive slope in some
regions, leading to loop instability. Therefore, in this regard MRCs such as LCC,
LLC [2], [8] etc., are becoming popular for increasing the switching frequency of
converters. A well designed MRC exhibits the ZVS condition of all the switches
and in all the required operating conditions, which is a highly desirable
characteristic for the high frequency operation of converters. Therefore, in this
regard, the MRC is considered for evaluating the designed planar core based
power transformer. The schematic diagram of the ZVS half bridge MRC is depicted
in fig.62. The principle of operation of the MRC can be explained [119] in four
different stages, involving the switch resonant stage, rectifier capacitor discharging
stage, inductor discharging stage and the rectifier resonant stage. In fig, 62, C1 and
C2 are the output capacitances of the primary switches where CDR1 and CDR2 are
79
the junction capacitances of the rectifiers. An external capacitor can be added in
parallel to the diode if the junction capacitance is not sufficient to obtain the
desired resonant frequency. Here, the inductor L comprises the leakage
inductances of the primary/secondary windings of the transformer, the stray
inductances of the circuit and the external resonant inductor, if required.

Figure 62. Schematic diagram of multiresonant half bridge converter [119]
In case of MRC, the junction capacitance/output capacitances of all the switching
devices form a multiresonant network with the leakage inductance and stray
inductances, which results in the ZVS condition of the converter circuit. In this
regard, it is required to select the proper switching devices in order to attain the
ZVS condition of the circuit. Here, the circuit forms an LCC resonant tank circuit,
also known as the SPRC, which involves the advantages of both the series resonant
converter (SRC) and the parallel resonant converter (PRC) [8]. In this circuit, the
series LsCs elements are connected to the capacitance Cp which is connected
parallel to the load. The series inductor Ls or L comprises the leakage inductance
of the transformer and the stray inductances of the circuit referred to primary. The
series capacitance Cs is the output capacitance of the primary MOSFETs whereas
the capacitance Cp is the output capacitance of the synchronous MOSFET/diode
junction capacitance, referred to primary. The resonant frequency fres,
characteristic impedance Z, normalized load resistance rn and the voltage
conversion ratio M(D) [119] of the circuit are given by the following equations.

eq
s
C
L
Z
2
= (45)
s eq
res
L C
f
2 2
1
= (46)
80
Z
R n
r
L
n
2
= (47)
in
o
V
nV
D M
2
) ( = (48)
where, '
p s eq
C C C + =
The condition required for obtaining the ZVS operation of the circuit is given by
the equation (49)
1
) (
n
r
D M
(49)
By knowing all the above parameters, the switching frequency of the MRC can be
calculated [119] as follows.
( )
(
(
(
(
(
|
|
\
|
+ +
|
|
\
|
+
2
2
1
) (
1 1
2
) (
) (
sin
) (
2 2
D M
r
r
D M
D M
r
D M
r
V
f nV V
f
n
n
n n
in
res o in
sw
(50)
8.3 SIMULATION RESULTS OF MRC
The converter has been initially simulated using the high frequency model of the
designed planar power transformer. The schematic diagram of the designed high
frequency multiresonant half bridge converter is illustrated in fig.63. Since the GaN
switches possess better high frequency characteristics as discussed in chapter 4,
these devices were selected in preference to their Si counterparts.

Primary switches: The primary switches i.e., Q1 and Q2 of fig.63 were considered
as the EPC1012, whose breakdown voltage rating is 200V with the on state
resistance of 100m based on the considered converter specifications. The typical
gate charge Qg and the output capacitance Coss of these devices are 1.9nC and
80pF, respectively.

8.3.1 Gate drive circuitry
Regarding the driving signal for low side switch, the PWM signal from the
dsPIC33F microcontroller is fed to one of the inputs of the MOSFET driver
LM5112, from which the strengthened output signal is fed to the low side switch.
For driving the high side switch, a high speed digital optocoupler TLP117 was
chosen from which the isolated output signal is strengthened by using a LM5112
driver with a bootstrap circuit as shown in figure 63. The selected optocoupler
provides the minimum isolation voltage of 3.5kVrms and has the maximum
propagation delay of 20ns. Here, the digital optocoupler was chosen over any
passive solution because the GaN devices are more prone to parasitic when
compared to the Si devices. Therefore, in terms of robustness and device failure
rate, the optocoupler solution was considered.
81
8.3.2 Synchronous rectification
Secondary side switches: The secondary side HEMTs Q3 and Q4 are considered
as the EPC1009, whose breakdown voltage is 60V with the on state resistance of
30m, gate charge of 2.4nC and typical output capacitance of 120pF.
These two switches were also driven with the assistance of high speed digital
optocouplers and an LM5111 MOSFET driver as shown in fig.63.

Cpp Cs-sv
C6
D2
C4
C3
D1
LM5111-1M
In1 Out1
Out2 In2
R3
R1
SV
P
TLP1
LM5112
P1 S1
S2
C2
Lf
Q3
Cps'
Q2
Rs1
Rs2
Rp
Cin
Vin
RL
Cps
Llk
Lm
Cf
Q1
Q4
C1
Rc
dsPIC33F
PWM1
PWM2
PWM3
PWM4
Vss
3.3V
LM5112
TLP117
TLP117
Dr2 : Driver with Bootstrap Circuit
P'
S
S'
R2
R4
C5
Csv-s'
Rsh
D3
D4

Figure 63. Schematic diagram of multiresonant half bridge converter

Bridge capacitors: Regarding bridge capacitors, the C0G ceramic capacitors were
selected since they possess a better high frequency and thermal characteristics [48].
The two bridge capacitor values were selected as 680pF each of whose voltage
rating is 200V with a 5% tolerance.

Output filter: A filter inductor of 150nH is designed on a multilayered PCB and
utilized as a filter inductor on the secondary side. The DC resistance of the
designed inductor is 58m. Two ceramic capacitors of 1F/50V were paralleled on
the output side resulting in the filter cut-off frequency of 300 kHz.

8.3.3 Simulation waveforms of MRC
With the above mentioned devices and high frequency transformer, the converter
was simulated using SiMetrix software v6.10d. The simulations were carried out
for an input voltage of 120Vdc and at a load resistance of 10. The switching
frequency of the converter is considered to be 3.4MHz. The gate and drain signals
of all the switching devices are shown in fig.64 (a). From this figure, it can be
observed that all the switching devices are operating in the ZVS condition. The
High side driving
Circuit (Dr2)
Synchronous
driving scheme
Synchronous
Rectification (SR)
High frequency model of Transformer
82
corresponding switching waveforms of the converter are illustrated in fig. 64(b).
This figure shows, from top to bottom, the gate/drain signal of Q1, the current
through the shunt Rsh, voltage across bridge capacitor C2, voltage across the
primary winding Vpri, output voltage Vo and the current through the primary
winding of the transformer.

Q
4
_
V
d
s

/

V
-0
30
60
Q
4

/

V
0
2
4
Q
3
_
V
d
s

/

V
-0
30
60
Q
3

/

V
-0
2
4
Q
2
_
V
d
s

/

V
-0
40
80
120
Q
2

/

V
-0
1.5
3
4.5
Q
1
_
V
d
s

/

V
-0
40
80
120
Q
1

/

V
0
2
4
V
p
r
i
/

V
-100
-40
20
80
V
o
u
t

/

V
19.425
19.435
19.445
V
c
a
p

/

V
20
60
100
Q
1
_
V
d
s

/

V
-0
40
80
120
Q
1

/

V
0
2
4
I
i
n

/

A
-0.5
0.5
1.5
49.1 49.2 49.3 49.4 49.5 49.6 49.7 49.8 49.9
I
p
r
i
/

A
-1.5
-0.5
0.5
1.5

(a) (b)
Figure 64. (a) Gate, drain signals of switching devices and (b) switching waveforms of MRC
at 120Vdc
For an input voltage of 120Vdc, the output voltage for the converter is 19.4Vdc as
shown in fig. 64 (b). The simulated energy efficiency of the converter under these
conditions is approximately 91% at the output power level of 37.6W.

8.4 PROTOTYPE OF MRC
After the successful simulation of the MRC, a high frequency multiresonant
converter prototype was built and the experiments were carried out. The converter
prototype is depicted in fig.65.

8.4.1 Experimental results of MRC Unregulated converter
Initially, the experiments were conducted on the designed converter for a wide
input voltage variation of 30 120Vdc and load variations of 10 - 25 in steps of 5
.
83

Figure 65. Prototype of MRC with high frequency planar power transformer & GaN HEMTs

The measured gate signals of the switching devices in converter, at a switching
frequency of 3.4MHz, are depicted in fig.66 (a). Here, the duty cycle ratio of each
primary switch is considered to be 36% whereas, for the synchronous switches, it is
considered to be 38%. The dead time between Q1, Q2 and Q3, Q4 are
considered to be 44ns and 38ns, respectively as shown in figure in order to avoid
short through currents between the switching devices. The corresponding energy
efficiency of the unregulated converter w.r.t input voltage variation under
different load conditions is shown in fig.66 (b).

30 40 50 60 70 80 90 100 110 120
80
82
84
86
88
90
92
94
Input Voltage,V
in
[V]
E
n
e
r
g
y

E
f
f
i
c
i
e
n
c
y
,

[
%
]

R
L
=10
R
L
=15
R
L
=20
R
L
=25

(a) (b)
Figure 66. (a) Measured gate signals and (b) energy efficiency of unregulated MRC

EPC 1012
EPC 1009
Novel
Transformer
PCB Inductor
dsPIC microcontroller
44ns
38ns
Q1
Q2
Q3
Q4 Unregulated Converter
Load
84
From fig.66 (b), it can be observed that the peak energy efficiency of the converter
is 92% at an input voltage of 50V.
At the maximum tested input voltage of 120V, the output power of the converter is
37.6W with an output voltage of 19.3V. Under this condition, the energy efficiency
of the converter is 90.29%. Here, both the primary and secondary switches are soft
switched under all the load conditions. The measured series resonant inductance
Ls in the circuit, which is a combination of the leakage inductance and stray
inductance, is 2.8H. The equivalent capacitance of the circuit obtained from the
output capacitances of both the primary and synchronous switches is 88pF.
Therefore, the calculated resonant frequency of the circuit, obtained by using
equation (46) is 7.13MHz. Here, it should be noted that no external inductor and
capacitors are utilized for achieving the ZVS condition of the devices in the
converter circuit. Under these conditions, the calculated characteristic impedance
Z and the normalized load resistance rn using equations (45) and (47) are
obtained as 125 and 1.16 respectively. The calculated M (D)/r ratio is greater
than 1, which satisfies the condition required for achieving the ZVS of the
converter. In addition to this, the calculated switching frequency of the converter
using equation (50) is 3.44MHz, which is in good agreement with the selected
switching frequency of the converter in the simulation. It can be observed that the
measured results agree well with the simulation results.

Loss estimation of the converter:

From the measurements carried out at the maximum input voltage of 120Vdc, the
losses in the converter were estimated and are shown in the pie diagram in fig.67.
Here, the measured input/output powers of the converter are 41.64/37.6W,
respectively, resulting in the converter losses of 4.04W. Under these conditions, the
measured RMS value of the primary and each secondary winding of the
transformer are 1.13 and 1.49A, respectively. The measured AC resistance of the
winding at the corresponding switching frequency of 3.4MHz are 0.75 and 0.19,
respectively. The corresponding primary/secondary copper losses are 0.97W and
0.44W. Under these conditions, the estimated core losses obtained from the specific
power loss density of the core material and the maximum flux density [120], [121]
are 1.09W. Since, the converter is operating in ZVS condition, there exists only the
turn-off losses and the turn-on losses become zero. Therefore, the conduction and
switch turn-off losses of the switches obtained by using equations (34) and (36) are
1.29W. The measured RMS current flowing through the filter inductor is 2.08A,
resulting in the filter inductor loss as 0.152W. The remaining loss of 98mW is
contributed by the bridge capacitors placed in the circuit.

85

6%
6%
10%
10%
25%
11%
28%
4% < 1%
C L
sec
T
core
T
sec
T
pri
Q
4
Q
3
Q
2
Q
1

Figure 67. Loss estimation of MRC at an input voltage of 120Vdc

8.4.2 Efficiency of regulated DC-DC converter: case (i)
Converter specifications:
Nominal input voltage: 90Vdc with 10% variation
Output voltage of converter: 15Vdc with 1% tolerance
Load range: 15 - 100
Nominal switching frequency of converter: 3.4MHz
Converter regulation: constant OFF time frequency modulation and
Pulse Skip Modulation (PSM)
For the aforementioned converter specifications, the experiments were carried out
and the energy efficiency of the regulated converter as a function of line and load
variations is depicted in figs.68 (a) and (b), respectively. In fig.68 (a), the maximum

81 84.6 88.2 91.8 95.4 99
70
75
80
85
90
Input Voltage,V
in
[V]
E
n
e
r
g
y

E
f
f
i
c
i
e
n
c
y
,

[
%
]
3.14MHz
4MHz
Constant OFF time Frequency Modulation
3.4MHz
15 2530 40 50 60 7580 90 100
70
75
80
85
90
Load[%]
E
n
e
r
g
y

E
f
f
i
c
i
e
n
c
y
,

[
%
]

Measured % with PWM
Simulated % with PSM

(a) (b)
Figure 68. Measured efficiency of MRC as a function of (a) line & (b) load variations
energy efficiency of the converter is obtained at a nominal input voltage of 90Vdc
and it is 90%. The energy efficiency of the converter is reduced at a lower input
Q1 Q4: Transistors Q1 Q4
switching + conduction losses

Tpri: Transformer primary copper
losses

Tsec: Transformer secondary copper
losses

Tcore: Transformer core losses

Lsec : Secondary inductor losses

C: Bridge capacitors (C1 + C2) losses
86
voltage because, for the same load power, the current drawn from the input
increases, which results in higher copper and core losses of the transformer. In
addition to this, the conduction losses of the switching devices get increased.
Similarly, at a higher input voltage, the efficiency is reduced because of the
increased switching losses in the converter. Here, constant OFF time frequency
modulation technique is employed for regulating the output voltage of converter
for line variations. The switching frequency of the converter is varied from
3.14MHz - 4MHz for the specified input voltage range. In fig.68 (b), the
measurements were considered for the specified load range using the pulse width
modulation (PWM) technique at a constant switching frequency of 3.4MHz.
However, the energy efficiency of the converter under light load conditions is
reduced. At 15% of the full load condition, the energy efficiency of the converter is
around 75%. Therefore, in order to improve the energy efficiency of the converter
under light load conditions, the pulse skip modulation (PSM) technique has been
implemented using simulation which will be described in later sections. With this
modulation, the energy efficiency of the converter is improved from 75% to 84%
under 15% of the full load condition. The corresponding improved energy
efficiency of MRC under light load conditions is also illustrated in fig.68 (b).

8.4.3 Efficiency of AC/DC converter: case (ii) Laptop adapter
For realizing the laptop adapter power supply, two different approaches [122] exist
as shown in figs.69 (a) and (b). In the single stage approach, the supply voltage is
rectified to an unregulated DC voltage, which is then regulated to a desired output
voltage by using a DC-DC converter as shown in fig.69 (a).

Figure 69. Different approaches of laptop adapter a) single stage approach and b) two stage
approach
85
85
Single stage approach
Two stage approach
DC-DC
Converter
DC-DC
Converter
87
For the output power levels less than 75W, where there exists no power factor
correction requirement according to IEC 1000-3-2, the single stage approach [19],
[123] is widely used. On the other hand, when the required output power exceeds
75W, the two stage approach is commonly employed. Here, in this case, the single
stage approach is considered, as the targeted load power is 45W. However, due to
the non availability of the commercial high voltage GaN devices, the input voltage
was considered as a low line input voltage i.e., 85Vac including 10% variation,
instead of a universal input voltage range, in order to realise the high frequency
DC-DC converter. The specifications of the converter are as follows.

Input voltage range: V
in
min
to Vin
max
of 108 to 132Vdc with nominal
voltage of 120Vdc
Output voltage of converter: 22Vdc with 5% tolerance band
Output voltage ripple: Vo of 500mV
Load current range: IL
min
to IL
max
of 0.22 to 2.66A
Load power: Pout of 45W
Switching frequency range: 2.8MHz to 3.5MHz

For the above mentioned converter specifications, the standard pot core half of size
18x11 and whose cross sectional area Ac is 43.3mm
2
is considered. The
primary/secondary number of turns of the center tapped half bridge transformer is
taken as 8:2:2 respectively. Here, on the other side of the transformer, the circular
flat ferrite plate is considered, unlike the one discussed in an earlier section. The
design details of the transformer utilized for this application are given in [124]. For
the aforementioned converter specifications, this transformer was considered and
evaluated in the multiresonant half bridge converter topology shown in fig.63.
Here, the primary side switches of the MRC i.e., Q1 and Q2 are considered as
second generation GaN HEMTs from the Efficient Power Conversion Corporation
i.e., EPC2012, whose drain source voltage is 200V with the typical output
capacitance of 70pF and with a gate charge of 1.5nC. The typical reverse transfer
capacitance of EPC1012 is 7.5pF whereas it is only 3.3pF in case of EPC2012.

8.4.3.1 Synchronous rectification (SR) vs Diode rectification (DR)

In relation to the secondary side of the converter, both synchronous rectification
(SR) using EPC1009 devices, as discussed earlier, and diode rectification (DR) were
considered in order to determine the efficient power conversion at the desired high
frequency operation of the converter. In addition to this, unlike the previous case,
the signals to the SR were provided by considering a single high speed digital
isolator HCPL-9030 [125] from Avago technologies instead of two optocouplers
TLP117 as shown in fig.63 in order to reduce the components count. The maximum
propagation delay of the digital isolator is 15ns and it provides a maximum
88
isolation voltage of 2.5kV. In the case of the DR, the secondary side GaN HEMTs
were replaced by SR1660 Schottky diodes. The measured energy efficiency of the
converter, using SR and DR for the considered IL
min
to IL
max
, are illustrated in fig.70.
Here, the converter is regulated to 22V5% tolerance with the maximum output
power of 45W. Under the full load condition, the measured energy efficiency of the
converter with SR and DR are 91% and 90.3%, respectively. Here, while making the
comparison, the gate drive power consumption of synchronous HEMTs along with
the power consumed by the digital isolator, low-dropout regulator (LDO),
including the losses incurred by the other passive elements, are considered. The
total power consumption for the SR drive circuitry is 0.21W where the power
consumed by the MOSFET gate driver, digital isolator and LDO are 0.1, 0.03 and
0.08W, respectively.
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4
50
55
60
65
70
75
80
85
90
Load Current,I
L
[A]
E
n
e
r
g
y

E
f
f
i
c
i
e
n
c
y
,

[
%
]

DR@3.2MHz
SR@3.45MHz

Figure 70. Measured energy efficiency of regulated MRC using SR and DR

From fig.70, it can be observed that the energy efficiency of the converter is higher
in the case of the SR w.r.t DR from a full load to 3/4
th
load conditions. However, the
energy efficiency of the converter with the DR improves under light load
conditions by a maximum of 3.6% as shown in fig.70. This is due to the significant
contribution of the total drive power consumption as well as the circulating
currents in the case of the SR under the light load conditions. In the case of the SR,
the extra elements required, other than the synchronous HEMTs, are one isolator,
one MOSFET gate driver, one LDO and other passive components. This results in
an increased cost and space requirement for the converter, which is in addition to
the complexity in the control of the SR together with the primary HEMTs.
Therefore, in this case, DR is considered when compared to SR since there is only a
minor improvement in terms of energy efficiency with SR under full load
conditions.
SR: 91%
DR: 90.3%
SR: 60%
DR: 63.6%
SR: 85.6%
DR: 87%
89
8.4.3.2 Simulation and experimental results of converter for nominal input
voltage of 120Vdc
The simulations were performed for the converter at the nominal input voltage of
120Vdc corresponding to 85Vac at the switching frequency of 3.19MHz using
SIMetrix software. The corresponding switching waveforms of the converter are
depicted in fig.71. Here, the switch duty cycle ratio is considered as being 36% and
the output voltage is regulated to 22Vdc with a 5% tolerance.

V
o
u
t

/

V
21.06
21.1
21.14
V
D
2

/

V
-50
-30
-10
V
D
1

/

V
-50
-30
-10
Q
2
_
V
d
s

/

V
-0
40
80
120
Q
2

/

V
0
2
4
I
m
e
a
n

/

A
-0.6
0.2
1
Q
1

/

V
0
2
4
Q
1
_
V
d
s

/

V
-0
40
80
120
99.1 99.2 99.3 99.4 99.5 99.6 99.7 99.8 99.9
I
p
r
i

/

A
-1.5
-0.5
0.5
1.5

Figure 71. Simulation waveforms of MRC for RL=9.3 and fsw=3.19MHz at Vin
nom
=120Vdc

From fig.71, it can be observed that both the high side and low side switches were
operated under the ZVS condition resulting in lower switching losses for the
converter. Under these conditions, the load power of the converter is
approximately 45W. Similarly, the simulations were carried out for the entire load
range from 10% load to full load and it was observed that the devices are in the
ZVS condition.

Gate signal of Q1
Drain signal of Q1
Drain signal of Q2
Gate signal of Q2
Voltage across D1
Voltage across D2
Output voltage
Input current
Primary current
90
Under these conditions, the measurements were also carried out for the MRC and
the corresponding switching waveforms of the converter at full load condition are
illustrated in fig.72. The figure shows the gate voltage CH1, voltage across the
capacitor C2 CH3 and the drain-source voltage CH4.

Figure 72. Measured waveforms of MRC for RL=9.3 and fsw=3.19MHz at Vin
nom
=120Vdc

For the load power rating of 40W, the thermal profile of the converter, which gives
the temperature across various elements at an ambient temperature of 25
o
C, is
shown in fig.73. Here, it should be noted that no external cooling is applied while
considering the thermal profile of the converter

Figure 73. Thermal profile of converter at load power of 40W

In fig.73, it can be observed that a difference of 3.5
o
C exists in the spot
temperatures of the two GaN HEMTs (Sp1 and Sp2), though the converter is fed
with symmetrical gate signals. The reason for the difference can be explained as
follows. As the high side GaN HEMT is supplied with the bootstrap circuit, the
supply voltage fed to MOSFET driver is 4.5V, which is the difference between the
Gate signal of Q1
Voltage across capacitor
Drain signal of Q1
Microcontroller
GaN
HEMTs
Bridge capacitors
Transformer
Schottky
Diode
Filter Inductor
91
supply voltage 5V and the diode forward voltage drop. However, the supply
voltage of the low side GaN HEMT is still 5V. Due to this voltage difference, the on
state resistance of the devices is altered, thus resulting in the variation of the
conduction losses of these two devices. However, one of the solutions to this
problem is to add an external diode while also supplying the low side GaN HEMT,
so that the supply voltages fed to the MOSFET driver can be equalized.

The simulated and measured energy efficiency of the converter for the
aforementioned load range is depicted in fig.74. It can be observed from this figure
that the simulated and measured converter efficiencies are in good coordinance
with each other.
5 10 15 20 25 30 35 40 45 50
60
65
70
75
80
85
90
95

X: 5.026
Y: 83.2
Output Power [W]
E
n
e
r
g
y

E
f
f
i
c
i
e
n
c
y
,

[
%
]
X: 5.026
Y: 63.6
Measured@120V
dc
Simulation@120V
dc
Simulated PSM

Figure 74. Measured and simulated energy efficiency of MRC

Under these conditions, the measured output voltage as a function of load power is
shown in fig. 75.
0 5 10 15 20 25 30 35 40 45 50
19
20
21
22
23
24
Output Power,[W]
O
u
t
p
u
t

V
o
l
t
a
g
e
,
V
o
u
t
[
V
]

V-
V
out
,+/- 5% tolerance
V+

Figure 75. Measured output voltage of MRC for load variation of 10 100%
with full load of 9.3
PSM
92
Here, it can be observed that the output voltage of the converter is well regulated
throughout the load range, which is within 5% tolerance band. In fig.74, it can be
observed that the efficiency of the converter is degrading as the load power is
decreasing in nature. Therefore, a pulse skip modulation (PSM) technique is
implemented by using simulation in order to improve the efficiency under light
load conditions. In this coming section, the PSM technique, which can be
implemented digitally using the microcontroller, will be discussed.

8.4.3.3 Pulse skip modulation (PSM) technique

In order to improve the light load efficiency in converters, generally, the pulse skip
modulation or burst mode of operation is employed [126], [127]. In this regard,
prior to the implementation of the PSM technique on the prototype, the no. of
pulses required in order to improve the light load efficiency are calculated and the
procedure used to obtain them is described as follows. Initially, the burst
frequency is selected as 100 kHz, which can be multiplied by the prescalar 32 so
that the nominal switching frequency of the converter would be approximately
3.2MHz. The burst frequency is also selected in such a way that the output voltage
of the converter is maintained to always fall within the tolerance band of 5% of
the nominal output voltage. Here, the maximum allowed ripple voltage, which is
given as the difference between the upper and lower threshold voltages i.e., VH-VL,
is selected to be 400mV. From this knowledge, the pulse skipping time for different
load conditions [126] can be calculated as follows.
( )
L H
L
F
skip
V V
I
C
T = (51)
where,
CF Output filter capacitor
IL Load current
VH Upper threshold limit
VL Lower threshold limit

For the considered converter specifications, the output filter capacitor value of
MRC shown in fig.63 is considered as 4.4F. By using the aforementioned equation
(51), the calculated skipping time corresponding to a 10% load condition is
approximately 8s, which results in the duty cycle ratio as 20%. Therefore, the
required no. of pulses for a 10% load is 7 and the graph representing the no. of
pulses as a function of load resistance is shown in fig.76. From this figure, it can be
observed linearity does exist in the required no. of pulses as the load resistance is
increasing in nature. With this process, the PSM technique can be implemented
using a dsPIC microcontroller as discussed earlier.
93

Figure 76. Required no. of pulses as a function of load resistance

The simulated waveforms of the converter corresponding to the 10% load
condition using the PSM technique are depicted in fig.77.

Figure 77. Simulated waveforms of MRC for 10% load condition
7 No. of Pulses
94
It can be observed from the figure that, with the calculated no. of pulses using
equation (51), the output voltage of the converter is regulated well below the
tolerance band. By using this PSM technique, the simulated energy efficiency of the
converter for the wide load conditions is depicted in fig.74. From this figure, it can
be observed that there is a drastic energy efficiency improvement under light load
conditions. For example, if the energy efficiency is considered at a 5% load
condition, there is an improvement of about 19.6% with the assistance of the PSM
technique.

8.4.3.4 Energy efficiency for line variations

In the previous sections, the energy efficiency of the converter for the considered
power transfer application w.r.t load variations is discussed. Here, in this section,
the measured efficiency of the converter for the specified line voltage variations is
depicted in fig.78. In order to maintain the constant output voltage of converter as
22Vdc and within the considered tolerance band, the constant off time frequency
modulation is utilized as discussed earlier. The frequency of operation is varied
from 2.89MHz to 3.49MHz in order to obtain the desired output voltage as shown
in fig.78 whereas the nominal switching frequency of the converter is considered to
be 3.19MHz.

108 112 116 120 124 128 132
85
87
89
91
93
95
Input Voltage,[V
in
]
E
n
e
r
g
y

E
f
f
i
c
i
e
n
c
y
,

[
%
]

Frequency Modulation (T
off
=Constant)

Figure 78. Measured efficiency of MRC as a function of line variation

2.89MHz
3.19MHz
3.49MHz
95
9 HIGH FREQUENCY LLC RESONANT CONVERTER USING PLANAR
POWER TRANSFORMER
In the earlier chapter, the performance of one of the SPRC converter or
multiresonant converter topology i.e., LCC resonant converter is considered using
a high frequency planar power transformer. Here, the multiple resonances occur
between the inductor Ls, series capacitor Cs and the parallel capacitor Cp across
the load. In this converter, no external inductor/capacitors are utilized in relation to
obtaining the ZVS condition of the converter. The output capacitance of the
primary and secondary side synchronous GaN HEMTs/Schottky diode rectifiers
together with the leakage inductance and the stray inductances were utilized in the
converter circuit. However, if the energy efficiency of the converter is considered
for the given load range in fig. 68 (b) and fig.74, it can be observed that it is
dropping rapidly from 3/4
th
1/10
th
load conditions. In addition to this, for the
considered line variation of the converter in fig.78, the switching frequency is
varied from 2.89MHz to 3.49MHz, which is approximately a 600 kHz difference for
the 24V input voltage variation. This becomes one of the drawbacks if the universal
line input voltage is considered. Due to these limitations of the LCC resonant
converter, i.e., low energy efficiency for wide load range and wide switching
frequency range requirement for line changes, in this chapter the other
multiresonant converter topology i.e., the LLC resonant converter using the
designed planar power transformer is studied.

In modern days, LLC resonant converter topology is gaining importance when
compared to conventional resonant converter topologies. This is because it can
regulate the output voltage of the converter for wide line and load variations while
maintaining excellent efficiency and, also, with the small variation of the switching
frequency [2], [8], [128]. In addition to this, it can also achieve the ZVS condition
for the entire load and line variations while regulating the output voltage, as in the
case of LCC resonant converter. Unlike the LCC resonant converter, the ZVS
condition is achieved in this converter by utilizing all the parasitic elements, the
junction capacitance of the devices together with the leakage and magnetizing
inductances [129] of the transformer. Here, in the LLC resonant converter, two
inductors and a single capacitor are required for obtaining the multiple resonances
in the converter. In order to avoid additional spacing requirement for the extra
inductor, an integrated transformer can be designed by adjusting the air gap in
order to improve the power density of the converter. In this regard, a high
frequency half bridge integrated planar power transformer is designed and
evaluated in the LLC resonant converter using the commercially available GaN
HEMTs for the considered converter specifications.

96
9.1 LLC RESONANT CONVERTER
The schematic diagram of the LLC resonant converter is shown in fig.79 [128]. It
consists of a (a) square wave generator (b) resonant circuit and (c) secondary side
rectifier circuit as shown in fig.79. The uni-polar square wave signal is obtained by
using the high frequency switching devices Q1 and Q2, which is then fed to the
resonant circuit. A small dead time is ensured between the two switches to avoid
the short through currents and to allow time for the ZVS of the converter. The
signal fed to the primary winding of the transformer becomes alternating in nature
due to the DC blocking capacitor Cr as shown in fig.79. This voltage is transferred
to the secondary side of the converter using a transformer with a turns ratio n,
which is rectified by using diodes D1 and D2 and hence fed to the load with the
assistance of a filter capacitor Co.

Figure 79. Schematic diagram of LLC resonant converter [128]
In case of LLC resonant converter, there exists two different resonant frequencies
which determine the operating frequency region for the given line and load
specifications and is given as follows.
The frequency of the series resonant circuit i.e., between Lr and Cr is given by
equation (25), whereas the frequency corresponding to all resonant elements of
circuit i.e., Lr, Lm and Cr is given as follows
( )
r r m
p
C L L
f
+
=
2
1
(52)
The quality factor Qe of the series resonant circuit, which is dependent on load
condition is given by the following equation
e
r r
e
R
C L
Q = (53)
L e
R
n
R
2
2
8
= (54)
where,
97
n turns ratio of transformer
RL load resistance

The detailed explanation of LLC resonant converter operation in different
conditions such as (a) operation at resonant frequency (b) below resonant
frequency and (c) above resonant frequency fr are covered in various literatures
[128] - [130]. In the coming sections, the implementation of the high frequency LLC
resonant converter is explained with the aid of analytical equations, simulation and
experimental results.

9.2 DESIGN OF HIGH FREQUENCY LLC RESONANT CONVERTER
9.2.1 Converter specifications
The converter is aimed to target the following specifications for laptop adapter
applications.

Input voltage range: V
in
min
to Vin
max
of 127 to 155Vdc with nominal
voltage of 141Vdc
Output voltage of converter: 22Vdc with 5% tolerance band
Output voltage ripple: Vo of 500mV
min
to IL
max
of 0.22 to 2.045A
Switching frequency range: 3MHz to 4MHz
Energy efficiency : >90%

Here, the low line input voltage is considered as being 90Vac which is the worst
case condition while designing the universal input voltage adapter. Therefore, the
targeted full load energy efficiency of the converter is considered as being >90% for
the worst case condition. Based on the aforementioned converter specifications, the
high frequency half bridge integrated planar power transformer is designed. In
case of the LLC resonant converter, the ratio of Lm to Lr should be sufficiently large
[8], [129] so that the magnetizing current can be reduced and the energy efficiency
can be improved [131]. Therefore, a large Lm/Lr ratio of 11 is considered by varying
the air gap at the center post of the transformer. This results in Lm and Lr of the
transformer being 4.4H and 0.4H, respectively. The design guidelines and
structure of the integrated planar transformer along with its electrical parameters
and characteristics are given in [132].

9.2.2 DC gain characteristics of LLC resonant converter
The calculated DC gain characteristics [128], [129] & [131] of the LLC resonant
converter which determine the converter operation, by considering the
aforementioned converter specifications, are depicted in fig.80. The figure
98
illustrates the gain curves for the quality factors corresponding to the minimum
and maximum load conditions. By using an external resonant capacitor Cr of
1.36nF, the series resonant frequency fr obtained by using equation (25) is 6.8MHz.
At this particular operating frequency, the gain of the converter reaches unity for
all the load conditions as shown in fig.80. The frequency fp obtained, by
considering all the resonant elements of the converter using equation (52), is
1.96MHz.

0 0.2 0.4 0.6 0.8 1 1.2
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
F
sw
/F
r
G
a
i
n
,
M
g

f
min
=2.8MHz, M
gmax
=1.61
f
r
=6.8MHz,M
gmin
=1
f
p
=1.96MHz
ZCS
4MHz
3.3MHz
V
inmin
=127V
DC
V
inmax
=155V
DC
ZVS

Figure 80. DC gain characteristics of LLC resonant converter

The minimum and maximum gains (Mgmin and Mgmax) as shown in fig.80 for the
converter specifications are obtained as 1 and 1.61 by using the following equations
and by assuming the converter energy efficiency as being 92%.

( )
in
f o
g
V
V V n
M
5 . 0
min
+
= (55)
( )
in
loss f o
g
V
V V V n
M
5 . 0
max
+ +
= (56)
where,
Vo output voltage of converter
Vf forward voltage drop of the diode
max o
rem
o
loss
I
P
V
\
|
= (57)
99
Here, if the converter efficiency is assumed to be 92%, the remaining losses are
given as rem through which the term Vloss is estimated [128]. The calculated
minimum fmin and maximum switching frequency fmax limits for the designed
converter at their corresponding gain points are 2.8MHz and 6.8MHz, respectively.
The right hand side of the gain plot, after the resonant peak, leads to the ZVS
condition of the converter whereas by operating the converter below the resonant
peak results in the ZCS operation of the converter as shown in the region within
red dotted line in fig.80.

9.2.3 Simulation results of LLC resonant converter
The schematic of the LLC resonant converter using the high frequency model of
the designed integrated transformer and the GaN HEMTs is depicted in fig. 81.
The details of the devices utilized in the converter can be found in an earlier
chapter.

Dr2
---------
-
-
-
-
-
-
-
-
-
---------
D4
Rsh
Csv-s'
R2
S'
S
P'
Dr2 : Driver with Bootstrap Circuit
TLP117
LM5112
dsPIC33F
3.3V
Vss
PWM4
PWM3
PWM2
PWM1
Rc
Q1
Cf
Lm
Llk=Lr
Cps
RL
Vin
Cin
Rp
Rs2
Rs1
Q2
Cps'
P1 S1
S2
LM5112
P
SV
R1
D1
C3
C4
D2
Cs-sv
Cpp
D3
Cr
-
-
-
-
-
-
-
-
-

This converter has been initially simulated for the converter specifications
mentioned in section 9.2.1. The simulated results of the converter for the minimum
input voltage of 127Vdc and full load resistance of 9.5 are depicted in fig.82. From
this figure, it can be observed that both the switches are operated in the ZVS
condition and also the secondary side diodes are commutated softly. Here, it can
be also observed that the diodes are operating in discontinuous conduction mode.
The resonant primary current reaches the magnetizing current before the end of
the driving pulse as shown by dotted blue line in fig.82, which shows that the
converter is operated below the resonant frequency [128]. This can also be verified
from the DC gain characteristics of the LLC resonant converter shown in fig.80. At
Figure 81. Schematic diagram of LLC resonant converter
Series resonant capacitor
Transformer
100
this particular operating voltage, the switching frequency of the converter is
3.3MHz.
I
d
i
o
d
e
4

/

A
-0
2
4
I
d
i
o
d
e
3

/

A
-0
2
4
V
o
u
t

/

V
21.24
21.27
21.3
V
g
s
_
L

/

V
0
2
4
V
g
s
_
H

/

V
-0
2
4
V
d
s
_
L
S

/

V
-0
40
80
120
V
d
s
_
H
S

/

V
-0
40
80
120
V
c

/

V
20
60
100
I
p
r
i

/

A
-1.5
-0.5
0.5
1.5
I
m
e
a
n

/

A
-0.6
-0
0.6
1.2
49.1 49.2 49.3 49.4 49.5 49.6 49.7 49.8 49.9
V
p
r
i
1

/

V
-120
-60
20
80

Figure 82. Simulation waveforms of LLC resonant converter at 127Vdc and RL=9.5

Drain voltage
of Q1
Drain voltage
of Q2
Gate voltage of Q2
Current through
Diode D3
Current through
Diode D4
Capacitor voltage
Output voltage
Primary current
Magnetizing
current
Input current
Primary voltage
Gate voltage of Q1
101
9.2.4 Experimental results of LLC resonant converter
After the successful simulations of the converter, the prototype of the high
frequency LLC resonant converter was designed and evaluated experimentally.
The prototype of the high frequency DC/DC converter stage together with the
existing laptop adapter operating at a switching frequency of 100 kHz is shown in
fig.83.

Figure 83. Comparison of designed prototype w.r.t existing laptop adapter

The measurements were taken on the prototype for the considered converter
specifications. The simulated and measured energy efficiency of the regulated LLC
resonant converter at a minimum input voltage of 127Vdc, for the considered load
range, is depicted in fig.84 (a). From this figure, it can be observed that the
simulated and measured efficiency are in good agreement with each other. Here,
the measured input/output power of the converter is 52.8/47.6W, respectively,
under full load conditions resulting in an efficiency of 90.1%. The switching
frequency of the converter is maintained at 3.3MHz. The converter light load
efficiency is improved by the PSM as described in the previous chapter. The
corresponding measured waveforms of the converter are depicted in fig.84 (b). The
figure shows the gate voltage (CH1), drain source voltage (CH2) and the voltage
across the capacitor (CH4). From this figure, it can be observed that the ZVS of the
converter is attained.
Here, the experiments were also carried out for AC/DC converter by using a bridge
rectifier. The measured efficiency of the regulated AC/DC and the DC/DC
converter is shown in fig.85 (a). It can be observed that approximately 1%
efficiency is lost due to the diode bridge rectifier as compared to the DC-DC
converter efficiency under the full load condition. The efficiency under these
conditions was measured by using the agilent AC power source analyzer (6811B).
Similarly, the energy efficiency of the LLC converter with line variations is shown
100 kHz transformer
3 4MHz transformer
TO220 Package MOSFET
LGA Package GaN HEMTs
102
in fig.85 (b). The switching frequency range of the converter for the considered line
variations is 3.3MHz 3.96MHz and can be observed from fig.85 (b).
4 8 12 16 20 24 28 32 36 40 44 48
64
68
72
76
80
84
88
92
Power,P
out
[W]
E
n
e
r
g
y

E
f
f
i
c
i
e
n
c
y
,

[
%
]

Measured@127V
DC
Simulated@127V
DC
Simulated(PSM)

(a) (b)
Figure 84. (a) Simulated/Measured efficiency and (b) measured waveforms of LLC resonant
converter at 127Vdc and RL=9.5
Here, the efficiency of the converter is decreasing drastically after the nominal
voltage due to the distortion in the gate signal of the high side GaN HEMT. By
improving the corresponding gate signal, the energy efficiency of the converter can
be maintained at a higher level. From fig. 74 and 85(a), it can be observed that, in
the LLC resonant converter, the measured energy efficiency is maintained at a high
level in the range of the full load to half load conditions, unlike the LCC converter.
However, there is a little variation in terms of switching frequency range due to the
large Lm/Lr ratio i.e., m=11. Both the switching frequency range and the
magnetizing current can be maintained at a low level by considering the optimal
Lm/Lr ratio while designing the integrated transformer as there exits trade-off
between the two parameters. Therefore, by redesigning the transformer and with
the availability of high voltage GaN HEMTs, an energy efficient high frequency,
low profile laptop adapter for a universal ac input voltage can be realized.

4 8 12 16 20 24 28 32 36 40 44 48
64
68
72
76
80
84
88
92
Power,P
out
[W]
E
n
e
r
g
y

E
f
f
i
c
i
e
n
c
y
,

[
%
]

Measured@127V
DC
Measured@90V
AC
125 130 135 140 145 150 155
80
82
84
86
88
90
92
Input Voltage,V
in
[V]
E
n
e
r
g
y

E
f
f
i
c
i
e
n
c
y
,

[
%
]

Measured@P
load
=45W,V
out
=22V
3.6MHz
3.96MHz
3.3MHz

(a) (b)
Figure 85. Measured efficiency of LLC converter for (a) 90Vac, 127Vdc and for (b) line
variations
ZVS
103
10 HIGH FREQUENCY CLASS E ISOLATED DC-DC CONVERTER USING
HIGH PERFORMANCE PLANAR POWER TRANSFORMER
In the previous chapters 8 and 9, the performance of various multiresonant
converter topologies such as LCC and LLC resonant converters suitable for
consumer applications was discussed. Here, in this chapter, another resonant
converter known as class E resonant converter which is suitable for high frequency
applications is also investigated. This converter topology operates at ZVS, with the
well designed circuit parameters such as resonant inductor and capacitors. This
results in high energy efficiency and low EMI emissions from the circuit and makes
it possible to increase the switching frequency of converter to MHz frequency
region [9]. The other advantage of this topology is that it possesses single
switching device which eliminates the complexity of the driving circuit. In this
topology, the parasitic elements of the considered inductive, capacitive and
switching devices can be fully absorbed into the circuit elements and hence
demands few number of components making it possible to obtain high power
density converters. Due to less number of components and ZVS condition of the
class E inverter and its high energy efficiency, the resonant DC-DC converter
applications employing class E converter topology can be realized [9], [133], [134].
Since, some of the applications demand isolated class E resonant converters such as
high frequency electronic lamp ballasts, multiple output telecom applications,
satellite applications and so on..., lot of research is progressing in this direction
[47], [135]. In this regard, this chapter discusses about the feasibility of high
frequency class E DC - DC converter using high performance planar power
transformer designed at Mid Sweden University.

The schematic diagram of the isolated class E resonant DC-DC converter with
center tapped transformer is shown in fig. 86 [136].

Figure 86. Schematic diagram of Class E resonant isolated DC-DC converter

Series resonant circuit elements
Center tapped transformer
104
A large value of choke inductance Lchoke is usually employed in order to reduce the
ripple content of the input current. Here, Lseries and Cseries forms the resonant
network and usually the switching frequency of converter is considered to be
greater than resonant frequency of converter. The resonant frequency of the circuit
is obtained by the following equation.
series series
resonant
C L
f
=
2
1
(58)
The design considerations of the isolated class E DC-DC converter and its
simulation results are discussed in coming sections.

10.1 DESIGN CONSIDERATIONS OF ISOLATED CLASS E DC-DC CONVERTER
The isolated class E DC-DC converter is aimed to target the following
specifications.

DC input voltage: V
in
nom
of 60V
Output voltage of converter: V
o
of 15Vdc
min
to IL
max
of 0.35 to 1.06A
Targeted Switching frequency: fsw of 5MHz
Energy efficiency : converter>88%

The converter is considered to be designed for optimum operation and hence the
quality factor Q and duty cycle D is considered as 5 and 0.5 respectively [137].
By considering the low voltage drop Vf of 0.5V for schottky diodes, the estimated
rectifier efficiency using equation (59) is 96%.
|
|
\
|
+
=
o
f
rectifier
V
V
1
1
(59)
By assuming transformer efficiency (transformer) and inverter efficiency (inverter) as 96%
and 95% respectively, the total estimated converter efficiency by using equation
(60) is obtained as 88%.
inverter r transforme rectifier converter
= (60)
Based upon the aforementioned converter specifications, initially the required
converter elements are determined by following the procedure and equations
given in [12], [47], [136] and [137]. The required minimum choke inductance using
equation (61) for the given specifications is obtained as 19.5H.
sw
i
choke
f
R
L
|
|
\
|
+ = 1
4
2
2
(61)
where,
Ri input resistance of the rectifier at the fundamental frequency fsw
105
By considering the amplifier parameters and load network component values for
the considered Q and D given in [137], the parallel and series capacitances, series
inductance and the magnetizing inductance of the transformer are determined. The
calculated parallel and series capacitances using equations (62) and (63) are
obtained as 63pF and 69.2pF respectively.
max
R
c
C
parallel
(62)
max
R
d
C
series
(63)
where, =2fsw
Here, the constants c=0.2067 and d=0.2269 are obtained from [137] for the
considered Q and D.
The inductance L is obtained as
max
eR
L = (64)
where, the constant e=5.673 [137]
min
min
LS
s
X
L = (65)
where,
max min
R X
LS
= (66)
Therefore, the required series inductance of the resonant network is calculated by
using equation (67) and is obtained as 15.5H.
min s series
L L L = (67)
The magnetizing inductance of the transformer is calculated as follows and
obtained as 6.2H.
i mag
L L =
8
2
(68)
where,

i
i
X
L = (69)

max
2 R X
i
= (70)
Based upon the converter requirements, the turns ratio of the transformer is
determined by using the following equation and obtained as 4:1:1.
min
min
8
l
i
R
R
n
= (71)
where,
max min
2 R R
i
= (72)
out
o
l
P
V
R
2
min
= (73)
106
With the aforementioned guidelines, a customized pot core high frequency planar
transformer of 4:1:1 turns ratio [138] suitable for class E DC-DC converter is
designed and evaluated. The measured electrical parameters of the transformer by
using sine phase impedance analyzer at the considered switching frequency of
converter are given in table.11.

The transformer has been characterized in the frequency range of 1 10MHz and
also evaluated its performance up to 62W at an operating frequency of 6.78MHz.
The peak energy efficiency of the designed transformer with sinusoidal excitation
is reported to be 98.5% with an achieved power density [138] of 67W/cm
3
. With the
assistance of designed high frequency planar power transformer, the simulations
were carried out for the class E isolated DC-DC converter for the considered
converter specifications which will be discussed in coming section.

10.2 SIMULATION RESULTS OF CLASS E ISOLATED DC-DC CONVERTER
The GaN HEMT, EPC 2012 is considered while simulating the circuit. The
schematic diagram of the isolated class E DC-DC converter using the high
frequency model of the planar transformer and the spice model of GaN HEMT is
illustrated in fig. 87.

100m
R9
3G
R3
Vout
Coss
Ipri
Vpri
3.3k
R8
SW
s
o
u
r
c
e
in
d
r
a
in
in
g
a
t
e
in
C2
18.5p
100m
R7
219n
L1
1.057
R6
109m
R5
SR1660A
D2
SR1660A
D1
P1 S1
S2
TX1
42
R2
C8
69.2p
Vgs
Vds
V7
30m
R1
60
Vin
25u
L4
15.5u
L3
C1
4.7u
109m
R4
C3
18.5p
Iin

Figure 87. Schematic diagram of isolated class E DC-DC converter using planar transformer
Here, from equation (62), the calculated parallel capacitance value is 63pF,
however, the output capacitance of the considered GaN HEMT is 63pF. Therefore,
Lp[H] Ls[H] Llk[H] Cps[pF] Rp[] Rs[]
6.79 0.42 0.21 18.5 1.05 0.10
E
P
C

2
0
1
2

of transformer
Parallel capacitor
Series inductor
Series
Capacitor
Choke
107
no external capacitor is placed across the GaN HEMT. At an input voltage of 60Vdc,
the full load resistance is considered as 14.06 and the converter has been
simulated at the operating frequency of 5MHz with 50% duty cycle ratio.

The simulated switching waveforms of the converter are depicted in fig. 88.

V
p
r
i

/

V
-100
-60
0
40
80
V
o
u
t

/

V
16.069
16.071
16.073
16.075
16.077
V
g
s

/

V
0
1
2
3
4
5
V
d
s

/

V
-0
50
100
150
200
250
I
i
n

/

m
A
200
300
400
500
199.1 199.2 199.3 199.4 199.5 199.6 199.7 199.8 199.9
I
p
r
i

/

m
A
-800
-400
0
400
Vpri
Vout
Mean/cycle=16.074442V
Vgs
Vds
Ipri
Iin
Mean/cycle=346.08154mA

Figure 88. Simulated waveforms of class E DC-DC converter at 60Vdc and RL=14.06

Here, the output voltage of the converter is obtained as 16V for the input voltage of
60V. Under these conditions, the input/output power of the converter is
20.76/18.37W respectively and the energy efficiency of the converter is reported to
be 88.5%.

Similarly, the simulations were also carried out for the considered maximum load
resistance of 42 and the corresponding waveforms are illustrated in fig. 89. From
these figures 88 and 89, it can be observed that the converter is operating in ZVS
condition in both the cases.

For regulating the output voltage of the class E resonant converter, the constant
OFF time frequency modulation can be utilized. However, for some applications
where there exist stringent frequency variation limitations such as by operating the
converter in ISM band frequency at 6.78MHz, the output voltage cannot be
Gate signal
Drain signal
Output voltage
Input current
Primary voltage
Primary current
108
regulated by using frequency modulation techniques for both line and load
variations. This is due to the constraints by operating at ISM band which is
restricted to frequency band of 15kHz [139]. Under these circumstances, the
output voltage of class E converter can be regulated at a fixed switching frequency
by replacing the secondary side diode with the MOSFET as suggested in [47], [140]
or preferably GaN HEMT and hence the high power density class E DC-DC
converter operating at 6.78MHz can be realized.

V
p
r
i

/

V
-80
-20
40
80
V
o
u
t

/

V
17.449
17.451
17.453
17.455
V
g
s

/

V
0
2
4
V
d
s

/

V
-0
60
120
180
240
I
i
n

/

m
A
50
150
250
199.1 199.2 199.3 199.4 199.5 199.6 199.7 199.8 199.9
I
p
r
i

/

m
A
-400
0
400
Vpri
Vout
Mean/cycle=17.45232V
Vgs
Vds
Ipri
Iin
Mean/cycle=149.00668mA

Figure 89. Simulated waveforms of class E DC-DC converter at 60Vdc and RL=42

Gate signal
Drain signal
Output voltage
Input current
Primary voltage
Primary current
109
11 PAPERS SUMMARY AND AUTHORS CONTRIBUTION
11.1 PAPERS SUMMARY
PAPER I
In this paper, a multi-layered coreless PCB step down transformer is utilized for
building a high speed SMPS. The analytical and experimental analysis of a quasi
resonant ZVS flyback converter in MHz frequency region is presented. The input
voltage fed to the converter is in the range of 25 - 40V and tested up to the
maximum power level of 10W in the frequency range of 2.7 - 4.3MHz. Here, the
output voltage of the converter was regulated to 13V with the assistance of a
constant-off time frequency modulation technique for both line and load
variations. In this paper, the feasibility of operating the converter in the MHz
frequency region for DC-DC converter applications with multi-layered coreless
PCB step-down transformers is analysed and discussed.

PAPER II
In this paper, two material switching devices i.e. GaN HEMT and conventional Si
MOSFET performances were compared in a quasi resonant ZVS flyback converter
in MHz frequency region. The input to the converter was varied from 30 - 60 V and
the output voltage of the converter is regulated to 15V, by using the frequency
modulation technique. Here, the switching frequency of the converter is varied
from 3.2 - 5MHz and tested up to the maximum power level of 12W. An energy
efficiency improvement of 8 - 10% was achieved including the gate drive power
consumption by using a GaN device compared to state-of-the-art Si MOSFET. It
can be observed that, the GaN HEMT produces better results because of lower
switching losses, reduced conduction loss due to its low on-state resistance, minor
gate drive power consumption due to the low gate charge Qg when compared to
its counterpart. This paper shows that it is possible to obtain the higher energy
efficiencies of the converter using GaN HEMTs in the MHz frequency region when
compared to the existing Si MOSFET.

PAPER III
The design and analysis of a cascode flyback converter operated in the MHz
frequency region using a multilayered coreless PCB step down transformer is
presented in this paper. A cascode flyback converter using low voltage GaN
HEMT/Si MOSFET and high voltage Si MOSFET was compared to that of the
traditional single switch flyback converter in terms of energy efficiency, switching
frequency, gate drive power consumption and the device voltage stress. The
switching frequency of the converters is in the range of 2.6 - 3.7MHz and tested up
to the power level of 30W for given specific converter conditions. The energy
110
efficiency in the case of the cascode converter with low voltage GaN HEMT is
improved by 3 - 4% compared to the single switch flyback converter due to the
reduced gate drive power consumption, lower switching loss, increased switching
speeds, despite of minor increment in the conduction losses of the converter.

PAPER IV
In this paper, a high speed half bridge DC/DC converter circuit using a MLCLPCB
power transformer was demonstrated. Due to the limitations imposed by the
commercially available high side MOSFET gate drivers in terms of higher input
voltage and MHz frequency region, a passive gate drive circuitry was built up by
using MLCLPCB gate drive transformer. Here, a step-down center tapped power
transformer of 4:1:1 turn ratio, which is of 22mm diameter, is utilized. The energy
efficiency of this multi-layered coreless PCB step-down center tapped transformer
is found to be greater than 92% for sinusoidal excitation. The converter was tested
within the frequency range of 2 - 3MHz with the maximum DC input voltage of
170V. The maximum energy efficiency of the unregulated converter is found to be
82% at a maximum tested load power of 40W. This paper shows the successful
implementation of passive gate drive circuitry in MHz frequency region for
driving the high side MOSFET in double ended converter topology.

PAPER V
This paper deals with the design and analysis of a MLCLPCB step down power
and signal transformer useful for SMPS applications. The guidelines for designing
the MLCLPCB step down transformer for the given power transfer application and
the signal transformer for driving high side MOSFET in double ended converter
topologies are proposed. A 4:1:1 multilayered coreless PCB power transformer was
designed by considering the proposed design guidelines. The parameters of the
transformer were extracted and performance analyses for the input impedance,
energy efficiency as a function of frequency and load power are presented. The
designed power transformer was characterized up to the power level of 50W with
the energy efficiency range of 87 96% at an operating frequency of 2.6MHz. The
achieved power density of the transformer for the maximum tested load power is
107W/cm
3
. Similarly, MLCLPCB gate drive transformer operated with wide
frequency band was designed and successfully evaluated for driving the high side
MOSFET in the MHz frequency region. Both the designed signal and power
transformers were evaluated in the SRC in the switching frequency range of 2.4
2.75MHz. The converter was simulated and tested up to the power level of 34.5W
with the maximum converter energy efficiency being 86.5% at these operating
frequencies. The loss estimation of the converter along with the thermal profile at
one particular operating condition was presented.

111
PAPER VI
In this paper, a novel high frequency core based planar power transformer
operating in the MHz frequency region was designed and analyzed. A hybrid core
structure, which consists of a pot core half and a flat ferrite plate of high frequency
NiZn 1F material was considered in order to have excellent shielding
characteristics in MHz frequency region. The designed power transformer has
been characterized in the high frequency region of 3 - 5 MHz up to the power level
of 50W with the achieved power density of 47W/cm
3
. The designed power
transformer has been evaluated in a multiresonant half bridge converter topology
using high performance wide band gap material devices i.e., GaN HEMTs and
synchronous rectification. The converter has been evaluated in the switching
frequency range of 3 4.5MHz and tested up to the power level of 40W. It has been
tested at the DC nominal input voltage of 90V and the output voltage of the
converter is regulated to 15V1% for both line and load variations. This paper
shows the feasibility of achieving isolated DC-DC converters in the MHz frequency
region using the novel planar transformer technology and the latest GaN HEMTs
with efficiencies greater than 90%.

PAPER VII
The design guidelines of the novel hybrid core planar power transformer for the
given power transfer application are discussed in detail. The optimal core material
is suggested from the experimental analysis in order to operate the transformer
within the desired frequency region (1 10MHz). The feasibility of achieving high
frequency, low profile power converter for 45W laptop adapter applications for
low line input voltage using multiresonant converter topology is discussed. The
simulation and experimental analysis for the considered converter specification is
presented. Here, for the given converter application, the efficient power processing
method on the secondary side of the converter in terms of diode rectification or
synchronous rectification is proposed, especially in terms of energy efficiency,
power density and control complexity. The converter is operated in the frequency
range of 2.8 3.5 MHz using diode rectification and the peak energy efficiency of
the converter is reported to be 92% with the maximum tested output power of the
converter being 45W. The PSM technique for improving the light load energy
efficiency is explained analytically and the simulation waveforms of the converter
for 10% load conditions are presented.

PAPER VIII
The design guidelines and experimental analysis of the high frequency LLC
resonant converter using novel planar power transformer suitable for laptop
adapter application are presented. The designed converter was operated in the
frequency range of 3 4MHz for the input voltage variation of 127 155Vdc
112
corresponding to an equivalent 90 110Vac due to the non availability of the high
voltage GaN HEMT in the market. The converter was regulated to 22Vdc for both
line and load variations, where the achieved maximum energy efficiency of
converter is 91% under the full load condition of 45W. The light load energy
efficiency of the converter was improved by using the PSM technique. From this
paper, we can conclude that the low profile energy efficient AC/DC converter
operating in the MHz switching frequency region can be realized in the near future
for a laptop adapter application with the assistance of high voltage GaN HEMTs
and the high frequency energy efficient planar power transformers designed at
Mid Sweden University.

PAPER IX
In this paper, a record power density transformer using custom made pot core
design details is presented. The targeted frequency range of the designed
transformer is 4 - 10MHz. It has been characterized up to the power level of 62W
with sinusoidal excitation at an operating frequency of 6.78 MHz. The power
density of the designed high performance transformer is reported to be ~67W/cm
3

at the maximum tested power level with peak energy efficiency of 98.5%. The
performance of the transformer is also evaluated by considering class E resonant
converter topology. The simulation results show that, for the output power level of
18W, the energy efficiency of the isolated class E DC-DC converter with GaN
HEMT at a switching frequency of 5MHz is reported to be 88.5%. This paper
emphasizes the feasibility for the development of the next generation high power
density, low profile, highly energy efficient isolated converter suitable for various
applications.

113
11.2 AUTHORS CONTRIBUTIONS
The contribution of all the authors of nine papers in this thesis is summarized and
is given in table 12. In this table, M and C corresponds to main author and co-
author of the papers.
Table 12. Authors Contributions
Paper HK RA KB AM SH Contributions
I M C C - - HK: Estimation of transformer parameters for flyback
converter, implementation of flyback topology,
experimental and theoretical analysis of hard switching
and soft switching of converter, loss estimation of
converter
RA: Transformer design, parameter extraction and
analysis of transformer in converter circuit, review of
paper
KB: Review of paper and supervision

II M C C - - HK: Idea, implementation and analyzing the Converter
results using two different material devices (Si MOSFET
and GaN HEMT) in MHz frequency region
RA: Transformer design, analysis of transformer in
converter circuit, review of paper
KB: Review of paper and Supervision

III M C C - - HK: Idea and implementation of using GaN HEMT as
low side switch in Cascode flyback converter. Simulation
and experimental analysis of the designed converter
using coreless PCB transformer
RA: Transformer design, modelling, analysis of
transformer operation in converter, review of paper
KB: Review of paper and supervision

IV C C C M - HK: Design of passive gate drive circuitry, discussion
and review of paper
RA: Power and signal transformer design, secondary
inductor design and parameter extraction for the
designed elements, review of paper
KB: Supervision and review of paper
AM: Implementation and experimental analysis of half
bridge converter

V M C C - - HK: Implementation of series resonant converter
topology using coreless PCB transformer, theoretical,
simulation and experimental analysis of the designed
converter and loss estimation of the converter, PCB
design of converter
RA: Proposal of design guidelines for both the power
and signal transformers, design and analysis of the
transformers, parameter extraction and experimental
114
analysis of transformer, review of paper

VI M C C - C HK: Design and analysis of multiresonant converter
using novel planar power transformer, implementation
and optimization of code using dsPIC microcontroller for
optimized dead time between gate drive signals of main
GaN HEMTs and synchronous devices (GaN HEMTs) to
obtain high energy efficiency, experimental evaluation of
the designed multiresonant converter
RA: Design of novel planar transformer and secondary
inductor, parameter extraction, power tests of designed
power transformer and review of paper
SH: PCB Design, selection of high speed digital
optocoupler

VII M C C - - HK: Design and analysis of multiresonant converter for
given power transfer application, simulation and
experimental evaluation of converter, improvement of
light load efficiency using pulse skip modulation
technique. Comparison of synchronous rectification
using GaN HEMTs and diode rectification using
schottky diodes for the given power transfer application
RA: Power transformer design guidelines, secondary
inductor design, parameter extraction, review of paper

VIII M C C - - HK: Theoretical estimation, simulation and experimental
evaluation of LLC resonant converter in MHz frequency
region for laptop adapter application at low line input
voltage
RA: Power transformer design, discussion and analysis
of transformer performance in high frequency region,
review of paper

IX C M C - - HK: Simulation and theoretical analysis of class E
resonant converter and discussion of results, review of
paper
RA: Design and characterization of high performance
transformer suitable for class E resonant converter

[1] Hari Babu Kotte (HK); [2] Radhika Ambatipudi (RA); [3] Kent Bertilsson (KB)
[4] Abdul Majid (AM); [5] Stefan Haller (SH)
115
12 THESIS SUMMARY, CONCLUSIONS AND FUTURE WORK
In this chapter, the summary of the thesis, conclusions drawn from the thesis and
the future work based upon the presented work will be covered.

12.1 THESIS SUMMARY
The overall thesis is summarized in chapters as follows.

Chapter 1: This chapter provides a brief introduction to the requirement of high
frequency, low profile and energy efficient converters in the modern era and the
challenges to be faced during this process. In addition to this, the background of
the thesis and the motivation behind the work together with the objectives of the
thesis and the method followed to achieve these goals. Finally, the outline of the
thesis is presented.

Chapter 2: This chapter introduces the importance of the gate drivers for driving
the power MOSFETs utilized in high speed SMPS. It gives a brief idea of the
switching model of a MOSFET and describes various modes of operation during
both the turn-on and turn-off operation of a power MOSFET together with a gate
driver, which signifies the importance of parasitic elements. The significance of the
gate drive power consumption in switching converters is described and also
various types of gate drive losses caused by the total gate charge, quiescent
currents and output voltage transitions were introduced. Different commercially
available MOSFET drivers were compared in terms of their rise/fall times and the
gate drive power consumption both analytically and practically.

Chapter 3: In this chapter, a brief introduction to a flyback converter and their
different modes of operation was discussed. The amount of inductance required
for the multilayered coreless PCB flyback transformer with respect to frequency
was estimated in both the DCM and CCM modes of operation. An introduction to
a multi-layered coreless PCB transformer, its geometrical and electrical parameters
was provided. A hard switched flyback converter, the problems corresponding to
it and the solutions to those problems were discussed briefly. Different types of
soft switched flyback converters such as ZVS and ZCS, the operation and condition
for the ZVS in quasi resonant flyback converters were presented. The modelling of
a MOSFET and the analysis of a converter using a coreless PCB transformer with
simulation software was also covered in this chapter. Finally the experimental
results of the ZVS quasi resonant flyback converter for a power level of up to 10W
and the associated waveforms were illustrated.

Chapter 4: This chapter introduces the importance of power MOSFETs in modern
high frequency SMPS and the limitations of Si material for these applications. The
116
need for the new semiconductor materials for the latest power management
developments was discussed. Also a brief idea about the new semiconductor
materials and their important features utilised for power conversion applications
was presented. The advantages of GaN HEMTs were discussed as compared to its
counterpart Si MOSFET in ZVS flyback converters operated in the MHz frequency
region were examined. A figure of merit in terms of conduction loss and gate drive
power consumption was also calculated for both devices and presented. The
experimental results of the converter with both devices was carried out and it was
found that for the same output power, the energy efficiency when using the GaN
HEMT was increased by 8 - 10% as compared to the Si MOSFET. In the case of the
converter with the GaN HEMT, the gate drive power consumption is
approximately reduced by a factor of 11 as compared to that for the Si MOSFET at
4MHz switching frequency. For the same load power, the loss estimation w.r.t to
switching devices in quasi resonant flyback converter is performed and is
represented as bar graph.

Chapter 5: In this chapter, initially, the significance for implementing the cascode
converter using two MOSFETs in high speed SMPS is discussed. The electrical
parameters of a multi-layered coreless PCB step-down 8:1 power transformer
utilized in the converter circuit are presented. The operating principle of the
cascode converter with a low voltage (GaN/Si) and a high voltage (Si) MOSFET in
different modes of operation is covered. Simulation and experimental results of the
cascode flyback converter in one of the cases is demonstrated. The energy
efficiency improvement in the cascode converter with the low voltage GaN HEMT
as compared to that for the single flyback converter is obtained due to the
improvement in gate drive power consumption, lower stress on high voltage
MOSFET and reduced switching losses of the devices. Detailed loss estimation of
the cascode converter in terms of switching/conduction losses of devices,
transformer losses, diode conduction losses etc., is presented. The comparison of
the cascode converter with a single switch flyback converter shows that there is a
significant improvement in the energy efficiency and higher switching speeds with
the assistance of the cascode converter for the given output power.

Chapter 6: This chapter gives a brief introduction to the requirement of gate drive
transformer for driving the high side power MOSFET in high speed SMPS.
Different possibilities in relation to building floating gate drive circuitry are
described. The designed gate drive circuitry including a MLCLPCB signal
transformer was simulated for different duty cycle ratios in the frequency range of
1.1 - 4.5MHz. The measured gate drive signals and its power consumption over the
frequency range are shown, and it is found to be around 0.6W within the
frequency range of 1.5 - 3.75MHz.
117
Chapter 7: This chapter discusses the implementation of the isolated low profile
series resonant converter using a multilayered coreless PCB transformer in the
MHz frequency region complemented with the necessary theory related to SRC.
For the given specifications of the converter, the simulation and experimental
results of the SRC using the gate drive circuitry discussed in chapter 6 are
presented. The measured energy efficiency of the SRC at the tested output power
level of 34.5W and in the frequency range of 2.4 2.75MHz is 86.5%.

Chapter 8: In this chapter, the design and analysis of a high frequency
multiresonant (LCC) converter using a novel planar power transformer and GaN
HEMTs is described. For different converter specifications, the simulation and
experimental results of an MRC suitable for both DC/DC and AC/DC converter
applications are presented. The comparative results of diode rectification and
synchronous rectification for the given power transfer application are discussed.
The concept of pulse skip modulation technique for light load efficiency
improvement was presented, with the aid of analytical equations and simulations
for the high frequency MRC.

Chapter 9: This chapter presents the other version of a multiresonant converter i.e.,
an LLC resonant converter in the MHz frequency region using the integrated
planar power transformer and GaN HEMTs suitable for laptop adapter
applications. The simulation and experimental results of the converter for the
considered converter specifications are presented. The comparison of the LCC
resonant converter with respect to the designed high frequency LLC resonant
converter is discussed.

Chapter 10: In this chapter, the simulation results of the class E isolated DC/DC
converter using the high performance high power density planar power
transformer is discussed. The potential applications using the designed
transformer with the assistance of class E resonant converter topology is proposed.

12.2 CONCLUSIONS
This thesis has studied several isolated resonant converter topologies which are
suitable for various consumer applications using GaN HEMTs along with the
novel multilayered coreless and core based planar transformer technology. The
special feature of the converters are that they were operated in the MHz frequency
region rather than the current industrial switching frequencies which are in the
range of few hundred kHz making it feasible for obtaining the low profile, high
power density converters without sacrificing the energy efficiency.
The experimental results of the converter operating in MHz frequency region using
coreless PCB transformer technology show the potential of utilizing these coreless
118
PCB transformers for various stringent height DC-DC converter low power
applications where the total height of the converter is a major concern.
As the obtained experimental results of the converters with the assistance of novel
core based planar transformer technology together with GaN HEMTs shows the
promising performance in MHz frequency region which is considered as a special
feature compared to commercially available isolated DC/DC or AC/DC converters,
they have the potential to be commercialized for various applications such as
laptop adapter, mobile chargers, telecommunication etc., In this regard, the
research on these converters laid a path for the development phase in the SEPS
Technologies AB, where these converters are going to be commercialized in near
future.

12.3 FUTURE WORK
Due to the non-availability of the commercial high voltage GaN HEMTs, in this
thesis, the experiments were performed on the AC/DC converter for low line input
voltage corresponding to the universal input voltage range for realizing the
consumer applications such as laptop adapter. In future, the work can be extended
for the universal input voltage range either with the availability of these devices or
by utilizing the multilevel converter topologies. However, the latter solution
requires more no. of switches which in turn increases the switching losses of the
device, increases the complexity of the control and component cost.

For wide line input voltage range, it is required to investigate the modulation
strategy for regulating the output voltage of the converter and it should be
implemented in closed loop control.

In terms of isolated class E resonant converter topology, the simulations were
carried out and based on these results, in future, the experimental analysis of the
converter has to be carried out. The isolated class E resonant converter can be
implemented at ISM band frequency of 6.78MHz with the designed high
performance transformer by replacing the secondary side diode with the GaN
HEMT which makes it suitable for many applications.

119
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Thesis for the degree of Doctor of Technology

Vgs >Vgs_miller): During this mode of operation, the input capacitance

Vth): In this mode of operation, the gate source voltage starts

FET-Silicon Shoot-Out Vol.9:

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