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FPGA by using ChipScope
analyzer. You should have a clear understanding on the flow of packets through different
interfaces of your design when debugging PCIe issues. You should be able to identify what types of packets are seen
on those interfaces by analyzing the packet header. This document provides a detailed description on tracking
packets through different interfaces in the core. Some helpful techniques on how to select signals for triggering in
ChipScope analyzer and how to set the correct trigger to capture packets on different interfaces are discussed.
The main objective of this document is to help you debug your design by going into the low level details of the core.
This document will help you to debug issues related to both link training and PCIe packet traffic. ChipScope analyzer
screenshots are provided to illustrate how to analyze packets and signals.
Signal and Packet Analysis Interfaces
Figure 1 shows a block diagram of different components in Integrated PCIe Block in Virtex-6 FPGA. It shows different
interfaces between those components. The interfaces are numbered to make it easier to reference in rest of the
document.
Xilinx Answer 50234 - Virtex-6 Integrated PCIe Block Wrapper Debugging and Packet Analysis Guide 1
Copyright 2012 Xilinx
Figure 1 Top-level Functional Blocks and Interfaces
The main interfaces are as follows:
1. PCIe Link Interface
2. Transceiver Interface
3. MIM Interface
4. TRN TX Interface
5. TRN RX Interface
6. PIO TX Interface
7. PIO RX Interface
8. CFG Interface
9. Physical Layer Interface
In this document, it is illustrated on how to use ChipScope analyzer to capture and track a particular packet along
each of these interfaces. It does not offer much flexibility in triggering for the correct capture with only one trigger port.
If you need to trigger only when a completion packet is presented to the core for a particular incoming read, you would
need to trigger only after two conditions are met; memory read packet on the receive interface and the corresponding
completion packet on the transmit interface. In the following sections, techniques to capture packets in similar
scenarios are discussed.
Inserting ChipScope Core
This section describes the process of using ChipScope
v1.7
generated from the CORE Generator