IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 11, NO.

3, MAY 2012 431

Research Letters
A Low-Power 40-Gb/s 1:2 Demultiplexer IC Based on a Resonant
Tunneling Diode
Jooseok Lee, Jongwon Lee, and Kyounghoon Yang, Senior Member, IEEE
AbstractA low-power 1:2 demultiplexer (DEMUX) IC based
on a resonant tunneling diode (RTD) is proposed. In order to
achieve low-power consumption, the unique negative differential
resistance (NDR) characteristics arising from the quantum effect
of the RTD are exploited. The proposed DEMUX IC consists of an
return to zero (RZ)-mode 1:2 demultiplexing block and an RZ-to-
nonreturnto zero converting block, whichhave a compact structure
based on the NDR-based circuit topologies. By implementing the
proposed IC using an InP RTD/heterojunction bipolar transistor
monolithic microwave integrated circuit technology, 1:2 demulti-
plexing operation up to 40 Gb/s has been achieved with low-power
consumption of 61 mW. In addition, the result is the rst demon-
stration of a 40-Gb/s-level current-mode-logic-type DEMUX IC
based on the NDR topology.
Index TermsDemultiplexing, negative differential resistance
(NDR), quantum effect, resonant tunneling diode (RTD).
I. INTRODUCTION
I
N the near future, conventional semiconductor devices are
expected to reach the saturation point of performance en-
hancement by device scaling. Recently, nanoscale quantum-
effect devices have gained attention in relation to efforts to
overcome the physical limitations faced by the current semicon-
ductor technology [1]. Among various nanoscale devices, reso-
nant tunneling diodes (RTDs) are considered the most promis-
ing devices. The unique nonlinear IV characteristic of RTDs,
which exhibit the negative differential resistance (NDR), can be
exploited to develop new functional digital logic circuits with
a small device count [2]. Furthermore, the RTDs show high
switching capability due to the fast quantum-effect tunneling
phenomena and small parasitic capacitance [3]. Using these
characteristics of RTDs, various RTD-based high-performance
digital circuit topologies [4][8] have been reported to date. In
our previous study, we carried out the fundamental develop-
ment work for implementing high-speed digital communication
ICs using the RTD-based IC topology. The key electronic com-
ponents of the high-speed digital communication system, such
Manuscript received May 26, 2011; accepted September 27, 2011. Date of
publication November 15, 2011; date of current version May 9, 2012. The
review of this paper was arranged by Associate Editor S. Assefa.
The authors are with the Department of Electrical Engineering, Korea Ad-
vanced Institute of Science and Technology, Daejeon 305-701, Korea (e-mail:
leejooseok@kaist.ac.kr; temuchin80@kaist.ac.kr; khyang@ee.kaist.ac.kr).
Color versions of one or more of the gures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identier 10.1109/TNANO.2011.2171988
Fig. 1. Block diagram of the proposed RTD-based 1:2 DEMUX IC.
as a D-ip op [9], a multiplexer [10], and a static frequency
divider [11], were developed with signicantly reduced circuit
complexity at much lower power consumption. In the present
paper, we propose a new RTD-based 1:2 demultiplexer (DE-
MUX) IC, which is a crucial receiver component of high-speed
digital communication systems. The proposed DEMUX IC has
been implemented by using an InP RTD/heterojunction bipo-
lar transistor (HBT) monolithic microwave integrated circuit
(MMIC) technology, and performance up to 40 Gb/s has been
measured by on-wafer high-speed test setups.
II. CIRCUIT TOPOLOGY
Fig. 1 shows a block diagram of the proposed RTD-based
1:2 DEMUX IC. The DEMUX IC is basically composed of
a 1:2 return to zero (RZ)-mode demultiplexing block and an
RZ-to-nonreturn to zero (NRZ) converting block. The 1:2 RZ-
mode demultiplexing block consists of two current-mode logic
monostable to bistable logic elements (CML-MOBILEs) and
two RZ-to-NRZ converting blocks of SET/RESET latches. As
shown in Fig. 2, each basic building block has a compact circuit
structure by exploiting the high circuit functionality based on
the NDR-based topology. The detailed operation principles of
each building block have been previously reported [9], [12].
Fig. 3 shows the timing diagramof the proposed 1:2 DEMUX
IC. The operation principle of the RTD-based 1:2 DEMUX IC
is as follows. In the 1:2 DEMUX IC, the CML-MOBILEs,
1536-125X/$26.00 2011 IEEE
432 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 11, NO. 3, MAY 2012
Fig. 2. Circuit schematics of the basic building blocks. (a) CML MOBILE
RZ-mode D-ip op and (b) SET/RESET latch.
Fig. 3. Timing diagram of the proposed RTD-based 1:2 DEMUX IC (dotted
arrows represent the edge-triggering operations).
which are driven by two clock signals (Clock and Clock) with
a phase difference of 180

, generate RZ-mode demultiplexed

data streams (RZ
A
and RZ
B
) from the input data stream of D
in
.
The demultiplexed RZ-mode data streams are then converted
to NRZ-mode data streams by the SET/RESET latch circuit.
Consequently, the nal output data signals (OUT
A
and OUT
B
)
are demultiplexed NRZ data with a half bitrate of the input NRZ
data bit stream.
The major differences in the circuit topology of the RTD-
based DEMUX IC from the conventional transistor-based DE-
MUX IC can be described as follows. The conventional DE-
MUX IC topology requires two master/slave D-latch circuits
at each data path to generate the edge-triggered and latched
data [13], [14]. Furthermore, since the conventional D-latch
circuit has positive feedback path for holding operation, the
self-loading effect of the D-latch circuit is relatively large. On
the contrary, the proposed RTD-based DEMUX IC needs only
one CML-MOBILE with the self-latching chracteristic for both
the edge-triggering and latching operation at each data path. By
using the compact CML-MOBILE toplogy with self-latching
characterstics, the circuit complexity is signicantly reduced,
as shown in Table I. The device count in the RTD-based 1:2
DEMUX core IC is reduced to be less than 60% of that in the
conventional latch-based DEMUX core IC topology [13], [14].
In addition, there is no feedback path, the self-loading effect is
eliminated. Therefore, the high-speed opertaion can be achieved
with low tail current and reduced device count.
TABLE I
COMPARISON OF DEVICE COUNT BETWEEN THE RTD-BASED 1:2 DEMUX
AND THE CONVENTIONAL LATCH-BASED 1:2 DEMUX CORE ICS
Fig. 4. Chip microphotograph of the fabricated RTD-based 1:2 DEMUX IC.
III. FABRICATION TECHNOLOGY
The RTD-based DEMUX IC has been fabricated by using an
InP RTD/HBTMMICtechnology based on a stacked RTD/HBT
epitaxial structure. The detailed nanoscale quantum well and
stacked layer structures of RTD/HBT have been previously re-
ported [10]. The fabricated 2 2 m
2
RTDs have a peak voltage
(V
P
) of 0.3 V, a peak current density (J
P
) of 60 kA/cm
2
, and a
peak-to-current ratio (PVCR) of 13.5 at room temperature. The
fabricated 1.5 4.0 m
2
HBT shows a maximum current gain
of 50 and maximum f
T
and f
max
of 100 and 100 GHz, respec-
tively. A chip microphotograph of the implemented RTD-based
1:2 DEMUX IC is shown in Fig. 4. The chip area is 1.5
2.0 mm
2
, including the pads for probing. This chip area is ex-
pected to be further reduced by using an improved scale-down
device technology and layout optimization.
IV. MEASUREMENT RESULTS AND DISCUSSION
The performances of the RTD-based DEMUX ICs have been
characterized with an on-wafer microwave measurement setup.
In order to conrm the operational performances of the fabri-
cated RTD-based 1:2 DEMUX IC, time-domain measurements
were rst performed at 20 Gb/s. The NRZ input data signal
was generated by using two pulse pattern generators (Anritsu
MP1763B) and a commercial multiplexing unit (SHF 4005).
A signal synthesizer (Anritsu MG3694A), RF splitter, and ad-
justable phase shifters were used to obtain the clock signals
(Clock and Clock). The voltage swings for the input data and
the clock signal are 0.6 and 0.8 V
P P
, respectively. The output
waveforms of the DEMUXICwere observed by a 50-GHz band-
width digital sampling oscilloscope (Agilent 83484A). Fig. 5
shows the test input data pattern (D
in
= 1110110011011101) at
IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 11, NO. 3, MAY 2012 433
Fig. 5. Input and corresponding output waveforms of the RTD-based 1:2
DEMUX IC at 20 Gb/s operation (vertical scale: 100 mV/div; horizontal scale:
200 ps/div).
Fig. 6. Input and corresponding output waveforms of the RTD-based DEMUX
ICat 40 Gb/s operation (vertical scale: 100 mV/div; horizontal scale: 100 ps/div).
20 Gb/s and the corresponding demultiplexed output patterns at
10 Gb/s.
In order to characterize the demultiplexing operation at higher
speed, the time-domain measurement for the 1:2 RTD-based
DEMUX IC was conducted up to 40 Gb/s. Fig. 6 shows the test
input data patterns (D
in
= 1010010011110001) at 40 Gb/s and
the corresponding output patterns at 20 Gb/s. The correct output
data patterns (OUT
A
=11001100 and OUT
B
=00101101) have
been obtained from the RTD-based DEMUX IC. Fig. 7 shows
the measured eye diagrams for the outputs of the fabricated IC
at an operation speed of 40 Gb/s for input data with a word
length of 2
31
1 pseudorandom bit stream. The obtained eye
opening of the fabricated IC was 120 mV. The measured total
power consumption of the fabricated DEMUX IC including the
output buffer is 61 mW, where the 1:2 RZ-mode demultiplexing
block consumes 16 mW and the RZ-to-NRZ converter block
consumes 20 mW at a single supply voltage of 2.5 V. The
obtained power consumption of 61 mW at an operation speed
of 40 Gb/s is 60% of that in the CMOS-based conventional 40-
Gb/s-level 1:2 DEMUX [13].
While the power consumption of the CMOS-based 1:2 DE-
MUX was obtained by using a deep-submicron device technol-
ogy, that of the RTD-based 1:2 DEMUX has been obtained by
using a relatively larger device size on a 1.5 m scale in this
Fig. 7. Measured eye diagram for the outputs of the RTD-based DEMUX IC
at an operation speed of 40 Gb/s (vertical scale: 100 mV/div; horizontal scale:
20 ps/div). (a) OUT
A
. (b) OUT
B
.
paper. The high-speed and low-power performance characteris-
tics of the RTD-based DEMUX IC are expected to be further
improved compared to current state-of-the-art CMOS-based 1:2
DEMUX results [15], [16] by using an improved scaled-down
device technology.
V. CONCLUSION
An RTD-based 1:2 DEMUX IC has been proposed and
demonstrated. The unique NDR characteristics of the RTD have
been utilized in the proposed compact low-power DEMUX IC
topology. The device count used in the RTD-based DEMUX IC
is 60% of that in the conventional CML-type latch-based DE-
MUX IC. The fabricated DEMUX IC has the low-power con-
sumption of 61 mWat an operation speed of 40 Gb/s. According
to the results obtained in this paper, the quantum-effect RTD-
based IC technology is one of the most mature nanoelectron-
ics technologies suitable for the high-speed, high-functionality
applications.
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