International Journal of Research in Wireless Systems (IJRWS), Volume 2, Issue 3, October (2013)

75

Comparison of Full Adder Designs in CMOS

Amit Grover
Shaheed Bhagat Singh State Technical Campus, Moga road, Ferozepur, Punjab, India
Email: amitgrover321@gmail.com


























































ABSTRACT
A full adder circuit is one of the basic building blocks of a digital design. In general it is made by CMOS technology. In the
CMOS technology the full adder is built by 28 transistors. So, the transistor count is very high. The average power
consumption, leakage power consumption and delay are very high. In this article, a new circuit has been proposed which
is made by mainly the Transmission Gate (TG) technology that uses 18 transistors for the implementation of the Boolean
Expression of the Full Adder circuit. The decrease in the transistor count reduces the average power, Leakage power,
delay and noise. The circuit is optimized by different threshold of MOSFET technology. The comparison in terms of power
consumption of different adders is also considered. It has been found that the Carry look-ahead and Carry bypass adder
consumes more power. For the purpose of comparative analysis of TG based 8-bit different adder designs 180nm
technology is used with TANNER tool.



CONCLUSION
It has been observed that TG Based Ripple Carry Adder (RCA) logic design style exhibit better characteristics (power
dissipation and area) as compared to other design styles and the propagation delay at sum and carry output of TG Based
RCA is lesser than that of TG Based CLA and TG Based CBA. So, RCA logic style can be used where lesser power, higher
speed and lesser area are the main objectives.

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Amit Grover, Comparison of Full Adder Designs in CMOS, International Journal of
Research in Wireless Systems (IJRWS), Volume 2, Issue 3, pp. 75-78, October, 2013
ISSN: 2320 - 3617

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Comparison of Full Adder Designs in CMOS

76 International Journal of Research in Wireless Systems (IJRWS), Volume 2, Issue 3, October (2013)

I. INTRODUCTION
Realization of Very Large Scale Integrated (VLSI) circuits
includes low-power and high-speed as the important
parameters, which must be taken care of. In combinational
circuits, adder is the most commonly used circuit that play a
major role in the implementation of low power and high
speed circuits. The major research in the previous years has
been directed towards the design of low power circuits. Apart
from this smaller area, lesser delay and lesser power
dissipation are the important parameters that measure the
quality of the circuits. The major sources of power
consumption in digital CMOS circuits are shown in the
equation 1.

P
total
= P
switching
+ P
short-circuit
+ P
leakage

= (
01
x C
L
x V
dd
2
x f
clk)
+ (I
sc x
Vdd)
+ (I
leakage
x V
dd
) (1)

The first term represents the switching component of power,
where C is the load capacitance, f
clk
is the clock frequency and

01
is the node transition activity factor. The second term is
due to the direct path short circuit currents, I
sc
and the other
one is leakage current, I
leakage
that arises from substrate
injection and sub threshold effects. In our study, novel
designs for a full adder will be proposed and verified. The 8-
bit carry-select adders were designed in a 0.4pm CMOS
technology using 4 different circuit design styles. The
performance is better than the previous designs as shown
through simulation.
II. LOGIC DESIGN STYLE
The different logic styles used for a full adder design are
Ripple carry adder, Carry look-ahead and carry bypass adder.

A. Ripple Carry Adder
Figure 1 show the TG based full adder built by 18 transistors.
The circuit has been designed using a minimum length of .18
m for NMOS and PMOS with different gate widths for
NMOS and PMOS.


Fig 1: Full Adder using TG Technology
.
B. Carry Look-ahead Adder
Figure 2 shows the carry look-ahead adder built by 30
transistors using TG technology. All the simulations in the
design process has been considered using Micron
Technologys 0.18 m process models with typical n-channel
and p-channel drive, a 1.8 V power supply.


Fig 2: Carry Look-ahead Adder using TG Technology

C. Carry Bypass Adder
Figure 3 shows the 2 bit carry bypass adder built by 60
transistors using TG technology. All the simulations in the
design process has been considered using Micron
Technologys 0.18 m process models with typical n-channel
and p-channel drive, a 1.8 V power supply.


Fig 3: Carry Bypass Adder using TG Technology

III.PROPAGATION DELAY AT SUM AND CARRY OUTPUTS
OF 8-BIT TG BASED RIPPLE CARRY ADDER
In Figure 4 and 5 the results of 8-bit ripple carry adder are
obtained. In this the result is carried out at different widths
and minimum length of 0.18m. In the below waveforms we
calculate delay at sum output and at carry output. The value
of delay at output sum is 2.18 n sec and at carry is 0.73 n sec.

Comparison of Full Adder Designs in CMOS

International Journal of Research in Wireless Systems (IJRWS), Volume 2, Issue 3, October (2013)

77




Fig 4: Delay at sum output of full adder



Fig 5: Delay at carry output of full adder

IV.PROPAGATION DELAY AT SUM AND CARRY OUTPUTS
OF 8-BIT TG BASED CARRY LOOK AHEAD ADDER
In Figure 6 and 7 the results of 8-bit carry look-ahead adder
are obtained. In this the result is carried out at different
widths and minimum length of 0.18m. In these waveforms
we have calculated delay at sum output and at carry output.
The value of delay at output sum and carry is 1.46 n sec.


Fig 6: Delay at sum output of carry look-ahead adder



Fig 7: Delay at Carry output of carry look-ahead adder

V.PROPAGATION DELAY AT SUM AND CARRY OUTPUTS
OF 8-BIT TG BASED CARRY BYPASS ADDER
In Figure 8 and 9 the results of 8-bit carry bypass adder are
obtained. In this the result is carried out at different widths
and minimum length of 0.18m. In these waveforms we have
calculated delay at sum output and at carry output. The value
of delay at output sum 1.46 n sec and at carry is 1.09 n sec.



Fig 8: Delay at sum output of carry bypass adder


Fig 9: Delay at carry output of carry bypass adder
Comparison of Full Adder Designs in CMOS

78 International Journal of Research in Wireless Systems (IJRWS), Volume 2, Issue 3, October (2013)


VI.RESULTS
The result is carried out at 1.8v supply voltage using a gate
width of .64 m for NMOS and 1.7 m PMOS and a
minimum length of .18 m for NMOS and PMOS.

TABLE I. PERFORMANCE PARAMETERS OF 8 BIT ADDERS


It has been concluded from table I, that TG based ripple carry
adder has lesser no. of transistor count which signify lesser
area. Lesser area means lesser average power consumption
and lesser power delay.

VII.CONCLUSIONS
It has been observed that TG Based Ripple Carry Adder (RCA)
logic design style exhibit better characteristics (power
dissipation and area) as compared to other design styles and
the propagation delay at sum and carry output of TG Based
RCA is lesser than that of TG Based CLA and TG Based CBA.
So, RCA logic style can be used where lesser power, higher
speed and lesser area are the main objectives
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AUTHOR'S BIOGRAPHY




Amit Grover became a Member (M) of
Association ISTE in 2006, a Senior Member
(SM) of society SELCOME in September
2009, and a Project-In charge (PI) in august 2011 and in
September 2012. The author place of birth is Ferozepur,
Punjab, India on 27
th
, September 1980.The author received
his M. Tech degree in Electronics and Communication
Engineering from Punjab Technical University, Kapurthla,
Punjab, India in 2008 and received his B. Tech degree in
Electronics and Communication Engineering from Punjab
Technical University, Kapurthala, Punjab, India in 2001.
Currently, he is working as an Assistant Professor in Shaheed
Bhagat Singh State Technical Campus, Ferozepur, Punjab,
India. The author is a Reviewer of many Reputed
International Journals. His area of interest includes signal
processing, MIMO systems, Wireless mobile communication;
high speed digital communications, 4G Wireless
Communications and VLSI Design.