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DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING


K.S.R. COLLEGE OF ENGINEERING: TIRUCHENGODE 637 215.
COURSE / LESSON PLAN SCHEDULE
NAME
CLASS
SUBJECT

: SIVASANKAR RAJAMANI.P
: M.E (VLSI)
: CMOS VLSI Design

TEXT BOOKS:

1. Neil.H.E. Weste and K.Eshragian, Principles of CMOS VLSI Design, 2nd Edition, Addison.
Wesley,2005.
REFERENCES:

1. Wayne Wolf, Modern VLSI Design, Pearson Education, 2002, 3rd Edition, 2007.
2. Douglas a. Pucknell and K.Eshragian, Basic VLSI Design, 3rd Edition, PHI, 2011.
3. R. Jacob Baker, Harry W. LI. & David K. Boyce., CMOS Circuit Design, 3rd Indian reprint,
PHI- 2000.
LEGEND:
L
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pp
Sl. No

- Lecture
- Black Board
- Pages

Lecture
Hour

1.
1

L1

2.
2
3.
3
4.

L2

PPT
OHP
Rx

- Power Point
- Over Head Projector
- Reference

Topics to be covered

Teaching
Aid
Required

UNIT-I INTRODUCTION TO CMOS CIRCUITS


BB
MOS Transistors, MOS Transistor Switches
BB

L3

CMOS Logic, Circuit and System


Representations
MOS Transistor Theory

L4

Introduction MOS Device Design Equations

5.
4

L5

The Complementary CMOS Inverter - DC


Characteristics

BB

6.
5

L6

Static Load MOS Inverters,

BB

7.

L7

8.
7
9.
8

L8

The Differential Inverter, The Transmission


Gate
The Tri State Inverter, Bipolar Devices..

BB

L9

Latch up in CMOS circuits

BB

KSRCE/ECE

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Book No./Page No

TX1/pp 27-29
RX2/pp 81-91
TX1/pp31 43
RX3/pp RX5/pp
TX1/pp 63 -83,
RX2/pp 187 -190
TX1/pp 38 -48,
TX1/pp 83 94
RX2/pp 303-304
RX3/pp 364-404
TX1/pp 94 - 103
RX2/pp 295-299
RX1/pp 579,583
TX1/pp 103 - 108
TX1/pp 113 118
RX3/pp 37
TX1/pp 150 151

CMOS VLSI Design

2. 2
UNIT- II CIRCUIT CHARACTERSATION AND PERFORMANCE ESTIMATION
10. L10, L11
8
11.
L12
9
12.
L13
10
13.
L14
11
14.
L15
12
15. L16, L17
13
16.
L18
14

Introduction, Resistance Estimation

BB

Capacitance Estimation, Inductance

OHP

Switching Characteristics

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CMOS-Gate Transistor Sizing,

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Power Dissipation, Sizing Routing


Conductors,
Charge Sharing, Design Margining,
Reliability
Propagation delays

BB
OHP
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TX1/pp 198-201
RX2/pp 126-128
TX1/pp 201-229
RX3/pp 291-209
TX1/pp 229-245
RX3/pp 296-312
TX1/pp 248-252
RX3/pp 240-246
TX1/pp 253-260
TX1/pp 262-269
RX2/pp 119-120
TX1/pp 394-395

UNIT III CMOS CIRCUIT AND LOGIC DESIGN


17.
13
18.
14
19.
15
20.
21.
16
22.
17

L19
L20,
L21
L22,
L23
L24, L25
L26
L27

CMOS Logic Gate Design


Basic Physical Design of Simple Gate
CMOS Logic Structures
Clocking Strategies
I/O Structures, Low Power Design.
Stick Diagram & Design rules

BB
BB
BB
BB
OHP
BB

TX1/pp 284-294
RX1/pp 291-292
TX1/pp 295-313
RX1/pp 326-367
TX1/pp 317-336
RX3/pp176-179
TX1/pp 339-377
RX3/pp182-188
TX1/pp,379-390
RX3/pp 229-240
TX1/pp 472-476

UNIT - IV SYSTEMS DESIGN AND DESIGN METHOD


23.
19

L28

Design Strategies ,CMOS Chip Design


Options

BB

24. L29, L30


20

Design Methods, Design Capture Tools,


Design Verification Tools

PPT

25.

L31

Design Economics, Data Sheets,

PPT

26.
21
27.
22
28.
23
29.
24

L32

CMOS Testing ,Manufacturing Test


Principles
Design Strategies for Test, Chip Level Test
Techniques
System Level Test Techniques, Layout
Design for Improved Testability.

PPT

The Real World VLSI DESIGN

BB

L33,
L34
L35
L36

KSRCE/ECE

BB
BB

TX1/pp 404-444
RX2/pp 353-385
RX3/pp 95-100
TX1/pp 446-460
RX2/pp 525-530
RX3/pp 360-361
TX1/pp 470-478
RX4/pp 532-542
TX1/pp 488-505
TX1/pp 507-520
RX3/pp 404-412
TX1/pp 520-526,
RX3/pp 353-356
TX1/pp 735-740

CMOS VLSI Design

2. 3
UNIT V- CMOS SUB SYSTEM DESIGN
30.
L37,
26
L38
31. L39 ,L40
27
32.
L41
29
33.
L42
30
34.
L43
31
35.
L44
32
36.
L45

Data Path Operations-Addition/Subtraction

BB

OHP

TX1/pp 535-556
RX1/pp 274-278
TX1/pp 559-560
RX3/pp 124-129
TX1/pp 561-563
RX3/pp 428-429
TX1/pp 564-605
RX3/pp 415-418
TX1/pp 612-613

Parity Generators ,Comparators, Zero/One


Detectors
Binary Counters, ALUs

PPT

Multiplication, Shifters, Memory Elements

BB

Control Logic Implementation

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TX1/pp 617-626

CASE Study in VLSI

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TX1/pp 537-538

Control-FSM

STAFF IN-CHARGE
C.Arun Prasath

KSRCE/ECE

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HOD-ECE

CMOS VLSI Design

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