CLOSED LOOP CONTROL OF PSFB CONVERTER

A new algorithm is proposed to implement the closed loop control of magnetically integrated
and decoupled phase shifted forward bridge dc-dc converter with a voltage doubler :
The algorithm for closed loop control is developed from the switching scheme, so first
switching scheme is discussed in fig 4.1 and fig 4.2:

(a)

b)


c)
Fig. 4.1a) magnetically integrated & decoupled PSFB dc/dc converter with voltage doubler . b) pulse generation
scheme for the switches A(S1) and B(S3).c) matlab implementation of the switching scheme
A saw tooth voltage signal is compared with a dc voltage signal Vdc base ,where the Vdc
base can change values within the limits upper and lower values as shown in the figure 4.1b),
corresponding to a movement in V
dc
base theres a phase displacement in the switching signal
switch_ A relative to switch C. Thus a given load demand is achieved by controlling the
overlap of switching pulses A and C.
State_1 is achieved by comparing saw tooth with the lower limit and the state_2 by
comparing with the V
dc
reference. The pulse are fed to an edge triggered (divide by 2 mode)
D flip-flop as clock signals, to get the switching states A and C.
Commonly used closed loop model makes the moving pulse(the pulse that makes phase
displacement) oscillate when the load demand is met at the steady state, thereby giving the
system the property of inertia with the output voltage oscillating about the reference voltage,
though within the error limits. This makes the power transfer and the flux density across the
transformer, the function of oscillating frequency, shown in fig 4.1. The conventional closed
loop control is shown in fig 4.2.

a) flux density variation vs. time

b) Detailed flux density variation at the peaks
Fig 4.2 Dependency of flux density on oscillating frequency


4.1 Conventional closed loop control for PSFB dc/dc converter
Start
Inintialize
Vdc_base
Calculate
error,e
If
e=0
Vdc_base=
current
value
K=contant, e>0
Vdc_base=ke
No
If
Vdc_lower<Vdc_base
Vdc_base=
Vdc_lower
No
If
Vdc_base<Vdc_upper
Yes
Vdc_base=
Vdc_upper
No
Yes
stop
yes

Fig 4.2 conventional closed loop control.


4.2 Proposed closed loop control for PSFB dc/dc converter
An algorithm is developed and implemented on a simulink model of PSFB converter boost
mode to mitigate this problem. The algorithm basically freezes the Vdc_base value when it
crosses the steady state value sufficient number of times.
The algorithm is shown as a flow chart in fig 4.3.
Start
Inintialize
Vdc_base
If time t< Ts
Calculate
error,e
If
Lower limit ,-
l<e<upper
limit,l
K=contant, e>0
Vdc_base=ke
No
Yes
Yes
Vdc_base=
current
value
Calculate
error,e
If
Lower limit ,-
l<e<upper
limit,l
Yes
No
If theres a change in
input voltage or
reference or load
Vdc_base=
current
value
No
K=contant, e>0
Vdc_base=ke
No
If
Vdc_lower<Vdc_base
Vdc_base=
Vdc_lower
No
If
Vdc_base<Vdc_upper
Yes
Vdc_base=
Vdc_upper
No
Yes
stop
Reset
time=0
yes

Fig 4.3 Vdc_base control algorithm
4.2.1 Explanation
The flowchart first initializes Vdc_base , then it takes care of the transient response of the
system by giving a delay in its action of time Ts, otherwise the system behavior may be
poorly read by the algorithm. After Ts the algorithm continuously updates the Vdc_base
value so that output voltage can be achieved within limits. When this is achieved the
corresponding Vdc_base value is freezed.
A safety measure is taken to stop any dynamic behavior that causes the Vdc_base values to
overshoot its limits; in that case the Vdc_base is updated to the crossed limit value till the
error is analyzed again.
A dynamic state change like change in reference, input or load will bring out the system from
its frozen state and it will start working all over again in the same way as above.
The block wise implementation on simulink is as follows,
Fig 4.4 closed loop control and pulse generation for switches A,B,C and D.

Fig 4.5 subsystem details of algorithm implementation
Fig 4.6 error estimate details
Fig 4.6 shows the logic for error estimation, whenever the error is within limits it sets the
out1=1.

Fig 4.7 Vdc_estimate details (the dynamic behavior of the system is excluded to make it simpler).


Fig 4.8 a) circuit diagram of 4-bit ripple counter b) clock cycle of counter
Whenever the error signal comes within limit it triggers the ripple counter, after eight such
crossing the fourth flip-flop is set to 1, this value is latched onto the D latch. This latching
enables Vdc_base state check to 1 which in turn latches the current value of Vdc_base.
The number of bits of the ripple counter can be increased or decreased depending upon the
response of the system.
In this whole set the algorithmic block that deals with the dynamic state change of the
system is excluded to make the implementation simpler.

Fig 4.9 Vdc_limit details
Whenever any dynamic change i.e sudden change in input, load or reference makes the
Vdc_base to cross the upper or lower limits, it sets the Vdc_base value to the last crossed
limit until the system in reset or restarted or the error calculation is within limits again.

a)

b)
Fig 4.10 flux density vs. time
4.3 Conclusions:
Closed loop control scheme is implemented for PSFB dc/dc converter.
A new control scheme is proposed and implemented on the PSFB dc/dc converter for
eliminating high frequency components in the flux density, on the matlab(simulink) platform.