Testability Management Action Group

TP-101D 2008









Testability
Guidelines



















2008 SMTA Publishing 5200 Willson Road Suite 215 Edina, MN 55424 952-920-7682 smta@smta.org www.smta.org
SMTA/TMAG TESTABILITY GUIDELINES TP-101D
Table of Contents 1
FORWARD 2
INTRODUCTION 4
CHAPTER 1
Design for Testability and Intelligent Test 7
CHAPTER 2
Probing and Fixturing Guidelines 12
CHAPTER 3
Flying Probe Guidelines 20
CHAPTER 4
Vectorless Test and Fixturing Guidelines 24
Board Layout Issues 27
Vectorless Fixture Design 29
CHAPTER 5
Automated Optical Inspection (AOI) Inspectability Guidelines 31
CHAPTER 6
X-ray Inspection Guidelines 37
Transmission AXI Guidelines 40
Cross-section AXI Guidelines 41
Combo AXI Guidelines 42
CHAPTER 7
Electrical Design Guidelines 43
CHAPTER 8
Boundary Scan Guidelines 52
Device selection and documentation 55
General board design rules 56
TAP (Test Access Port) signals 57
In-system programming considerations 58
Design practices 59
Access to the target board 60
CHAPTER 9
Analog and Mixed Signal Guidelines 61
CHAPTER 10
Built-In Self Test Guidelines 63
General Guidelines 65
Board-Level BIST Guidelines 68
System Level and Software BIT 69
CHAPTER 11
Design for Testability (DFT) Diagnoses and Support Guidelines 74
GLOSSARY 79
REFERENCES AND BIBLIOGRAPHY 81
TABLE OF CONTENTS
SMTA/TMAG Testability Guidelines Forward
2 Fourth Edition
FORWARD
The 2008 SMTA Testability Guidelines were con-
structed by several groups of test and testability pro-
fessionals. Building on the 2002 SMTA Testability
Guidelines many of the SMTA members stepped up to
the plate to update the Guidelines, which is something
they helped create 6 years earlier. There were also new
SMTA members who contributed to this more recent
document. Additionally, SMTA was joined in this ef-
fort by a group of testability professionals with their
own organization. Much of this effort was the product
of members of a recently formed not-for-proft orga-
nization, the Testability Management Action Group
(TMAG).
No one working on this document was paid. Their mo-
tivation was the ability to help their profession by mak-
ing it possible to comprehensively test and accurately
diagnose the complex circuitry produced at least for
the next few years. What follows is an alphabetical
list of individuals who helped create these Guidelines
either by working on the 2008 edition, or a previous
edition. We placed in bold the names of those who
worked on this issue:
Gerry Adams, Siemens Healthcare Diagnostics
Tony Ambler, University of Texas *
Jim Arient, Test Coach Corp.
David Bernard, Dage Precision Industries Inc.
James Chen, Huawei Technologies
Phillip Chen, L3 Communications
Jinwen Chen, Huawei Technologies
C.J. Clark, Intellitech *
Luciano Cornelio, Teradyne
Scott Davidson, Sun Microsystems *
Ray Dellecker, JTAG Technologies
Craig DePaul, DSI International *
Michael Early, Teradyne
Heiko Ehrenberg, Goepel Electronics *
Brian Erickson, JTAG Technologies *
Ryan Flaherty, SMTA
Josh Ferry, Teradyne/ATE Ops
Dennis E. Hecht, The Boeing Company *
Steve Hoover, Test Coach Corp.
Chris Jacobsen, Agilent Technologies
Stacy Johnson, Agilent Technologies
Brad Jolly, Agilent Technologies
Jesse Katzman of SMTA
Michael Keller, American Society of Test Engineers
Joe Kirschling, Agilent
Jana Knezovich, Agilent Technologies
Jim Lauffer, DSI International *
Ruben Lebron, US Navy *
Glen Leinbach, Agilent Technologies
John E. McDermid, JEM Consulting
Guoqing Li, Huawei Technologies
Duane Lowenstein, Agilent Technologies *
John Maxwell, JM Inc.
Vishal Narang, Enterasys
Carl Nielsen, Intellitech *
Carlos OFarrill, Jabil Circuit, Inc.
Barry Odbert, Agilent Technologies
Stig Oresjo, Agilent Technologies
Kenneth Parker, Agilent Technologies
Steve Pateras, LogicVision *
Jeremy Pemberton-Pigott, Agilent Technologies
Ron Press, Mentor Graphics *
John Radman, Trace Laboratories
David Rager, Design Solutions, Inc.
Jozef Scesnak, Teradyne
Russell Shannon, US Navy *
Bob Stasonis, Pickering Test
Robert Twigg, JTAG Technologies Inc.
Louis Y. Ungar, A.T.E. Solutions, Inc. *
Don Walsh, Jabil Circuit, Inc.
Keith Wainionpaa, Mesabi Electronics Inc.
Liz Weese, Jabil Circuit, Inc.
Klaus-Jurgen Wolter, Technische Universitat Dresden
Zafei Yan, Huawei Technologies
Patrick Zarrabi, Harman OEM Group
* denotes a member of TMAG
The above list includes those who constructed previ-
ous releases of this document. These individuals were
an integral part of our group and their contributions
should also be recognized.
SMTA/TMAG Testability Guidelines Forward
3
Fourth Edition
In addition to these professionals others have contrib-
uted. Our work was recognized and encouraged by Mr.
Rod Howell, former President of the Surface Mount
Technology Association and by Mr. Michael Keller of
the American Society of Test Engineers. Ms. JoAnn
Stromberg has been encouraging this effort for many
years and it was due to her leadership and foresight
that these Testability Guidelines are available to the
Electronics Industry. Special thanks are due to Mr.
Ryan Flaherty of the SMTA, who kept us organized
and who took the raw engineering writings we pro-
duced and made them ft well in a readable document.
He was helped by Ms. Stacy Johnson and others from
Agilent in editing the text. Ms. Johnson has also been
active in TMAG.
There are many others to thank managers, wives,
husbands, and children who gave up these members
free time so they could contribute to the profession.
We hope you fnd that these guidelines are a great deal
more valuable than the low price at which the SMTA
is making it available.
SMTA/TMAG Testability Guidelines Introduction
4 Fourth Edition
These Testability Guidelines were developed by vari-
ous Task Forces, each concentrating on its own disci-
pline. We present the work of the various Task Forces
as separate chapters.
A general format applies to each task force and it was
intended to assist the reader in dealing with the myriad
of testability considerations that need to go into the de-
sign, development, and test of a product. The format
we adopted was one used in previous SMTA Testabil-
ity Guidelines. Each of the following chapters, deal-
ing with the work of individual Task Forces, begins
with an introduction and overview describing the sub-
ject matter the Task Force considered. Some of this
is tutorial for those who need it, but it also provides
valuable information to those who may be familiar
with the subject of the chapter. It is intended to put
into perspective the enumerated guidelines that follow.
The guidelines are generally numbered, but there is no
specifc sequence intended.
Each bold-lettered guideline is usually followed by one
or more paragraphs explaining when, why, and how or
otherwise qualifying the guideline.
The Design for Testability and Intelligent Test Task
Force, led by Duane Lowenstein of Agilent, had a goal
of commencing the guidelines with a general statement
of why testability is important and also to give a basic
explanation of the purpose of each chapter. This frst
chapter starts with an explanation of why test is impor-
tant. It then goes into basic testability strategies. The
guidelines highlight general ideas to be considered at
the conceptual design stage.
The Probing and Fixturing Task Force, led by James
Chen of Huawei Technologies, updated the Probing
and Fixturing Guidelines for Chapter 2. These guide-
lines begin with considerations for tooling holes, da-
tum point dimensions, probe pad sizes, and test via
drill sizes. Guidelines follow on where probing should
be performed, how probing points should be placed
around tall components and near board edges. Test
pad targets need also be properly planned in terms of
solder coating, and guidelines are provided on what
points should or should not be probed. Guidelines are
given on head style probes to use for various contacts
and how the probes should be distributed on the board.
Some guidelines are also provided on minimizing the
changes that will be required in the fxture when design
changes occur.
The Flying Probe Task Force, with Jim Arient of Test
Coach Corporation as the Task Force leader, updated
Chapter 3 Flying Probe Guidelines. Much has devel-
oped in the area of Flying Probe Testing since the pre-
vious edition, which merited the designation of Flying
Probe as its own chapter. This section provides a for-
mula for calculating the Keep Out Area and guide-
lines on optimizing fying probe test times.
In this version, there were no updates in the Vectorless
Test and Fixturing Task Force. Its work is included in
Chapter 4. The chapter begins with a clear description
of how vectorless testing works. The guidelines start
by advising against using vectorless testing with tape
automated bonding (TAB) devices or with devices that
have a ground plane above the devices lead frame. It
also cautions using vectorless testing with boards con-
taining heatsinks, tall components, ceramic stadium
BGAs, and recommends adding labels after the in-
circuit test. It contains some guidelines on the type
of connectors to use on the board, and it recommends
placing devices on the opposite side of the board if they
create problems for vectorless testing. Some guide-
lines are offered to deal with polarized capacitors and
through-hole devices as well. A number of guidelines
are offered about building test fxtures that will be used
in conjunction with vectorless test.
Brad Jolly of Agilent led the Automatic Optical Inspec-
tion (AOI) Task Force, whose work is documented in
Chapter 5. The group maintained that these guidelines
be called inspectability, rather than testability,
guidelines. The guidelines request unobstructed areas
around the parameter of devices. They also guide on
INTRODUCTION
SMTA/TMAG Testability Guidelines Introduction
5
Fourth Edition
placement of markings and shading of areas around de-
vice leads. Guidelines include placement fducials in-
formation in the computer-aided design (CAD). There
are restrictions on shared pads between components
and split pads on a single component. Guidelines exist
on marking pin 1 of integrated circuits (ICs), and on
polarities of tantalum capacitors. Areas are to be re-
served for conveyer belt clamping. Use of bar coding
is encouraged.
The X-ray Task Force was led by David Bernard of
Dage Group, and its work is contained in Chapter 6. A
distinction is made between manual X-ray inspection
(MXI) and automated X-ray inspection (AXI), which
requires no operator intervention. There is also a dis-
tinction between a 2-dimensional X-ray, called a trans-
mission AXI, and a 3-dimensional X-ray, called cross-
section AXI. First, there are eight guidelines that apply
to all X-ray methods. They include considerations for
board rigidity, and uniform size for pin 1. A guideline
is provided for transmission AXI to minimize overlap-
ping solder joints on double-sided boards. A guideline
for cross-section AXI requires surface map locations
for laminographic systems.
Chapter 7 is the work of the Electrical Design Task
Force. Vishal Narang of Enterasys led this task force
to update the 30-or-so guidelines created in the last
edition that cover a variety of applications, includ-
ing, in-circuit test, functional board test, and analog
test. Many of the guidelines are methods traditionally
used to gain controllability and observability of circuit
nodes. Some of the guidelines are new. Others are
revised. For example, a table is included that provides
guidelines on the resistance values for pull-up resistors
for various logic families and for various supply volt-
ages. This chapter contains general testability guide-
lines and includes all those that could not be directly
attributed to a specialized Task Force.
The Boundary-Scan Task Force, led by Ray Dellecker
of JTAG Technologies, produced Chapter 8. In a pre-
vious edition of the SMTA Testability Guidelines, the
IEEE-1149.1 was relatively new, and nearly the only
relevant guideline was to encourage people to use it.
With boundary-scan offering access without the need
for bed-of-nails or fying probe, it has become a fexi-
ble element in most test strategies. Chapter 8 discusses
the uses of boundary-scan extensively before it offers
specifc guidelines. The guidelines themselves are cat-
egorized in the following groupings:
Device selection and documentation
General board design rules
Test access port (TAP) signals
In-system programming considerations
Design practices
Access to the target board
Within each of these categories there are suggestions
on how to optimize the benefts that one can gain from
the use of boundary-scan. The importance of these
guidelines are coming to light as more and more ICs
come out of foundries with boundary-scan as a stan-
dard rather than an optional feature. Many board de-
signers are fnding their boards testable (with bound-
ary-scan) often without even trying.
This edition produced no updates the Analog & Mixed
Signal Task Force. In the previous edition, discussions
about what to include resulted in an agreement to limit
the work of this task force and the scope of Chapter 9
to the IEEE-1149.4 standard. A short discussion of
the standard is included as a tutorial, since at the time
of this writing 1149.4 is sparsely used. Like its digital
predecessor, the IEEE-1149.1 is slow to be accepted
but is likely to pick up quickly. Thus we felt that it
was appropriate to provide some guidelines here. The
guidelines deal with the use and connection of 1149.4
components at the board level.
Chapter 10 is the work of the Built-In Self Test (BIST)
Task Force, led by Steve Pateras of Logic Vision. A
brief tutorial on BIST demonstrates how chip-level,
board-level, and system-level BIST structures can be
built and integrated in a hierarchical manner to become
part of the overall test strategy. The guidelines encour-
age the use of devices equipped with BIST and bound-
ary-scan and the use of both of these mechanisms to as-
sist board-level BIST. Diagnostic capabilities of BIST
are stressed, and the building block approach of testing
SMTA/TMAG Testability Guidelines Introduction
6 Fourth Edition
the built-in tester before it tests the rest of the circuit
is encouraged. Some guidelines are also offered on
software and frmware built-in test (BIT). Guidelines
are provided to reduce the reliability impact of addi-
tional circuit for BIST, as well as for fltering of false
alarms.
New to this edition is the concluding chapter on Diag-
noses and Support, led by Craig DePaul of DSI Inter-
national. Chapter 11 discusses in general what system
designers need to take into consideration about system
level testability and diagnosability. Introduced in this
chapter is the Integrated Systems Diagnostics Design
(ISDD) process, which requires collaboration between
the end user, system level designers, all of the sub-sys-
tem designers, down to the component level design-
ers.
A glossary is provided for terminology used in these
guidelines, as well as in testing in general.
Finally, a reference section is included for further re-
search.
The effort of revising the 2008 SMTA/TMAG Test-
ability Guidelines proved that a great deal has changed
in just the past few years. Undoubtedly, readers will
fnd new issues that were not addressed. We ask that
such issues be brought to the attention of the SMTA
Testability Committee. Address all correspondence
to the SMTA Director of Communications, Mr. Ryan
Flaherty at ryan@smta.org, and hopefully the next
document will address those issues.
SMTA/TMAG Testability Guidelines Chapter 1 DFT
7
Fourth Edition
Figure 1: Test is a Risk Reduction Process
the health of electronic products. During production
the only process to ensure they are working properly is
some sort of test. Much like medical monitoring equip-
ment, the right test at the right place is critical to en-
sure that information on the quality of the product and
process can be extracted from manufacturing. Figure
2 shows an example of where test steps can be imple-
mented on a production line. With the current complex-
Although test has always been thought of as a necessary
evil, in reality it is the single best way to ensure that a
product meets the needs of your customer. Throughout
the development process test is used to reduce the risk
that the design, theory, and fnal product, reality, are
as close to each other as possible. Figure 1 illustrates
how test used properly can mitigate the risk. At vari-
ous stages of development, namely Design, Valida-
tion, Manufacturing and Support, there is an expected
amount of risk that problems stay hidden until the fnal
product is delivered to customers. As Figure 1 shows,
the highest risk is found in design faws, and the lowest
risk exists when a product is already at the customers
site. The curve in the graph represents the tests which
occur at each stage to lower the risk of bad parts and
systems being passed on to the next stage and ulti-
mately to the customer. There are many tools that have
been developed to ensure that designers can simulate
reality but they are only as good as the ability to feed-
back any gaps between the theory and fnal product.
Similar to the way monitoring equipment is used in
hospitals to analyze and keep track of a patients vital
signs, test in the electronics world is used to monitor
CHAPTER 1
Design for Testability and Intelligent Test
Figure 2: The Right Test at the Right Place
SMTA/TMAG Testability Guidelines Chapter 2 Probing
12 Fourth Edition
Probing guidelines are needed when bed-of-nails con-
tact is anticipated. Automatic Test Equipment (ATE),
such as In-Circuit (ICT), Connectivity, and Manufac-
turing Defect Analyzers (MDAs) depend on making
reliable contacts with certain circuit nodes. These
guidelines are intended to increase the number of pos-
sible contacts as well as the reliability of those contacts
at a feasible cost.
Test Points
The term Test Point, as used in this section, refers to
any feature that is probed during electrical test, such as
test via, test pad, and through-hole lead.
A test via is a plated through hole with an exposed an-
nular ring; the test probe strikes either the solder that
flls via holes during processing or the outer edges of
the empty via barrel.
A test pad is a solid area of exposed metallization;
there is no through hole; the test probe strikes the fat
surface of the feature.
All test points should be identifed properly as a test
point and associated with a net in the PC boards data-
base in computer aided design (CAD) or on the Sche-
matic. In CAD if a surface pad is placed and connected
with a trace to a component pin but not logically con-
nected in the PC board database, it may be missed and
not assigned a test probe in the test fxture.
Tolerances
The criteria used in the tolerance analyses consisted
of:
a single point (spear head) probe,
the worst-case tolerance internal to the probes and
their mounting,
tolerances associated with unit under test (UUT)
platen (probe plate) alignment, and
test pad diameter.
Statistical analysis of the number of contact misses
was not considered, since a contact failure on any test
caused by improper tolerancing is not acceptable and
invalidates the test.
With larger PC boards, these tolerances become more
diffcult to control than with smaller boards. The toler-
ance build-up directly and adversely impacts test pad
size. As the board size increases, larger diameter test
pads may be required in order to maintain probe con-
tact reliability.
Flying probe fxturing guidelines are discussed in the
next chapter with guideline numbers starting with
Guideline #FP-1. General guidelines that typically ap-
ply to bed-of-nails fxtures are discussed frst and are
starting with Guideline #P-1.
GUIDELINE P-1: Provide accurate tooling holes.
(See Figure P-1)
This frst guideline has the most impact on the prob-
ability of spring-loaded probes reliably contacting the
UUT.
GUIDELINE P-2: Tolerance from the UUT datum
point to the test pad should be within +0.002 inches
(0.05 Mm).
Tooling pin location is critical and every effort should
be made to reduce this indexing tolerance. In cases
where printed circuit (PC) boards are manufactured in
panels and then broken out, datum holes should be sup-
plied both in the mother panel and in each individual
board. There should be at least two datum holes in the
panels to ensure accurate processing, for subsequent
testing, and for possible rework. If necessary, because
of space considerations, breakaway tabs can be used
to carry the datum holes for the assembly process and
testing the UUT. To ensure probing accuracy, the
same datum holes must be used to fabricate, populate,
and test the PC board.
GUIDELINE P-3: Place a minimum of 2 tooling
holes on the uut as far apart as possible with a
CHAPTER 2
Probing and Fixturing Guidelines
SMTA/TMAG Testability Guidelines Chapter 3 Flying Probe
20 Fourth Edition
A fying probe tester can perform many of the same
tests that ICT accomplishes, but without the bed-of-
nails fxture. The fying probe tester is a fxtureless tes-
ter that utilizes several moving arms with test probes
providing net access to the board. Typically, the board
under test is placed upside down in the tester and mul-
tiple arms with test probes move across the bottom side
of the board, touching down on test points and taking
measurements. The biggest advantage of this test is
that it does not usually require a test fxture. Its great-
est limitation is that it has long test times due to the
arm movements.
This chapter discusses DFT principles and test guide-
lines for boards that are to be tested on fying probe tes-
ters starting out with discussing test points. But frst,
lets question why we need a chapter on DFT concern-
ing fying probe testers.
Flying probe testers can probe the leads of SMD de-
vices, so you should be able to test everything on the
board, right?
One may question, Why add test points? and Why
invest DFT time during CAD layout?
The main answer is, To save Time and Money! This
can be broken down into avoiding false failures, de-
creasing test time, and increasing test coverage. Now
lets begin.
GUIDELINE FP-1: Test point guidelines for use
with fying probe testers.

Test Points should follow the same basic rules as de-
scribed in previous guidelines for bed-of-nails fxtures,
although it can access much smaller targets. Addition-
ally it can utilize SMD component pads as test targets.
GUIDELINE FP-1a: Test points - options.
Test vias and pads should be at least 14mil in size.
Vias should have the annual ring free of solder
mask.
SMD component pads should have at least a 14mil
free area to target, so that it does not hit the compo-
nent lead and mask an open failure.
Some through-hole components can be probed with
the Flying Probe technique as long as the leads are
rigid and not too long. The leads must be free of
pin-n-paste residue and it is desirable to probe a
lead that is not longer than the diameter of the pad
through which it is protruding.
All multiple pin nets on the board should be acces-
sible from one side of the board.
GUIDELINE FP-1b: Avoid probing large via holes
Large via holes create problems with the needle type
test probes used. If the hole is too large the probe will
actually bottom out on hole contaminates and never
make contact with the edges of the via barrel.
GUIDELINE FP-1c: Test points - probe tips style.
If proper test points are not provided, test targets are
usually split between probing vias and SMD device
pads, which may require very different probe head
styles to reliably probe. Typically the fying prober is
equipped with the same probe type in each arm. Imag-
ine trying to hit 12mil component pads with a large
chisel head probe that is required for the large routing
vias. A good tip choice for SMD pads may be unreli-
able for vias.
A DFT effort should be put into selecting and adding
test points during the CAD layout process so a tip can
be selected to reduce false failures and reduce re-prob-
ing which may fragment solder joints.
GUIDELINE FP-1d: Test points - access all nets
from one side of the board
Most fying probers can only access one side of the
board at a time, so it is best to give the prober test ac-
cess of all multiple pin nets from one side of the board.
CHAPTER 3
Flying Probe Guidelines
SMTA/TMAG Testability Guidelines Chapter 4 Vectorless Test
24 Fourth Edition
other device pins (Cig). A vectorless test sensor plate
above the device-under-test receives a test voltage
through the capacitive coupling between the device
lead frame and the sensor plate (Cvt). A test system
Digital Volt Meter (DVM) measures this voltage. The
amount of voltage at the sensor plate varies with the
Cvt impedance. If a sensor plate amplifer is used, a
typical Cvt value (50-100 fF) couples suffcient sensor
plate voltage for a repeatable vectorless test.
If the pin-under-test is open, the open forms a small ca-
pacitance between the pin and the PC board pad. This
produces the signal in Figure VT-2.
Figure VT-2: Signal produced by open pin-under-
test
This open capacitance (Copen) forms a voltage divider
with Cig. This greatly reduces the voltage applied to
the pin-under-tests lead frame, also reducing the mea-
sured sensor plates voltage. A typical IC open reduc-
es the lead frame voltage by 1 to 2 orders of magnitude
from the input voltage, facilitating open pin detection.
This basic technique, with some modifcations, tests
ICs, connectors and polarized capacitors. To check ca-
pacitor polarity with this technique, the test adds very
precise low impedance analog measurements across
the capacitor.
In some cases devices may be tested using vectorless
test techniques. These devices are generally
Complex digital devices where library tests either
do not exist or would take a long time to create,
Connectors using in-circuit test (ICT) methods to
test for solder opens, and
Polarized capacitors using ICT methods to check
for proper polarity.
When a board includes any of these devices, this sec-
tion describes appropriate Design For Test (DFT)
guidelines.
Vectorless tests check device pins for open solder
joints without testing the device core logic (or IC die).
These tests use analog measurements to check the sol-
der joints. Since core logic is not tested, these tests do
not require any library device test, and can be executed
on digital, analog or mixed signal devices.
Figure VT-1: Low voltage sine wave to a device
pin-under-test.
The basic vectorless test procedure applies a low volt-
age sine wave to a device pin-under-test (see Figure
VT-1). The test also ties all other (accessible) pins on
that device to system ground. The source voltages
load becomes the cumulative capacitance between the
pin-under-tests lead frame and the lead frames of all
CHAPTER 4
Vectorless Test and Fixturing Guidelines
SMTA/TMAG Testability Guidelines Chapter 5 AOI
31
Fourth Edition
These guidelines apply to the majority of AOI equip-
ment available today. There are limitations to the scope
of these guidelines. Certain advanced detection capa-
bilities and their DFI requirements are not discussed
due to their specialized nature.
Background
In the high volume manufacture of Printed Circuit As-
semblies (PCAs) it is critically important to automate
every step in the process in order to meet the desired
production rate and quality levels. This includes com-
pletely automated product inspection. Automated
Optical Inspection (AOI) is enables comprehensive
inspection of a complex PCA at full production line
speed.
Manufacturing comprises many steps. Case studies
have shown that manufacturing stages can be opti-
mized for speed and their cost reduced if the manufac-
turing stages are taken into consideration during the
design phase. Today, design for manufacturing is a
requirement for successful, effcient production of reli-
able products.

To remain competitive, an increasing number of man-
ufacturers have realized that designers must consider
more than just design for manufacturing as it relates to
product assembly. To keep costs low and quality high,
design for testability and inspectability has gained
wide acceptance.
Automated Optical Inspection is now being deployed
widely, with many benefts:
Automated systems are much faster than human in-
spectors.
AOI systems are more accurate and objective than
human inspectors.
AOI systems make repeatable, stable judgments.
As with design for testability, design for inspectability
can greatly improve both manufacturing effciency and
product quality.
It is useful to identify inspectability issues and cre-
ate design guidelines to address them. This document
identifes the most common inspection issues and sug-
gests guidelines to maximize AOI defect detection.
Current AOI systems have a fairly well defned set of
capabilities. The faults that leading AOI systems can
detect include:
Placement faults (missing, misaligned, wrong po-
larity, skewed, tombstoned, billboarded, extra part,
etc.)
Solder faults (no, low, excess, bridging, etc.)
Other (lifted lead, bent lead, wrong component,
etc.)
Optical inspection techniques depend on visual access
to the areas of interest, and they also depend on visual
attributes in making good-versus-bad judgments. If
visual access is blocked, or if the visual attributes of
the PCA are not consistent with the requirements of the
AOI techniques, fault coverage is degraded.
To ensure high AOI fault coverage, the design group
can follow a set of Design for Inspection (DFI)
guidelines. Following these guidelines can result in
higher product quality, more effcient manufacturing,
and reduction of missed faults (escapes) reaching the
customer.
The reader can gain the following from this chapter:
An understanding of the basic AOI techniques
An understanding of some of the PCA visual at-
tributes required for reliable fault detection using
AOI
A list of design practices for maximizing the in-
spectability of a PCA
DFI GUIDELINE 1: Maintain An Unobstructed
Area Above And Around The Perimeter Of Each
Component For Camera And Lighting Access.
AOI systems incorporate one or more vertical cameras.
Some also use angled cameras. To perform an optical
inspection, the cameras must have visual access to the
CHAPTER 5
Automated Optical Inspection (AOI) Inspectability Guidelines
SMTA/TMAG Testability Guidelines Chapter 6 X-ray Inspection
37
Fourth Edition
Denition and Discussion of Terms
1. Manual X-ray Inspection (MXI) and Automated
X-ray Inspection (AXI)
X-ray inspection systems are available in both man-
ual (MXI) and automated (AXI) varieties. MXI sys-
tems can provide varying degrees of automation and
can include varying degrees of automated board han-
dling and image processing functions. By using, so
called, open or sealed transmissive types of x-ray
tube within an MXI system, the magnifcation avail-
able for inspection is substantially greater than in MXI
and AXI systems that use the sealed x-ray tube type.
What generally distinguishes AXI systems from MXI
systems is that AXI systems are often in-line capable
and may not require the help of an operator to make
pass/fail decisions. The x-ray image quality from MXI
systems can be substantially better than that from AXI
systems. As all automated analysis is based on classify-
ing details within the x-ray image, it should be recog-
nised that as device and joint sizes continue to shrink,
issues of image quality can provide an opportunity for
increased false call rates at the expense of maintaining
zero escapes from the automated inspection.
MXI equipment is almost exclusively transmission X-
ray technology whereas AXI equipment can be trans-
mission, cross-section or combo (see below). Trans-
mission technology with appropriate sample/detector
movement in MXI systems can allow oblique angle
views of joints to be provided that have a larger an-
gle than a Combo AXI technology. Variations in joint
shape across certain types of devices, post refow, are
often made more obvious when viewed at an oblique
angle.
2. Transmission, Cross-section and Combo AXI:
AXI equipment is generally available in three forms:
Transmission AXI commonly referred to as 2D
X-ray
Cross-section AXI commonly referred to as 3D
X-ray
Combo AXI
Transmission x-ray (whether used in MXI or AXI)
automatically generates images of all features, in all
layers, between the x-ray source and the detector.
Cross-section AXI automatically generates images
of horizontal 2D x-ray slices through different layers
within the board thickness, with usually a minimum
provided of one slice of the boards top and bottom
sides. This is achieved by using laminography or digi-
tal tomosynthesis techniques.
Combo AXI equipment uses a combination of trans-
mission and cross-section techniques concurrently
during the inspection of a printed circuit board (PCB).
Combo systems automatically apply each technique
where it is best suited and allow users the ability to
select one technique over another if desired. The AXI
systems which use digital tomosynthesis are usually
able provide this type of Combo AXI technique be-
cause the x-ray images used for analysis are derived
from oblique angle 2D transmission images.
Transmission, cross-section and combo x-ray tech-
niques are all capable of detecting PCB assembly
defects that cause changes in the solder joint profle.
These types of assembly defects include but are not
limited to: solder shorts, solder opens, solder voids,
insuffcient solder joints, missing devices and skewed
devices.
On double sided boards, some subset of the solder
joints will be inaccessible to the transmission x-ray
technique due to overlap whereas the cross-section
technique will have greater test access. However, the
use of oblique angle views in MXI systems can sepa-
rate top and bottom side components suffciently for
manual inspection evaluation. Because the transmis-
sion x-ray technique captures information from the
entire solder volume and the cross-section technique
captures specifc slice information, these techniques
have both unique and common capabilities to detect
some types of solder defects. For more detailed in-
formation, contact the manufacturers of MXI and AXI
systems who can provide information about the capa-
bilities of their techniques and systems.
CHAPTER 6
X-ray Inspection Guidelines
SMTA/TMAG Testability Guidelines Chapter 7 Electrical
43
Fourth Edition
In addition to specifc testability guidelines discussed
in other chapters, the Electrical Design Guidelines
serve as a general Design for Testability approach.
GUIDELINE E-1: Provide test access to all electrical
nodes.
A node is defned as an electrical connection between
two or more components, either analog or digital. Test
pads should be provided for all inputs and outputs (I/
Os), power, ground, and return signals for in-circuit
testing. Alternately, access could be provided using
boundary-scan or other techniques. Also include un-
used pins of ICs, connectors, etc.
NOTE: Jumpers (zero ohm resistors), fuses, and SPST
switches are treated as two lead components and are
connected between two electrical nodes. Therefore,
each node requires a separate test pad.
NOTE: Test pads should not be under any compo-
nents.
GUIDELINE E-2: Place test pads as close as possible
to signal sources (i.e. driving digital devices).
When the test system overdrives these digital output
pins, large amounts of current can fow between the
test system and the digital output pins. Minimizing the
distance that this current fows on the board also mini-
mizes the voltage drop caused by the large current.
NOTE: Keep a spacing of 18mil or higher for test pads
exposed copper
GUIDELINE E-3: Include two test pads on each
electrical node tied to critical low impedance
devices.
If a low impedance device is critical to a circuits op-
eration, include two test pads on each node tied to the
device. To accurately measure small analog imped-
ances, test systems utilize 4-wire (or Kelvin) measure-
ments. While this eliminates system and fxture wire
impedance, probe contact resistance may be included
in the measurement. Figure E-1 illustrates an example
of two 0.5 Ohm resistors. R1s test includes a 4-wire
measurement through 2 test pads. This measurement
includes the 0.05 Ohm contact resistance of each probe,
producing a very accurate measurement of 0.6 ohms.
R2s test, however, performs the same measurement
through 4 test pads. In this case, the 4-wire measure-
ment eliminates the contact resistance, making a 0.5
Ohm measurement.
Figure E-1: Two 0.5 Ohm resistors.
These additional test pads should be used when testing
critical small resistors, large capacitors, and polarized
capacitors, where capacitor polarity will be measured.
If the value of the small impedance is inconsequential
to circuit operation, such as jumpers, fuses or isolation
resistors, only 1 test pad per node is required.
GUIDELINE E-4a: Do not rely on edge connectors,
circuit traces, or surface mount device pads as test
points for In-Circuit test.
Probing an edge connector plating or circuit trace may
produce poor contact reliability. Gold plated fngers
are also easily damaged with test probes. Probing a
surface mount device pad could damage the fxture
probe or mask a solder open. A better approach is to
use a dedicated soldered test pad. Conductor traces
can be expanded to 0.030 (0.76 mm) to 0.040 (1.02
CHAPTER 7
Electrical Design Guidelines
SMTA/TMAG Testability Guidelines Chapter 8 Boundary Scan
52 Fourth Edition
Purpose of this Document and Background of IEEE
Std. 1149.1
The increase in pin density of electronic packaging has
led to a limitation in access to device signals that al-
low for testing of devices once mounted on a Printed
Circuit Board. This limitation of accessible test points
led a group of interested manufacturers to propose a
means of serial access over a small number of wires or
contact points. This group developed into the Joint Test
Action Group (JTAG), which later became a working
group of the IEEE and was chartered to develop the
idea into a standard. The results of their work are de-
fned in the IEEE Std. 1149.1 Test Access Port and
Boundary-Scan Architecture, often referred to as the
JTAG standard.
The IEEE-1149.1 standard defnes a four-wire serial
interface (with an optional ffth reset line). This Test
Access Port (TAP) allows for access within complex
digital integrated circuits (ICs) such as microproces-
sors, DSPs, ASICs FPGAs, and CPLDs. The TAP
is often referred to as the JTAG port. The standard
defnes a Finite State Machine to act as a TAP control-
ler. This TAP Controller allows for the execution of
boundary-scan functions. The TAP pins are defnes
as follows: Test Data In (TDI) provides for data to be
clocked into a device. Test Data Out (TDO) provides
for data to be clocked out of the device. Test Mode Se-
lect (TMS) allows for changing states within the TAP
controller. TestClocK (TCK) provides a clock for reg-
istering data in, data out and state machine transitions.
An additional, optional, Test ReSeT (TRST) signal is
provided to reset the TAP controller.
In normal operation, a boundary-scan compatible IC
performs its intended function as though the TAP cir-
cuits were not present. The TAP is activated during
testing or In-System Programming (ISP). This allows
for data to be clocked into the device, test functions to
be performed and data to be clocked out of the device.
A typical mode of operation is EXTEST. This mode
provides for data to be clocked in on TDI and into a
long shift register call the Data Register. The Data
Register allows for input and output structures, ie pins,
to be sensed and driven. That is, a pin can be driven to
a logic level of 1 on one device. If this pin is connected
to a PCB trace of another boundary-scan device, it can
be sensed as having achieved a high state. This type of
testing can be utilized to verify that devices are properly
connected to traces without shorts to other circuits on
the board. In other words, the boundary-scan modes of
operation provide the ability of boundary-scan to test a
board for structural faults that can occur during manu-
facturing and to perform in-system device program-
mingall via the standard JTAG test access port. The
result is that each boundary-scannable pin becomes a
virtual test point, signifcantly reducing the number of
physical access pints required on the board.
Multiple boundary-scan-compatible ICs may be seri-
ally connected on the printed circuit board, forming
the boundary-scan chain. A board may contain more
than one scan chain. The scan chain provides electri-
cal access, from the serial TAP interface, to input and
output structures on a majority of pins on every IC that
is part of the chain. These pins were traditionally at
the periphery or boundary of the die, hence, the name
boundary-scan.
In this chapter the terms IEEE-1149.1 and JTAG
will be used interchangeably and unless otherwise
stated, it is assumed that boundary-scan is part of the
circuit. Several related IEEE specifcations and exten-
sions have developed around this concept of test ac-
cess via a serial test port. IEEE-1149.4 defnes ana-
log test access with such a serial port. IEEE-1149.6
defnes differential and AC-coupled signal testing via
JTAG. IEEE-1532 defnes utilizing a JTAG port for
in-system programming of devices, including CPLDs
and PROMs.
Taking advantage of the test capabilities of boundary-
scan requires that the unit under test (UUT), typically
a Printed Circuit Board, be designed properly, in com-
pliance with a number of device selection and control
CHAPTER 8
Boundary Scan Guidelines
SMTA/TMAG Testability Guidelines Chapter 9 Analog and Mixed Signal
61
Fourth Edition
The Electrical Design guideline contains a number of
general analog and mixed signal testability guidelines.
This chapter concentrates on those that involve circuits
that comply to the IEEE-1149.4 standard.
The IEEE 1149.4 standard is an extension of the IEEE
1149.1 standard and consists of additional structures
added to an 1149.1-conformant component. The IEEE
1149.4 standard defnes test features and associated
protocols for testing opens and shorts among device
interconnections, for making analog characterization
measurements, and for testing the presence and value
of discrete components both between and within de-
vices.
Test access is gained through the familiar Test Ac-
cess Port (TAP) and to additional analog busses AT1
and AT2. Stimulus is provided to the AT1 bus and
measurements are through the AT2 bus. The test bus
interface circuit connects AT1 and AT2 to a pair of in-
ternal busses AB1 and AB2 connecting to each analog
boundary module. Instructions passed to the TAP con-
trols how a pin is connected to the AB1 and AB2 bus-
ses and disconnected from the analog circuits within
the device.
Within each analog boundary module, in addition to
the switches that connect to the AB1 and AB2 bus-
ses, is the circuitry necessary to both drive and receive
a logical level at a device pin. The protocols to drive
and receive logical levels parallel the IEEE 1149.1
standard, allowing interconnect testing between both
1149.4 devices and 1149.1 devices.
The IEEE 1149.4 standard was originally conceived
to address the problem of mixed-signal device testing.
During the period between its conception and the pres-
ent digital parts have taken on some of the character-
istics of mixed signal devices. In the quest for speed,
digital interconnections have become networks. The
IEEE 1149.4 standard is equally well suited to test
strictly digital devices and their interconnection net-
works.
CHAPTER 9
Analog and Mixed Signal Guidelines
IEEE 1149.4 Mixed Signal Test Bus
SMTA/TMAG Testability Guidelines Chapter 10 BIST
63
Fourth Edition
BIST is a natural evolution of two distinct test ap-
proaches: External ATE and conventional Design for
Test (DFT). Building on conventional DFT approaches
such as scan, BIST integrates the high-speed and high-
bandwidth portions of the external ATE directly into
the ICs. This integration facilitates chip-, board-, and
system-level test, diagnosis, and debug. BIST consists
of user-confgurable IP (intellectual property), in the
form of design objects delivered as Register Transfer
Language (RTL) soft cores. These IP design objects
implement pattern generators (either random or algo-
rithmic), results compression, the collection of diag-
nostic data, and precision timing for at-speed delivery
of the tests. The BIST solution cost-effectively replaces
most of the ad-hoc DFT methods in use today and the
time-consuming task of creating functional test pat-
terns. BIST seamlessly integrates multiple disciplines:
DFT features, such as scan.
Precision, high-speed timing for at-speed test.
Test support for many different block types (logic,
memories, processors, and analog circuitry).
Capabilities for diagnosis and characterization.
Because the test technology is embedded, it provides
benefts throughout the product life cycle. The aim of
the BIST approach is to design in a chip all ATE fea-
tures that are block specifc or bandwidth limited by
chip I/O, as Figure BIST-1 illustrates.
On-chip data generation reduces the volume of
external patterns and can be customized per block
type.
On-chip go/no-go and diagnostic data compression
reduce ATE data logging.
On-chip timing generation achieves true at-speed
test that can scale to match process performance.
At the chip, board, and system levels, BIST provides
the following key advantages:
Cost-effective at-speed test of logic, memory, cores,
mixed-signal modules, and board-level intercon-
nect.
Diagnostics and debug for random logic, embedded
memories, mixed-signal cores, and legacy cores at
the chip level.
Diagnostics and debug for I/Os, interconnects, and
memory modules at the board and system levels.
While the terms BIT and BIST are used in different
operations, the difference between them is primarily
semantic. The Testability Management Action Group
(TMAG) formulated the following defnitions of each
term, and we will use these defnitions in this docu-
ment.
Figure BIST-1: Solving the Bandwidth Problem
Built-In Self-Test (BIST) is a method of design gen-
erally for ICs whereby the mission circuit tests itself.
Though this is seldom performed strictly without ad-
ditional external circuitry, if the entire circuitry per-
forming the test is contained within an IC, we call it
self-test, in situ test, or built-in self-test.
Built-In Test (BIT) is similar to BIST in that it per-
forms test of the circuit it resides in, but it is generally
used at board and system levels and often uses extra
internal hardware, software, and/or frmware to imple-
ment the test. When the added circuitry is substantial,
it may be called embedded test. If BIT is implemented
in software, it is called BIT software.
BIT in system-level application, especially software-
driven BIT is quite mature and has been part of elec-
tronic systems for most of the past 50 years.
CHAPTER 10
Built-In Self Test Guidelines
SMTA/TMAG Testability Guidelines Chapter 11 Diagnoses and Support
74 Fourth Edition
The term DFT has been around for over 30 years and
has been focused on designing a circuit so that effec-
tive production tests can be written with minimal ef-
fort. DFT objectives have been driven by performance
specifcations at the component level. The primary
goal of DFT has been to provide assurance that the
component performance parameters are tested prior to
production acceptance. The term DFT - Design for
Testability, has been defned traditionally as the pro-
cess by which a system design takes into consideration
the test coverage (Fault Detection / Fault Isolation) that
can be achieved in production.
The challenge facing DFT today is the need to look
ahead to system level requirements and specifcally
the needs of the system / platform health management
system, and the life cycle maintenance support. This
challenge brings in the need for the Integrated Systems
Diagnostics Design (ISDD) process.
DFT 1) The diagnostic aspects of the product design
process whose goal is to ensure that the testability of
the end product is competently and suffciently devel-
oped. 2) Design for testability, the process by which a
system design drives the requirements for test coverage
at the component level in production and at all levels
of assembly through systems integration and the life-
cycle support of the integrated system or end product.
Health Management - The ability to monitor the fail-
ure effects of an operating system by means of embed-
ded diagnostics, and to manage any occurring failure
to determine the failure mode and perform corrective
action to prevent a system operational failure. This is
accomplished through an embedded test executive that
directs the monitoring of the diagnostics sensors, and
through a diagnostics reasoner that provides the intel-
ligence to determine the impact of the failure, isolate
to the failure, and direct remediation, if necessary, to
prevent system operational failure. In selected critical
failure modes, prognostics monitoring and reasoning
may be used to predict a failure prior to occurrence.
The health management effectiveness is dependant on
how well the diagnostics capability has been designed
into the system through ISDD.
ISDD The process of developing diagnostics capa-
bilities for production test, operational health manage-
ment and life cycle maintenance support. This process
relies on a standard diagnostics analysis capability that
can provide integration of all levels of the system di-
agnostics design, the dissemination of understood re-
quirements, and the integration of design disciplines
such as Diagnostics Engineering, Reliability, Main-
tainability, Logistics Engineering, Test Engineering,
Safety, Production Engineering, and others depend-
ing on the individual organizational structures. This
process also requires accountability of the diagnostics
design at all levels of development where the diagnos-
tics capabilities are tested through approved Validation
and Verifcation procedures.
Since the ISDD Process encompasses all levels of the
design hierarchy (from the system level to the lowest-
level components to drive requirements, and then from
the lowest level components to the system level to vali-
date diagnostic design capability ), the focus for DFT
in todays design environment must include a full un-
derstanding of how the lower level component needs
to perform at the system level. This performance goes
beyond the typical functional parameters to the need
for integrated systems diagnostics. The component
failure modes must be observable at the system level
(in other words, how a fault will manifest itself at the
system level) and the effect of these failure modes must
be understood at each level of the system hierarchical
relationships. Even though DFT enables effective pro-
duction level tests to be written, using, this provides
no assurance that the component is diagnosable at a
higher level of integration.
The ISDD Process begins early in the design phase
when the system is being conceptualized and when the
performance requirements of the system or end product
are being determined. In time, system requirements are
formed and fowed down to contractors and suppliers
CHAPTER 11
Design for Testability (DFT) Diagnoses and Support Guidelines
SMTA/TMAG Testability Guidelines Glossary
79
Fourth Edition
For a more comprehensive Test Glossary we urge
readers to visit one maintained by Test & Measure-
ment World:
http://www.tmworld.com/info/CA6433114.html
AOI
Automated Optical Inspection
ATE
Automatic Test Equipment, a class of board testing
equipment, which accesses the target via a set of test,
probes (bed of nails)
BGA
Ball-grid array, a chip-size packaging technique in
which the electrical connections to the device are made
by re-fow solder balls on the bottom of the device,
thereby eliminating the possibility of direct physical
contact for electrical probing
BIST
Built-in Self-Test, a test algorithm supported by the de-
vice itself, which can be activated by an IEEE 1149.1
instruction
BSDL
Boundary-Scan Descriptive Language, a fle conform-
ing to the format prescribed in 1149.1, which describes
the boundary-scan implementation contained in a spe-
cifc device
(C)PLD
(Complex) Programmable Logic Device, an IC that is
in almost all cases programmable in-system via bound-
ary-scan
Defect Detection
Faults found and indicted as unacceptable by the AOI
system.
DFI
Design For Inspectability
DFT
Design For Testability, the process by which a system
design takes into consideration the test coverage that
can be achieved in production
EIA
Electronic Industries Alliance
Escape
A true defect that was undetected by the test or AOI
system.
False Flag
An incorrect defect detection made by the AOI sys-
tem.
Fault Class
Refers to the specifc sub types of faults that an AOI
system can detect such as missing component, skewed,
tombstone, billboard, low solder, etc.
Fault Coverage
Refers to a group of fault classes that describe intended
or resultant (actual measured) defect detection.
FPGA
Field-programmable gate arrays
Customizable logic arrays usually available in very
large confgurations and suitable for on-board pro-
gramming
Flash memory
A non-volatile memory technology that can be pro-
grammed in-system
IEEE 1149.1
The boundary-scan standard, frst published by the
IEEE in 1990
ICT
In-Circuit Test
GLOSSARY
SMTA/TMAG Testability Guidelines Glossary
80 Fourth Edition
ISP
In-system programming, the technique of program-
ming devices after they have been soldered into the
circuit board
IPC
Association Connecting Electronic Industries
JTAG
Joint Test Action Group, the ad-hoc industry commit-
tee that formulated the IEEE 1149.1 specifcation
MDA
Manufacturing Defect Analyzers
OSP
Organic Solderability Preservatives
PCA
Printed Circuit Assembly
PCB
Printed Circuit Board
TAP
Test Access Port, the 4- or 5-wire interface to a bound-
ary-scan device, consisting of the TDI, TDO, TMS,
TCK, and, optionally, TRST* signals
Test Pad
A solid area of exposed metallization; there is no
through hole; the test probe strikes the fat surface of
the feature.
Test Point
Any feature that is probed during electrical test, such
as test via, test pad, and through-hole lead.
Test via
A plated through hole with an exposed annular ring;
the test probe strikes either the solder that flls via holes
during processing or the the outer edges of the empty
via barrel.
SMEMA
Surface Mount Equipment Manufacturers Association
UUT
Unit Under Test
SMTA/TMAG Testability Guidelines References
81
Fourth Edition
Standards
TP-101C The SMTA Testability Guidelines, Surface
Mount Technology Association, 2002.
EIA Package Standard EIA-JEP95
This document contains registered and standard out-
lines for solid state and related products
IEEE Standard 1149.1-1990 IEEE Standard Test Ac-
cess Port and Boundary-Scan Architecture, New York,
1990
IEEE Standard 1149.4-1999 IEEE Standard for a
Mixed Signal Test Bus, New York, 1999
IEEE Standard 1149.5-1995 IEEE Standard Module
Test and Maintenance (MTM) Bus Protocol, New
York, 1995
IEEE Standard for Embedded Core Test, http://grou-
per.ieee.org/groups/1500/
IPC 7351 - Generic Requirements for Surface Mount
Design and Land Pattern Standard
IPC A-610D - Acceptability of Printed Board Assem-
blies
NEXUS 5001 Forum, http://www.ieee-isto.org/Nex-
us5001/about.html
SMEMA 3.1 Fiducial Mark Standard
This SMEMA standard is for fducial marks. It facili-
tates the accurate placement of components on printed
circuit boards.
Books and Tutorials
A.T.E. Solutions, Inc., Design for Testability and Built-
In Self Test courses, www.BestTest.com/courses.htm
Harry Bleeker, Peter van den Eijnden, Frans de Jong,
Boundary-Scan Test, A Practical Approach, 1993,
Kluwer Academic Publishers.
Kenneth P. Parker, The Boundary-Scan Handbook,
2nd ed. Kluwer Academic Publishers, Norwell MA,
1998
A. Osseiran, Editor, Analog and Mixed-Signal Bound-
ary-Scan, A Guide to the IEEE-1149.4 Test Standard,
Kluwer Academic Publishers, Norwell MA, 1999
Dr. David Bernard and Bob Willis, A Practical Guide
to X-Ray Inspection Criteria & Common Defect Anal-
ysis, 2006, Dage Precison Industries
Technical Papers
Louis Y. Ungar, Industry-Wide Design for Testability
Guidelines, Proceedings of Nepcon, December 2002
Louis Y. Ungar, Harry Bleeker, Ray Dellecker, John
E. McDermid and Harry Hulvershorn IEEE-1149.x
Standards: Achievements vs. Expectations, Proceed-
ings, AutoTestCon, August 2001.
J. McDermid, K. Parker, Analog and Mixed-Signal
Boundary-Scan: A New Standard and its Applica-
tions, Proceedings of EtroniX 2001, Anaheim, Febru-
ary 2001
K. Parker, J. McDermid, S. Oresjo, Structure and Me-
trology for an Analog Testability Bus, Proceedings,
International Test Conference, pp.309-322, Baltimore,
Oct 1993
Louis Y. Ungar, Boundary-Scan Application of a Sin-
gle-Chip Built-In Tester Proc. ATE & Instrumenta-
tion Conf., Jan. 1991
T. Chakraborty, C-H. Chiang, B. Van Treuren A
Practical Approach to Comprehensive System Test
REFERENCES AND BIBLIOGRAPHY
SMTA/TMAG Testability Guidelines References
82 Fourth Edition
and Debug Using Boundary-Scan-based Test Archi-
tecture, Lecture Series Paper L3.2., International Test
Conference Proceedings, 2007
Covers embedded boundary scan based self test.
T. Vo, Z. Wang, T. Eaton, P. Ghosh, H. Li, Y. Lee,
W. Wang, R. Fang, D. Singletary, X. Gu, Design for
Board- and System-level Structural Test and Diagno-
sis, International Test Conference Proceedings, Paper
14.1, 2006.
Joshua Ferry, Jozef Scesnak, Shoeib Shaikh, A Strat-
egy for Board-level In-System Programmable Built-in
Assisted-Test and Built-in Self-Test, International
Test Conference Proceedings, Paper 32.3, 2005.
Testability Products on the Internet
A.T.E. Solutions, Inc., The Testability Director Soft-
ware, 1998, http://www.besttest.com/ourproducts/
TestabilityDir.htm
Texas Instruments, SN74LVT8996 Addressable Scan
Port, http://focus.ti.com/docs/prod/productfolder.jhtm
l?genericPartNumber=SN74LVT8996
National Semiconductor, SCANPSC100F Embedded
Boundary-Scan Controller, http://www.national.com/
pf/SC/SCANPSC100F.html
Test & Measurement World Magazine, Design for
Testability/Built-in Self-Test Section, http://www.e-
insite.net/tmworld/index.asp?layout=Community&ind
ustry=Design+for+Test+%2F+Built%2Din+Self%2D
Test&industryid=19026
Boundary-Scan Tools are commercially available from
the following companies (and perhaps others):
Acculogic www.acculogic.com
ASSET Intertech www.asset-intertech.com
Corelis www.corelis.com
Flynn Systems www.fynn.com
Goepel Electronics www.goepel.com
Intellitech www.intellitech.com
JTAG Technologies www.jtag.com