Systematic Design for a Successive

Approximation ADC
Mootaz M. ALLAM
M.Sc Cairo University - Egypt
Supervisors
Prof. Amr Badawi
Dr. Mohamed Dessouky
Background
Principles of Operation
System and Circuit Design
Case Study
Simulations
Layout Generation
Performance Evaluation
Conclusion
Perspectives
Outline
2
Emerging new Applications
MEMS Sensor Interface:
Resolution: 7-8 bits, BW=50kHz [Scott 2003]
Multi-standards RF receiver
Resolution: 8 bits, BW = 20 MHz [Montaudon 2008]
Ultra Wide Band (wireless UWB):
Resolution: 5-6 bits, BW=300MHz [Chen 2006]
3
The Successive Approximation ADC
The Return
Moderate
Resolution
Low
Power
Minimum
Active blocs
Reconfigurable
Figure of Merit
Resolution
FOM
2 *2*
P
BW

4
Objectives
5
Develop a systematic design method for successive approximation ADC
from system to layout level .
Develop a general simulation environment with different levels of
abstraction and programmed performance analysis.
Emphasis on analog design automation and reuse techniques:
Automatic sizing
Layout generation
Optimizing Layout for best matching
Principle of Operation
6
MSB
LSB
1 1
0 0
Comp
1 2 3 4
2 4 8 16
REF REF REF REF
V V V V
Vin b b b b
Outline
Background
Principles of Operation
System and Circuit Design
Case Study
Simulations
Layout Generation
Performance Evaluation
Conclusion
Perspectives
7
Single Ended SAR-ADC.
8
2
REF
V
REF
V
REF
V
REF
V
in
v
8C
4C
2C C C
Clock
sample
sample
Sampling Mode
9
REF
V
REF
V
in
v
8C
4C
2C C C
Clock
sample
sample
sample
invert
Clock
2
REF
V
Ref
V
REF
V
VDAC
VDAC
VIn
VIn
Inversion Mode
10
sample
invert
Clock
gnd
REF
V
REF IN
V v
8C
4C
2C C C
Clock
invert
REF
V
VDAC
REF
V vin
VDAC =
IN
v
Charge redistribution mode (MSB)
11
sample
invert
Clock
REF
V
2
REF
REF
V
V vin
8C
4C
2C C C
Clock
REF
V
2
REF
INITIAL
V
V
8C
8C
REF
V
REF
V
2
REF
V
1
VDAC=
VDAC
Charge redistribution mode (MSB-1)
12
sample
invert
Clock
REF
V
2 4
REF REF
REF
V V
V vin
8C
4C
2C C C
Clock
REF
V
4
REF
INITIAL
V
V
4C
12C
REF
V
REF
V
4
REF
V
1 0
VDAC =
VDAC
Mode Redistribution de la charge (MSB-2)
13
sample
invert
Clock
REF
V
2 8
REF REF
REF
V V
V vin
8C
4C
2C C C
Clock
REF
V
REF
V
8
REF
V
REF
V
1 0 1
VDAC =
VDAC
1 2 3 4
2 4 8 16
REF REF REF REF
V V V V
Vin b b b b
Mode Redistribution de la charge (LSB)
14
sample
invert
Clock
REF
V
2 8 16
REF REF REF
REF IN
V V V
V v
8C
4C
2C C C
Clock
REF
V
REF
V
16
REF
V
REF
V
1 0 1
0
VDAC =
VDAC
1 2 3 4
2 4 8 16
REF REF REF REF
V V V V
Vin b b b b
Problem
15
dd
V
Sometimes
DAC dd
V V
8C
4C
2C C C
Clock
dd
V
dd
V
dd
V
Leakage when using
normal PMOS switch.
Possible Solution: Switched charge-pump [scott03] or Bootstrap [dessouky01]
Selecting To increase the dynamic range
REF dd
V V
DAC
V
dd
V
dd
V
dd
V
Possible solutions - Leakage
16
Bootstrap Switch
Charge pump Switch
0 < VDAC < 1.5 VDD
VDAC
VDAC
VDD
Since sometimes VDAC value=1.5 VDD
While VG1 = 0 when M1 is ON, VGD,M1 exceeds VDD
Reliability problem
Possible solutions - Reliability
17
0 < VDAC < 1.5 VDD
Shielding Switch
Max OFF = VDD - Vtn
Possible solutions - Circuitry
18
Bootstrap [dessouky01] Modified Shielding
Bootstrap
Differential SAR-ADC
19
2
dd
V
dd
V 2
in
v
4C 2C C C
Clock
sample
sample
2
in
v
4C
2C C C
2
dd
V
dd
V
2
dd
V
2
dd
V
Triple Reference
Differential SAR-ADC
20
sample
invert
Clock
2
dd
V
DAC1
In1
2
dd
V
4C 2C C C
Clock
4C
2C C C
DAC2
dd
V
In2
2
dd
V
2 2 4 8 16
dd dd dd dd
V V V V vin

2 2 4 8 16
dd dd dd dd
V V V V vin

1 0 1
0
dd
V
dd
V
2
dd
V
4C 2C C C
Clock
dd
V
Operation Summary
21
Single Ended Double reference Differential Triple reference
2 times the numbers of capacitors
6 times the numbers of switches
Special Switch
(charge-pump - bootstrap)
No need for special switch
Differential architectures advantages :
- Suppressing even harmonics
-Common mode rejection
-Offset removal
Lower power consumption Better performance at high frequencies
Outline
Background
Principles of Operation
System and Circuit Design
Case Study
Simulations
Layout Generation
Performance Evaluation
Conclusion
Perspectives
22
Design - Architecture
23
Capacitor
array
Comp
Control
SAR
Clock
Switches Control
Switches
In
Sample invert
Capacitor
array
Switches
Capacitor array design issues - Noise
24
dd
V
dd
V
in
v
8C 4C 2C C C
Clock
sample
sample
C increases, thermal noise decreases
Unit
16
TOT
C C
dd
V
Switch
R
in
v
1- Thermal noise [ ], due to Sampling
TOT
kT
C
Capacitor array design issues - Mismatch
25
2 Capacitor Mismatch (Introduced in fabr ication)
- Affects Generated comparison levels of the capacitve DAC

2
dd
V

8( ) C C
8C
dd
V
C increases, mismatch effect decreases
Unit
Capacitor array design issues -
26
16
TOT
C C
dd
V
Switch
R
in
v
Switch Total
R C
sample
Clock
For an accurate sampling
2
Clock
sampling
T
t
Sampling
f
3- Sampling Frequency
C decreases, bandwidth increases
Unit
Switches
27
NMOS to switch Vgnd and Vcm
PMOS to switch Vdd
CMOS to switch Vin
Bootstrap to force deep off-state of critical switches
1) Switches selection
2) Sizing switches (compromise)
Increasing W/L reduces Rswitch and so , on the account of
increasing switch parasitcs.
In the used DAC, this will be of minor importance if operating in
low frequency because the switches are all connected to the
bottom plates
Design - Architecture
28
Capacitor
array
Comp
Control
SAR
Clock
Switches Control
Switches
In
Sample invert
29
ep
Qm
h
h
h
h
em
MP7 MP8
MN5
MN6
MN1 MN2
MP9
MP11
MN3 MN4
Qp
Cuts the current path
in the RESET phase
Reset to Vdd
Comparator Circuit
Input Signal
Latch
30
Comparison phase
Reset phase to Vdd
Latch starts
Inputs
Comparator Operation phases
Resolution >
2
LSB
V
Response time < 0.5 T
H
31
Sizing input pair and latch
Improve with
decreasing L
Tradeoff
Comparator Design tradeoff
Improve with
increasing L
init

latch

Total
I
offset
V
Design - Architecture
32
Capacitor
array
Comp
Control
SAR
Clock
Switches Control
Switches
In
Sample invert
33
LFSR: Linear Feedback Shift Register
DAC outputs C
0
0 0 0 0 0 0 0 0
X
1
1 0 0 0 0 0 0 0
a8
2
a8 1 0 0 0 0 0 0
a7
3
a8 a7 1 0 0 0 0 0
a6
4
a8 a7 a6 1 0 0 0 0
a5
5
a8 a7 a6 a5 1 0 0 0
a4
6
a8 a7 a6 a5 a4 1 0 0
a3
7
a8 a7 a6 a5 a4 a3 1 0
a2
8
a8 a7 a6 a5 a4 a3 a2 1
a1
SAR algorithm - Implementation
Systematic design for SA-ADC
34
Resolution BW Power - Techno
Non idealities and noise
Thermal noise, mismatch,
Cmax >Cmin
Switches
Sizing
Yes
No
Clock frequency
Cmax
C unity = C min
Sizing procedure
System architecture
DAC topology,
SAR algorithm,
Sampling technique
Cmin
Comparator specs
Settling, resolution, kickback.
Select number of
stages
Check Specs
Layout
No No
Yes
Finalize design
No
Outline
Background
Principles of Operation
System and Circuit Design
Case Study
Simulations
Layout Generation
Performance Evaluation
Conclusion
Perspectives
35
Case Study
36
Case Study
Differential Architecture
Resolution: 8bit
BW: 50 KHz
F
clock
: 1MHz
Technology: 0.13u ST, MIM Capacitors
Verification
VHDL AMS used for verification with simulation
Different levels of abstraction (Behavioral , gates, transistor, )
Mixed blocs simulation (Analog / Digital)
Multiple abstractions
37
Capacitor
array
Comp
+
Latch
Control
In
Switches
Macro
model
Macro
model
Transistor
Transistor
MIM
VHDL
Macro
model
Clock gen VHDL
Transistor
Verification Environment
38
Resolution BW
Sketch output
spectrum
Verification Environment presets
DAC topology,
SAR algorithm,
Sampling technique
Abstraction level
Ideal, mismatched, techno,
Component sizes
Type of analysis
Calculate SNDR
Sketch SNDR v.s.
fin
Sketch SNDR v.s.
Ain
Sketch INL and
DNL
Sketch Transient
response at each node
Transiant Single Ended - Output
39
Vdd 1.2V
Fin 1.4KHz
Fclk 1MHz
Vinp-p 1.2V
Transistor level simulations
Transiant Differential - Output
40
Vdd 1.2V
Fin 1.4KHz
Fclk 1MHz
Vinp-p 1.2V
Transistor level simulations
Transiant Differential - DACs
41
Vdd 1.2V
Fin 1.4KHz
Fclk 1MHz
Vinp-p 1.2V
Differential DACs output
Transistor level simulations
Transiant Differential - Comparator
42
Vdd 1.2V
Fin 1.4KHz
Fclk 1MHz
Vinp-p 1.2V
Full conversion: Differential DACs output Comparator output
Transistor level simulations
Transient SAR control
43
Vdd 1.2V
Fin 1.4KHz
Fclk 1MHz
Vinp-p 1.2V
VHDL Description
Control block turning ON and OFF DAC switches [case of 0 input]
Transient Full Scale Ramp
44
Full Scale Slow ramp excitation
Vinp-p 1.2V
Zoom - in
Static Performance - Transistor Level
45
Static performance Evaluation in (LSB): DNL and INL [16 sample / bin]
Dynamic Performance Ideal Models
46
Vdd 1.2V
Fin 1.4KHz
Fclk 1MHz
Vinp-p 1.2V
SNDR = 47.47 dB
4096 point FFT
Ideal models simulation
SNDR = 47.44 dB
SNDR = 47.47 dB
SNDR = 46.78 dB
SNDR = 46.69 dB
Dynamic Performance Mixed Models
47
Vdd 1.2V
Fin 1.4KHz
Fclk 1MHz
Vinp-p 1.2V
4096 point FFT
Ideal
MOS
switches
MOS
comparator
0.01
mismatch
in Cu
Dynamic Performance Transistor Level
48
Vdd 1.2V
Fin 1.4KHz
Fclk 1MHz
1024 point FFT
P
o
w
e
r

S
p
e
c
r
a
l

D
e
n
s
i
t
y

(
d
B
)
Frequency (Hz)
SNDR = 46.2 dB
Transistor level simulations
49
Vdd 1.2V
Fin 1.4KHz
Fclk 1MHz
SNDR max
Ideal =47.47 dB
Transistor Level = 46.2
S
i
g
n
a
l

t
o

n
o
i
s
e

a
n
d

d
i
s
t
o
r
t
i
o
n

r
a
t
i
o

S
N
D
R
(
d
B
)
Amplitude of input signal(dB)
4096 point FFT
Transistor level simulations
Dynamic Performance
50
Vdd 1.2V
Fclk 1MHz
Vinp-p 1.2V
BW =55 KHz
S
i
g
n
a
l

t
o

n
o
i
s
e

a
n
d

d
i
s
t
o
r
t
i
o
n

r
a
t
i
o

S
N
D
R
(
d
B
)
4096 point FFT
Transistor level simulations
Dynamic Performance
Frequency of input signal (Hz)
Mismatch analysis
51
Vdd 1.2V
Fin 1.4KHz
Fclk 1MHz
Vinp-p 1.2V
4096 point FFT
0.1
mismatch
in Cu
0.05
mismatch
in Cu
SNDR = 46.36 dB
SNDR = 44.13 dB
Layout generation for SA-ADC
52
Comparator
transistor sizes
Unit
capacitance
Common centroid
placement algorithm
Desired layout
shape
Layout template s
-Component connectivity
-Relative place and route
CAIRO Layout generation
DRC LVS
Design phase
Number of
capacitors and
sizes
Target technology
Verification
Parasitics Ext.
Fabrication
Layout Comparator - Floorplan
53
Layout Comparator - Generated
54
Dummies Removed for Layout verification
Area 22 x 39 m
2
Layout Differential DACs - Floorplan
55
Common centroid placement for 16 capacitor
Layout Differential DACs - Generated
56
Layout 1 - 256 Cu Placed and Routed Area
1.26 x 0.26 mm
2
and Huge routing parasitics
Layout Differential DACs - Manual
57
Layout 2 - 256 Cu Placed
and Routed 2/3 less
routing parasitics
ZOOM
Area 0.1056 mm
2
Performance
58
[Hong07] This work* [scott03]
Technology 0.18 m 0.13 m 0.25 m
Supply 0.83 V 1.2 V 1.0 V
Input range Rail to Rail Rail to Rail Rail to Rail
Sampling rate 111 KHz 111 KHz 100 KHz
Unit Cap. 24 fF 30fF 12f
Power (Analog) 1.16 W 0.72W 2.2 W
Area 0.062 mm2 0.122 mm2 0.053 mm2
SNDR@BW 47.40 dB 46.2dB 43.8 dB
Architecture Single Ended Differential Single Ended
FOM 65 fJ/bit 64fJ/bit 2163 fJ/bit
Outline
Background
Principles of Operation
System and Circuit Design
Case Study
Simulations
Layout Generation
Performance Evaluation
Conclusion
Perspectives
59
Summary and Conclusion
60
Systematic design methodology for SA-ADC from
system to layout.
General simulation environment
Different abstraction levels.
Different verification tests.
Emphasis on analog design automation and reuse
Optimizing Layout for best component matching
Verification with case study for WSN specs
Perspectives
61
Targeting high frequency specs (>500 Msample/S)
Redundant system error correction code [Kuttner02]
Digital calibration [Promitzer01]
Asynchronous operation [Chen06]
Time interleaving [Chen06]
Full Automation
Sizing procedure with layout parasitics awareness
Layout generation for the full ADC
Thank You
62